SCAN182245ASSCQB - National Semiconductor

TL/F/11657

SCAN182245A Transceiver with 25XSeries Resistor Outputs

February 1996

SCAN182245A

Non-Inverting Transceiver with

25XSeries Resistor Outputs

General Description

The SCAN182245A is a high performance BiCMOS bidirec-

tional line driver featuring separate data inputs organized

into dual 9-bit bytes with byte-oriented output enable and

direction control signals. This device is compliant with

IEEE 1149.1 Standard Test Access Port and Boundary

Scan Architecture with the incorporation of the defined

boundary-scan test logic and test access port consisting of

Test Data Input (TDI), Test Data Out (TDO), Test Mode Se-

lect (TMS), and Test Clock (TCK).

Features

YHigh performance BiCMOS technology

Y25Xseries resistors in outputs eliminate the need for

external terminating resistors

YDual output enable control signals

YTRI-STATEÉoutputs for bus-oriented applications

Y25 mil pitch SSOP (Shrink Small Outline Package)

YIEEE 1149.1 (JTAG) Compliant

YIncludes CLAMP, IDCODE and HIGHZ instructions

YAdditional instructions SAMPLE-IN, SAMPLE-OUT and

EXTEST-OUT

YPower Up TRI-STATE for hot insert

YMember of National’s SCAN Products

Connection Diagram

TL/F/11657–1

Pin Names Description

A1(0–8) Side A1 Inputs or TRI-STATE Outputs

B1(0–8) Side B1 Inputs or TRI-STATE Outputs

A2(0–8) Side A2 Inputs or TRI-STATE Outputs

B2(0–8) Side B2 Inputs or TRI-STATE Outputs

G1,G2 Output Enable Pins (Active Low)

DIR1, DIR2 Direction of Data Flow Pins

Order Number Description

SCAN182245ASSC SSOP in Tubes

SCAN182245ASSCX SSOP Tape and Reel

SCAN182245AFMQB Flatpak Military

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A. http://www.national.com

Truth Tables

Inputs A1(0–8) B1(0–8)

²G1 DIR1

LL H

LL L

LH H

LH L

HX Z Z

Inputs A2(0–8) B2(0–8)

²G2 DIR2

LL H

LL L

LH H

LH L

HX Z Z

HIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

ZeHigh Impedance

²eInactive-to-Active transition must occur to enable outputs upon

power-up.

Functional Description

The SCAN182245A consists of two sets of nine non-invert-

ing bidirectional buffers with TRI-STATE outputs and is in-

tended for bus-oriented applications. Direction pins (DIR1

and DIR2) LOW enables data from B ports to A ports, when

HIGH enables data from A ports to B ports. The Output

Enable pins (G1 and G2) when HIGH disables both A and B

ports by placing them in a high impedance condition.

Block Diagrams

A1, B1, G1 and DIR1

TL/F/11657–2

Note: BSR stands for Boundary Scan Register.

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Block Diagrams (Continued)

Tap Controller

TL/F/11657–18

A2, B2, G2 and DIR2

TL/F/11657–3

Note: BSR stands for Boundary Scan Register.

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Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are

one of the following two types depending upon their loca-

tion. Scan cell TYPE1 is intended to solely observe system

data, while TYPE2 has the additional ability to control sys-

tem data. (See IEEE Standard 1149.1

Figure 10-11

for a

further description of scan cell TYPE1 and

Figure 10-12

for

a further description of scan cell TYPE2.)

Scan cell TYPE1 is located on each system input pin while

scan cell TYPE2 is located at each system output pin as

well as at each of the two internal active-high output enable

signals. AOE controls the activity of the A-outputs while

BOE controls the activity of the B-outputs. Each will activate

their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage iden-

tical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

TL/F/11657–17

SCAN182245A Product IDCODE

(32-Bit Code per IEEE 1149.1)

Version Entity Part Manufacturer Required by

Number ID 1149.1

0000 111111 0000000000 00000001111 1

MSB LSB

The INSTRUCTION register is an 8-bit register which cap-

tures the default value of 10000001 (SAMPLE/PRELOAD)

during the CAPTURE-IR instruction command. The benefit

of capturing SAMPLE/PRELOAD as the default instruction

during CAPTURE-IR is that the user is no longer required to

shift in the 8-bit instruction for SAMPLE/PRELOAD. The se-

quence of: CAPTURE-IR

EXIT1-IR

UPDATE-IR

will update the SAMPLE/PRELOAD instruction. For more

information refer to the section on instruction definitions.

Instruction Register Scan Chain Definition

TL/F/11657–10

MSB

LSB

Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGH-Z

01000001 SAMPLE-IN

01000010 SAMPLE-OUT

00100010 EXTEST-OUT

10101010 IDCODE

11111111 BYPASS

All Others BYPASS

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Description of BOUNDARY-SCAN Circuitry (Continued)

Scan Cell TYPE1

TL/F/11657–11

Scan Cell TYPE2

TL/F/11657–12

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Description of BOUNDARY-SCAN Circuitry (Continued)

BOUNDARY-SCAN Register

Scan Chain Definition (80 Bits in Length)

TL/F/11657–32

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Description of BOUNDARY-SCAN Circuitry (Continued)

Input BOUNDARY-SCAN Register

Scan Chain Definition (40 Bits in Length)

When Sample In is Active

TL/F/11657–33

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Description of BOUNDARY-SCAN Circuitry (Continued)

Output BOUNDARY-SCAN Register

Scan Chain Definition (40 Bits in Length)

When Sample Out and EXTEST-Out are Active

TL/F/11657–34

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Description of BOUNDARY-SCAN Circuitry (Continued)

BOUNDARY-SCAN Register Definition Index

Bit No. Pin Name Pin No. Pin Type Scan Cell Type

79 DIR1 3 Input TYPE1

Control

Signals

78 G1 54 Input TYPE1

77 AOE1Internal TYPE2

76 BOE1Internal TYPE2

75 DIR2 26 Input TYPE1

74 G2 31 Input TYPE1

73 AOE2Internal TYPE2

72 BOE2Internal TYPE2

71 A1055 Input TYPE1

A1–in

70 A1153 Input TYPE1

69 A1252 Input TYPE1

68 A1350 Input TYPE1

67 A1449 Input TYPE1

66 A1547 Input TYPE1

65 A1646 Input TYPE1

64 A1744 Input TYPE1

63 A1843 Input TYPE1

62 A2042 Input TYPE1

A2–in

61 A2141 Input TYPE1

60 A2239 Input TYPE1

59 A2338 Input TYPE1

58 A2436 Input TYPE1

57 A2535 Input TYPE1

56 A2633 Input TYPE1

55 A2732 Input TYPE1

54 A2830 Input TYPE1

53 B102 Output TYPE2

B1– out

52 B114 Output TYPE2

51 B125 Output TYPE2

50 B137 Output TYPE2

49 B148 Output TYPE2

48 B1510 Output TYPE2

47 B1611 Output TYPE2

46 B1713 Output TYPE2

45 B1814 Output TYPE2

44 B2015 Output TYPE2

B2– out

43 B2116 Output TYPE2

42 B2218 Output TYPE2

41 B2319 Output TYPE2

40 B2421 Output TYPE2

39 B2522 Output TYPE2

38 B2624 Output TYPE2

37 B2725 Output TYPE2

36 B2827 Output TYPE2

35 B102 Input TYPE1

B1–in

34 B114 Input TYPE1

33 B125 Input TYPE1

32 B137 Input TYPE1

31 B148 Input TYPE1

30 B1510 Input TYPE1

29 B1611 Input TYPE1

28 B1713 Input TYPE1

27 B1814 Input TYPE1

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Description of BOUNDARY-SCAN Circuitry (Continued)

BOUNDARY-SCAN Register Definition Index (Continued)

Bit No. Pin Name Pin No. Pin Type Scan Cell Type

26 B2015 Input TYPE1

B2–in

25 B2116 Input TYPE1

24 B2218 Input TYPE1

23 B2319 Input TYPE1

22 B2421 Input TYPE1

21 B2522 Input TYPE1

20 B2624 Input TYPE1

19 B2725 Input TYPE1

18 B2827 Input TYPE1

17 A1055 Output TYPE2

A1– out

16 A1153 Output TYPE2

15 A1252 Output TYPE2

14 A1350 Output TYPE2

13 A1449 Output TYPE2

12 A1547 Output TYPE2

11 A1646 Output TYPE2

10 A1744 Output TYPE2

9A1

843 Output TYPE2

8A2

042 Output TYPE2

A2– out

7A2

141 Output TYPE2

6A2

239 Output TYPE2

5A2

338 Output TYPE2

4A2

436 Output TYPE2

3A2

535 Output TYPE2

2A2

633 Output TYPE2

1A2

732 Output TYPE2

0A2

830 Output TYPE2

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SCAN ABT Live Insertion and Power Cycling Characteristics

SCAN ABT is intended to serve in Live Insertion backplane

applications. It provides 2nd Level Isolation1which indicates

that while external circuitry to control the output enable pin

is unnecessary, there may be a need to implement differen-

tial length backplane connector pins for VCC and GND. As

well, pre-bias circuitry for backplane pins may be necessary

to avoid capacitive loading effects during live insertion.

SCAN ABT provides control of output enable pins during

power cycling via the circuit in

Figure A

. It essentially con-

trols the Gnpin until VCC reaches a known level.

During

power-up

, when VCC ramps through the 0.0V to 0.7V

range, all internal device circuitry is inactive, leaving output

and I/O pins of the device in high impedance. From approxi-

mately 0.8V to 1.8V VCC, the Power-On-Reset circuitry,

(POR), in

Figure A

becomes active and maintains device

high impedance mode. The POR does this by providing a

low from its output that resets the flip-flop The output, Q,of

the flip-flop then goes high and disables the NOR gate from

an incidental low input on the Gnpin. After 1.8V VCC, the

POR circuitry becomes inactive and ceases to control the

flip-flop. To bring the device out of high impedance, the Gn

input must receive an inactive-to-active transition, a high-to-

low transition on Gnin this case to change the state of the

flip-flop. With a low on the Q output of the flip-flop, the NOR

gate is free to allow propagation of a Gnsignal.

During

power-down

, the Power-On-Reset circuitry will be-

come active and reset the flip-flop at approximately 1.8V

VCC. Again, the Q output of the flip-flop returns to a high and

disables the NOR gate from inputs from the Gnpin. The

device will then remain in high impedance for the remaining

ramp down from 1.8V to 0.0V VCC.

Some suggestions to help the designer with live insertion

issues:

#The Gnpin can float during power-up until the Power-On-

Reset circuitry becomes inactive.

#The Gnpin can float on power-down only after the Pow-

er-On-Reset has become active.

The description of the functionality of the Power-On-Reset

circuitry can best be described in the diagram of

Figure B

TL/F/11657–19

FIGURE A

TL/F/11657–20

FIGURE B

1Section 7, ‘‘Design Consideration for Fault Tolerant Backplanes’’, Application Note AN-881.

SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias

Ceramic b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

Voltage Applied to Any Output

in the Disabled or

Power-Off State b0.5V to a5.5V

in the HIGH State b0.5V to VCC

Current Applied to Output

in LOW State (Max) Twice the Rated IOL (mA)

DC Latchup Source Current

Commercial b500 mA

Military b300 mA

Over Voltage Latchup (I/O) 10V

ESD (HBM) Min. 2000V

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating

Conditions

Free Air Ambient Temperature

Military b55§Ctoa

125§C

Commercial b40§Ctoa

85§C

Supply Voltage

Military a4.5V to a5.5V

Commercial a4.5V to a5.5V

Minimum Input Edge Rate (DV/Dt)

Data Input 50 mV/ns

Enable Input 20 mV/ns

DC Electrical Characteristics

Symbol Parameter VCC Min Typ Max Units Conditions

VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized LOW Signal

VCD Input Clamp Diode Voltage Min b1.2 V IIN eb

18 mA

VOH Output HIGH Voltage Min 2.5 V IOH eb

3mA

Mil Min 2.0 V IOH eb

24 mA

Comm Min 2.0 V IOH eb

32 mA

VOL Output LOW Voltage

Mil Min 0.8 V IOL e12 mA

Comm Min 0.8 V IOL e15 mA

IIH Input HIGH Current All Others Max 5 mAV

IN e2.7V (Note 1)

Max 5 mAV

IN eVCC

TMS, TDI Max 5 mAV

IN eVCC

IBVI Input HIGH Current Max 7 mAVIN e7.0V

Breakdown Test

IBVIT Input HIGH Current Max 100 mAVIN e5.5V

Breakdown Test (I/O)

IIL Input LOW Current All Others Max b5mAV

IN e0.5V (Note 1)

Max b5mAV

IN e0.0V

TMS, TDI Max b385 mAV

IN e0.0V

VID Input Leakage Test 0.0 4.75 V IID e1.9 mA

All Other Pins Grounded

IIH aIOZH Output Leakage Current Max 50 mAV

OUT e2.7V

IIL aIOZL Output Leakage Current Max b50 mAV

OUT e0.5V

IOZH Output Leakage Current Max 50 mAV

OUT e2.7V

IOZL Output Leakage Current Max b50 mAV

OUT e0.5V

Note 1: Guaranteed not tested.

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DC Electrical Characteristics (Continued)

Symbol Parameter VCC Min Typ Max Units Conditions

IOS Output Short-Circuit Current Max b100 b275 mA VOUT e0.0V

ICEX Output HIGH Leakage Current Max 50 mAV

OUT eVCC

IZZ Bus Drainage Test 0.0 100 mAVOUT e5.5V

All Others GND

ICCH Power Supply Current Max 250 mAV

OUT eVCC; TDI, TMS eVCC

Max 1.0 mA VOUT eVCC; TDI, TMS eGND

ICCL Power Supply Current Max 65 mA VOUT eLOW; TDI, TMS eVCC

Max 65.8 mA VOUT eLOW; TDI, TMS eGND

ICCZ Power Supply Current Max 250 mA TDI, TMS eVCC

Max 1.0 mA TDI, TMS eGND

ICCT Additional ICC/Input

All Other Inputs Max 2.9 mA VIN eVCC b2.1V

TDI, TMS inputs Max 3 mA VIN eVCC b2.1V

ICCD Dynamic ICC No Load Max 0.2 mA/ Outputs Open

MHz One Bit Toggling, 50% Duty Cycle

AC Electrical Characteristics Normal Operation

Symbol Parameter VCC*

(V)

Military Commercial

Units

TAeb

55§Ctoa

125§CT

40§Ctoa

85§C

CLe50 pF CLe50 pF

Min Typ Max Min Typ Max

tPLH Propagation Delay 5.0 1.0 3.1 5.2 ns

tPHL AtoB,BtoA 1.5 4.4 6.5

PLZ Disable Time 5.0 1.5 4.8 8.6 ns

tPHZ 1.5 5.2 8.9

tPZL Enable Time 5.0 1.5 5.5 9.1 ns

tPZH 1.5 4.6 8.2

*Voltage Range 5.0V g0.5V

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AC Electrical Characteristics Scan Test Operation

Symbol Parameter VCC*

(V)

Military Commercial

Units

TAeb

55§Ctoa

125§CT

40§Ctoa

85§C

CLe50 pF CLe50 pF

Min Typ Max Min Typ Max

tPLH Propagation Delay 5.0 2.9 6.1 10.2 ns

tPHL TCK to TDO 4.2 7.7 12.1

tPLZ Disable Time 5.0 2.1 5.9 10.7 ns

tPHZ TCK to TDO 3.3 7.4 12.5

tPZL Enable Time 5.0 4.6 8.7 13.7 ns

tPZH TCK to TDO 2.8 6.8 11.5

tPLH Propagation Delay 2.8 6.3 10.7 ns

tPHL TCK to Data Out 5.0 4.5 8.2 13.0

during Update-DR State

tPLH Propagation Delay 3.3 7.2 12.2 ns

tPHL TCK to Data Out 5.0 5.0 9.3 14.8

during Update-IR State

tPLH Propagation Delay 3.7 8.4 14.0 ns

tPHL TCK to Data Out 5.0 5.7 10.8 17.2

during Test Logic

Reset State

tPLZ Disable Time 2.8 7.6 13.9 ns

tPHZ TCK to Data Out 5.0 3.5 8.4 14.5

during Update-DR State

tPLZ Disable Time 3.6 8.7 15.1 ns

tPHZ TCK to Data Out 5.0 3.8 9.2 15.9

during Update-IR State

tPLZ Disable Time 4.0 9.8 17.1 ns

tPHZ TCK to Data Out 5.0 4.2 9.9 16.6

during Test Logic

Reset State

tPZL Enable Time 4.4 9.3 15.5 ns

tPZH TCK to Data Out 5.0 3.0 7.5 13.3

during Update-DR State

tPZL Enable Time 5.2 10.7 17.4 ns

tPZH TCK to Data Out 5.0 3.9 9.0 15.4

during Update-IR State

tPZL Enable Time 5.7 12.0 19.8 ns

tPZH TCK to Data Out 5.0 3.0 10.2 17.6

during Test Logic

Reset State

*Voltage Range 5.0V g0.5V

All Propagation Delays involving TCK are measured from the falling edge of TCK.

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AC Operating Requirements Scan Test Operation

Symbol Parameter VCC*

(V)

Military Commercial

Units

TAeb

55§Ctoa

125§CT

40§Ctoa

85§C

CLe50 pF CLe50 pF

Guaranteed Minimum

tSSetup Time 5.0 4.8 ns

Data to TCK (Note 1)

tHHold Time 5.0 2.5 ns

Data to TCK (Note 1)

tSSetup Time, H or L 5.0 4.1 ns

G1,G2to TCK (Note 2)

tHHold Time, H or L 5.0 1.7 ns

TCK to G1,G2(Note 2)

tSSetup Time, H or L 5.0 4.2 ns

DIR1, DIR2 to TCK (Note 4)

tHHold Time, H or L 5.0 2.3 ns

TCK to DIR1, DIR2 (Note 4)

tSSetup Time 5.0 3.8 ns

Internal OE to TCK (Note 3)

tHHold Time, H or L 5.0 2.3 ns

TCK to Internal OE (Note 3)

tSSetup Time, H or L 5.0 8.7 ns

TMS to TCK

tHHold Time, H or L 5.0 1.5 ns

TCK to TMS

tSSetup Time, H or L 5.0 6.7 ns

TDI to TCK

tHHold Time, H or L 5.0 5.0 ns

TCK to TDI

tWPulse Width TCK H 5.0 10.2 ns

L 8.5

fmax Maximum TCK 5.0 50 MHz

Clock Frequency

tPU Wait Time, 5.0 100 ns

Power Up to TCK

tDN Power Down Delay 0.0 100 ms

*Voltage Range 5.0V g0.5V

All Input Timing Delays involving TCK are measured from the rising edge of TCK.

Note 1: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71).

Note 2: Timing pertains to BSR 74 and 78 only.

Note 3: Timing pertains to BSR 72, 73, 76 and 77 only.

Note 4: Timing pertains to BSR 75 and 79 only.

Capacitance

Symbol Parameter Typ Units Conditions, TAe25§C

CIN Input Capacitance 5.9 pF VCC e0.0V (Gn, DIRn)

CI/O (Note 1) Output Capacitance 13.7 pF VCC e5.0V (An,B

)

Note 1: CI/O is measured at frequency f e1 MHz, per MIL-STD-883B, Method 3012.

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Ordering Information

SCAN 18 2245 A SS C X

Serially Controlled Access Network Special Variations

XeTape and Reel

18-Bit Logic QB eMilitary grade device with

environmental and burn-in

Function Type processing.

Technology Designator Temperature Range

TeTTL Input TTL Output CMOS Device CeCommercial (b40§Cto

CeCMOS Input/Output CMOS Device a85§C)

BeBipolar TTL Device MeMilitary (b55§Ctoa

125§C)

EeECL Device

AeBiCMOS Device Package Code

FeTTL Input/CMOS Output CMOS Device SS e25 mil Pitch (JEDEC) SSOP

Fe25 mil Pitch Ceramic Flatpak

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Physical Dimensions inches (millimeters)

56-Lead SSOP (0.300×Wide) (SS)

Order Number SCAN182245ASSC or SCAN182245ASSCX

NS Package Number MS56A

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SCAN182245A Transceiver with 25XSeries Resistor Outputs

Physical Dimensions inches (millimeters) (Continued)

56-Lead Ceramic Flatpak (F)

Order Number SCAN182245AFMQB

NS Package Number WA56A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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Corporation Europe Hong Kong Ltd. Japan Ltd.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.