CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 - APRIL 2003 D D D D D D D D D M PACKAGE (TOP VIEW) AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Buffered Inputs Contains Four Flip-Flops With Double-Rail Outputs Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays 24-mA Output Drive Current - Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 Applications Include: - Buffer/Storage Registers - Shift Registers - Pattern Generators CLR 1Q 1Q 1D 2D 2Q 2Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4Q 4Q 4D 3D 3Q 3Q CLK description/ordering information This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. ORDERING INFORMATION -55C 55C to 125C ORDERABLE PART NUMBER PACKAGE TA SOIC - M Tube CD74AC175M Tape and reel CD74AC175M96 TOP-SIDE MARKING AC175M Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS CLR CLK D Q Q L X X L H H H H L H L L H H L X Q0 Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 - APRIL 2003 logic diagram (positive logic) CLR CLK 1D 1 9 4 2 1D 1Q C1 3 R 1Q To Three Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25C VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL High-level output current t/v Input transition rise or fall rate -40C to 85C UNIT MIN MAX MIN MAX MIN MAX 1.5 5.5 1.5 5.5 1.5 5.5 VCC = 1.5 V VCC = 3 V 1.2 1.2 1.2 2.1 2.1 2.1 VCC = 5.5 V VCC = 1.5 V 3.85 VCC = 3 V VCC = 5.5 V 3.85 0 3.85 0.3 0.3 0.9 0.9 0.9 VCC VCC 1.65 0 0 V V 0.3 1.65 0 Output voltage Low-level output current -55C to 125C VCC VCC V 1.65 0 0 VCC VCC V V VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V -24 -24 -24 mA 24 24 24 mA VCC = 1.5 V to 3 V VCC = 3.6 V to 5.5 V 50 50 50 20 20 20 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 - APRIL 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN IOH = -50 A VOH VI = VIH or VIL IOH = -4 mA IOH = -24 mA IOH = -50 mA IOH = -75 mA IOL = 50 A VOL II ICC VI = VIH or VIL VI = VCC or GND VI = VCC or GND, -55C to 125C TA = 25C MAX MIN -40C to 85C MAX MIN 1.5 V 1.4 1.4 1.4 2.9 3V 2.9 2.9 4.5 V 4.4 4.4 4.4 3V 2.58 2.4 2.48 4.5 V 3.94 3.7 3.8 5.5 V UNIT MAX V 3.85 5.5 V 3.85 1.5 V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 12 mA IOL = 24 mA IOL = 50 mA 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 IOL = 75 mA 5.5 V 5.5 V 5.5 V IO = 0 5.5 V Ci V 1.65 1.65 0.1 1 1 A 8 160 80 A 10 10 10 pF Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85C and 75- transmission-line drive capability at 125C. timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless otherwise noted) -55C to 125C MIN fclock Clock frequency tw Pulse duration tsu th Setup time before CLK trec Recovery time, before CLK -40C to 85C MAX MIN 8 9 MHz CLR low 50 44 CLK high or low 63 55 2 2 ns 2 2 ns 1 1 ns Data Hold time, data after CLK CLR POST OFFICE BOX 655303 UNIT MAX * DALLAS, TEXAS 75265 ns 3 CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 - APRIL 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) -55C to 125C MIN fclock Clock frequency tw Pulse duration tsu th Setup time before CLK trec Recovery time, before CLK -40C to 85C MAX MIN 71 CLR low UNIT MAX 81 MHz 5.6 4.9 CLK high or low 7 6.1 Data 2 2 ns 2 2 ns 1 1 ns Hold time, data after CLK CLR ns timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) -55C to 125C MIN fclock Clock frequency MAX -40C to 85C MIN 100 tw Pulse duration tsu th Setup time before CLK trec Recovery time, before CLK UNIT MAX 114 MHz CLR low 4 3.5 CLK high or low 5 4.4 Data 2 2 ns 2 2 ns 1 1 ns Hold time, data after CLK CLR ns switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) -55C to 125C MIN MAX 8 CLK Any Q CLR Any Q -40C to 85C MIN UNIT MAX 9 MHz 153 139 153 139 153 139 153 139 ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL 4 FROM (INPUT) TO (OUTPUT) -55C to 125C MIN MAX MIN 4.3 17.1 4.4 15.5 4.3 17.1 4.4 15.5 4.3 17.1 4.4 15.5 4.3 17.1 4.4 15.5 71 CLK Any Q CLR Any Q POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 -40C to 85C UNIT MAX 81 MHz ns ns CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 - APRIL 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) -55C to 125C MIN MAX 100 CLK Any Q CLR Any Q -40C to 85C MIN UNIT MAX 114 MHz 3.1 12.2 3.2 11.1 3.1 12.2 3.2 11.1 3.1 12.2 3.2 11.1 3.1 12.2 3.2 11.1 ns ns operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd Power dissipation capacitance POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TYP UNIT 55 pF 5 CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 - APRIL 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 From Output Under Test 2 x VCC Open GND CL = 50 pF (see Note A) R2 = 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND tw VCC When VCC = 1.5 V, R1 = R2 = 1 k Input 50% VCC 50% VCC 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME tf VCC 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 90% VOH 50% VCC 10% VOL tf Output Waveform 1 S1 at 2 x VCC (see Note B) tPLH 50% VCC 10% tf 50% 10% 90% tr VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VCC Output Control 50% VCC 50% VCC 0V tPLZ tPZL 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VCC 20% VCC VOL 50% VCC VOH 80% VCC 0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp CD74AC175M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC175M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC175M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC175M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC175ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC175MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC175M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC175M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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