High Voltage, Differential
18-Bit ADC Driver
Data Sheet ADA4922-1
Rev. A Document Feedback
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Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Single-ended-to-differential conversion
Low distortion (VO, dm = 40 V p-p)
−99 dBc HD at 100 kHz
Low differential output referred noise: 12 nV/√Hz
High input impedance: 11 MΩ
Fixed gain of 2
No external gain components required
Low output-referred offset voltage: 1.1 mV maximum
Low input bias current: 3.5 μA maximum
Wide supply range
5 V to 26 V
Can produce differential output signals in excess of 40 V p-p
High speed
38 MHz, −3 dB bandwidth at 0.2 V p-p differential output
Fast settling time
200 ns to 0.01% for 12 V step on ±5 V supplies
Disable feature
Available in space-saving, thermally enhanced packages
8-lead, 3 mm × 3 mm LFCSP
8-lead SOIC
Low supply current: IS = 10 mA on ±12 V supplies
APPLICATIONS
High voltage data acquisition systems
Industrial instrumentation
Spectrum analysis
ATE
Medical instruments
GENERAL DESCRIPTION
The ADA4922-1 is a differential driver for 16-bit to 18-bit
analog-to-digital converters (ADCs) that have differential input
ranges up to ±20 V. Configured as an easy-to-use, single-ended-
to-differential amplifier, the ADA4922-1 requires no external
components to drive ADCs. The ADA4922-1 provides essential
benefits such as low distortion and high SNR that are required
for driving ADCs with resolutions up to 18 bits.
With a wide supply voltage range (5 V to 26 V), high input
impedance, and fixed differential gain of 2, the ADA4922-1 is
designed to drive ADCs found to in a variety of applications,
including industrial instrumentation.
FUNCTIONAL BLOCK DIAGRAM
NIC
REF
V
S+
OUT+
DIS
IN
V
S–
OUT–
NOTES
1. EX P OSE D P AD M UST BE CONNECTED TO G ND.
2. NI C = NO I NTERAL CO NNECT IO N.
3
4
1
2
6
5
8
7
A
DA4922-1
TOP VIEW
05681-001
Figure 1.
The ADA4922-1 is manufactured on Analog Devices, Inc.,
proprietary, second-generation XFCB process that enables the
amplifier to achieve excellent noise and distortion performance
on high supply voltages.
The ADA4922-1 is available in an 8-lead 3 mm × 3 mm LFCSP
as well as an 8-lead SOIC package. Both packages are equipped
with an exposed paddle for more efficient heat transfer. The
ADA4922-1 is rated to work over the extended industrial
temperature range, −40°C to +85°C.
–84
–120
05681-012
FREQUENCY (kHz)
DISTORTION (dBc)
1 10 100
–87
–90
–93
–102
–99
–96
–105
–108
–111
–114
–117
SECOND HARMONIC
THIRD HARMONIC
R
L
= 2k
V
S
= 12V, V
O, dm
= 40V p-p
V
S
= 5V, V
O, dm
= 12V p-p
Figure 2. Harmonic Distortion for Various Power Supplies
ADA4922-1 Data Sheet
Rev. A | Page 2 of 19
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 16
ADA4922-1 Differential Output Noise Model .......................... 16
Using the REF Pin ...................................................................... 16
Internal Feedback Network Power Dissipation ...................... 17
Disable Feature ........................................................................... 17
Driving a Differential Input ADC ............................................ 17
Printed Circuit Board Layout Considerations ....................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Change CP-8-2 to CP-8-13 ........................................... Throughout
Changes to Figure 1 .......................................................................... 1
Changes to Figure 4 .......................................................................... 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
10/2005—Revision 0: Initial Version
Data Sheet ADA4922-1
Rev. A | Page 3 of 19
SPECIFICATIONS
VS = ±12 V, TA = 25°C, RL = 1 kΩ, DIS = high, CL = 3 pF, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +2, VO = 0.2 V p-p, differential 34 38 MHz
G = +2, VO = 40 V p-p, differential 6.5 7.2 MHz
Overdrive Recovery Time VS+ + 0.5 V to VS− − 0.5 V; +recovery/−recovery 180/330 ns
Slew Rate
V
O, dm
= 2 V step
260
V/µs
VO, dm = 40 V step 730 V/µs
Settling Time to 0.01% VO, dm = 40 V step 580 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion fC = 5 kHz, VO = 40 V p-p, RL = 2 kΩ, HD2/HD3 −116/−109 dBc
fC = 100 kHz, VO = 40 V p-p, RL = 2 kΩ, HD2/HD3 −99/−100 dBc
Differential Output Voltage Noise f = 100 kHz 12 nV/√Hz
Input Current Noise f = 100 kHz 1.4 pA/√Hz
DC PERFORMANCE
Differential Output Offset Voltage 0.35 1.1 mV
Differential Output Offset Voltage Drift 14 µV/°C
Input Bias Current 1.8 3.5 µA
Gain 2 V/V
Gain Error −0.05 %
Gain Error Drift 0.0002 %/°C
INPUT CHARACTERISTICS
Input Resistance 11 MΩ
Input Capacitance 1 pF
Input Voltage Range ±10.7 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output, RL = 1 kΩ ±10.65 ±10.7 V
DC Output Current 40 mA
Capacitive Load Drive 30% overshoot 20 pF
POWER SUPPLY
Operating Range
5
26
V
Quiescent Current 9.4 10.1 mA
Quiescent Current (Disabled) 1.5 2.0 mA
Power Supply Rejection Ratio (PSRR)
−PSRR −89 −80 dB
+PSRR −91 −83 dB
DISABLE
DIS Input Voltage Threshold Disabled ≤ −11 V
Enabled ≥ −9 V
Turn-Off Time 160 µs
Turn-On Time 78 ns
DIS Bias Current
Enabled DIS = −9 V 114 µA
Disabled DIS = −11 V −125 µA
ADA4922-1 Data Sheet
Rev. A | Page 4 of 19
VS = ±5 V, TA = 25°C, RL = 1 kΩ, DIS = high, CL = 3 pF, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +2, VO = 0.2 V p-p, differential 36 40.5 MHz
G = +2, VO = 12 V p-p, differential 6.5 13.5 MHz
Overdrive Recovery Time +Recovery/−Recovery 200/670 ns
Slew Rate VO, dm = 2 V step 220 V/µs
VO, dm = 12 V step 350 V/µs
Settling Time to 0.01% VO, dm = 12 V step 200 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion fC = 5 kHz, VO = 12 V p-p, RL = 2 kΩ, HD2/HD3 −102/−108 dBc
f
C
= 100 kHz, V
O
= 12 V p-p, R
L
= 2 kΩ, HD2/HD3
−101/−98
dBc
Differential Output Voltage Noise f = 100 kHz 12 nV/√Hz
Input Current Noise f = 100 kHz 1.4 pA/√Hz
DC PERFORMANCE
Differential Output Offset Voltage 0.4 1.2 mV
Differential Output Offset Voltage Drift 12 µV/°C
Input Bias Current 2.0 3.5 µA
Gain 2 V/V
Gain Error −0.05 %
Gain Error Drift 0.0002 %/°C
INPUT CHARACTERISTICS
Input Resistance
11
MΩ
Input Capacitance 1 pF
Input Voltage Range ±3.6 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output, RL = 1 kΩ ±3.55 ±3.6 V
DC Output Current 40 mA
Capacitive Load Drive 30% overshoot 20 pF
POWER SUPPLY
Operating Range 5 26 V
Quiescent Current 7.0 7.6 mA
Quiescent Current (Disabled)
0.7
1.6
mA
Power Supply Rejection Ratio (PSRR)
−PSRR −93 −82 dB
+PSRR −91 −83 dB
DISABLE
DIS Input Voltage Disabled ≤ −4 V
Enabled ≥ −2 V
Turn-Off Time 160 µs
Turn-On Time 78 ns
DIS Bias Current
Enabled DIS = −2 V 41 µA
Disabled DIS = −4 V 49 µA
Data Sheet ADA4922-1
Rev. A | Page 5 of 19
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 26 V
Power Dissipation See Figure 3
Storage Temperature Range –65°C to +125°C
Operating Temperature Range –40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC with EP on 4-Layer Board 79 25 C/W
8-Lead LFCSP with EP on 4-Layer Board 81 17 C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4922-1
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4922-1. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
packages vs. the ambient temperature for the 8-lead SOIC
(79°C/W) and for the 8-lead LFCSP (81°C/W) on a JEDEC
standard 4-layer board, each with its underside paddle soldered
to a pad that is thermally connected to a PCB plane. θJA values
are approximations.
3.0
0
–40 80
05681-041
AMBIENT TEMPERATURE (C)
MAXIMUM POWER DISSIPATION (W)
2.5
2.0
1.5
1.0
0.5
–20 0 20 40 60
SOIC
LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ADA4922-1 Data Sheet
Rev. A | Page 6 of 19
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NIC
REF
V
S+
OUT+
DIS
IN
V
S–
OUT–
NOTES
1. E X P OS E D P AD MUST BE CONNECT ED TO GND.
2. NIC = NO I NTERAL CO NNECTIO N.
3
4
1
2
6
5
8
7
05681-104
ADA4922-1
TOP VI EW
(Not t o Scale)
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 NIC No Internal Connection
2 REF Reference Voltage for Single-Ended Input Signal
3 VS+ Positive Power Supply
4 OUT+ Noninverting Side of Differential Output
5 OUT− Inverting Side of Differential Output
6 VS− Negative Power Supply
7 DIS Disable
8 IN Single-Ended Signal Input
Data Sheet ADA4922-1
Rev. A | Page 7 of 19
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, VS = ±12 V, RL, dm = 1 kΩ, REF = 0 V, DIS = high, TA = 25°C.
3
–3011000
05681-013
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
V
O, dm
= 0.2V p-p
V
S
= 12V
V
S
= 5V
Figure 5. Small Signal Frequency Response for Various Power Supplies
3
–3011000
05681-014
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
V
O, dm
= 0.2V p-p
V
S
= 12V @ +85C
V
S
= 12V @ +25C
V
S
= 12V @ –40C
V
S
= 5V @ +85C
V
S
= 5V @ +25C
V
S
= 5V @ –40C
Figure 6. Small Signal Frequency Response for
Various Temperatures and Supplies
3
–3011000
05681-015
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
V
S
= 12V R
L, dm
= 1k
V
S
= 5V R
L, dm
= 1k
V
S
= 12V R
L, dm
= 500
V
S
= 5V R
L, dm
= 500
V
O
, dm = 0.2V p-p
Figure 7. Small Signal Frequency Response for
Various Resistive Loads and Supplies
3
–30
05681-016
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
110 100
V
S
= 5V, V
O, dm
= 12V p-p
V
S
= 12V, V
O, dm
= 40V p-p
Figure 8. Large Signal Frequency Response for Various Power Supplies
3
–301100
05681-017
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
10
(ALL VOLTAGES ARE V
O, dm
)
40V p-p +85C
40V p-p +25C
40V p-p –40C
12V p-p +85C
12V p-p +25C
12V p-p –40C
V
O, dm
= 12V p-p (V
S
= 5V)
V
O, dm
= 40V p-p (V
S
= 12V)
Figure 9. Large Signal Frequency Response at
Various Temperatures and Supplies
3
–301100
05681-018
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
10
V
S
= 12V, R
L, dm
= 1k
V
S
= 5V, R
L, dm
= 1k
V
S
= 12V, R
L, dm
= 500
V
S
= 5V, R
L, dm
= 500
V
O, dm
= 12V p-p (V
S
= 5V)
V
O, dm
= 40V p-p (V
S
= 12V)
Figure 10. Large Signal Frequency Response for
Various Resistive Loads and Supplies
ADA4922-1 Data Sheet
Rev. A | Page 8 of 19
3
–3011000
05681-019
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
V
O
, dm = 0.2V p-p
V
S
= 5V, C
L, dm
= 10pF
V
S
= 5V, C
L, dm
= 20pF
V
S
= 12V, C
L, dm
= 0pF
V
S
= 12V, C
L, dm
= 20pF
Figure 11. Small Signal Frequency Response for Various Capacitive Loads
3
–3311000
05681-020
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
10V p-p
12V p-p
16V p-p
0.2V p-p
2V p-p
Figure 12. Frequency Response for Various Output Amplitudes, VS = ±5 V
–50
–120 1000
05681-011
FREQUENCY (MHz)
ISOLATION (dB)
1 10 100
–60
–70
–80
–90
–100
–110
V
IN
= 0.1V p-p
DIS = LOW
V
S
= 12V
V
S
5V
Figure 13. Isolation vs. Frequency—Disabled
3
–301100
05681-050
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
10
V
S
= 5V, V
IN
= 12V p-p, C
L, dm
= 0pF
V
S
= 12V, V
IN
= 40V p-p, C
L, dm
= 0pF
V
S
= 5V, V
IN
= 12V p-p, C
L, dm
= 20pF
V
S
= 12V, V
IN
= 40V p-p, C
L, dm
= 20pF
Figure 14. Large Signal Frequency Response for Various Capacitive Loads
3
–3311000
05681-023
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
0.2V p-p
2V p-p
40V p-p
20V p-p
10V p-p
Figure 15. Frequency Response for Various Output Amplitudes, VS = ±12 V
3
–3011000
05681-024
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10 100
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
V
REF
= 0.1V p-p
V
S
= 5V
V
S
= 12V
Figure 16. REF Small Signal Frequency Response for Various Power Supplies
Data Sheet ADA4922-1
Rev. A | Page 9 of 19
–84
–120
05681-012
FREQUENCY (kHz)
DISTORTION (dBc)
1 10 100
–87
–90
–93
–102
–99
–96
–105
–108
–111
–114
–117
SECOND HARMONIC
THIRD HARMONIC
R
L
= 2k
V
S
= 12V, V
O, dm
= 40V p-p
V
S
= 5V, V
O, dm
= 12V p-p
Figure 17. Harmonic Distortion for Various Power Supplies
–60
–140 47
05681-021
OUTPUT AMPLITUDE (V p-p)
DISTORTION (dBc)
72221712 42373227
–70
–80
–90
–120
–100
–130
–110
SECOND HARMONIC
THIRD HARMONIC
R
L
= 2k
V
S
= 12V
V
S
= 5V
Figure 18. Harmonic Distortion vs. Output Amplitude and
Supply Voltage (f =10 kHz)
0
–100
05681-025
FREQUENCY (MHz)
PSRR (dB)
0.001 0.01 10010.1 10
–10
–20
–70
–60
–40
–30
–80
–90
–50
–PSRR
+PSRR
Figure 19. PSRR vs. Frequency
–84
–120
05681-022
FREQUENCY (kHz)
DISTORTION (dBc)
1 10010
–87
–90
–93
–111
–108
–102
–99
–96
–114
–117
–105
SECOND HARMONIC
THIRD HARMONIC
V
S
= 12V
V
O, dm
= 40V p-p
R
L
= 600R
L
= 1k
R
L
= 2k
Figure 20. Harmonic Distortion for Various Loads
100
0.01
0.001 100
05681-030
FREQUENCY (MHz)
IMPEDANCE (
)
0.01 0.1 1 10
0.1
1
10 VON
V
S
= 5V
VOP
V
S
= 5V
VOP
V
S
= 12V
VON
V
S
= 12V
Figure 21. Single-Ended Output Impedance vs. Frequency and Supplies
ADA4922-1 Data Sheet
Rev. A | Page 10 of 19
100
01100M
05681-032
FREQUENCY (Hz)
DIFFERENTIAL VOLTAGE NOISE (RTO) (nV/ Hz)
10 100 1k 10k 100k 1M 10M
90
80
70
60
50
40
30
20
10
Figure 22. Differential Output Noise vs. Frequency
0.12
–0.12
05681-033
OUTPUT VOLTAGE (V)
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
V
S
= 5V
V
S
= 12V
20ns/DIV
Figure 23. Small Signal Transient Response for Various Power Supplies
0.125
–0.125
05681-037
OUTPUT VOLTAGE (V)
0.100
0.075
0.050
0.025
0
–0.025
–0.050
–0.075
–0.100
C
L
= 0pF
C
L
= 10pF
C
L
= 20pF
5ns/DIV
Figure 24. Small Signal Transient Response for Various Capacitive Loads
50
0
05681-026
FREQUENCY (Hz)
INPUT CURRENT NOISE (pA/
Hz)
110 1M100k1k100 10k
45
40
15
20
30
35
10
5
25
Figure 25. Input Current Noise vs. Frequency
22
–22
05681-027
OUTPUT VOLTAGE (V)
18
14
10
6
2
–2
–6
–10
–14
–18
TIME (s)
100ns/DIV
C
L
= 20pF
V
OUT
= 40V p-p
Figure 26. Large Signal Transient Response for Various Power Supplies
22
–22
05681-040
OUTPUT VOLTAGE (V)
18
14
10
6
2
–2
–6
–10
–14
–18 20ns/DIV
C
L
= 0pF
C
L
= 20pF
Figure 27. Large Signal Transient Response for Various Capacitive Loads
Data Sheet ADA4922-1
Rev. A | Page 11 of 19
8
–8
–6
05681-028
AMPLITUDE (V)
6
4
–4
–2
–4.8
–3.6
ERROR (mV)
1 DIV = 0.01%
–2.4
–1.2
1.2
0
2.4
3.6
4.8
0
2
VS = 5V
VO, dm = 12V p-p
VOUT, dm
ERROR
VIN
1s/DIV
Figure 28. Settling Time, VS = ±5 V
12
–12
05681-029
OUTPUT VOLTAGE (V)
0
4
8
–8
–4
INPUT 2
OUTPUT
1s/DIV
Figure 29. Input Overdrive Recovery, VS = ±5 V
1.2
–1.2
05681-036
TEMPERATURE (C)
DIFFERENTIAL OUTPUT OFFSET VOLTAGE (mV)
–40 –20 806020040
1.0
0.8
–0.4
–0.2
0
0.4
0.6
–0.6
–1.0
–0.8
0.2
V
S
= 12V
V
S
= 5V
Figure 30. Differential Output Offset Voltage vs. Temperature
28
–28
–21
AMPLITUDE (V)
21
14
–14
–7
–16
–12
ERROR (mV)
1 DIV = 0.01%
–8
–4
4
0
8
12
16
0
7
VS = 12V
VO, dm = 40V p-p
VOUT, dm
ERROR
VIN
05681-031
1s/DIV
Figure 31. Settling Time, VS = ±12 V
26
22
–26
05681-035
OUTPUT VOLTAGE (V)
2
10
6
18
14
–18
–22
–2
–6
–10
–14
INPUT 2
OUTPUT
1s/DIV
Figure 32. Input Overdrive Recovery, VS = ±12 V
50
0
05681-043
DIFFERENTIAL OUTPUT OFFSET VOLTAGE (mV)
FREQUENCY
–1.000
–0.875
–0.750
–0.625
–0.500
–0.375
–0.250
0.625
0.750
0.875
1.000
0.125
0.250
0.375
–0.125
0
0.500
45
40
15
20
25
30
35
10
5
V
S
= 5V
MEAN = 0.25mV
STD. DEV. = 0.19mV
V
S
= 12V
MEAN = –0.07mV
STD. DEV. = 0.17mV
NUMBER OF
UNITS = 590
Figure 33. Differential Output Offset Voltage Distribution
ADA4922-1 Data Sheet
Rev. A | Page 12 of 19
12.0
6.0
05681-038
TEMPERATURE (C)
POWER SUPPLY CURRENT (mA)
–40 –20 806020040
11.5
11.0
8.0
8.5
9.0
10.0
10.5
7.5
6.5
7.0
9.5 V
S
= 12V
V
S
= 5V
Figure 34. Power Supply Current vs. Temperature
3.0
1.0
05681-039
TEMPERATURE (C)
INPUT BIAS CURRENT (
A)
–40 –20 806020040
2.0
2.5
1.5 INPUT BIAS CURRENT, V
S
= 5V
REFERENCE BIAS CURRENT, V
S
= 5V
INPUT BIAS CURRENT, V
S
= 12V
REFERENCE BIAS CURRENT, V
S
= 12V
Figure 35. Input Bias Current vs. Temperature
05681-046
500mV/DIV
VO, dm = 2V p-p
VDIS = –8.5V
VDIS = –10.5V
DIS INPUT
VO, dm 40s/DIV
Figure 36. Disable Turn-On Time
10
0
05681-044
DIS INPUT VOLTAGE WITH RESPECT TO V
S–
(V)
POWER SUPPLY CURRENT (mA)
0 0.5 4.03.53.02.01.0 1.5 2.5
8
9
7
6
5
4
3
2
1
I
SUPPLY
= 5V
I
SUPPLY
= 12V
Figure 37. Power Supply Current vs. Disable Input Voltage
5
–5
05681-045
INPUT VOLTAGE WITH RESPECT TO V
S–
(V)
INPUT BIAS CURRENT (A)
042242216141210 188620
0
1
2
3
4
–4
–3
–2
–1
I
B
= 5V
I
B
= 12V
Figure 38. Input Bias Current vs. Input Voltage
05681-048
500mV/DIV
VO, dm = 2V p-p
VDIS = –10.5V
DIS INPUT
VO, dm
VDIS = –8.5V
40s/DIV
Figure 39. Disable Turn-Off Time
Data Sheet ADA4922-1
Rev. A | Page 13 of 19
300
250
200
150
100
–150
–100
–50
0
50
05681-047
DIS VOLTAGE WITH RESPECT TO V
S–
(V)
DIS INPUT CURRENT (A)
05 1510 20
I
DIS
= 5V
I
DIS
= 12V
PART ON
PART OFF
Figure 40. Disable Current vs. Disable Voltage
ADA4922-1 Data Sheet
Rev. A | Page 14 of 19
THEORY OF OPERATION
The ADA4922-1 is dual amplifier that has been optimized to
drive a differential ADC from a single-ended input source with
a minimum number of external components (see Figure 41).
R
R
IN OUT+
OUT–
REF
05681-002
Figure 41. Functional Diagram
The differential output voltage is defined as
VO, dm = VOUT+ − VOUT− (1)
Each amplifier in Figure 41 is identical, and the value of Resistor R
is set at 600 Ω, yielding an optimal trade-off between output
differential noise, internal power dissipation, and overall
system linearity. For basic operation, the REF input is tied to
the midswing level of the input signal, which is often midsupply.
The input signal (referenced to REF) produces a differential
output signal with an overall gain of +2. Figure 42 shows typical
operation on ±12 V supplies with the source referenced to 0 V
and the REF pin tied to 0 V.
20
–10050
05681-003
TIME (s)
VOLTAGE (V)
10
0
–10
–20
10
5
0
–5
51510 20 25 30 35 40 45
OUT+
OUT–
REF
V
IN
Figure 42. Typical Input/Output Response—Centered Reference
If an application uses an input midswing voltage other than
midsupply, the REF pin needs to be offset to the input midswing
level to obtain outputs that do not exhibit a differential offset
(see Figure 43). If the voltage applied to the REF pin is different
from the midswing level of the input signal, a dc offset is
created between outputs VOUT+ and VOUT−. Figure 44 illustrates
this condition when the input signal is referenced to a positive
level, and the REF pin is connected to 0 V.
10
–2.5050
05681-004
TIME (s)
VOLTAGE (V)
5
0
–5
–10
10
5
0
51510 20 25 30 35 40 45
OUT+
OUT–
REF
V
IN
Figure 43. Typical Input/Output Response—Equal Input/Reference
20
–10050
05681-005
TIME (s)
VOLTAGE (V)
15
10
5
0
–5
10
5
0
–5
51510 20 25 30 35 40 45
OUT+
OUT–
REF
V
IN
Figure 44. Typical Input/Output Response—Unequal Input/Reference
Data Sheet ADA4922-1
Rev. A | Page 15 of 19
A more detailed view of the amplifier is shown in Figure 45.
Each amplifier is a 2-stage design that uses an input H-Bridge
followed by a rail-to-rail output stage (see Figure 46).
R
IN
MIRROR
C
OUTPUT
STAGE
MIRROR
INN OUTINP
I
I
I
I
05681-006
Figure 45. Internal Amplifier Architecture
R
OUT
MIRROR
MIRROR
INTERNAL
REF OUTIN
I
I
I
I
05681-007
Figure 46. Output Stage Architecture
Figure 47 illustrates the open-loop gain and phase relationships
of each amplifier in the ADA4922-1.
125
–125
–100
–75
–50
–25
100 1k 10k 100M
05681-008
FREQUENCY (Hz)
MAGNITUDE/PHASE (dB/Degrees)
75
100
50
25
0
1M100k 10M
GAIN
PHASE
Figure 47. Amplifier Gain/Phase Relationship
The architecture used in the ADA4922-1 results in excellent
SNR and distortion performance when compared to other
differential amplifiers.
One of the more subtle points of operation arises when the two
amplifiers are used to generate the differential outputs. Because
the differential outputs are derived from a follower amplifier
and an inverting amplifier, they have different noise gains and,
therefore, different closed-loop bandwidths. For frequencies up
to 1 MHz, the bandwidth difference between outputs causes
little difference in the overall differential output performance.
However, because the bandwidth is the sum of both amplifiers,
the 3 dB point of the inverting amplifier defines the overall
differential 3 dB corner (see Figure 48).
0
1
10k 100M
05681-010
FREQUENCY (Hz)
CLOSED-LOOP GAIN
–2
–4
–6
7
5
3
1M100k 10M
DIFFERENTIAL OUTPUT
OUT+
OUT–
Figure 48. Closed-Loop AC Gain (Differential Outputs)
Small delay and gain errors exist between the two outputs
because the inverting output is derived from the noninverting
output through an inverting amplifier. The gain error is due to
imperfect matching of the inverting amplifier gain and feedback
resistors, as well as differences in the transfer functions of the
two amplifiers, as illustrated in Figure 48. The delay error is due
to the delay through the inverting amplifier relative to the
noninverting amplifier output. The delay produces a reduction
in differential gain because the two outputs are not exactly 180°
out of phase. Both of these errors combine to produce an overall
gain error because the outputs are completely balanced. This
error is very small at the frequencies involved in most
ADA4922-1 applications.
ADA4922-1 Data Sheet
Rev. A | Page 16 of 19
APPLICATIONS INFORMATION
The ADA4922-1 is a fixed-gain, single-ended-to-differential
voltage amplifier, optimized for driving high resolution ADCs
in high voltage applications. There are no gain adjustments
available to the user.
ADA4922-1 DIFFERENTIAL OUTPUT NOISE MODEL
The principal noise sources in a typical ADA4922-1 application
circuit are shown in Figure 49.
V
n1
V
nRg
V
nRs
I
n1
R
s
R
g
V
nRf
R
f
OUT–
OUT+
REF
V
n2
05681-042
Figure 49. ADA4922-1 Differential Output Noise Model
Using the traditional approach, a noise source is applied in
series with one of the inputs of each op amp to model input-
referred voltage noise. The input current noise that matters the
most is present at the input pin. The output voltage noise due to
this noise current depends on the source resistance feeding the
input, as well as the downstream gain in the amplifier. Resistor
noise is modeled by placing a noise voltage source in series with
a noiseless resistor. Rf and Rg are both 600 Ω and therefore have
the same noise voltage density.
At room temperature,
HznV/3.2600kT4 nRf
nRg VV (2)
The noise at OUT+ is due to the input-referred current and
voltage noise sources of the noninverting amplifier and the
noise of the source resistance, all reflected to the output with a
noise gain of 1, and is equal to:
Voltage Noise @ OUT+: Vn1 + RS(In1) + VnRs (3)
where RS is the source resistance feeding the input, and VnRs is
the source resistance noise.
The noise at OUT− originates from a number of sources:
Voltage Noise @ OUT− due to Vn1: n1
g
f
n1 V
R
R
V
(4)
Voltage Noise @ OUT− due to In1:
11 n
S
g
f
n
SIR
R
R
IR
(5)
Voltage Noise @ OUT− due to RS: nRs
g
f
nRs V
R
R
V
(6)
Voltage Noise @ OUT− due to VnRg: nRg
g
f
nRg V
R
R
V
(7)
Voltage Noise @ OUT− due to VnRf: VnRF (8)
Voltage Noise @ OUT− due toVn2: 2
21 n
g
f
n2 V
R
R
V
(9)
When looking at OUT− by itself, the contributing noise sources
are uncorrelated, and therefore, the total output noise is
calculated as the root-sum-square (rss) of the individual
contributors. When looking at the differential output noise, the
noise contributors are uncorrelated except for three, Vn1, RS(In1),
and VnRs, which are common noise sources for both outputs. It
can be seen from the previous results that the output noise due
to Vn1, RS(In1), and VnRs each appear at OUT+ with a gain of +1
and at OUT− with a gain of −1. This produces a gain of 2 for each
of these three sources at the differential output.
The total differential output noise density is calculated as
Von, dm =
2
22 4HznV/3.22)HzpA/(1.42 n
nRs
sn VVRV (10)
where Vn1 = Vn2
Vn = 3.9 nV/√Hz; the input referred voltage
noise of each amplifier is the same.
The output noise due to the amplifier alone is calculated by
setting RS and VnRs equal to zero. In this case:
Von, dm = 12 nV/√Hz (11)
Clearly, the output noise is not balanced between the outputs,
but this is not an issue in most applications.
USING THE REF PIN
The REF pin sets the output baseline in the inverting path and
is used as a reference for the input signal. In most applications,
the REF pin is set to the input signal midswing level, which in
many cases is also midsupply. For bipolar signals and power
supplies, REF is generally set to ground. In single-supply
applications, setting REF to the input signal midswing level
provides optimal output dynamic range performance with
minimum differential offset. Note that the REF input only
affects the inverting signal path, or OUT−.
Most applications require a differential output signal with the
same dc common-mode level on each output. It is possible for
the signal measured across OUT+ and OUT− to have a common-
mode voltage that is of the desired level but has different dc
levels at both outputs. Typically, this situation is avoided,
because it wastes the output dynamic range of the amplifier.
Data Sheet ADA4922-1
Rev. A | Page 17 of 19
Defining VIN as the voltage applied to the input pin, the
equations that govern the two signal paths are given in
Equation 12 and Equation 13.
VOUT+ = +VIN (12)
VOUT− = −VIN + 2(REF) (13)
When the REF voltage is set to the midswing level of the input
signal, the two output signals fall directly on top of each other
with minimal offset. Setting the REF voltage elsewhere results
in an offset between the two outputs. This effect is illustrated in
the Theory of Operation section.
The best use of the REF pin can be further illustrated by
considering a single-supply example that uses a 10 V dc power
supply and has an input signal that varies between 2 V and 7 V.
This is a case where the midswing level of the input signal is not
at midsupply but is at 4.5 V. By setting the REF input to 4.5 V
and neglecting offsets, Equation 12 and Equation 13 are used to
calculate the results. When the input signal is at its midpoint of
4.5 V, VOUT+ is at 4.5 V, as is VOUT−. This can be considered as a
type of baseline state where the differential output voltage is
zero. When the input increases to 7 V, VOUT+ tracks the input to
7 V and VOUT− decreases to 2 V. This can be viewed as a positive
peak signal where the differential output voltage equals 5 V.
When the input signal decreases to 2 V, VOUT+ again tracks to
2 V, and VOUT− increases to 7 V. This can be viewed as a negative
peak signal where the differential output voltage equals −5 V.
The resulting differential output voltage is 10 V p-p.
The previous discussion exposes how the single-ended-to-
differential gain of 2 is achieved.
INTERNAL FEEDBACK NETWORK POWER
DISSIPATION
While traditional op amps do not have on-chip feedback
elements, the ADA4922-1 contains two on-chip 600 Ω resistors
that comprise an internal feedback loop. The power dissipated
in these resistors must be included in the overall power dissipation
calculations for the device. Under certain circumstances, the
power dissipated in these resistors could be considerably more
than the quiescent current of the device. For example, on ±12 V
supplies with the REF pin tied to ground and OUT− at 9 V dc,
each 600 Ω resistor carries 15 mA and dissipates 135 mW. This
is a significant amount of power and must therefore be included
in the overall device power dissipation calculations. For ac
signals, rms analysis is required.
DISABLE FEATURE
The ADA4922-1 includes a disable feature that can be asserted
to minimize power consumption in a device that is not needed
at a particular time. When asserted, the disable feature does not
place the device output in a high impedance or three-state
condition. The disable feature is asserted by applying a control
voltage to the DIS pin and is active low. See the Specifications
section for the high and low level voltage specifications.
DRIVING A DIFFERENTIAL INPUT ADC
The ADA4922-1 provides the single-ended-to-differential
conversion that is required to drive most high resolution ADCs.
Figure 50 shows how the ADA4922-1 simplifies ADC driving.
V
IN
10V
0.1F
–12V
HIGH VOLTAGE
HIGH RESOLUTION
ADC
V
S–
V
S+
DIS
05681-049
R
R
IN8OUT+
ADA4922-1
OUT–
4
5
6
73
REF2
0.1F
–12V
0.1F
+12
V
0.1F
+12V
R
R
C
C
Figure 50. Driving a Differential Input ADC
For example, consider the case where the input signal
bandwidth is 100 kHz and R = 41.2 Ω and C = 3.9 nF, as is
shown in Figure 50, to form a single-pole filter with −3 dB
bandwidth of approximately 1 MHz. The ADA4922-1 output
noise (with zero source resistance) integrated over this
bandwidth appears at the ADC input and is calculated as
rmsμV15MHz1
2
π
HznV/12)(
,
rmsV dmADCn, (14)
The rms value of a 20 V p-p signal at the ADC input is 7 V rms,
yielding a SNR of 113 dB at the ADC input.
ADA4922-1 Data Sheet
Rev. A | Page 18 of 19
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Although the ADA4922-1 is used in many applications
involving frequencies that are well below 1 MHz, some general
high speed layout practices must be adhered to because it is a
high speed amplifier. Controlled impedance transmission lines
are not required for low frequency signals, provided the signal
rise times are longer than approximately 5 times the electrical
delay of the interconnections. For reference, typical 50 Ω
transmission lines on FR-4 material exhibit approximately
140 ps/in delay on outer layers and 180 ps/in for inner layers.
Most connections between the ADA4922-1 and the ADC can
be kept very short.
Place broadband power supply decoupling networks as close as
possible to the supply pins. Small surface-mount ceramic
capacitors are recommended for these networks, and tantalum
capacitors are recommended for bulk supply decoupling.
Data Sheet ADA4922-1
Rev. A | Page 19 of 19
OUTLINE DIMENSIONS
COM P LI ANT TO JE DEC STANDARDS MS-0 12-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 MAX
0.05 NOM
3.81 RE F
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BS C
S
EATING
PLANE
FOR PROPER CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P I N CO NFI G URATI O N AND
FUNCT IO N DES CRI P TI O NS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VI EW
0.51
0.31
1.65
1.25
Figure 51. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN1
INDICATOR
(R0.15)
Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option Branding
ADA4922-1ARDZ –40°C to +85°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4922-1ARDZ-RL –40°C to +85°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4922-1ACPZ-R2 –40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 HUB
ADA4922-1ACPZ-RL7 –40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 HUB
ADA4922-1ACP-EBZ Evaluation Board
1 Z = RoHS-Compliant Part.
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05681-0-5/16(A)
