UPI-41AH/42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER Y UPI-41: 6 MHz; UPI-42: 12.5 MHz Y Y Pin, Software and Architecturally Compatible with all UPI-41 and UPI-42 Products Fully Compatible with all Intel and Most Other Microprocessor Families Y Interchangeable ROM and OTP EPROM Versions Y Expandable I/O Y Sync Mode Available Y Over 90 Instructions: 70% Single Byte Y Available in EXPRESS Standard Temperature Range Y inteligent Programming Algorithm Fast OTP Programming Y Available in 40-Lead Plastic and 44Lead Plastic Leaded Chip Carrier Packages Y Y Y Y 8-Bit CPU plus ROM/OTP EPROM, RAM, I/O, Timer/Counter and Clock in a Single Package 2048 x 8 ROM/OTP, 256 x 8 RAM on UPI-42, 1024 x 8 ROM/OTP, 128 x 8 RAM on UPI-41, 8-Bit Timer/Counter, 18 Programmable I/O Pins One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface DMA, Interrupt, or Polled Operation Supported (See Packaging Spec., Order Y240800-001) Package Type P and N The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer to develop customized solutions for peripheral device control. They are essentially ``slave'' microcontrollers, or microcontrollers with a slave interface included on the chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems. To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM (OTP). All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to production level designs. 210393 - 2 Figure 1. DIP Pin Configuration 210393 - 3 Figure 2. PLCC Pin Configuration November 1994 Order Number: 210393-008 UPI-41AH/42AH 210393 - 1 Figure 3. Block Diagram UPI PRODUCT MATRIX UPI Device ROM OTP EPROM RAM Programming Voltage 8042AH 2K 256 8242AH 2K 256 8742AH 2K 256 12.5V 8041AH 1K 128 8741AH 1K 128 12.5V THE INTEL 8242 As shown in the UPI-42 product matrix, the UPI-42 will be offered as a pre-programmed 8042 with several software vendors' keyboard controller firmware. The current list of available 8242 versions include keyboard controller firmware from both Phoenix Technologies Ltd., IBM, and Award Software Inc. The 8242 is programmed with Phoenix Technologies Ltd. keyboard controller firmware for AT-compatible systems. This keyboard controller is fully compatible with all AT-compatible operating systems and applications. The 8242PC also contains Phoenix Technologies Ltd. firmware. This keyboard controller provides support for AT, PS/2 and most EISA platforms as well as PS/2-style mouse support for either AT or PS/2 platforms. The Intel 8242BB is programmed with IBM's keyboard controller firmware. The 8242BB provides an off the shelf keyboard and auxiliary device controller for AT, PS/2, EISA, and PCI architectures. The 8242WA contains Award Software Inc. firmware. This device provides at AT-compatible keyboard controller for use in IBM PC AT compatible computers. The 8242WB contains a version of Award Software Inc. firmware that provides PS/2 style mouse support in addition to the standard features of the 8242WA. *Contact factory for current code revision available in all versions of the 8242 product lines. 2 UPI-41AH/42AH Table 1. Pin Description Symbol DIP Pin No. PLCC Pin Type No. TEST 0, TEST 1 1 39 2 43 I TEST INPUTS: Input pins which can be directly tested using conditional branch instructions. FREQUENCY REFERENCE: TEST 1 (T1) also functions as the event timer input (under software control). TEST 0 (T0) is used during PROM programming and ROM/EPROM verification. It is also used during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1. See the Sync Mode Section. XTAL 1, XTAL 2 2 3 3 4 I INPUTS: Inputs for a crystal, LC or an external timing signal to determine the internal oscillator frequency. RESET 4 5 I RESET: Input used to reset status flip-flops and to set the program counter to zero. RESET is also used during EPROM programming and verification. SS 5 6 I SINGLE STEP: Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM). This should be tied to a 5V when not used. This pin is also used to put the device in Sync Mode by applying 12.5V to it. CS 6 7 I CHIP SELECT: Chip select input used to select one UPI microcomputer out of several connected to a common data bus. EA 7 8 I EXTERNAL ACCESS: External access input which allows emulation, testing and ROM/EPROM verification. This pin should be tied low if unused. RD 8 9 I READ: I/O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register. A0 9 10 I COMMAND/DATA SELECT: Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0, F1 is reset) or command (A0 e 1, F1 is set). A0 e 0 during program and verify operations. WR 10 11 I WRITE: I/O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER. SYNC 11 13 O OUTPUT CLOCK: Output signal which occurs once per UPI instruction cycle. SYNC can be used as a strobe for external circuitry; it is also used to synchronize single step operation. Name and Function 12 - 19 14- 21 I/O DATA BUS: Three-state, bidirectional DATA BUS BUFFER lines used to interface the UPI microcomputer to an 8-bit master system data bus. P10 - P17 27 - 34 30- 33 35- 38 I/O PORT 1: 8-bit, PORT 1 quasi-bidirectional I/O lines. P10 -P17 access the signature row and security bit. P20 - P27 21 - 24 24- 27 35 - 38 39- 42 I/O PORT 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits (P20 -P23) interface directly to the 8243 I/O expander device and contain address and data information during PORT 4-7 access. The upper 4 bits (P24 -P27) can be programmed to provide interrupt Request and DMA Handshake capability. Software control can configure P24 as Output Buffer Full (OBF) interrupt, P25 as Input Buffer Full (IBF) interrupt, P26 as DMA Request (DRQ), and P27 as DMA ACKnowledge (DACK). PROG 25 28 I/O PROGRAM: Multifunction pin used as the program pulse input during PROM programming. During I/O expander access the PROG pin acts as an address/data strobe to the 8243. This pin should be tied high if unused. VCC 40 44 POWER: a 5V main power supply pin. VDD 26 29 POWER: a 5V during normal operation. a 12.5V during programming operation. Low power standby supply pin. VSS 20 22 GROUND: Circuit ground potential. D0 - D7 (BUS) 3 UPI-41AH/42AH UPI-41AH and UPI-42AH FEATURES 1. Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave protocol. During the time that the host CPU is reading the status register, the UPI is prevented from updating this register or is `locked out.' 4. P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master processor. These pins default to port pins on Reset. If the ``EN FLAGS'' instruction has been executed, P24 becomes the OBF (Output Buffer Full) pin. A ``1'' written to P24 enables the OBF pin (the pin outputs the OBF Status Bit). A ``0'' written to P24 disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is available from the UPI (in Output Data Bus Buffer). 210393 - 4 2. 8 Bits of Status If ``EN FLAGS'' has been executed, P25 becomes the IBF (Input Buffer Full) pin. A ``1'' written to P25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit. A ``0'' written to P25 disables the IBF pin (the pin remains low). This pin can be used to indicate that the UPI is ready for data. ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 -ST7 are user definable status bits. These bits are defined by the ``MOV STS, A'' single byte, single cycle instruction. Bits 4-7 of the acccumulator are moved to bits 4-7 of the status register. Bits 0-3 of the status register are not affected. MOV STS, A Op Code: 90H 210393 - 5 1 0 0 1 0 0 0 0 D7 D0 3. RD and WR are edge triggered. IBF, OBF, F1 and INT change internally after the trailing edge of RD or WR. Data Bus Buffer Interrupt Capability EN FLAGS 1 D7 210393 - 6 4 1 Op Code: 0F5H 1 1 0 1 0 1 D0 UPI-41AH/42AH 5. P26 and P27 are port pins or DMA handshake pins for use with a DMA controller. These pins default to port pins on Reset. If the ``EN DMA'' instruction has been executed, P26 becomes the DRQ (DMA Request) pin. A ``1'' written to P26 causes a DMA request (DRQ is activated). DRQ is deactivated by DACK # RD, DACK # WR, or execution of the ``EN DMA'' instruction. If ``EN DMA'' has been executed, P27 becomes the DACK (DMA ACKnowledge) pin. This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers. 210393 - 8 Figure 5. 8088-UPI-41AH/42AH Interface 210393 - 7 DMA Handshake Capability EN DMA 1 210393 - 10 Figure 6. 8048H-UPI-41/42 Interface Op Code: 0E5H 1 1 0 0 1 0 1 D7 D0 6. When EA is enabled on the UPI, the program counter is placed on Port 1 and the lower three bits of Port 2 (MSB e P22, LSB e P10). On the UPI this information is multiplexed with PORT DATA (see port timing diagrams at end of this data sheet). 7. The 8741AH and 8742AH support the inteligent Programming Algorithm. (See the Programming Section.) 210393 - 9 Figure 7. UPI-41/42-8243 Keyboard Scanner APPLICATIONS 210393 - 30 Figure 4. UPI-41AH/42AH Keyboard Controller 5 UPI-41AH/42AH The Program/Verify sequence is: 1. CS e 5V, VCC e 5V, VDD e 5V, RESET e 0V, A0 e 0V, TEST 0 e 5V, clock applied or internal oscillator operating, BUS floating, PROG e 5V. 2. Insert 8741AH or 8742AH in programming socket 3. TEST 0 e 0V (select program mode) 4. EA e 12.5V (active program mode) 5. VCC e 6V (programming supply) 6. VDD e 12.5V (programming power) 7. Address applied to BUS and P20-22 8. RESET e 5V (latch address) 9. Data applied to BUS 10. PROG e 5V followed by one 1 ms pulse to 0V 11.TEST 0 e 5V (verify mode) 210393 - 11 Figure 8. UPI-41AH/42AH 80-Column Matrix Printer Interface PROGRAMMING AND VERIFYING THE 8741AH AND 8742AH OTP EPROM Programming Verification In brief, the programming process consists of: activating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. Each word is programmed completely before moving on to the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions: Pin Function XTAL 1 2 Clock Inputs Reset Initialization and Address Latching Test 0 Selection of Program or Verify Mode EA Activation of Program/Verify Signature Row/Security Bit Modes BUS Address and Data Input Data Output During Verify P20-22 Address Input VDD Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a missocketed 8741AH or 8742AH will result in severe damage to the part. An indication of a properly socketed part is the appearance of the SYNC clock output. The lack of this clock may be used to disable the programmer. 6 12. Read and verify data on BUS 13. TEST 0 e 0V 14. Apply overprogram pulse 15. RESET e 0V and repeat from step 6 16. Programmer should be at conditions of step 1 when 8741AH or 8742AH is removed from socket Please follow the inteligent Programming flow chart for proper programming procedure. inteligent Programming Algorithm The inteligent Programming Algorithm rapidly programs Intel 8741AH/8742AH EPROMs using an efficient and reliable method particularly suited to the production programming environment. Typical programming time for individual devices is on the order of 10 seconds. Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. A flowchart of the 8741AH/8742AH inteligent Programming Algorithm is shown in Figure 9. The inteligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial PROG pulse(s) is one millisecond, which will then be followed by a longer overprogram pulse of length 3X msec. X is an iteration counter and is equal to the number of the initial one millisecond pulses applied to a particular 8741AH/ 8742AH location, before a correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram pulse is applied. UPI-41AH/42AH 210393 - 12 Figure 9. Programming Algorithm 7 UPI-41AH/42AH The entire sequence of program pulses and byte verifications is performed at VCC e 6.0V and VDD e 12.5V. When the inteligent Programming cycle has been completed, all bytes should be compared to the original data with VCC e 5.0, VDD e 5V. Verify A verify should be performed on the programmed bits to determine that they have been correctly programmed. The verify is performed with T0 e 5V, VDD e 5V, EA e 12.5V, SS e 5V, PROG e 5V, A0 e 0V, and CS e 5V. SECURITY BIT The security bit is a single EPROM cell outside the EPROM array. The user can program this bit with the appropriate access code and the normal programming procedure, to inhibit any external access to the EPROM contents. Thus the user's resident program is protected. There is no direct external access to this bit. However, the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not. The security bit has no effect on the signature mode, so the security byte can always be examined. SECURITY BIT PROGRAMMING/ VERIFICATION Programming a. Read the security byte of the signature mode. Make sure it is 00H. 8 b. Apply access code to appropriate inputs to put the device into security mode. c. Apply high voltage to EA and VDD pins. d. Follow the programming procedure as per the inteligent Programming Algorithm with known data on the databus. Not only the security bit, but also the security byte of the signature row is programmed. e. Verify that the security byte of the signature mode contains the same data as appeared on the data bus. (If DB0 - DB7 e high, the security byte will contain FFH.) f. Read two consecutive known bytes from the EPROM array and verify that the wrong data are retrieved in at least one verification. If the EPROM can still be read, the security bit may have not been fully programmed though the security byte in the signature mode has. Verification Since the security bit address overlaps the address of the security byte of the signature mode, it can be used to check indirectly whether the security bit has been programmed or not. Therefore, the security bit verification is a mere read operation of the security byte of the signature row (0FFH e security bit programmed; 00H e security bit unprogrammed). Note that during the security bit programming, the reading of the security byte does not necessarily indicate that the security bit has been successfully programmed. Thus, it is recommended that two consecutive known bytes in the EPROM array be read and the wrong data should be read at least once, because it is highly improbable that random data coincides with the correct ones twice. UPI-41AH/42AH SIGNATURE MODE The UPI-41AH/42AH has an additional 32 bytes of EPROM available for Intel and user signatures and miscellaneous purposes. The 32 bytes are partitioned as follows: A. Test code/checksumThis can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory. The test code/checksum is present on ROMs, and OTPs. B. Intel signatureThis allows the programmer to read from the UPI-41AH/42AH the manufacturer of the device and the exact product name. It facilitates automatic device identification and will be present in the ROM and OTP versions. Location 10H contains the manufacturer code. For Intel, it is 89H. Location 11H contains the device code. The code is 43H and 42H for the 8042AH and OTP 8742AH, and 41H and 40H for the 8041AH and OTP 8741AH, respectively. The code is 44H for any device with the security bit set by Intel. C. User signatureThe user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signature code (for identification purposes and quick sorting of previously programmed materials). D. Test signatureThis memory is used to store testing information such as: test data, bin number, etc. (for use in quality and manufacturing control). E. Security byteThis byte is used to check whether the security bit has been programmed (see the security bit section). The signature mode can be accessed by setting P10 e 0, P11 - P17 e 1, and then following the programming and/or verification procedures. The location of the various address partitions are as follows: Address Device Type No. of Bytes 25 Test Code/Checksum 0 16H 0FH 1EH ROM/OTP Intel Signature 10H 11H ROM/OTP 2 User Signature 12H 13H OTP 2 Test Signature 14H 15H ROM/OTP 2 Security Byte 1FH OTP 1 9 UPI-41AH/42AH SYNC MODE The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time. The Sync Mode may also be utilized by automatic test equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the DUT (device under test). Sync Mode is enabled when SS pin is raised to high voltage level of a 12 volts. To begin synchronization, T0 is raised to 5 volts at least four clock cycles after SS. T0 must be high for at least four X1 clock cycles to fully reset the prescaler and time state generators. T0 may then be brought down during low state of X1. Two clock cycles later, with the rising edge of X1, the device enters into Time State 1, Phase 1. SS is then brought down to 5 volts 4 clocks later after T0. RESET is allowed to go high 5 tCY (75 clocks) later for normal execution of code. SYNC MODE TIMING DIAGRAMS 210393 - 28 Minimum Specifications SYNC Operation Time, tSYNC e 3.5 XTAL 1 Clock cycles. Reset Time, tRS e 4 tCY. NOTE: The rising and falling edges of T0 should occur during low state of XTAL1 clock. 10 UPI-41AH/42AH ACCESS CODE The following table summarizes the access codes required to invoke the Sync Mode, Signature Mode, and the Security Bit, respectively. Also, the programming and verification modes are included for comparison. Control Signals Modes Access Code Data Bus T0 RST SS EA PROG VDD VCC 0 1 2 3 4 Port 2 5 6 7 Programming Mode 0 0 1 HV 1 VDDH VCC Address Addr 0 1 1 HV STB VDDH VCC Data In Addr Verification Mode 0 0 1 HV 1 VCC VCC Address Addr 1 1 1 HV 1 VCC VCC Data Out Addr Sync Mode STB High 0 X VCC VCC X Signature Prog Mode 0 0 1 HV 1 VDDH VCC Addr. (see Sig Mode Table) 0 1 1 HV STB VDDH VCC Data In Verify 0 0 1 HV 1 VCC VCC Addr. (see Sig Mode Table) 0 0 0 1 1 1 HV 1 VCC VCC Data Out 0 0 0 0 0 1 HV 1 VDDH VCC Address 0 0 0 0 1 1 HV STB VDDH VCC Data In 0 0 0 0 0 1 HV 1 VCC VCC Address 0 0 0 1 1 1 HV 1 VCC VCC Data Out 0 0 0 Security Bit/Byte Prog Verify HV 0 X X X X X X Port 1 0 1 2 0 1 2 3 4 5 6 7 a0 a1 X X X X X X a0 a1 X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X 1 0 0 0 NOTES: 1. a0 e 0 or 1; a1 e 0 or 1. a0 must e a1. ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias AAAA0 C to a 70 C Storage Temperature AAAAAAAAAA b 65 C to a 150 C Voltage on Any Pin with Respect to GroundAAAAAAAAAAAAAA b 0.5V to a 7V Power Dissipation AAAAAAAAAAAAAAAAAAAAAAAAA1.5 W D.C. CHARACTERISTICS Symbol NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. TA e 0 C to a 70 C, VCC e VDD e a 5V g 10% Parameter UPI-41AH/42AH Units Min Max Input Low Voltage (Except XTAL1, XTAL2, RESET) b 0.5 0.8 V VIL1 Input Low Voltage (XTAL1, XTAL2, RESET) b 0.5 0.6 V VIH Input High Voltage (Except XTAL1, XTAL2, RESET) 2.0 VCC V VIH1 Input High Voltage (XTAL1, RESET) 3.5 VCC V VIH2 Input High Voltage (XTAL2) 2.2 VCC V VOL Output Low Voltage (D0 -D7) 0.45 V VIL Notes IOL e 2.0 mA 11 UPI-41AH/42AH D.C. CHARACTERISTICS Symbol TA e 0 C to a 70 C, VCC e VDD e a 5V g 10% (Continued) Parameter UPI-41AH/42AH Min Units Notes Max VOL1 Output Low Voltage (P10P17, P20P27, Sync) 0.45 V IOL e 1.6 mA VOL2 Output Low Voltage (PROG) 0.45 V IOL e 1.0 mA VOH Output High Voltage (D0 -D7) 2.4 VOH1 Output High Voltage (All Other Outputs) 2.4 IIL Input Leakage Current (T0, T1, RD, WR, CS, A0, EA) g 10 mA VSS s VIN s VCC IOFL Output Leakage Current (D0 -D7, High Z State) g 10 mA VSS a 0.45 s VOUT s VCC ILI Low Input Load Current (P10P17, P20P27) 0.3 mA VIL e 0.8V ILI1 Low Input Load Current (RESET, SS) 0.2 mA VIL e 0.8V IDD VDD Supply Current 20 mA Typical e 8 mA ICC a IDD Total Supply Current 135 mA Typical e 80 mA IDD Standby Power Down Supply Current 20 mA Typical e 8 mA IIH Input Leakage Current (P10 -P17, P20 -P27) 100 mA VIN e VCC CIN Input Capacitance 10 pF TA e 25 C (1) CIO I/O Capacitance 20 pF TA e 25 C (1) V IOH e b 400 mA IOH e b 50 mA NOTE: 1. Sampled, not 100% tested. D.C. CHARACTERISTICSPROGRAMMING TA e 25 C g 5 C, VCC e 6V g 0.25V, VDD e 12.5V g 0.5V Symbol Parameter Min Max Units 12 13 V(1) 4.75 5.25 V V VDDH VDD Program Voltage High Level VDDL VDD Voltage Low Level VPH PROG Program Voltage High Level 2.0 5.5 VPL PROG Voltage Low Level b 0.5 0.8 V VEAH Input High Voltage for EA 12.0 13.0 V(2) VEAL EA Voltage Low Level b 0.5 5.25 V IDD VDD High Voltage Supply Current 50.0 mA IEA EA High Voltage Supply Current 1.0 mA NOTES: 1. Voltages over 13V applied to pin VDD will permanently damage the device. 2. VEAH must be applied to EA before VDDH and removed after VDDL. 3. VCC must be applied simultaneously or before VDD and must be removed simultaneously or after VDD. 12 UPI-41AH/42AH A.C. CHARACTERISTICS TA e 0 C to a 70 C, VSS e 0V, VCC e VDD e a 5V g 10% DBB READ Symbol Parameter Min tRA v CS, A0 Hold After RDu tRR RD Pulse Width tAD CS, A0 to Data Out Delay tRD RD tAR CS, A0 Setup to RD tDF Max 0 Units ns 0 ns 160 ns v to Data Out Delay RDu to Data Float Delay 0 Parameter Min 130 ns 130 ns 85 ns Max Units DBB WRITE Symbol v u tAW CS, A0 Setup to WR tWA CS, A0 Hold After WR tWW tDW Data Setup to WR tWD 0 ns 0 ns WR Pulse Width 160 ns u Data Hold After WRu 130 ns 0 ns CLOCK Symbol Parameter Min Max Units tCY (UPI-41AH/42AH) Cycle Time 1.2 9.20 ms(1) tCYC (UPI-41AH/42AH) Clock Period 80 613 ns tPWH Clock High Time 30 ns tPWL Clock Low Time 30 ns tR Clock Rise Time 10 ns tF Clock Fall Time 10 ns NOTE: 1. tCY e 15/f(XTAL) A.C. CHARACTERISTICS Symbol DMA Parameter Min tACC DACK to WR or RD tCAC RD or WR to DACK 0 tACD DACK to Data Valid 0 tCRQ RD or WR to DRQ Cleared Max 0 Units ns ns 130 ns 110 ns(1) NOTE: 1. CL e 150 pF. 13 UPI-41AH/42AH A.C. CHARACTERISTICSPROGRAMMING TA e 25 C g 5 C, VCC e 6V g 0.25V, VDDL e a 5V g 0.25V, VDDH e 12.5V g 0.5V (8741AH/8742AH ONLY) Symbol Parameter Min Max Units 1.05 ms(1) 4tCY tWD u Address Hold Time After RESETu Data in Setup Time to PROGv Data in Hold Time After PROGu tPW Initial Program Pulse Width 0.95 tTW Test 0 Setup Time for Program Mode 4tCY tWT Test 0 Hold Time After Program Mode 4tCY tDO Test 0 to Data Out Delay tWW RESET Pulse Width to Latch Address tr, tf PROG Rise and Fall Times 0.5 100 ms tCY CPU Operation Cycle Time 2.5 3.75 ms tRE RESET Setup Time Before EA tOPW Overprogram Pulse Width 2.85 78.75 ms(2) tDE EA High to VDD High 1tCY tAW Address Setup Time to RESET tWA tDW 4tCY 4tCY 4tCY 4tCY u 4tCY 4tCY NOTES: 1. Typical Initial Program Pulse width tolerance e 1 ms g 5%. 2. This variation is a function of the iteration counter value, X. 3. If TEST 0 is high, tDO can be triggered by RESETu. A.C. CHARACTERISTICS PORT 2 TA e 0 C to a 70 C, VCC e a 5V g 10% Parameter f(tCY)(3) Min tCP Port Control Setup Before Falling Edge of PROG 1/15 tCY b 28 55 ns(1) tPC Port Control Hold After Falling Edge of PROG 1/10 tCY 125 ns(2) Symbol tPR PROG to Time P2 Input Must Be Valid tPF Input Data Hold Time tDP Output Data Setup Time 2/10 tCY tPD Output Data Hold Time tPP PROG Pulse Width NOTES: 1. CL e 80 pF. 2. CL e 20 pF. 3. tCY e 1.25 ms. 14 8/15 tCY b 16 0 Max Units 650 ns(1) 150 ns(2) 250 ns(1) 1/10 tCY b 80 45 ns(2) 6/10 tCY 750 ns UPI-41AH/42AH A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT INPUT/OUTPUT 210393 - 14 210393 - 15 DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS l 6 MHz 210393 - 16 210393 - 17 Rise and Fall Times Should Not Exceed 10 ns. Resistors to VCC are Needed to Ensure VIH e 3.5V if TTL Circuitry is Used. LC OSCILLATOR MODE L C NOMINAL 45 H 20 pF 5.2 MHz 120 H 20 pF 3.2 MHz CRYSTAL OSCILLATOR MODE fe 1 2q0LCE CE e C a 3Cpp 2 Cpp j 5- 10 pF Pin-to-Pin Capacitance 210393 - 18 Each C Should be Approximately 20 pF, including Stray Capacitance. C1 C2 C3 210393 - 19 5 pF (STRAY 5 pF) (CRYSTAL a STRAY) 8 pF 20 - 30 pF INCLUDING STRAY Crystal Series Resistance Should be Less Than 30X at 12.5 MHz. 15 UPI-41AH/42AH WAVEFORMS READ OPERATIONDATA BUS BUFFER REGISTER 210393 - 20 WRITE OPERATIONDATA BUS BUFFER REGISTER 210393 - 21 CLOCK TIMING 210393 - 22 16 UPI-41AH/42AH WAVEFORMS (Continued) COMBINATION PROGRAM/VERIFY MODE 210393 - 23 NOTES: 1. A0 must be held low (0V) during program/verify modes. 2. For VIH, VIH1, VIL, VIL1, VDDH, and VDDL, please consult the D.C. Characteristics Table. 3. When programming the 8741AH/8742AH, a 0.1 mF capacitor is required across VDD and ground to suppress spurious voltage transients which can damage the device. VERIFY MODE 210393 - 29 NOTES: 1. PROG must float if EA is low. 2. PROG must float or e 5V when EA is high. 3. P10 - P17 e 5V or must float. 4. P24 - P27 e 5V or must float. 5. A0 must be held low during programming/verify modes. 17 UPI-41AH/42AH WAVEFORMS (Continued) DMA 210393 - 25 PORT 2 210393 - 26 PORT TIMING DURING EXTERNAL ACCESS (EA) 210393 - 27 On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync the Program Counter Contents are Available. 18 UPI-41AH/42AH Table 2. UPI Instruction Set Mnemonic Description ACCUMULATOR ADD A, Rr Add register to A Add data memory ADD A, @ Rr to A Add immediate to A ADD A, Ydata ADDC A, Rr Add register to A with carry Add data memory ADDC A, @ Rr to A with carry ADDC A, Ydata Add immediate to A with carry ANL A, Rr AND register to A AND data memory ANL, A @ Rr to A ANL A, Ydata AND immediate to A ORL A, Rr OR register to A OR data memory ORL, A, @ Rr to A OR immediate to A ORL A, Ydata XRL A, Rr Exclusive OR register to A Exclusive OR data XRL A, @ Rr memory to A Exclusive OR immeXRL A, Ydata diate to A INC A Increment A DEC A Decrement A CLR A Clear A CPL A Complement A DA A Decimal Adjust A SWAP A Swap nibbles of A RL A Rotate A left RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry INPUT/OUTPUT IN A, Pp Input port to A OUTL Pp, A Output A to port ANL Pp, Ydata AND immediate to port ORL Pp, Ydata OR immediate to port IN A, DBB Input DBB to A, clear IBF OUT DBB, A Output A to DBB, set OBF MOV STS, A A4 - A7 to Bits 4-7 of Status MOVD A, Pp Input Expander port to A MOVD Pp, A Output A to Expander port ANLD Pp, A AND A to Expander port ORLD Pp, A OR A to Expander port Bytes Cycles Mnemonic 1 1 1 1 DATA MOVES MOV A, Rr MOV A, @ Rr 2 1 2 1 1 1 2 2 1 1 1 1 2 1 1 2 1 1 2 1 2 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 2 1 2 1 2 1 2 MOV A, Ydata MOV Rr, A MOV @ Rr, A MOV Rr, Ydata MOV @ Rr, Ydata MOV A, PSW MOV PSW, A XCH A, Rr XCH A, @ Rr XCHD A, @ Rr MOVP A, @A MOVP3, A, @A Description Bytes Cycles Move register to A Move data memory to A Move immediate to A Move A to register Move A to data memory Move immediate to register Move immediate to data memory Move PSW to A Move A to PSW Exchange A and register Exchange A and data memory Exchange digit of A and register Move to A from current page Move to A from page 3 1 1 1 1 2 1 1 2 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Enable DMA Handshake Lines Enable IBF Interrupt 1 1 1 1 Diable IBF Interrupt Enable Master Interrupts Select register bank 0 Select register bank 1 No Operation 1 1 1 1 1 1 1 1 1 1 Increment register Increment data memory Decrement register 1 1 1 1 1 1 TIMER/COUNTER MOV A, T Read Timer/Counter MOV T, A Load Timer/Counter STRT T Start Timer STRT CNT Start Counter STOP TCNT Stop Timer/Counter EN TCNTI Enable Timer/ Counter Interrupt DIS TCNTI Disable Timer/ Counter Interrupt CONTROL EN DMA EN I DIS I EN FLAGS SEL RB0 SEL RB1 NOP REGISTERS INC Rr INC @ Rr DEC Rr 19 UPI-41AH/42AH Table 2. UPI Instruction Set (Continued) Mnemonic SUBROUTINE CALL addr RET RETR FLAGS CLR C CPL C CLR F0 CPL F0 CLR F1 CPL F1 BRANCH JMP addr JMPP @ A DJNZ Rr, addr JC addr JNC addr JZ addr JNZ addr JT0 addr JNT0 addr JT1 addr JNT1 addr JF0 addr JF1 addr JTF addr JNIBF addr JOBF addr JBb addr Description Bytes Cycles Jump to subroutine Return Return and restore status 2 1 1 2 2 2 Clear Carry Complement Carry Clear Flag 0 Complement Flag 0 Clear F1 Flag Complement F1 Flag 1 1 1 1 1 1 1 1 1 1 1 1 Jump unconditional Jump indirect Decrement register and jump Jump on Carry e 1 Jump on Carry e 0 Jump on A Zero Jump on A not Zero Jump on T0 e 1 Jump on T0 e 0 Jump on T1 e 1 Jump on T1 e 0 Jump on F0 Flag e 1 Jump on F1 Flag e 1 Jump on Timer Flag e 1, Clear Flag Jump on IBF Flag e0 Jump on OBF Flag e1 Jump on Accumulafor Bit 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000 INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511 Printed in U.S.A./xxxx/1196/B10M/xx xx