IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 1Document Number: 91280
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Power MOSFET
FEATURES
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Surface Mount (IRFR9120, SiHFR9120)
Straight Lead (IRFU9120, SiHFU9120)
Available in Tape and Reel
•P-Channel
Fast Switching
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effictiveness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU, SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 25 V, starting TJ = 25 °C, L = 10 mH, Rg = 25 , IAS = - 5.6 A (see fig. 12).
c. ISD - 6.8 A, dI/dt 110 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
PRODUCT SUMMARY
VDS (V) - 100
RDS(on) ()V
GS = - 10 V 0.60
Qg (Max.) (nC) 18
Qgs (nC) 3.0
Qgd (nC) 9.0
Configuration Single
S
G
D
P-Channel MOSFET
DPAK
(TO-252)
IPAK
(TO-251)
GDS
S
D
G
D
ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
Lead (Pb)-free and Halogen-free SiHFR9120-GE3 SiHFR9120TR-GE3aSiHFR9120TRL-GE3aSiHFU9120-GE3
Lead (Pb)-free IRFR9120PbF IRFR9120TRPbFa IRFR9120TRLPbFa IRFU9120PbF
SiHFR9120-E3 SiHFR9120T-E3aSiHFR9120TL-E3aSiHFU9120-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 100 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at - 10 V TC = 25 °C ID
- 5.6
ATC = 100 °C - 3.6
Pulsed Drain CurrentaIDM - 22
Linear Derating Factor 0.33 W/°C
Linear Derating Factor (PCB Mount)e0.020
Single Pulse Avalanche EnergybEAS 210 mJ
Repetitive Avalanche CurrentaIAR - 5.6 A
Repetitive Avalanche EnergyaEAR 4.2 mJ
Maximum Power Dissipation TC = 25 °C PD
42 W
Maximum Power Dissipation (PCB Mount)eTA = 25 °C 2.5
Peak Diode Recovery dV/dtcdV/dt - 5.5 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature)dfor 10 s 260
IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 2Document Number: 91280
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - - 110
°C/W
Maximum Junction-to-Ambient
(PCB Mount)aRthJA --50
Maximum Junction-to-Case (Drain) RthJC --3.0
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 100 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.098 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 100 V, VGS = 0 V - - - 100 μA
VDS = - 80 V, VGS = 0 V, TJ = 125 °C - - - 500
Drain-Source On-State Resistance RDS(on) V
GS = - 10 V ID = - 3.4 Ab- - 0.60
Forward Transconductance gfs VDS = - 50 V, ID = - 3.4 A 1.5 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
- 390 -
pFOutput Capacitance Coss - 170 -
Reverse Transfer Capacitance Crss -45-
Total Gate Charge Qg
VGS = - 10 V ID = - 6.8 A, VDS = - 80 V,
see fig. 6 and 13b
--18
nC Gate-Source Charge Qgs --3.0
Gate-Drain Charge Qgd --9.0
Turn-On Delay Time td(on)
VDD = - 50 V, ID = - 6.8 A,
Rg = 18 , RD = 7.1 , see fig. 10b
-9.6-
ns
Rise Time tr -29-
Turn-Off Delay Time td(off) -21-
Fall Time tf -25-
Internal Drain Inductance LD
Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance LS-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--- 5.6
A
Pulsed Diode Forward CurrentaISM --- 22
Body Diode Voltage VSD TJ = 25 °C, IS = - 5.6 A, VGS = 0 Vb--- 6.3V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = - 6.8 A, dI/dt = 100 A/μsb- 100 200 ns
Body Diode Reverse Recovery Charge Qrr - 0.33 0.66 μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 3Document Number: 91280
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 4Document Number: 91280
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 5Document Number: 91280
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Pulse width 1 µs
Duty factor 0.1 %
R
D
V
GS
R
g
D.U.T.
- 10 V
+
-
V
DS
V
DD
VGS
10 %
90 %
VDS
td(on) trtd(off) tf
IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 6Document Number: 91280
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
R
g
I
AS
0.01 Ω
t
p
D.U.T
L
VDS
+
-V
DD
- 10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
QGS QGD
QG
VG
Charge
- 10 V
D.U.T.
- 3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
www.vishay.com Vishay Siliconix
S13-0167-Rev. C, 04-Feb-13 7Document Number: 91280
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91280.
P.W. Period
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Body diode forward
current
Driver gate drive
Inductor current
D = P.W.
Period
+
-
-
-
-
+
+
+
Peak Diode Recovery dV/dt Test Circuit
dV/dt controlled by Rg
D.U.T. - device under test
D.U.T.
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
Rg
Compliment N-Channel of D.U.T. for driver
VDD
ISD controlled by duty factor “D”
Note
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
VGS = - 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
VDD
Re-applied
voltage
Ripple 5 % ISD
Reverse
recovery
current
Package Information
www.vishay.com Vishay Siliconix
Revision: 16-May-16 1Document Number: 71197
For technical questions, contact: pmostechsupport@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TO-252AA Case Outline
Notes
Dimension L3 is for reference only.
L3
D
L4
L5
bb2
e1
E1
D1
C
A1
gage plane height (0.5 mm)
e
b3
E
C2
A
L
H
MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
A 2.18 2.38 0.086 0.094
A1 - 0.127 - 0.005
b 0.64 0.88 0.025 0.035
b2 0.76 1.14 0.030 0.045
b3 4.95 5.46 0.195 0.215
C 0.46 0.61 0.018 0.024
C2 0.46 0.89 0.018 0.035
D 5.97 6.22 0.235 0.245
D1 4.10 - 0.161 -
E 6.35 6.73 0.250 0.265
E1 4.32 - 0.170 -
H 9.40 10.41 0.370 0.410
e 2.28 BSC 0.090 BSC
e1 4.56 BSC 0.180 BSC
L 1.40 1.78 0.055 0.070
L3 0.89 1.27 0.035 0.050
L4 - 1.02 - 0.040
L5 1.01 1.52 0.040 0.060
ECN: T16-0236-Rev. P, 16-May-16
DWG: 5347
Document Number: 91362 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Base
metal
Plating b1, b3
(b, b2)
c1
(c)
Section B - B and C - C
D
A
c2
c
Lead tip
5
5
(Datum A)
Thermal PAD
E1
4
D1
View A - A
A1
A
A
C
Seating
plane
CC
BB
θ1
θ2
B
4
4
4
3
5
L1
L
L3
3 x b2
3 x b
3
b4
E
2 x e 0.010 C B
M
A
0.25
0.010 BA
0.25
L2
A
C
M
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -
A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265
b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -
b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC
b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380
b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090
b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050
c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060
c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'
c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'
D 5.97 6.22 0.235 0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Application Note 826
Vishay Siliconix
Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.420
(10.668)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.224
(5.690)
0.180
(4.572)
0.055
(1.397)
0.243
(6.180)
0.087
(2.202)
0.090
(2.286)
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Revision: 08-Feb-17 1Document Number: 91000
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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