LTC2376-20
1
237620fb
For more information www.linear.com/LTC2376-20
Typical applicaTion
FeaTures DescripTion
20-Bit, 250ksps, Low Power
SAR ADC with 0.5ppm INL
The LTC
®
2376-20 is a low noise, low power, high speed
20-bit successive approximation register (SAR) ADC. Op-
erating from a 2.5V supply, the LTC2376-20 has a ±VREF
fully differential input range with VREF ranging from 2.5V
to 5.1V. The LTC2376-20 consumes only 5.3mW and
achieves ±2ppm INL maximum, no missing codes at 20
bits with 104dB SNR.
The LTC2376-20 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 250ksps
throughput with no cycle latency makes the LTC2376-20
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2376-20 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
The LTC2376-20 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
Integral Nonlinearity vs Output Code
applicaTions
n 250ksps Throughput Rate
n ±0.5ppm INL (Typ)
n Guaranteed 20-Bit No Missing Codes
n Low Power: 5.3mW at 250ksps, 5.3µW at 250sps
n 104dB SNR (Typ) at fIN = 2kHz
n –125dB THD (Typ) at fIN = 2kHz
n Digital Gain Compression (DGC)
n Guaranteed Operation to 85°C
n 2.5V Supply
n Fully Differential Input Range ±VREF
n VREF Input Range from 2.5V to 5.1V
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
OUTPUT CODE
–524288 –262144 0 262144
524288
–2.0
INL ERROR (ppm)
0.5
1.0
1.5
0
–0.5
–1.0
–1.5
2.0
237620 TA02
10Ω
V
REF
0V
V
REF
0V 10Ω
3300pF
6800pF
6800pF
–
+
VREF
SAMPLE CLOCK
237620 TA01
10µF 0.1µF
2.5V
REF
1.8V TO 5V
2.5V TO 5.1V
47µF
(X7R, 1210 SIZE)
REF GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
REF/DGC
LTC2376-20
VDD OVDD
IN+
IN–
L, LT, LT C, LTM , Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents Pending. Protected by U.S. Patents, including
7705765, 7961132, 8319673.
LTC2376-20
2
237620fb
For more information www.linear.com/LTC2376-20
pin conFiguraTion
absoluTe MaxiMuM raTings
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF) ................................................. 6V
Analog Input Voltage (Note 3)
IN+, IN– .........................(GND – 0.3V) to (REF + 0.3V)
REF/DGC Input (Note 3) ....(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF/
DGC
TOP VIEW
DE PACKAGE
16-LEAD (4mm
×
3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF/
DGC
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2376CMS-20#PBF LTC2376CMS-20#TRPBF 237620 16-Lead Plastic MSOP 0°C to 70°C
LTC2376IMS-20#PBF LTC2376IMS-20#TRPBF 237620 16-Lead Plastic MSOP –40°C to 85°C
LTC2376CDE-20#PBF LTC2376CDE-20#TRPBF 23760 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2376IDE-20#PBF LTC2376IDE-20#TRPBF 23760 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Digital Output Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2376C ................................................ 0°C to 70°C
LTC2376I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
http://www.linear.com/product/LTC2376-20#orderinfo
LTC2376-20
3
237620fb
For more information www.linear.com/LTC2376-20
DynaMic accuracy
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2kHz, VREF = 5V l101 104 dB
SNR Signal-to-Noise Ratio fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
l
l
l
101
99
95.5
104
102
98
dB
dB
dB
THD Total Harmonic Distortion fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
l
l
l
–125
–125
–123
–115
–114
–113
dB
dB
dB
SFDR Spurious Free Dynamic Range fIN = 2kHz, VREF = 5V l115 128 dB
–3dB Input Bandwidth 34 MHz
Aperture Delay 500 ps
Aperture Jitter 4 ps
Transient Response Full-Scale Step 1 µs
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (IN+) (Note 5) l–0.1 VREF + 0.1 V
VIN– Absolute Input Range (IN–) (Note 5) l–0.1 VREF + 0.1 V
VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN–l–VREF +VREF V
VCM Common-Mode Input Range lVREF/2–
0.1
VREF/2 VREF/2+
0.1
V
IIN Analog Input Leakage Current 0.01 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
45
5
pF
pF
CMRR Input Common Mode Rejection Ratio fIN = 125kHz 86 dB
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
converTer characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l20 Bits
No Missing Codes l20 Bits
Transition Noise 2.3 ppmRMS
INL Integral Linearity Error (Note 6)
REF/DGC = GND, (Note 6)
l
l
–2
–2
±0.5
±0.5
2
2
ppm
ppm
DNL Differential Linearity Error (Note 10) l–0.5 ±0.2 0.5 ppm
BZE Bipolar Zero-Scale Error (Note 7) l–13 0 13 ppm
Bipolar Zero-Scale Error Drift ±7 ppb/°C
FSE Bipolar Full-Scale Error (Note 7) l–100 ±10 100 ppm
Bipolar Full-Scale Error Drift ±0.05 ppm/°C
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2376-20
4
237620fb
For more information www.linear.com/LTC2376-20
aDc TiMing characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l250 ksps
tCONV Conversion Time l2 3 µs
tACQ Acquisition Time tACQ = tCYC – tHOLD (Note 10) l3.312 µs
tHOLD Maximum Time Between Acquisitions l688 ns
tCYC Time Between Conversions l4 µs
tCNVH CNV High Time l20 ns
tBUSYLH CNV↑ to BUSY Delay CL = 20pF l13 ns
tCNVL Minimum Low Time for CNV (Note 11) l20 ns
tQUIET SCK Quiet Time from CNV↑(Note 10) l20 ns
tSCK SCK Period (Notes 11, 12) l10 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
power requireMenTs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l2.375 2.5 2.625 V
OVDD Supply Voltage l1.71 5.25 V
IVDD
IOVDD
IPD
Supply Current
Supply Current
Power Down Mode
250ksps Sample Rate
250ksps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
l
l
2.1
0.1
1
2.5
90
mA
mA
µA
PDPower Dissipation
Power Down Mode
250ksps Sample Rate
Conversion Done (IVDD + IOVDD + IREF)
5.25
2.5
6.25
225
mW
µW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
reFerence inpuT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Reference Voltage (Note 5) l2.5 5.1 V
IREF Reference Input Current (Note 9) l0.24 0.3 mA
VIHDGC High Level Input Voltage REF/DGC Pin l0.8VREF V
VILDGC Low Level Input Voltage REF/DGC Pin l0.2VREF V
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
DigiTal inpuTs anD DigiTal ouTpuTs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IO = –500µA lOVDD – 0.2 V
VOL Low Level Output Voltage IO = 500µA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 µA
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2376-20
5
237620fb
For more information www.linear.com/LTC2376-20
aDc TiMing characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKH SCK High Time l4 ns
tSCKL SCK Low Time l4 ns
tSSDISCK SDI Setup Time From SCK↑(Note 11) l4 ns
tHSDISCK SDI Hold Time From SCK↑(Note 11) l1 ns
tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l13.5 ns
tDSDO SDO Data Valid Delay from SCK↑CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
7.5
8
9.5
ns
ns
ns
tHSDO SDO Data Remains Valid Delay from SCK↑CL = 20pF (Note 10) l1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↑CL = 20pF (Note 10) l5 ns
tEN Bus Enable Time After RDL↑(Note 11) l16 ns
tDIS Bus Relinquish Time After RDL↑ (Note 11) l13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 250kHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 0000
and 1111 1111 1111 1111 1111. Full-scale bipolar error is the worst-case
of –FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
0.2*OVDD
50% 50%
237620
F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specifications
LTC2376-20
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For more information www.linear.com/LTC2376-20
FREQUENCY (kHz)
SNR, SINAD (dBFS)
108
237620 G05
92
94
96
98
100
102
106
104
0 25 50 75 100
125
SNR
SINAD
FREQUENCY (kHz)
HARMONICS, THD (dBFS)
–90
237620 G06
–140
–120
–130
–110
–100
–125
–135
–115
–105
–95
0 25 50 10075
125
3RD
2ND
THD
Typical perForMance characTerisTics
128k Point FFT fS = 250ksps,
fIN = 2kHz SNR, SINAD vs Input Frequency
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input Level,
fIN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
OUTPUT CODE
–2.0
INL ERROR (ppm)
0.5
1.0
1.5
0
–0.5
–1.0
–1.5
2.0
237620 G01
–524288 –262144 0 262144
524288
FREQUENCY (kHz)
0 25 50 75
100
–180
–60
–40
–20
–80
–100
–120
–140
–160
SNR = 104dB
THD = –128dB
SINAD = 104dB
SFDR = 132dB
OUTPUT CODE
–0.5
DNL ERROR (ppm)
0.4
0.3
0.2
0.1
0.0
–0.4
–0.3
–0.2
–0.1
0.5
237620 G02
–524288 –262144 0 262144
524288
OUTPUT CODE
–9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
8
0
COUNTS
20000
10000
5000
45000
30000
25000
15000
35000
40000
50000
237620 G03
σ = 2.3
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 250ksps, unless otherwise noted.
INPUT LEVEL (dB)
SNR, SINAD (dBFS)
105.0
237620 G07
103.0
103.5
104.0
104.5
–40 –30 –20 –10
0
SNR
SINAD
REFERENCE VOLTAGE (V)
SNR, SINAD (dBFS)
105
104
103
102
237620 G08
95
96
97
98
99
100
101
2.5 3.0 3.5 4.0 4.5
5.0
SINAD
SNR
HARMONICS, THD (dBFS)
–110
237620 G09
–140
–135
–130
–125
–120
–115
3RD
REFERENCE VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5
5.0
2ND
THD
LTC2376-20
7
237620fb
For more information www.linear.com/LTC2376-20
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
Typical perForMance characTerisTics
Supply Current vs Temperature
Shutdown Current vs Temperature CMRR vs Input Frequency
Reference Current
vs Reference Voltage
INL vs Temperature
Full-Scale Error vs Temperature Offset Error vs Temperature
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 250ksps, unless otherwise noted.
FREQUENCY (kHz)
0 5025 75 100
125
70
CMRR (dB)
85
80
75
100
95
90
237620 G17
0
REFERENCE CURRENT (mA)
0.2
0.1
0.3
237620 G18
REFERENCE VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5
5.0
TEMPERATURE (°C)
SNR, SINAD (dBFS)
106
105
104
103
237620 G10
100
101
102
–55 –35 –15 5 25 45 65 85 105
125
SINAD
SNR
TEMPERATURE (°C)
HARMONICS, THD (dBFS)
–120
237620 G11
–140
–135
–130
–125
–55 –35 –15 5 25 6545 85 105
125
THD
2ND
3RD
TEMPERATURE (°C)
INL ERROR (ppm)
2.0
237620 G12
–2.0
–1.0
–1.5
–0.5
0
1.5
1.0
0.5
–55 25 45 65–35 –15 5 85 105
125
MAX INL
MIN INL
TEMPERATURE (°C)
FULL-SCALE ERROR (ppm)
20
237620 G13
–20
0
10
5
15
–10
–5
–15
–55 –35 25 45 65–15 5 85 105
125
–FS
+FS
TEMPERATURE (°C)
POWER SUPPLY CURRENT (mA)
2.5
2.0
237620 G15
0
0.5
1.0
1.5
–55 –35 –15 5 25 45 65 85 105
125
IVDD
IREF
IOVDD
TEMPERATURE (°C)
OFFSET ERROR (ppm)
4
3
2
1
237620 G14
–4
–2
0
–1
–3
–55 –35 –15 255 45 65 85 105
125
TEMPERATURE (°C)
POWER-DOWN CURRENT (µA)
45
40
35
30
237620 G16
0
5
10
15
20
25
–50 –25 0 25 50 75 100
125
IVDD + IOVDD + IREF
LTC2376-20
8
237620fb
For more information www.linear.com/LTC2376-20
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2376-20 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2376-20 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by OVDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+, IN– (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
REF (Pin 7): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47µF ceramic capacitor
(X7R, 1210 size, 10V Rating).
REF/DGC (Pin 8): When tied to REF, digital gain compres-
sion is disabled and the LTC2376-20 defines full-scale ac-
cording to the ±VREF analog input range. When tied to GND,
digital gain compression is enabled and the LTC2376-20
defines full-scale with inputs that swing between 10% and
90% of the ±VREF analog input range.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
pin FuncTions
LTC2376-20
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237620fb
For more information www.linear.com/LTC2376-20
FuncTional block DiagraM
REF = 2.5V TO 5.1V
IN
+
V
DD
= 2.5V
OVDD = 1.8V TO 5V
IN
–
CHAIN
CNV
GND
BUSY
REF/DGC
SDO
SCK
RDL/SDI
CONTROL LOGIC
20-BIT SAMPLING ADC SPI
PORT
+
–
237620 BD01
LTC2376-20
10
237620fb
For more information www.linear.com/LTC2376-20
TiMing DiagraM
applicaTions inForMaTion
POWER-DOWNCONVERT
ACQUIREHOLD
D17D19 D18 D2 D1 D0
SDO
SCK
CNV
CHAIN, RDL/SDI = 0
BUSY
237620 TD01
Conversion Timing Using the Serial Interface
OVERVIEW
The LTC2376-20 is a low noise, low power, high speed
20-bit successive approximation register (SAR) ADC.
Operating from a single 2.5V supply, the LTC2376-20
supports a large and flexible ±VREF fully differential input
range with VREF ranging from 2.5V to 5.1V, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2376-20 achieves ±2ppm INL
maximum, no missing codes at 20 bits and 104dB SNR.
Fast 250ksps throughput with no cycle latency makes
the LTC2376-20 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the con-
version time, easing external timing considerations. The
LTC2376-20 dissipates only 5.3mW at 250ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
The LTC2376-20 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
CONVERTER OPERATION
The LTC2376-20 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins
to sample the differential analog input voltage. A rising
edge on the CNV pin initiates a conversion. During the
conversion phase, the 20-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/1048576)
using the differential comparator. At the end of conversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 20-bit digital
output code for serial transfer.
TRANSFER FUNCTION
The LTC2376-20 digitizes the full-scale voltage of 2 × REF
into 220 levels, resulting in an LSB size of 9.5µV with
REF = 5V. Note that 1 LSB at 20 bits is approximately
1ppm. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
ANALOG INPUT
The analog inputs of the LTC2376-20 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
LTC2376-20
11
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For more information www.linear.com/LTC2376-20
shown in Figure 3. The diodes at the input provide ESD
protection. In the acquisition phase, each input sees ap-
proximately 45pF (CIN) from the sampling CDAC in series
with 40Ω (RON) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
the CIN capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high imped-
ance inputs of the LTC2376-20 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For best
performance, a buffer amplifier should be used to drive the
analog inputs of the LTC2376-20. The amplifier provides low
output impedance, which produces fast settling of the analog
applicaTions inForMaTion
Figure 2. LTC2376-20 Transfer Function
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
237620 F02
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB
–FSR/2
FSR = +FS – –FS
1LSB = FSR/1048576 ≈ 1ppm
signal during the acquisition phase. It also provides isola-
tion between the signal source and the ADC input currents.
Noise and Distortion
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
RON
40Ω
CIN
45pF
RON
40Ω
REF
REF
CIN
45pF
IN
+
IN–
BIAS
VOLTAGE
237620 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2376-20
A coupling filter network (LPF2) should be used between
the buffer and ADC input to minimize disturbances reflected
into the buffer from sampling transients. Long RC time
constants at the analog inputs will slow down the settling
of the analog inputs. Therefore, LPF2 typically requires a
wider bandwidth than LPF1. This filter also helps minimize
the noise contribution from the buffer. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Input Currents
One of the biggest challenges in coupling an amplifier to
the LTC2376-20 is in dealing with current spikes drawn
by the ADC inputs at the start of each acquisition phase.
10Ω
3300pF
6600pF
10Ω
500Ω
LPF2
LPF1
BW = 1.2MHz
BW = 48kHz
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
SINGLE-ENDED-
INPUT SIGNAL
LTC2376-20
IN+
IN–
237620 F04
6800pF
6800pF
Figure 4. Input Signal Chain
LTC2376-20
12
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
The ADC inputs may be modeled as a switched capacitor
load of the drive circuit. A drive circuit may rely partially
on attenuating switched-capacitor current spikes with
small filter capacitors (CFILT) placed directly at the ADC
inputs, and partially on the driver amplifier having suffi-
cient bandwidth to recover from the residual disturbance.
Amplifiers optimized for DC performance may not have
sufficient bandwidth to fully recover at the ADC’s maximum
conversion rate, which can produce nonlinearity and other
errors. Coupling filter circuits may be classified in three
broad categories:
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is consider-
ably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2376-20), the disturbance will not contribute any error.
Partially Settled – In this case, the beginning of acquisition
causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switched-
capacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
Fully Averaged – If the coupling filter capacitors (CFILT) at the
ADC inputs are much larger than the ADC’s sample capacitors
(45pF), then the sampling glitch is greatly attenuated. The
driving amplifier effectively only sees the average sampling
current, which is quite small. At 250ksps, the equivalent input
resistance is approximately 89k (as shown in Figure 5), a
benign resistive load for most precision amplifiers. However,
resistive voltage division will occur between the coupling
filter’s DC resistance and the ADC’s equivalent (switched-
capacitor) input resistance, thus producing a gain error.
The input leakage currents of the LTC2376-20 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currents to an added input voltage error. The input leakage
currents, both common mode and differential, are typically
extremely small over the entire operating temperature
range. Figure 6 shows input leakage currents over tem-
perature for a typical part.
Figure 5. Equivalent Circuit for the Differential Analog
Input of the LTC2376-20 at 250ksps.
Figure 6. Common Mode and Differential Input Leakage Current
Over Temperature
LTC2376-20
BIAS
VOLTAGE
IN+
IN–
CFILT >> 45pF
237620 F05
REQ
REQ
CFILT >> 45pF
REQ =
1
fSMPL •45pF
TEMPERATURE (°C)
INPUT LEAKAGE (nA)
30
237620 F06
–10
0
10
20
–55 –35 –15 5 25 6545
85
DIFFERENTIAL
VIN = VREF
COMMON
Let RS1 and RS2 be the source impedances of the dif-
ferential input drive circuit shown in Figure 7, and let IL1
and IL2 be the leakage currents flowing out of the ADC’s
analog inputs. The voltage error, VE, due to the leakage
currents can be expressed as:
VE=
R
S1
+R
S2
2
•IL1 –IL2
( )
+RS1 –RS2
( )
•
I
L1
+I
L2
2
LTC2376-20
13
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
Figure 8. LT6203 Buffering a Fully Differential Signal Source
LT6203
237620 F08
0V
5V
0V
5V
57
6
+
–
0V
5V
31
2
+
–
0V
5V
as shown in Figure 8 can be used to get the full data sheet
distortion performance of –125dB.
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended-to-
differential conversion circuit must be used to produce
a differential signal at the inputs of the LTC2376-20.
The LT6203 ADC driver is recommended for performing
single-ended-to-differential conversions. The LT6203 is
flexible and may be configured to convert single-ended
signals of various amplitudes to the ±5V differential input
range of the LTC2376-20.
Figure 9a shows the LT6203 being used to convert a 0V to
5V single-ended input signal. In this case, the first amplifier
is configured as a unity gain buffer and the single-ended
Figure 7. Source Impedances of a Driver and Input Leakage
Currents of the LTC2376-20
The common mode input leakage current, (IL1 + IL2)/2, is
typically extremely small (Figure 6) over the entire operat-
ing temperature range and common mode input voltage
range. Thus, any reasonable mismatch (below 5%) of the
source impedances RS1 and RS2 will cause only a negligible
error. The differential input leakage current, (IL1 – IL2),
depends on temperature and is maximum when VIN = VREF,
as shown in Figure 6. The differential leakage current is
also typically very small, and its nonlinear component is
even smaller. Only the nonlinear component will impact
the ADC’s linearity.
For optimal performance, it is recommended that the
source impedances, RS1 and RS2, be between 10Ω and
50Ω and with 1% tolerance. For source impedances in
this range, the voltage and temperature coefficients of
RS1 and RS2 are usually not critical. The guaranteed AC
and DC specifications are tested with 10Ω source imped-
ances, and the specifications will gradually degrade with
increased source impedances due to incomplete settling
of the inputs.
Fully Differential Inputs
A low distortion fully differential signal source driven
through the LT6203 configured as two unity gain buffers
RS1
RS2
IL1
IL2
237620 F07
IN+
VE
IN–
+
–
LTC2376-20
LT6203
VCM = REF/2
237620 F09a
0V
5V
0V
5V
OUT2
499Ω 499Ω
249Ω
OUT1
3
7
1
5
6
2
+
–
+
–
–
+
0V
5V
10µF
FREQUENCY (kHz)
0 25 50 75 100
125
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237620 F09b
SNR = 104dB
THD = –121.4dB
SINAD = 103.9dB
SFDR = 122.1dB
Figure 9a. LT6203 Converting a 0V to 5V Single-
Ended Signal to a ±5V Differential Input Signal
Figure 9b. 128k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 9a
LTC2376-20
14
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
input signal directly drives the high-impedance input of the
amplifier. As shown in the FFT of Figure 9b, the LT6203
drives the LTC2376-20 to near full data sheet performance.
Digital Gain Compression
The LTC2376-20 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be be-
tween 10% and 90% of the ±VREF analog input range. To
enable digital gain compression, bring the REF/DGC pin
low. This feature allows the SAR ADC driver to be powered
off of a single positive supply since each input swings
between 0.5V and 4.5V as shown in Figure 10. Needing
only one positive supply to power the SAR ADC driver
results in additional power savings for the entire system.
With DGC enabled, the LTC2376-20 can be driven by the
low power LTC6362 differential driver which is powered
from a single 5V supply. Figure 11a shows how to configure
the LTC6362 to accept a ±3.28V true bipolar single-ended
input signal and level shift the signal to the reduced input
range of the LTC2376-20 when digital gain compression
is enabled. When paired with the LTC6655-4.096 for the
reference, the entire signal chain solution can be powered
from a single 5V supply, minimizing power consump-
tion and reducing complexity. As shown in the FFT of
Figure11b, the single 5V supply solution can achieve up
to 100dB of SNR.
DC Accuracy
Many driver circuits presented in this data sheet em-
phasize AC performance (distortion and signal-to-noise
ratio), and the amplifiers are chosen accordingly. The
very low level of distortion is a direct consequence of the
excellent INL of the LTC2376-20, and this property can
be exploited in DC applications as well. Note that while
the LTC6362 and LT6203 are characterized by excellent
AC specifications, their DC specifications do not match
those of the LTC2376-20. The offset of these amplifiers,
for example, is more than 500μV under certain conditions.
In contrast, the LTC2376-20 has a guaranteed maximum
offset error of 130µV (typical drift ±0.007ppm/°C), and a
guaranteed maximum full-scale error of 100ppm (typical
drift ±0.05ppm/°C). Low drift is important to maintain ac-
curacy over wide temperature ranges in a calibrated system.
Amplifiers have to be selected very carefully to provide a
20-bit accurate DC signal chain. A large-signal open-loop
gain of at least 126dB may be required to ensure 1ppm
linearity for amplifiers configured for a gain of negative
Figure 10. Input Swing of the LTC2376 with
Gain Compression Enabled
237620 F10
5V
4.5V
0.5V
0V
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237620 F11b
SNR = 100dB
THD = –110dB
SINAD = 99.7dB
SFDR = 113dB
FREQUENCY (kHz)
0 25 50 75 100
125
Figure 11b. 64k Point FFT Plot
with fIN = 2kHz for Circuit Shown
in Figure 11a
Figure 11a. LTC6362 Configured to Accept a ±3.28V Input Signal While Running from
a Single 5V Supply When Digital Gain Compression Is Enabled in the LTC2376-20
237620 F11a
1k
VCM V–
5
4
2
6
V+3
8
1
2
1k
1k
35.7Ω
3300pF
35.7Ω
1k
1k
VCM
1k
0.41V
3.69V
0.41V
3.69V
4.096V
5V
47µF
10µF
LTC2376-20
REF/DGC
IN+REF VDD
2.5V
IN–
LTC6655-4.096VIN
VOUT_S
VOUT_F
–3.28V
3.28V
0V
6800pF
6800pF
–
+
LTC6362
LTC2376-20
15
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For more information www.linear.com/LTC2376-20
1. However, less gain is sufficient if the amplifier’s gain
characteristic is known to be (mostly) linear. An ampli-
fier’s offset versus signal level must be considered for
amplifiers configured as unity gain buffers. For example,
1ppm linearity may require that the offset is known to
vary less than 5μV for a 5V swing. However, greater offset
variations may be acceptable if the relationship is known
to be (mostly) linear. Unity-gain buffer amplifiers typically
require substantial headroom to the power supply rails for
best performance. Inverting amplifier circuits configured
to minimize swing at the amplifier input terminals may
perform better with only little headroom than unity-gain
buffer amplifiers. The linearity and thermal properties
of an inverting amplifier’s feedback network should be
considered carefully to ensure DC accuracy.
ADC REFERENCE
The LTC2376-20 requires an external reference to define
its input range. A low noise, low temperature drift refer-
ence is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and high
accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2376-20. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications.
When choosing a bypass capacitor for the LTC6655-5, the
capacitor’s voltage rating, temperature rating, and pack-
age size should be carefully considered. Physically larger
capacitors with higher voltage and temperature ratings tend
to provide a larger effective capacitance, better filtering
the noise of the LTC6655-5, and consequently producing
a higher SNR. Therefore, we recommend bypassing the
LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210
size, 10V rating) close to the REF pin.
applicaTions inForMaTion
The REF pin of the LTC2376-20 draws charge (QCONV) from
the 47µF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
IREF = QCONV/tCYC. The DC current draw of the REF pin,
IREF, depends on the sampling rate and output code. If
the LTC2376-20 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSBs.
When idling, the REF pin on the LTC2376-20 draws only
a small leakage current (< 1µA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 12, IREF quickly goes from approximately
0µA to a maximum of 0.3mA at 250ksps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the refer-
ence output voltage will affect the accuracy of the output
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-5 refer-
ence is also recommended.
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave and
analyzing the digital output using an FFT algorithm, the ADC’s
spectral content can be examined for frequencies outside the
fundamental. The LTC2376-20 provides guaranteed tested
limits for both AC distortion and noise measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
CNV
IDLE
PERIOD
IDLE
PERIOD
237620 F12
Figure 12. CNV Waveform Showing Burst Sampling
LTC2376-20
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
frequency. Figure 13 shows that the LTC2376-20 achieves
a typical SINAD of 104dB at a 250kHz sampling rate with
a 2kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
POWER CONSIDERATIONS
The LTC2376-20 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2376-20 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Power Supply Sequencing
The LTC2376-20 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2376-20
has a power-on-reset (POR) circuit that will reset the
LTC2376-20 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 200µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2376-20 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up
the LTC2376-20. Once a conversion has been initiated,
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed.
Acquisition
A proprietary sampling architecture allows the LTC2376-20
to begin acquiring the input signal for the next conver-
sion 675ns after the start of the current conversion. This
Figure 13. 128k Point FFT Plot with fIN = 2kHz of the LTC2376-20
FREQUENCY (kHz)
0 25 50 75
100
–180
–60
–40
–20
–80
–100
–120
–140
–160
SNR = 104dB
THD = –128dB
SINAD = 104dB
SFDR = 132dB
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 13 shows
that the LTC2376-20 achieves a typical SNR of 104dB at
a 250kHz sampling rate with a 2kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD=20log V22+V32+V42+…+ VN
2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
LTC2376-20
17
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
extends the acquisition time to 3.312µs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2376-20 has an internal clock that is trimmed to
achieve a maximum conversion time of 3µs.
Auto Power-Down
The LTC2376-20 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2376-20 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2376-20 remains powered-down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 14.
DIGITAL INTERFACE
The LTC2376-20 has a serial digital interface. The flexible
OVDD supply allows the LTC2376-20 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D19 remains valid until the first rising edge of SCK.
The serial interface on the LTC2376-20 is simple and
straightforward to use. The following sections describe the
operation of the LTC2376-20. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
SAMPLING RATE (kHz)
0
250
150 20050 100
0
POWER SUPPLY CURRENT (mA)
2.5
2.0
1.5
1.0
0.5
237620 F14
IVDD
IREF
IOVDD
Figure 14. Power Supply Current of the LTC2376-20
Versus Sampling Rate
LTC2376-20
18
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
Normal Mode, Single Device
When CHAIN = 0, the LTC2376-20 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven.
Figure 15 shows a single LTC2376-20 operated in normal
mode with CHAIN and RDL/SDI tied to ground. With RDL/
SDI grounded, SDO is enabled and the MSB(D19) of the
new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2376-20.
CNV
LTC2376-20
BUSY
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
SDO
SCK
237620 F15a
RDL/SDI
CHAIN
237620 F15
CONVERT CONVERT
tACQ
tACQ = tCYC – tHOLD
POWER-DOWNPOWER-DOWN
CNV
CHAIN = 0
BUSY
SCK
SDO
RDL/SDI = 0
tBUSYLH
tDSDOBUSYL
tSCK
tHSDO
tSCKH tQUIET
tSCKL
tDSDO
tCONV
tCNVH
tHOLD
ACQUIRE
tCYC
tCNVL
D19 D18 D17 D1 D0
1 2 3 18 19 20
ACQUIRE
Figure 15. Using a Single LTC2376-20 in Normal Mode
LTC2376-20
19
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For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
Normal Mode, Multiple Devices
Figure 16 shows multiple LTC2376-20 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2376-20 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 16,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
237620 F16a
RDLB
RDLA
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2376-20 SDO
A
SCK
RDL/SDI
CNV
LTC2376-20 SDO
B
SCK
RDL/SDI
CHAIN BUSY
CHAIN
237620 F16
D19A
SDO
SCK
CNV
BUSY
CHAIN = 0
RDL/SDIB
RDL/SDIA
D19BD18BD1BD0B
D17B
D18AD17AD1AD0A
Hi-Z Hi-ZHi-Z
tEN
tHSDO
tDSDO tDIS
tSCKL
tSCKH
tCNVL
1 2 3 18 19 20 21 22 23 38 39 40
tSCK
CONVERT
CONVERT
tQUIET
tCONV
tHOLD
tBUSYLH
POWER-DOWN
ACQUIRE ACQUIRE
POWER-DOWN
Figure 16. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
LTC2376-20
20
237620fb
For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
OVDD
237620 F17a
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2376-20
BUSY
SDO
B
SCK
RDL/SDI
CNV
LTC2376-20
SDO
A
SCK
RDL/SDI
CHAIN
OV
DD
CHAIN
Chain Mode, Multiple Devices
When CHAIN = OVDD, the LTC2376-20 operates in chain
mode. In chain mode, SDO is always enabled and RDL/SDI
serves as the serial data input pin (SDI) where daisy-chain
data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 17 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 20 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
237620 F17
D0A
D1A
D18A
D19A
D17B
D18B
D19B
SDOB
SDOA = RDL/SDIB
RDL/SDIA = 0
D0B
D1B
D17A
D18A
D19AD0A
D1A
1 2 3 18 19 20 21 22 38 39 40
tDSDOBUSYL
tSSDISCK
tHSDISCK
tBUSYLH
tCONV
tHOLD
tHSDO
tDSDO
tSCKL
tSCKH
tSCKCH
tCNVL
tCYC
CONVERT
CONVERT
SCK
CNV
BUSY
CHAIN = OVDD
tQUIET
POWER-DOWN
POWER-DOWN
ACQUIREACQUIRE
Figure 17. Chain Mode Timing Diagram
LTC2376-20
21
237620fb
For more information www.linear.com/LTC2376-20
To obtain the best performance from the LTC2376-20
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1925A, the
evaluation kit for the LTC2376-20.
Top Silkscreen
boarD layouT
LTC2376-20
22
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For more information www.linear.com/LTC2376-20
boarD layouT
Layer 1 Component Side
LTC2376-20
23
237620fb
For more information www.linear.com/LTC2376-20
Layer 2 Ground Plane
boarD layouT
LTC2376-20
24
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For more information www.linear.com/LTC2376-20
boarD layouT
Layer 3 PWR Plane
LTC2376-20
25
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For more information www.linear.com/LTC2376-20
Layer 4 Bottom Layer
boarD layouT
LTC2376-20
26
237620fb
For more information www.linear.com/LTC2376-20
boarD layouT
Partial Schematic of Demoboard
C68
15pF
COG
C58
1µF
25V
BYPASS CAPACITORS FOR U10
V+
C42
0.1µF
25V
R54
OPT
C67
OPT
C18
10µF
6.3V
R55
0Ω
1
2
3
AC DC
JP7
COUPLING
AC DC
JP8
COUPLING
C66
OPT
C69
10µF
6.3V
C70
OPT
R56
OPT
C47
0.1µF
25V
C19
0.1µF
25V
1
2
3
J4
BNC
J2
BNC
R53
0Ω
AIN+
0 – VREF
AIN–
0 – VREF
U6
NC7SZ66P5X
C13
0.1µF
4
12
9
CNV
SCK
C20
47µF
10V
1206
X7R
C56
0.1µF
CNV
REF
GND
GND
GND
GND
REF/DGC
VDD
VREF
0.8VREF
OVDD
SCK
SDO
BUSY
RDL/SDI
SDO
BUSY
RD
LTC2376-20
IN–
IN+
5
4
3
2
1
5
4
13
14
11
12
B A
5
3
GND
VCC
OE
+3.3V
R5
49.9Ω
1206
R6
1k
U8
NC7SZ04P5X
U2
NC7SVU04P5X
U15
LTC6655AHMS8-5
U3
NL17SZ74
U4
NC7SVU04P5X
CNVST_33
FROM CPLD
CLK
TO CPLD
C5
0.1µF
C1
0.1µF
C11
0.1µF
SHDN
GND
GND
OUT_F
GND
GND
9V TO 10V 1
2
3
4
8
7
6
5
+3.3V +3.3V +3.3V
3
42
5
3
42
5
C2
0.1µF
R3
33Ω
R2
1k
R1
33Ω
+3.3V
+3.3V
3
1
4
6
2
8
7
5
R8
33Ω
C3
0.1µF
R15
33Ω
C4
0.1µF
VIN OUT_S GND VCC
CLR\
Q\
CP
Q
D
PR\
3
4 2
5
+3.3V
DC590 DETECT
TO CPLD
+3.3V
U9
NC7SZ04P5X C15
0.1µF
C16
0.1µF
3
42
5
+3.3V
R13
1k
R17
2k
R10
4.99k
U7
24LC025-I/ST R11
4.99k
R12
4.99k
C14
0.1µF
6
8
4
237620 BL
5
7
3
2
1
SCL
SDA
ARRAY
EEPROM
WP
A2
A1
A0
VSS
VCC
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J3
DC590
SDO
SCK
CNV
9V TO
10V
R7
1k
10
16
6
3
1
15
7
2
8
JP6
FS
1
2
3
HD1X3-100
OPT
C7
0.1µF
C6
10µF
6.3V
+2.5V
C10
0.1µF
C71
6800pF
NPO
C72
3300pF
1206 NPO
R51
10Ω
C73
6800pF
NPO
C9
10µF
6.3V
R9
0Ω
R4
0Ω
R48
10Ω
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
DB19
1
3
5
7
11
9
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P1
40
42
44
46
48
50
52
54
DB18
DB17
DB16
CLKOUT
CLK2
41
43
45
47
49
51
53
55
CLKIN
J1
V+
V–R46
0Ω
R44
OPT
C76
OPT
–
+
R45
OPT
U10A
LT6203MS8
C65
OPT
5
6
7
R49
OPT R50
0Ω
R52
0Ω
R58
OPT
C75
OPT
–
+
R47
OPT
U10B
LT6203MS8
U18B
LT6203MS8
C39
OPT
R39
0Ω
7
5
6
+
–
R38
249Ω
R34
499Ω
C62
10µF
6.3V
R40
OPT
C59
10µF
6.3V
C60
10µF
6.3V
C77
0.1µF
25V
C45
0.1µF
25V
R36
OPT
R35
OPT
R80
2k
0603
EDGE-CON-100
3.3V
C64
OPT
R33
499Ω
C63
OPT
3
2
1
5
4
V+
V–R41
0Ω
–
+
R30
0Ω
U18A
LT6203MS8
C61
OPT
R57
OPT
JP4
CM
E5
EXT_CM
1
2
3
VREF/2
VREF
EXT
C8
1µF
C74
1µF
25V
R18
249Ω
3
2
1
5
4
V+
V–
–
+
R88
1Ω
U5
LT6202CS8
R86
499k
C78
4.7µF
6.3V
R87
499k
C40
1µF
25V
C17
1µF
25V
V–
C55
1µF
25V
BYPASS CAPACITORS FOR U18
V+
C57
0.1µF
25V
C48
0.1µF
25V
C43
0.1µF
25V
C49
1µF
25V
C44
1µF
25V
V–
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
94
96
98
100
DB2
DB1
DB0
95
97
99
R81
4.99k
LTC2376-20
27
237620fb
For more information www.linear.com/LTC2376-20
package DescripTion
Please refer to http://www.linear.com/product/LTC2376-20#packaging for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ±0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ±0.05
0.45 BSC
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
LTC2376-20
28
237620fb
For more information www.linear.com/LTC2376-20
package DescripTion
Please refer to http://www.linear.com/product/LTC2376-20#packaging for the most recent package drawings.
MSOP (MS16) 0213 REV A
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.1016 ±0.0508
(.004 ±.002)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.280 ±0.076
(.011 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
LTC2376-20
29
237620fb
For more information www.linear.com/LTC2376-20
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 03/15 Corrected a typo in the schematic of Figure 11a and Typical Application 14 and 30
B 08/16 Updated graphs TA02, G01, G02, and G03 1 and 6
LTC2376-20
30
237620fb
For more information www.linear.com/LTC2376-20
↑ LINEAR TECHNOLOGY CORPORATION 2013
LT 0816 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2376-20
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2378-20 20-Bit, 1Msps, ±0.5ppm INL Serial, Low Power ADC 2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
LTC2379-18/LTC2378-18
LTC2377-18/LTC2376-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial,
Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC,
Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16
LTC2377-16/LTC2376-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low
Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,
Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2369-18/LTC2368-18/
LTC2367-18/LTC2364-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial,
Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V
Input Range, Pin Compatible Family in MSOP-16 and 4mm × 3mm
DFN-16 Packages
LTC2370-16/LTC2368-16
LTC2367-16/LTC2364-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low
Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V
Input Range, Pin Compatible Family in MSOP-16 and 4mm × 3mm
DFN-16 Packages
LTC2383-16/LTC2382-16/
LTC2381-16
16-Bit, 1Msps/500ksps/250ksps, Low Power ADC 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
DACS
LTC2756/LTC2757 18-Bit, Single Serial/Parallel IOUT SoftSpan™ DAC ±1LSB INL/DNL, SSOP-28 and 7mm × 7mm LQFP-48 Packages
LTC2641 16-/14-/12-Bit Single Serial VOUT DAC ±1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output
LTC2630 12-/10-/8-Bit Single VOUT DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
REFERENCES
LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
AMPLIFIERS
LTC6362 Low Power Rail-to-Rail Input/Output Differential
Output Amplifier/ADC Driver
Single 2.8V to 5.25V Supply, 1mA Supply Current, MSOP-8 and
3mm × 3mm DFN-8 Packages
LT6200/LT6200-5/
LT6200-10 165MHz/800MHz/1.6GHz Op Amp with
Unity Gain/AV = 5/AV = 10
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at
1MHz, TSOT23-6 Package
LT6202/LT6203 Single/Dual 100MHz Rail-to-Rail Input/Output Noise
Low Power Amplifiers
1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth, TSOT23-5, SO-8 ,
MSOP-8 and 3mm × 3mm DFN-8 Packages
LTC6362 Configured to Accept a ±3.28V Input Signal While Running from a Single
5V Supply with Digital Gain Compression Enabled in the LTC2376-20
237620 TA03
1k
VCM V–
5
4
6
V+3
8
1
2
1k
1k
35.7Ω
3300pF
35.7Ω
1k
1k
VCM
1k
0.41V
3.69V
0.41V
3.69V
4.096V
5V
47µF
10µF
LTC2376-20
REF/DGC
IN+REF VDD
2.5V
IN–
LTC6655-4.096VIN
VOUT_S
VOUT_F
–3.28V
3.28V
6800pF
6800pF
–
+
LTC6362
0V