Cover 88PH845 Field Programmable DSP SwitcherTM 500kHz, 4.5A Peak Current-Limit, High Voltage Synchronous Step-Down Regulator with AnyVoltageTM Technology Datasheet Doc. No. MV-S103880-00, Rev. D May 27, 2009 Marvell. Moving Forward Faster Document Classification: Proprietary 88PH845 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 3.0 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 1999-2009. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending--Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S103880-00 Rev. D Page 2 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 88PH845 Field Programmable DSP SwitcherTM Datasheet PRODUCT OVERVIEW The Marvell(R) 88PH845 device is a simple, easy to use synchronous buck switching regulator. A digital control algorithm provides a fast transient response and requires no external compensation components, minimizing the external component count. The output voltage of the Marvell regulator can be set with external resistors (one allows a minor range of settings, while two are used to achieve a full range of program settings), logic programmability, or a serial interface. The input voltage range is 4.5V to 15.7V. The output voltage range is 0.9V to 5.5V. The step-down regulator is internally self-compensated and requires no external compensation. The regulator works with low-ESR output capacitors to simplify the design, minimize board space, and reduce the amount of external components. The switching frequency for the step-down regulator is 500kHz, allowing the use of low profile surface mount inductors and low value capacitors. Features 3.0A DC output current 4.5V to 15.7V input operating range 0.9V to 5.5V output voltage 500kHz switching frequency Stable with low-ESR ceramic output capacitors Up to 95% efficiency Internal soft startup Serial/Logic Programmability 72 output voltage selections using AnyVoltageTM Technology RoHS 6/6 compliant package 4mm x 3mm QFN18 package Applications Point-of-load power supplies Network Access Server (NAS) Figure 1: 12V to 1.2V/3.0A Converter Caution: This is a very high frequency device and proper PCB layout is required. Refer to Section 6, Applications Information, on page 49 for further information. Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 3 88PH845 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103880-00 Rev. D Page 4 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configurations ...........................................................................................................................................11 1.2 Pin Type Definitions ........................................................................................................................................12 2 Electrical Specifications ............................................................................................................. 15 2.1 Absolute Maximum Ratings ............................................................................................................................15 2.2 Recommended Operating Conditions .............................................................................................................16 2.3 Electrical Characteristics .................................................................................................................................17 2.4 Switching Step-down Regulator ......................................................................................................................18 3 Functional Description................................................................................................................ 21 3.1 Overview .........................................................................................................................................................21 3.2 Soft Startup .....................................................................................................................................................22 3.3 Output Voltage Setting ....................................................................................................................................22 3.3.1 Logic Programmability ......................................................................................................................22 3.3.2 Serial Programmability......................................................................................................................24 3.3.3 Output Voltage--AnyVoltageTM Technology.....................................................................................26 3.4 Thermal Shutdown ..........................................................................................................................................28 3.5 Under Voltage Lockout (UVLO) ......................................................................................................................28 3.6 Input Over Voltage Protection (OVP) ..............................................................................................................29 3.7 Power Good (PG)............................................................................................................................................29 3.8 Hiccup Current Limit........................................................................................................................................30 4 Functional Characteristics ......................................................................................................... 31 4.1 Startup Waveforms .........................................................................................................................................31 4.2 Switching Waveforms......................................................................................................................................32 4.3 Load Transient Waveforms .............................................................................................................................34 4.3.1 Step-Down Regulator .......................................................................................................................34 5 Typical Characteristics ............................................................................................................... 37 5.1 Efficiency .........................................................................................................................................................37 5.2 Load Regulation ..............................................................................................................................................38 5.3 RDS (ON) Resistance .....................................................................................................................................39 5.4 IC Case and Inductor Temperature.................................................................................................................40 Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 5 88PH845 Datasheet 5.5 Input Voltage ...................................................................................................................................................42 5.5.1 Step-Down Regulator .......................................................................................................................43 5.6 Temperature....................................................................................................................................................45 5.6.1 Step-Down Regulator .......................................................................................................................47 6 Applications Information ............................................................................................................ 49 6.1 PC Board Layout Considerations and Guidelines ...........................................................................................49 6.1.1 PC Board Layout Examples..............................................................................................................51 6.2 Bill of Materials ................................................................................................................................................53 7 Mechanical Drawings .................................................................................................................. 55 7.1 Mechanical Drawings ......................................................................................................................................55 7.2 Mechanical Dimensions ..................................................................................................................................56 7.3 Typical Pad Layout Dimensions ......................................................................................................................57 7.3.1 Recommended Solder Pad Layout ...................................................................................................57 8 Part Order Numbering/Package Marking .................................................................................. 59 8.1 Part Order Numbering Scheme.......................................................................................................................59 8.2 Part Ordering Options .....................................................................................................................................59 8.3 Package Marking ............................................................................................................................................60 A Revision History .......................................................................................................................... 61 Doc. No. MV-S103880-00 Rev. D Page 6 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 List of Figures List of Figures Figure 1: 1 12V to 1.2V/3.0A Converter ................................................................................................................3 Signal Description ........................................................................................................................... 11 Figure 2: 4mm x 3mm FCQFN-18 Pin Diagram (Top View) ............................................................................11 2 Electrical Specifications ................................................................................................................. 15 3 Functional Description.................................................................................................................... 21 4 5 Figure 3: Block Diagram ..................................................................................................................................21 Figure 4: Soft Startup (1.0V, 1.5V, 2.5V, 3.3V, 5.0V) ......................................................................................22 Figure 5: Serial Programmability......................................................................................................................24 Figure 6: Startup and Soft Startup Sequences ................................................................................................27 Figure 7: VSET = 2.5V and PSET = -5% .........................................................................................................27 Figure 8: UVLO and OVP Waveforms .............................................................................................................29 Figure 9: Power Good Operating Waveform....................................................................................................29 Figure 10: Hiccup Period ...................................................................................................................................30 Functional Characteristics.............................................................................................................. 31 Figure 11: Startup Using the EN Pin .................................................................................................................31 Figure 12: Power Off Using the EN Pin .............................................................................................................31 Figure 13: Soft Start ...........................................................................................................................................31 Figure 14: Hot Plug ............................................................................................................................................31 Figure 15: PWM Mode--2x22F ......................................................................................................................32 Figure 16: PWM Mode--4x22F .......................................................................................................................32 Figure 17: DCM Mode .......................................................................................................................................32 Figure 18: DCM Mode--Zoom ...........................................................................................................................32 Figure 19: PWM Output Ripple Voltage ............................................................................................................33 Figure 20: Fast Load Rise Time ........................................................................................................................34 Figure 21: Slow Load Rise Time ........................................................................................................................34 Figure 22: Fast Load Fall Times .......................................................................................................................34 Figure 23: Slow Load Fall Time .........................................................................................................................34 Figure 24: Load Transient Response.................................................................................................................35 Figure 25: Double-Pulsed Load Response ........................................................................................................35 Figure 26: Load Transient Response.................................................................................................................35 Figure 27: Double-Pulsed Load Response ........................................................................................................35 Typical Characteristics ................................................................................................................... 37 Figure 28: Efficiency vs. Output Current ............................................................................................................37 Figure 29: Efficiency vs. Output Current in Log Scale .......................................................................................37 Figure 30: Output Voltage vs. Output Current ...................................................................................................38 Figure 31: Resistance vs. Input Voltage ............................................................................................................39 Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 7 88PH845 Datasheet 6 Figure 32: Resistance vs. Temperature .............................................................................................................39 Figure 33: Input Current vs. Output Current ......................................................................................................40 Figure 34: IC Case Temperature vs. Output Current .........................................................................................40 Figure 35: Inductor Temperature vs. Output Current .........................................................................................41 Figure 36: Supply Current vs. Input Voltage ......................................................................................................42 Figure 37: Shutdown Supply Current vs. Input Voltage .....................................................................................42 Figure 38: Enable Threshold vs. Input Voltage ..................................................................................................42 Figure 39: Output Voltage vs. Input Voltage ......................................................................................................43 Figure 40: Efficiency vs. Input Voltage...............................................................................................................43 Figure 41: Load Regulation vs. Input Voltage ....................................................................................................43 Figure 42: Frequency vs. Input Voltage .............................................................................................................43 Figure 43: Average Output Current Limit vs. Input Voltage ...............................................................................44 Figure 44: Supply Current vs. Temperature.......................................................................................................45 Figure 45: UVLO Threshold vs. Temperature ....................................................................................................45 Figure 46: OVP Threshold vs. Temperature ......................................................................................................45 Figure 47: Enable Threshold vs. Temperature ..................................................................................................45 Figure 48: Shutdown Supply Current vs. Temperature......................................................................................46 Figure 49: Output Voltage vs. Temperature.......................................................................................................47 Figure 50: Efficiency vs. Temperature ...............................................................................................................47 Figure 51: Line Regulation vs. Temperature......................................................................................................47 Figure 52: Load Regulation vs. Temperature ....................................................................................................47 Figure 53: Frequency vs. Temperature..............................................................................................................48 Figure 54: Average Output Current Limit vs. Temperature ................................................................................48 Applications Information ................................................................................................................ 49 Figure 55: 7 8 A PCB Layout Schematic .....................................................................................................................50 Figure 56: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale) ........................................................51 Figure 57: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale) ...................................................52 Mechanical Drawings ...................................................................................................................... 55 Figure 58: 4mm x 3mm 18-Pin FCQFN Mechanical Drawing ............................................................................55 Figure 59: 4mm x 3mm FCQFN-18 Land Pattern (mm).....................................................................................57 Part Order Numbering/Package Marking....................................................................................... 59 Figure 60: Sample Part Number ........................................................................................................................59 Figure 61: Package Marking and Pin 1 location ................................................................................................60 Revision History ............................................................................................................................... 61 Doc. No. MV-S103880-00 Rev. D Page 8 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 List of Tables List of Tables 1 2 3 Signal Description ............................................................................................................................ 11 Table 1: Pin Type Definitions ..........................................................................................................................12 Table 2: Pin Description..................................................................................................................................12 Electrical Specifications .................................................................................................................. 15 Table 3: Absolute Maximum Ratings ..............................................................................................................15 Table 4: Recommended Operating Conditions...............................................................................................16 Table 5: Electrical Characteristics ..................................................................................................................17 Table 6: Switching Step-down Regulator........................................................................................................18 Functional Description..................................................................................................................... 21 Table 7: Output Voltage Rise Time.................................................................................................................22 Table 8: VSET and PSET Logic Programming ...............................................................................................23 Table 9: Data Field Default Values .................................................................................................................25 Table 10: Data Field Default Values .................................................................................................................25 Table 11: VSET and PSET Programming for 5% Resistors .............................................................................26 Table 12: VSET and PSET Programming Steps ..............................................................................................28 4 Functional Characteristics............................................................................................................... 31 5 Typical Characteristics .................................................................................................................... 37 6 Applications Information ................................................................................................................. 49 Table 13: 7 Mechanical Drawings ....................................................................................................................... 55 Table 14: 8 4mm x 3mm 18-Pin FCQFN Dimensions..........................................................................................56 Part Order Numbering/Package Marking........................................................................................ 59 Table 15: A 88PH845 BOM..................................................................................................................................53 Part Ordering Options .......................................................................................................................59 Revision History ............................................................................................................................... 61 Table 16: Revision History ................................................................................................................................61 Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 9 88PH845 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103880-00 Rev. D Page 10 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Signal Description Pin Configurations 1 Signal Description 1.1 Pin Configurations Figure 2: 4mm x 3mm FCQFN-18 Pin Diagram (Top View) PG PWM PSET 18 17 16 VCC 1 15 VSET SVIN 2 14 SFB VDD 3 13 EN VBS 4 12 SGND SW 5 11 SW VIN 6 10 PGND 7 8 9 VIN SW PGND Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 11 88PH845 Datasheet 1.2 Table 1: Pin Type Definitions Pin Type Definitions Pi n Typ e D e s c r i p t io n I Input only O Output only S Supply NC Not Connected GND Ground Table 2: Pin Description Pi n N o. Pin Name P in Ty pe Pi n F u nc t io n 1 VCC S Internal 5V Regulator Output The internal control circuitry is powered from this voltage. This is a no connect pin. Do not connect an external load to this source. 2 SVIN S Internal LDO Power Supply Input Power supply input for the internal LDO for generating VCC and VDD. Decouple with a 4.7F ceramic capacitor to PGND. 3 VDD S Internal 5V Regulator Output VDD supplies the boot-strap circuitry and internal MOSFET driver. Do not connect an external load to this source. 4 VBS S Boot-Strap Voltage Node Supply to the topside floating driver. Place a 0.047 F ceramic capacitor as close as possible to the VBS and SW pins. 5, 8, 11 SW O Switching Node Internal top power MOSFET source. Connects to the output inductor. 6, 7 VIN S Power Input Voltage Internal top power MOSFET drain. Connect a ceramic decoupling capacitor between each VIN and PGND and position it as close as possible to the device. 9, 10 PGND GND Power Ground Connect to the (-) terminal of the input capacitors. 12 SGND GND Signal Ground Must be routed separately from the PGND and connected to the (-) terminal of the output capacitor. 13 EN I Enable Logic high (2.0V) enables the regulator and logic low (0.8V) disables the regulator. SW pin is high impedance when Enable is logic low. Doc. No. MV-S103880-00 Rev. D Page 12 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Signal Description Pin Type Definitions Table 2: Pin Description (Continued) Pi n N o. Pin Name P in Ty pe Pi n F u nc t io n 14 SFB I Switching Regulator Feedback Senses the output voltage of the switching regulator. 15 VSET I Voltage Set * Used for selecting the output voltage level, when it is connected to SGND or VCC in conjunction with PSET connected to SGND or VCC. See Table 8, VSET and PSET Logic Programming, on page 23 for information. * Connect to an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 11, VSET and PSET Programming for 5% Resistors, on page 26 for resistor values and Output Voltage Setting section. The total capacitance across this pin and SGND should be equal to 25 pF or less. Use resistor values with a tolerance of 5% or better. * Do not float this pin. 16 PSET I Percent Set * Used for selecting the output voltage level, when it is connected to SGND or VCC in conjunction with VSET connected to SGND or VCC. See Table 8, VSET and PSET Logic Programming, on page 23 for information. * Connect to an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 11, VSET and PSET Programming for 5% Resistors, on page 26 for resistor values and Output Voltage Setting section. Use resistor values with a tolerance of 5% or better. * Do not float this pin. 17 PWM I Operation Mode Control Input * Connect the PWM pin to VCC to allow forced PWM operation. Connect the PWM pin to SGND to allow SKIP operation mode at light load. * It also serves as a serial data input when it is connected to a programming device. The input data to this pin is used to program the output voltage (see Section 3.3.2, Serial Programmability, on page 24). Do not share this pin with other serial interface pins. * Do not float this pin. 18 PG O Power Good (active high) Open-drain output that indicates the status of the output voltage. An external 100 k pull-up resistor is connected between the PG pin and VOUT. The output is pulled to ground when the output voltage is not within the specified tolerance and a 25s falling edge deglitch delay prevents tripping of the power good comparator due to high frequency noise. Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 13 88PH845 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103880-00 Rev. D Page 14 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Range U n i ts VIN to PGND -0.3 to 18.0 V VSW to PGND2 -0.3 to (VIN + 0.3) V VSFB to SGND -0.3 to 6.0 V VCC to SGND -0.3 to minimum (VIN + 0.3, 5.5) V VDD to PGND -0.3 to minimum (VIN + 0.3, 5.5) V VSET , VPSET to SGND -0.3 to (VCC + 0.3) V VPWM to SGND -0.3 to (VCC + 0.3) V VEN to SGND -0.3 to 16.0 V VPG to SGND -0.3 to (VIN + 0.3) V VBS to PGND3 -0.3 to (VIN + 5.5) V PGND to SGND -0.3 to +0.3 V VIN to VSVIN -0.3 to +0.3 V -40 to 85 C 150 C -65 to 150 C Lead Temperature (soldering, 10s) 300 C ESD Rating5 Human Body Model 2.0 kV ESD Rating Machine Model 200 V Operating Ambient Temperature Range4 Maximum Junction Temperature Storage Temperature Range 1. Exceeding the absolute maximum rating may damage the device. 2. Capable of -1.0V to (VIN +0.3) for less than 50nS. 3. During normal operation, VBS is periodically boosted to (VIN + VDD). However, do not externally force the VBS pin to more than (VDD + 0.3V). 4. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization, and correlation with statistical process controls. 5. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 15 88PH845 Datasheet 2.2 Table 4: Recommended Operating Conditions Recommended Operating Conditions1 Sy m b o l P a r a m e te r M in VIN Input Voltage 4.5 JA Package Thermal Resistance2 JC TJMAX Maximum Operating Junction Temperature Ty p Max U n i ts 15.7 V 61.5 C/W 25.6 C/W 125 C 1. This device is not guaranteed to function outside the specified operating range. 2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board. Doc. No. MV-S103880-00 Rev. D Page 16 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10F, C2 = C3 = 10F, C4 = C5 = 22F, C6 = 0.047F, C7 = C8 = 4.7F, L1 = 6.9H, TA = 25 C. Bold values indicate -40oCTA85oC. Sy m b o l P a r a m e te r C o nd i tio n s Min Ty p Max Units VIN Input Voltage Range 4.5 12 15.7 V IQ Total Quiescent Current No Load, VPWM = 0V 2.65 4 mA ISVIN Shutdown Supply Current VEN = 0V 10 20 A VUVLO Under Voltage Lockout High Threshold, VIN increasing 4.4 4.5 V 17.5 V A Low Threshold, VIN decreasing VOVP Over Voltage Lockout High Threshold, VIN increasing Low Threshold, VIN decreasing IEN IPWM VIH VIL TOTS EN Input Current PWM Input Current 16.7 15.7 16.2 0.1 1 VEN = 12V 1.5 5 VPWM = 5V 1.5 5 VPWM = 0V 0.1 1 2.0 A V 0.4 TJ increasing (disables regulator) 150 TJ decreasing (enables regulator) 100 Copyright (c) 2009 Marvell May 27, 2009, 3.0 4.1 VEN = 0V EN and PWM Input Voltage Threshold Over-Temperature Thermal Shutdown 4.0 C Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 17 88PH845 Datasheet 2.4 Table 6: Switching Step-down Regulator Switching Step-down Regulator The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10F, C2 = C3 = 10F, C4 = C5 = 22F, C6 = 0.047F, C7 = C8 = 4.7F, L1 = 6.9H, TA = 25 C. Bold values indicate -40oCTA85oC. Sy m b o l P a r a m e te r C o nd i tio n s VOUT Output Voltage RVSET = 11k, PWM mode, ILOAD = 300mA Min Max 1.000 U ni t s V TA=25 C -3 +3 % Over Temperature -4 +4 % RVSET = 18k, PWM mode, ILOAD = 300mA TA=25 C Over Temperature 1.200 TA=25 C Over Temperature +2.5 % -3 +3 % 1.500 Over Temperature Doc. No. MV-S103880-00 Rev. D V -2.5 +2.5 % -3 +3 % RVSET = 51k, PWM mode, ILOAD = 300mA TA=25 C V -2.5 RVSET = 30k, PWM mode, ILOAD = 300mA Page 18 Ty p 1.800 V -2.5 +2.5 % -3 +3 % Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Electrical Specifications Switching Step-down Regulator Table 6: Switching Step-down Regulator The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10F, C2 = C3 = 10F, C4 = C5 = 22F, C6 = 0.047F, C7 = C8 = 4.7F, L1 = 6.9H, TA = 25 C. Bold values indicate -40oCTA85oC. Sy m b o l P a r a m e te r C o nd i tio n s Min RVSET = 100k, PWM mode, ILOAD = 300mA Ty p Max 2.500 U ni t s V VVSET = SGND, VPSET = SGND, PWM mode, ILOAD = 300mA TA=25 C -2 +2 % Over Temperature -3 +3 % RVSET = 160k, PWM mode, ILOAD = 300mA 3.000 V VVSET = SGND, VPSET = VCC, PWM mode, ILOAD = 300mA TA=25 C -2 +2 % Over Temperature -3 +3 % RVSET = 270k, PWM mode, ILOAD = 300mA 3.300 V VVSET = VCC, VPSET = SGND, PWM mode, ILOAD = 300mA TA=25 C -2 +2 % Over Temperature -3 +3 % RVSET = 470k, PWM mode, ILOAD = 300mA 5.000 V VVSET = VCC, VPSET = VCC, PWM mode, ILOAD = 300mA TA=25 C -2 +2 % Over Temperature -3 +3 % Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 19 88PH845 Datasheet Table 6: Switching Step-down Regulator The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10F, C2 = C3 = 10F, C4 = C5 = 22F, C6 = 0.047F, C7 = C8 = 4.7F, L1 = 6.9H, TA = 25 C. Bold values indicate -40oCTA85oC. Sy m b o l P a r a m e te r C o nd i tio n s Min Ty p Percentage Set RPSET = 11k -10 RPSET = 18k -7.5 RPSET = 30k -5 RPSET = 51k -2.5 RPSET = 0k 0 RPSET = 100k 2.5 RPSET = 160k 5 RPSET = 270k 7.5 RPSET = 470k 10 Max U ni t s % VLNREG Output Voltage Line Regulation VIN = 8.0V to 14V VOUT = 5.0V ILOAD = IOUT(MAX) / 2 0.02 % VLDREG Output Voltage Load Regulation VIN = 12V VOUT = 5.0V ILOAD = IOUT(MAX) / 4 to IOUT(MAX) 0.05 % fSW Switching Frequency 500 kHz DMAX Maximum Duty Cycle 95 % ILIM Minimum Peak Switch Current Limit 4.5 A RDSON_HS High Side Switch On Resistance 70 100 m RDSON_LS Low Side Switch On Resistance 35 50 m VPGTH Power Good (PG) Threshold Voltage VPGL PG Output Low Voltage tDEGLITCH tDELAY VOUT 1.35V VOUT x 90% VOUT 1.32V VOUT - 130mV ISINK = 1 mA, VEN = 12V V 0.4 V Deglitch1 25 s PG Delay 160 s 1. See Figure 9 for reference. Doc. No. MV-S103880-00 Rev. D Page 20 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Description Overview 3 Functional Description 3.1 Overview The 88PH845 device incorporates a control architecture that minimizes the number of external passive components, improves efficiency, and provides fast transient response. A non-linear control algorithm is able to detect and react to severe load changes in less than 100 ns with no external compensation components. Other features include under and over voltage lockout, over temperature shutdown, power good detection, skip or forced Pulse Width Modulation (PWM) operation, and cycle-by-cycle current limiting. The output voltage is set by using logic control, serial interface, or external resistors. External resistors connected to the VSET and PSET pins are measured once before startup. These two resistors provide up to 72 output voltage options from 0.9V to 5.5V. These external resistors can be eliminated by tying the VSET and PSET pin to VCC or GND, generating 2.5V, 3.0V, 3.3V, or 5.0V. Some applications require voltage margining, which forces the output voltage a percentage above and below its nominal value. In this case, the serial interface can be used to change the output 0%, 2.5%, 5.0%, 7.5%, 10% or any one of the 72 voltage options. Figure 3 shows an overall block diagram. Figure 3: Block Diagram Vin 12V C8 VCC SVIN VDD LDO EN C7 INTERNAL CIRCUITRY POWER SUPPLY ON OSCILLATOR OFF Current Sense VIN + - PWM PWM Serial Data Interface ANALOGDIGITAL CONVERTER VBS C6 PWM CONTROL DSP DCM VDD 10 Current Sense A THERMAL SHUTDOWN 150C BAND-GAP VOLTAGE REFERENCE UNDERVOLTAGE LOCKOUT + SFB RESISTOR NETWORK PG RESISTOR SENSING CIRCUITRY SGND VSET R3 Vout C4-C5 Vout R1 VPG PGood PSET R2 Copyright (c) 2009 Marvell May 27, 2009, 3.0 L1 SW PGND - FAULT C1-C3 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 21 88PH845 Datasheet 3.2 Soft Startup The 88PH845 controls the rise time of the output voltage, thereby dramatically reducing the inrush current. The rise time is independent of output capacitance and load current (Figure 4). Table 7: Output Voltage Rise Time O ut p u t Vo lta g e ( V ) R i s e Ti m e ( m s ) 1.0 2.5 1.2 3 1.5 4.5 1.8 5 2.5 5 3.0 5 3.3 5 5.0 5 Figure 4: Soft Startup (1.0V, 1.5V, 2.5V, 3.3V, 5.0V) VOUT 1V/DIV 1ms/DIV 3.3 Output Voltage Setting 3.3.1 Logic Programmability The output voltage of the step-down switching regulator can be programmed for the standard output voltages by connecting VSET and PSET pins to SGND and/or VCC (Table 8). This method eliminates the use of external resistors to set the output voltage. Doc. No. MV-S103880-00 Rev. D Page 22 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Description Output Voltage Setting Table 8: VSET and PSET Logic Programming V VSET V PSET V OUT SGND SGND 2.5V SGND VCC 3.0V VCC SGND 3.3V VCC VCC 5.0V Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 23 88PH845 Datasheet 3.3.2 Serial Programmability The output voltage of the step-down switching regulator can also be programmed by using 18-bit serial data into the PWM pin. Warning: Do not share the PWM pin with other serial interface pins. Figure 5: Serial Programmability WRITE MODE Stop Start Chip Select "1" Pulse "0" "0" "1" pulse Pulse pulse Register Address "1" Pulse The period of a pulse is 1 s 200 ns VHIGH > VIH VLow < VIL DATA FIELD "0" "0" "0" "1" pulse pulse Pulse pulse "1" Pulse D7 D6 D5 D4 D3 D2 D1 D0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 "1" pulse The write operation: VHIGH VLOW 1) Each write sequence needs 18 pulses to complete. 2) During a non-write operation, the input needs to be at VLOW (<VIL). 3) In between two successive write operations, the PWM input needs to be at VLOW (<VIL) for a minimum of 10 s. For "1" pulse, the high is 0.75 s 150 ns and the low period is 0.25 s 50 ns "0" pulse 1st Write sequence VLOW Low for at least 10 s 2nd Write sequence VHIGH For "0" pulse, the high is 0.25 s 50 ns and the low period is 0.75 s 150 ns Doc. No. MV-S103880-00 Rev. D Page 24 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Description Output Voltage Setting The first 4 bits (MSB) of the data field are used to select the output voltage where the second 4 bits (LSB) of the data field are used to trim the output voltage (percent of output voltage). Table 9 shows the default value for the data field. Table 9: Data Field Default Values D e s c r i p t io n Vo l ta g e S e t Percent Set Register Position 7 6 5 4 3 2 1 0 Default Value 0 0 1 0 0 1 0 0 The value for position 7 and 3 of the register will enable use of either logic or serial output voltage programmability. Bit value of "0" for positions 7 and 3 will enable the resistor/logic programmability and the output voltage will be set according to Section 3.3.1, Logic Programmability . A bit value of 1 enables serial programmability. Table 10 shows the output voltage and percent set. Table 10: Data Field Default Values V SE T Register Position V OUT (V) 7 6 5 4 1 0 0 0 1 0 0 1 0 1 P S ET P er c e nt S e t 3 2 1 0 1.0 1 0 0 0 -10% 1 1.2 1 0 0 1 -7.5% 1 0 1.5 1 0 1 0 -5.0% 0 1 1 1.8 1 0 1 1 -2.5% 1 1 0 0 2.5 1 1 0 0 +2.5% 1 1 0 1 3.0 1 1 0 1 +5.0% 1 1 1 0 3.3 1 1 1 0 +7.5% 1 1 1 1 5.0 1 1 1 1 +10% All combinations of the VSET (shown above) can be used with all combinations of the PSET (shown above) to provide maximum flexibility in output voltage selection. Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 25 88PH845 Datasheet 3.3.3 Output Voltage--AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 11 to select resistor values for the VSET and PSET pins. The VSET pin sets the output voltage, and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 100k resistor is selected for the VSET pin, and an 11k resistor is selected for the PSET pin. The 100k resistor sets the output voltage to 2.5V and the 11 k resistor trims the set voltage by -10%. Using a VSET resistor value greater than 619k or less than 7.68k disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor value is outside the 5% tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619k or less than 7.68k for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value is either higher or lower if the PSET resistor's value is outside the 5% tolerance. Table 11: VSET and PSET Programming for 5% Resistors V SE T P S ET -10% -7.50% -5.00% - 2. 5 0 % 2.50% 5.00% 7.50% 1 0% 11 k 18k 30k 51k GND 100k 160k 2 7 0k 4 70 k 11 k 0.900 0.925 0.950 0.975 1.00 1.025 1.050 1.075 1.100 18k 1.080 1.110 1.140 1.170 1.20 1.230 1.260 1.290 1.320 30k 1.350 1.388 1.425 1.463 1.50 1.538 1.575 1.613 1.650 51k 1.620 1.665 1.710 1.755 1.80 1.845 1.890 1.935 1.980 100k 2.250 2.313 2.375 2.438 2.50 2.563 2.625 2.688 2.750 160k 2.700 2.775 2.850 2.925 3.00 3.075 3.150 3.225 3.300 270k 2.970 3.053 3.135 3.218 3.30 3.383 3.465 3.548 3.630 470k 4.500 4.625 4.750 4.875 5.00 5.125 5.250 5.375 5.500 The VSET and PSET resistors are read once during startup before the output voltage is turned on. After the output voltage is turned on, the output voltage can be changed to different values using the serial programming interface. Otherwise to configure the output to a different voltage, power has to recycle or the device must turn OFF and back ON using the enable pin. Figure 6 shows the startup waveforms of the 88PH845. Once the input voltage (VIN) is above the Under Voltage Lockout (UVLO) Upper Threshold (UTH), the VSET and PSET pins become active. Current is first sourced out of the PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage, then the current source proceeds to the next set. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn-on. Figure 7 shows the VSET and PSET waveform for VSET = 2.5V and PSET = -5% output. The 88PH845 keeps track of the number of many steps required to determine the appropriate output voltage. Table 12 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 100k requires the current source to step five times, and a PSET resistor of 30k requires seven steps. Doc. No. MV-S103880-00 Rev. D Page 26 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Description Output Voltage Setting Figure 6: Startup and Soft Startup Sequences VIN 5V/DIV VOUT 2V/DIV VVSET 2V/DIV VPSET 2V/DIV 5ms/DIV Figure 7: VSET = 2.5V and PSET = -5% VVSET 500 mV/DIV VPSET 500 mV/DIV 200s/DIV Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 27 88PH845 Datasheet Table 12: VSET and PSET Programming Steps V OUT (V) R VSET (k ) PSET (% ) R PSET (k ) 1 Table 8 0V or VCC 1 Table 8 0V or VCC 2 5.0 470 2 +10 470 3 3.3 270 3 +7.5 270 4 3.0 160 4 +5.0 160 5 2.5 100 5 +2.5 100 6 1.8 51 6 -2.5 51 7 1.5 30 7 -5.0 30 8 1.2 18 8 -7.5 18 9 1.0 11 9 -10 11 Ste p Ste p The 88PH845 provide an innovative technique to set the output voltage. During startup they read the value of external resistors, which are located outside the regulator's feedback loop. By placing the output voltage programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. In conventional designs, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the 88PH845 initial accuracy is 2% for any output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for a RVSET and RPSET of 470 k. The parasitic resistance on these nodes must be greater than 3 M, and the stray capacitance must be less than 25pF. Otherwise, a 5.0V output can potentially end up at 3.3V. 3.4 Thermal Shutdown When the junction temperature of the 88PH845 exceeds OTS high threshold, the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to OTS low threshold. 3.5 Under Voltage Lockout (UVLO) The Under Voltage Lockout (UVLO) feature insures that both internal MOSFETs have adequate voltage levels to operate properly. When the input voltage drops below UVLO low threshold, both MOSFETs remain off until the input rises above UVLO high threshold. See section 2.3 for the UVLO low and high threshold voltages. Doc. No. MV-S103880-00 Rev. D Page 28 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Description Input Over Voltage Protection (OVP) 3.6 Input Over Voltage Protection (OVP) The Over Voltage Protection (OVP) feature uses a comparator to guard against transient overshoots, as well as other serious conditions, that may damage the device. When the input voltage is above OVP high threshold both internal N-channel MOSFETs are turned off until the input voltage drops below OVP low threshold. See section 2.3 for the OVP low and high threshold voltages. Figure 8: UVLO and OVP Waveforms V OVP_HTH VOVP_LTH VUVLO_HTH VUVLO_LTH VIN BUCK Output Enable BUCK Output Disable 3.7 Power Good (PG) The Power Good (PG) pin is an active-high, open-drain output. The output is held low when the output voltage of the step-down regulator is below the threshold. When the output voltage is above the threshold for more than tDELAY (160s typical), the power good signal goes high. Setting the output voltage greater than 1.32V, the threshold voltage is 0.9% * VOUT (typical). Setting the output voltage less than 1.32V, the threshold voltage is VOUT - 130mV (typical). A built-in tDEGLITCH (25s typical) delay is incorporated to prevent nuisance tripping. Figure 9: Power Good Operating Waveform VPG_TH < t DEGLITCH 0V VPG RPG _PULLUP x IPG V PGL tDELAY Copyright (c) 2009 Marvell May 27, 2009, 3.0 tDEGLITCH Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 29 88PH845 Datasheet 3.8 Hiccup Current Limit The "Hiccup" short-circuit protection is an unique feature among switching regulators. Hiccup mode offers extra protection against over-current situations since it limits the average current to the load, reducing power dissipation and case temperature of the device. When the current-sense circuit sees an over-current condition together with a low output voltage condition (Vout < 0.4V typical), the 88PH845 device shuts off for about 12ms and then tries to startup again (see Figure 10). If the over-load condition is removed, the device will startup normally; otherwise, the device will see another over-current event and shut off again, repeating the cycle. Figure 10: Hiccup Period VSW 5.0V/DIV IOUT 5.0A/DIV 10 ms/DIV Doc. No. MV-S103880-00 Rev. D Page 30 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Characteristics Startup Waveforms 4 Functional Characteristics Note: Unless otherwise specified, all scope pictures were taken using test circuit shown in Figure 1 in this datasheet. TA = 25C 4.1 Startup Waveforms When the input voltage rises above the UVLO's upper threshold, there is a delay (6ms typical) before the step-down regulator's output voltage powers on. Figure 11: Startup Using the EN Pin Figure 12: Power Off Using the EN Pin VEN VEN 5V/DIV 5V/DIV VOUT 2V/DIV VOUT 2V/DIV 2ms/DIV VIN = 12V 2ms/DIV ILOAD = 10mA VIN = 12V VOUT = 5V ILOAD = 10mA VOUT = 5V Figure 13: Soft Start Figure 14: Hot Plug VIN 5V/DIV VIN 5V/DIV VOUT 5V/DIV VOUT 5V/DIV VPG 5V/DIV VPG 5V/DIV 10ms/DIV VIN = 12V VOUT = 5V ILOAD = No load 10ms/DIV VIN = 12V VOUT = 5V Copyright (c) 2009 Marvell May 27, 2009, 3.0 ILOAD = No load Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 31 88PH845 Datasheet 4.2 Switching Waveforms Note: For repeatability of measuring output ripple (VOUT(P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. Figure 15: PWM Mode--2x22F Figure 16: PWM Mode--4x22F VSW 10V/DIV IIND 2A/DIV VOUT 50 mV/DIV VIN 50 mV/DIV VSW 10V/DIV IIND 2A/DIV VOUT 50 mV/DIV VIN 50 mV/DIV 1s/DIV CIN = 2x22F VIN(P-P) = 65.0mV 1s/DIV CIN = 4x22F VIN(P-P) = 33.4mV IIND(P-P) = 1.13A VIN = 12V IIND(P-P) = 1.11A VIN = 12V VOUT = 5V IIND(PK) = 3.57A VOUT = 5V IIND(PK) = 3.59A IOUT = 3A Frequency = 507kHz IOUT = 3A Frequency = 510kHz VOUT(P-P) = 30mV (Note) VOUT(P-P) = 28mV (Note) Figure 17: DCM Mode Figure 18: DCM Mode--Zoom 10V/DIV 10V/DIV VSW VSW 50 mV/DIV VOUT IIND 1A/DIV 50 mV/DIV VOUT IIND 1A/DIV 2s/DIV VIN = 12V 1s/DIV VOUT(P-P) = 55mV (Note) VIN = 12V IOUT = 24mA VOUT = 5V IIND(PK) = 0.76A VOUT = 5V Ringing Frequency = 3.5MHz IOUT = 24mA Frequency = 263kHz Doc. No. MV-S103880-00 Rev. D Page 32 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Characteristics Switching Waveforms Figure 19: PWM Output Ripple Voltage VOUT 20mV/DIV 100ms/DIV VIN = 12V IOUT = 3A VOUT = 5V VOUT(P-P) = 40mV (Note) Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 33 88PH845 Datasheet 4.3 Load Transient Waveforms 4.3.1 Step-Down Regulator Figure 20: Fast Load Rise Time Figure 21: Slow Load Rise Time VSW VSW 10V/DIV VOUT 200mV/DIV ILOAD 10V/DIV VOUT 200mV/DIV ILOAD 2A/DIV IIND IIND 2A/DIV 5s/DIV 5s/DIV VIN = 12V COUT = 2x22F VIN = 12V COUT = 2x22F VOUT = 5V tRISE = 27A/s VOUT = 5V tRISE = 4A/s IOUT = 1A to 3A IOUT = 1A to 3A Figure 22: Fast Load Fall Times Figure 23: Slow Load Fall Time VSW VSW 10V/DIV VOUT 200mV/DIV ILOAD 2A/DIV IIND 10V/DIV 200mV/DIV VOUT ILOAD 2A/DIV IIND 5s/DIV 5s/DIV VIN = 12V COUT = 2x22F VIN = 12V COUT = 2x22F VOUT= 5V tFALL = 185A/s VOUT = 5V tFALL = 4.2A/s IOUT = 3A to 1A IOUT = 3A to 1A Doc. No. MV-S103880-00 Rev. D Page 34 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Functional Characteristics Load Transient Waveforms Figure 24: Load Transient Response VOUT Figure 25: Double-Pulsed Load Response 200mV/DIV ILOAD 2A/DIV VOUT 200mV/DIV ILOAD 2A/DIV 20s/DIV 20s/DIV VIN = 12V ILOAD = 1A to 3A VIN = 12V ILOAD = 1A to 3A VOUT = 5V tRISE = 30A/s VOUT = 5V tRISE = 30A/s COUT = 2x22F tFALL = 200A/s COUT = 2x22F tFALL = 200A/s Figure 26: Load Transient Response VOUT Figure 27: Double-Pulsed Load Response 200mV/DIV ILOAD 2A/DIV VOUT 200mV/DIV ILOAD 2A/DIV 20s/DIV 20s/DIV VIN = 12V ILOAD = 1A to 3A VIN = 12V ILOAD = 1A to 3A VOUT = 5V tRISE = 60A/s VOUT = 5V tRISE = 60A/s COUT = 4x22F tFALL = 150A/s COUT = 4x22 F tFALL = 150A/s Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 35 88PH845 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103880-00 Rev. D Page 36 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Typical Characteristics Efficiency 5 Typical Characteristics Unless otherwise noted, the following typical scope photographs were taken using test circuit shown in Figure 1 at TA = 25 C. 5.1 Efficiency Figure 28: Efficiency vs. Output Current Efficiency vs. Output Current (PWM Mode) Vin = 12V Efficiency vs. Output Current (DCM Mode) Vin = 12V 100 100 5.0V 5.0V 90 3.0V 2.5V 80 1.8V 1.5V 70 Efficiency (%) Efficiency (%) 3.3V 1.0V 0 1 2 3.0V 2.5V 80 1.8V 1.5V 70 1.2V 60 3.3V 90 1.2V 1.0V 60 0 3 1 2 3 Output Current (A) Output Current (A) Figure 29: Efficiency vs. Output Current in Log Scale Efficiency vs. Output Current (PWM Mode) Vin = 12V Efficiency vs. Output Current (DCM Mode) Vin = 12V 100 100 5.0V 3.0V 80 2.5V 1.8V 60 1.5V 1.2V 1.0V 40 0.01 0.1 1 3.3V 3.0V 60 2.5V 1.8V 40 1.5V 20 1.2V 1.0V 0 0.01 10 0.1 1 10 Output Current (A) Output Current (A) Copyright (c) 2009 Marvell May 27, 2009, 3.0 5.0V 80 Efficiency (%) Efficiency (%) 3.3V Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 37 88PH845 Datasheet 5.2 Load Regulation Figure 30: Output Voltage vs. Output Current Output Voltage vs. Output Current (PWM Mode) Vout = 1V Output Voltage vs. Output Current (PWM Mode) Vout = 2.5V 2.58 1.02 Output Voltage (V) Output Voltage (V) 1.03 1.01 1.00 0.99 Vin: 0.98 12V 0.97 2.55 2.53 2.50 2.48 Vin: 2.45 2.43 0 1 2 3 0 Output Current (A) 1 2 3 Output Current (A) Doc. No. MV-S103880-00 Rev. D Page 38 12V Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Typical Characteristics RDS (ON) Resistance 5.3 RDS (ON) Resistance Figure 31: Resistance vs. Input Voltage TOP Switch Resistance vs. Input Voltage BOTTOM Switch Resistance vs. Input Voltage 0.050 Resistance () Resistance () 0.090 0.080 0.070 0.060 TA = 25C 0.040 0.030 TA = 25C 0.020 0.010 0.050 9 10 11 12 13 9 14 10 11 12 13 14 Input Voltage (V) Input Voltage (V) Figure 32: Resistance vs. Temperature TOP Switch Resistance vs. Temperature BOTTOM Switch Resistance vs. Temperature 0.050 0.090 Resistance () Resistance () 0.100 0.080 0.070 0.060 Vin = 8V Vin = 14V 0.050 0.040 -40 -20 0 20 40 60 80 Temperature (C) 0.030 0.020 Vin = 8V Vin = 14V 0.010 0.000 -40 -20 0 20 40 60 80 Temperature (C) Copyright (c) 2009 Marvell May 27, 2009, 3.0 0.040 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 39 88PH845 Datasheet 5.4 IC Case and Inductor Temperature The following data was taken using a 1.4 square inch PCB 1 oz. copper and L = 6.9H. Actual results depend upon the size of the PCB proximity to other heat emitting components. Figure 33: Input Current vs. Output Current Input Current vs . Output Current Vin = 12V, TA = 25 C Input Current vs . Output Current Vin = 9V, TA = 25 C 1.5 2.0 5.0V 5.0V 3.3V 3.0V 2.5V 1.0 1.8V 1.5V 0.5 Input Current (A) Input Current (A) 3.3V 1.5 3.0V 1.0 2.5V 1.8V 1.5V 0.5 1.2V 1.2V 1.0V 1.0V 0.0 0.0 0 0.5 1 1.5 2 2.5 3 0 0.5 Output Current (A) 1 1.5 2 2.5 3 Output Current (A) Figure 34: IC Case Temperature vs. Output Current IC Case Temperature vs . Output Current Vin = 12V, TA = 25 C IC Case Temperature vs . Output Current Vin = 9V, TA = 25 C 80 80 3.0V 2.5V 50 1.8V 40 1.5V 1.2V 30 1.0V 20 0 0.5 1 1.5 2 2.5 Temperature ( C ) Temperature ( C ) 3.3V 60 70 3.3V 60 3.0V 2.5V 50 1.8V 40 1.5V 30 1.2V 1.0V 20 3 0 Output Current (A) 0.5 1 1.5 2 2.5 3 Output Current (A) Doc. No. MV-S103880-00 Rev. D Page 40 5.0V 5.0V 70 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Typical Characteristics IC Case and Inductor Temperature Figure 35: Inductor Temperature vs. Output Current Inductor Temperature vs . Output Current Vin = 12V, TA = 25 C Inductor Temperature vs . Output Current Vin = 9V, TA = 25 C 60 5.0V 5.0V 3.3V 50 3.0V 2.5V 40 1.8V 1.5V 30 1.2V 3.3V Temperature (C) Temperature ( C) 60 50 3.0V 2.5V 40 1.8V 1.5V 30 1.2V 1.0V 1.0V 20 20 0 0.5 1 1.5 2 2.5 3 0 Output Current (A) 1 1.5 2 2.5 3 Output Current (A) Copyright (c) 2009 Marvell May 27, 2009, 3.0 0.5 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 41 88PH845 Datasheet 5.5 Input Voltage Figure 36: Supply Current vs. Input Voltage Figure 37: Shutdown Supply Current vs. Input Voltage Supply Current vs. Input Voltage PFM Mode 2.9 2.9 2.8 2.8 Current (mA) Current (mA) Supply Current vs. Input Voltage PFM Mode 2.7 2.6 2.7 2.6 2.5 2.5 9.0 10.0 11.0 12.0 13.0 9.0 14.0 10.0 11.0 12.0 13.0 14.0 Input Voltage (V) Input Voltage (V) IOUT = No Load; VPFM = 0V IOUT = No Load; VEN = 0V Figure 38: Enable Threshold vs. Input Voltage EN Threshold vs. Input Voltage Threshold (V) 1.65 1.60 1.55 UTH-Enable 1.50 LTH-Disable 1.45 9 10 11 12 13 14 Input Voltage (V) IOUT = 10mA Doc. No. MV-S103880-00 Rev. D Page 42 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Typical Characteristics Input Voltage 5.5.1 Step-Down Regulator Figure 39: Output Voltage vs. Input Voltage Figure 40: Efficiency vs. Input Voltage Efficiency vs. Input Voltage Output Voltage vs. Input Voltage 100% 5.10 Efficiency 98% Voltage (V) 5.05 5.00 95% 93% 4.95 90% 4.90 9.0 9.0 10.0 11.0 12.0 13.0 10.0 14.0 11.0 12.0 13.0 14.0 Input Voltage (V) Input Voltage (V) IOUT = 750mA VOUT = 5V; IOUT = 1.5A Figure 41: Load Regulation vs. Input Voltage Figure 42: Frequency vs. Input Voltage Frequency vs. Input Voltage 550 Load Regulation vs. Input Voltage Frequency (kHz) Regulation 0.20% 0.10% 0.00% 525 500 475 -0.10% 450 9 -0.20% 9 10 11 12 13 14 10 11 12 13 14 Input Voltage (V) Input Voltage (V) VOUT = 5V; IOUT = 750mA - 3A VOUT = 5V; IOUT = 1.5A Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 43 88PH845 Datasheet Figure 43: Average Output Current Limit vs. Input Voltage Average Output Current Limit vs. Input Voltage Current (A) 5.0 4.5 4.0 3.5 3.0 9 10 11 12 13 14 Input Voltage (V) VIN = 12V Doc. No. MV-S103880-00 Rev. D Page 44 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Typical Characteristics Temperature 5.6 Temperature Figure 44: Supply Current vs. Temperature Figure 45: UVLO Threshold vs. Temperature Supply Current vs. Temperature PFM Mode UVLO Thresholds vs. Temperature 5 UTH 4.8 Voltage (V) Current (m A) 4 3 2 1 -40 -20 0 20 40 60 LTH 4.6 4.4 4.2 4 80 -40 Temperature (C) -20 0 20 40 60 80 Temperature (C) IOUT = No Load; VPFM = 0V IOUT = 10mA Figure 46: OVP Threshold vs. Temperature Figure 47: Enable Threshold vs. Temperature OVP Thresholds vs. Temperature Enable Threshold vs. Temperature HTH 18 1.8 LTH 17 Threshold (V ) Voltage (V) 19 16 15 -40 -20 0 20 40 Temperature (C) 60 80 UTH - Enable LTH - Disable 1.6 1.4 1.2 -40 -20 0 20 40 60 80 Temperature (C) IOUT = 10mA IOUT = 10mA Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 45 88PH845 Datasheet Figure 48: Shutdown Supply Current vs. Temperature Shutdown Supply Current vs.Temperature 20 Current (uA) 15 10 5 0 -40 -20 0 20 40 60 80 Temperature (C) IOUT = No Load; VEN = 0V Doc. No. MV-S103880-00 Rev. D Page 46 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Typical Characteristics Temperature 5.6.1 Step-Down Regulator Figure 49: Output Voltage vs. Temperature Figure 50: Efficiency vs. Temperature Buck Efficiency vs. Temperature 5.10 100% 5.05 98% Efficiency Voltage (V) Output Voltage vs. Temperature 5.00 95% 4.95 93% 4.90 -40 -20 0 20 40 60 90% 80 -40 -20 Temperature (C) 20 40 60 80 Temperature (C) VIN = 12V; IOUT = 750mA VIN = 12V; VOUT = 5V; IOUT = 1.5A Figure 51: Line Regulation vs. Temperature Figure 52: Load Regulation vs. Temperature Buck Line Regulation vs. Temperature Buck Load Regulation vs. Temperature 0.20% 0.20% 0.10% 0.10% Regulation Regulation 0 0.00% -0.10% 0.00% -0.10% -0.20% -0.20% -40 -20 0 20 40 60 80 -40 Temperature (C) 0 20 40 60 80 Temperature (C) VIN = 8V to 14V; VOUT = 5V; IOUT = 1.5A VIN = 12V; VOUT = 5V; IOUT = 750mA - 3A Copyright (c) 2009 Marvell May 27, 2009, 3.0 -20 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 47 88PH845 Datasheet Figure 53: Frequency vs. Temperature Figure 54: Average Output Current Limit vs. Temperature Frequency vs. Temperature 550 Average Output Current Limit vs. Tem perature 525 Current (A) Frequency (kHz) 5.0 500 475 450 -40 4.5 4.0 3.5 3.0 -40 -20 0 20 40 60 -20 80 40 60 80 VIN = 12V Doc. No. MV-S103880-00 Rev. D Page 48 20 Temperature (C) Temperature (C) VIN = 12V; VOUT = 5V; IOUT = 1.5A 0 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Applications Information PC Board Layout Considerations and Guidelines 6 Applications Information 6.1 PC Board Layout Considerations and Guidelines Warning: To avoid noise and abnormal operating behavior, follow these layout recommendations. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Copy the layout in Figure 56 and Figure 57 as much as possible, and use the recommended BOM in Section 6.2, Bill of Materials, on page 53. Contact the factory if substitutions are made. Do not layout the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor (C1) is a square wave with rise and fall times of 8 ns and slew rates as high as 300 A/s. At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt. Therefore, the input capacitor (C1) must be placed as close to the VIN and PGND pins with as short and wide trace as possible. Also, the VIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. The 88PH845 have two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is PGND at pin 10. Connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors is recommended for best results. See Figure 56. Keep the switching node (SW) away from the feedback pins and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle. Try not to route analog or digital lines in close proximity to the power supply, especially the SW node. If this cannot be avoided, shield these lines with a power plane placed between the SW node and the signal lines. Do not replace the Ceramic input or output capacitors with Tantalum capacitors! Place any type of capacitor in parallel with the input capacitor as long as the Ceramic input capacitor is placed next to the device. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage needs to be derated by 50%. Place any type of capacitor in parallel with the output capacitor. Replace the Ceramic output capacitors with low-ESR capacitors like the POSCAP from SANYO as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. Use planes for the input and output power to maintain good voltage filtering and to keep power losses low. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. Review the recommended solder pad layout and notes (see Section 7.3.1, Recommended Solder Pad Layout, on page 57). The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of cleaning flux residues from beneath the QFN package. Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 49 88PH845 Datasheet Figure 55: PCB Layout Schematic VOUT R1 100K R2 PG PWM PSET 18 17 16 0 Ohm PSET PWM VBS SGND SW VIN SW PGND 6 EN 88PH845 PGND 15 VSET 14 VOUT 13 EN 12 11 SW 10 L1 6.9uH 9 SW 4 5 VDD SW 3 VBS VSET SFB 8 C6 0.047uF/25V VDD SVIN VIN C7 4.7uF/25V 2 VCC 7 C8 4.7uF/25V 1 VIN PG U1 VCC R3 53.6K SW LP1 LP2 VIN C1 0.1uF/25V C2 10uF/25V I Cin C3 10uF/25V VOUT C4 22uF/6. 3V I Cout C5 22uF/6. 3V LP2 LP1 Caution: Do not float Pin 13 and Pin 17. Doc. No. MV-S103880-00 Rev. D Page 50 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Applications Information PC Board Layout Considerations and Guidelines 6.1.1 PC Board Layout Examples Actual board size = 900 mil x 830 mil Total copper layers = 2 Figure 56: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale) Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 51 88PH845 Datasheet Figure 57: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale) Doc. No. MV-S103880-00 Rev. D Page 52 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Applications Information Bill of Materials 6.2 Bill of Materials Table 13: 88PH845 BOM It e m Qty Ref M a nu fact ur er P a rt Number M a n u fa c tu r e r 1 1 U1 88PH845 Marvell 2 1 C1 TMK105BJ104KV-F Taiyo Yuden CAP CER .10F 25V X5R 0402 3 1 C7 C2012X5R1E475K TDK Corporation CAP CER 4.7F 25V X5R 0805 4 1 C8 C2012X5R1E475K TDK Corporation CAP CER 4.7F 25V X5R 0805 GRM32DR61E106KA12L Murata CAP CER 10F 25V 10% X5R 1210 GRM21BR60J226ME39L Murata CAP CER 22F 6.3V X5R 0805 20% CAP CER .047F 10% 25V X7R 0603 5 D e s c r ip t io n 12V Step-Down Regulator C2 2 6 C3 7 C4 2 8 C5 9 1 C6 06033C473KAT2A AVX Corporation 10 1 L1 FDV0840-6R9M TOKO 11 1 R1 ERJ-3GEYJ104V Panasonic--ECG 12 1 R2 RC0603JR-070RL Yageo America 13 1 R3 ERJ-3EKF5362V Panasonic--ECG Copyright (c) 2009 Marvell May 27, 2009, 3.0 FDV0840 Series, 6.9H, 4.5A, 41m (max), H=4mm, L=9.4mm, W=8.7mm RES 100K 1/10W 5% 0603 SMD RES 0.0 1/10W 5% 0603 SMD RES 53.6K 1/10W 1% 0603 SMD Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 53 88PH845 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103880-00 Rev. D Page 54 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 Mechanical Drawings Mechanical Drawings 7 Mechanical Drawings 7.1 Mechanical Drawings Figure 58: 4mm x 3mm 18-Pin FCQFN Mechanical Drawing 3 INDE X A RE A (D/2xE /2) 2x 2x TOP VIEW NX S E A TING P LA NE SIDE VIEW e 18Xb Terminal Tip 7 INDE X A RE A 6 (D/ 2x E/2) 4 1 15 18 BOTTOM VIEW 17XL ''A'' Copyright (c) 2009 Marvell May 28, 2009, 3.0 DETAIL 'A' Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 55 88PH845 Datasheet 7.2 Mechanical Dimensions Table 14: 4mm x 3mm 18-Pin FCQFN Dimensions S y m b ol D im e n s io n i n m m MIN A A1 0.00 A3 D i m e n s io n i n in c h NOM MAX 0.90 1.00 0.02 0.05 M IN 0.000 0.20 REF NOM MAX 0.035 0.039 0.001 0.002 0.008 REF b 0.20 0.25 0.30 0.008 0.010 0.012 D 2.90 3.00 3.10 0.114 0.118 0.122 E 3.90 4.00 4.10 0.153 0.157 0.161 e 0.50 BSC L 0.40 0.50 0.020 BSC 0.60 0.012 0.016 0.020 aaa 0.15 0.006 bbb 0.10 0.004 ccc 0.10 0.004 Notes: Dimensioning and tolerancing conform to ASME Y14.5M-1994 Drawing not to scale Dimensions are in Millimeters Terminal #1 identifier and terminal numbering convension Pin 1 (0.6mm) is longer than the other pins (0.5mm) Doc. No. MV-S103880-00 Rev. D Page 56 Copyright (c) 2009 Marvell Document Classification: Proprietary May 28, 2009, 3.0 Mechanical Drawings Typical Pad Layout Dimensions 7.3 Typical Pad Layout Dimensions 7.3.1 Recommended Solder Pad Layout Figure 59: 4mm x 3mm FCQFN-18 Land Pattern (mm) 0.75 1 0.50 Package Outline 3.00 4.30 0.25 0.65 3.30 4x3 FCQFN -18 Land Pattern (mm) 0.25 mm 0.25 mm Pad SM Pad SM 0.051 mm 2.0 mils Pad 0.148 mm QFN Lead with Non-Solder Mask Defined Terminal Notes: Top view The "1" indicates Pin 1 location Drawing not to scale Oversize solder mask by 4 mils over pad size (2 mil annular ring) 0.148mm solder mask between pads Tolerance 0.05mm Pin 1 (0.6mm) is longer than the other pins (0.5mm) Copyright (c) 2009 Marvell May 28, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 57 88PH845 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103880-00 Rev. D Page 58 Copyright (c) 2009 Marvell Document Classification: Proprietary May 28, 2009, 3.0 Part Order Numbering/Package Marking Part Order Numbering Scheme 8 Part Order Numbering/Package Marking 8.1 Part Order Numbering Scheme Figure 60 shows the part order numbering scheme. Refer to a Marvell Field Application Engineer (FAE) or sales representative for further information when ordering parts. Figure 60: Sample Part Number 88PH845 -B1-NFB1C000-xxxx Custom code (optional) Part number Custom code Custom code Temperature code C = Commercial I = Industrial Custom code Environmental code 1 = RoHS 6/6 compliant 2 = Green compliant Package code r 8.2 Part Ordering Options The standard ordering part numbers for the respective solutions are as follows: Table 15: Part Ordering Options P a c k a g e Ty p e P ar t O r d e r (b o ok i ng ) N u m b e r 18-pin QFN 4mm x 3mm 88PH845-B1-NFB1C000 18-pin QFN 4mm x 3mm 88PH845-B1-NFB1C000-T (Tape and Reel) Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 59 88PH845 Datasheet 8.3 Package Marking Figure 61 shows a sample package marking and pin 1 location. Figure 61: Package Marking and Pin 1 location Marvell logo and partial part number 00B1P YWW$$ Pin 1 location Power code, revision, assembly house code 00 = power code B1 = custom code P = assembly house code Date code and lot traceability code Y = year WW = work week $$ = Lot traceability code Note: The above example is not drawn to scale. Location of markings are approximate. Doc. No. MV-S103880-00 Rev. D Page 60 Copyright (c) 2009 Marvell Document Classification: Proprietary May 27, 2009, 3.0 A Revision History Table 16: Revision History D o c u m e n t Ty p e D o cu m e n t R e v i s io n Rev. D 1. 2. 3. 4. Update schematic (Fig 1) and in the Application Section. Update BOM. Update layout recommendations. Edit Soft Startup section 3.2. Copyright (c) 2009 Marvell May 27, 2009, 3.0 Doc. No. MV-S103880-00 Rev. D Document Classification: Proprietary Page 61 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster