88PH845-B1-NFB1C000-T - MARVELL TECHNOLOGY GROUP

Marvell. Moving Forward Faster

Doc. No. MV-S103880-00, Rev. D

May 27, 2009

Document Classification: Proprietary

Cover

88PH845

Field Programmable DSP

Switcher™

500kHz, 4.5A Peak Current-Limit, High Voltage

Synchronous Step-Down Regulator with

AnyVoltage™ Technology

Datasheet

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Note: Provides related information or information of special importance.

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Doc Status: 3.0 Technical Publication: 0.xx

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88PH845

Datasheet

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88PH845

Field Programmable DSP Switcher™

Datasheet

May 27, 2009, 3.0 Document Classification: Proprietary Page 3

PRODUCT OVERVIEW

The Marvell® 88PH845 device is a simple, easy to use

synchronous buck switching regulator. A digital control

algorithm provides a fast transient response and

requires no external compensation components,

minimizing the external component count. The output

voltage of the Marvell regulator can be set with external

resistors (one allows a minor range of settings, while two

are used to achieve a full range of program settings),

logic programmability, or a serial interface. The input

voltage range is 4.5V to 15.7V. The output voltage range

is 0.9V to 5.5V.

The step-down regulator is internally self-compensated

and requires no external compensation. The regulator

works with low-ESR output capacitors to simplify the

design, minimize board space, and reduce the amount of

external components. The switching frequency for the

step-down regulator is 500kHz, allowing the use of low

profile surface mount inductors and low value capacitors.

Features

3.0A DC output current

4.5V to 15.7V input operating range

0.9V to 5.5V output voltage

500kHz switching frequency

Stable with low-ESR ceramic output capacitors

Up to 95% efficiency

Internal soft startup

Serial/Logic Programmability

72 output voltage selections using AnyVoltageTM

Technology

RoHS 6/6 compliant package

4mm x 3mm QFN18 package

Applications

Point-of-load power supplies

Network Access Server (NAS)

Figure 1: 12V to 1.2V/3.0A Converter

Caution: This is a very high frequency device and proper PCB layout is required. Refer to Section 6,

Applications Information, on page 49 for further information.

88PH845

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Table of Contents

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Table of Contents

Table of Contents .......................................................................................................................................5

List of Figures.............................................................................................................................................7

List of Tables .............................................................................................................................................. 9

1 Signal Description .......................................................................................................................11

1.1 Pin Configurations...........................................................................................................................................11

1.2 Pin Type Definitions ........................................................................................................................................12

2 Electrical Specifications ............................................................................................................. 15

2.1 Absolute Maximum Ratings ............................................................................................................................15

2.2 Recommended Operating Conditions .............................................................................................................16

2.3 Electrical Characteristics.................................................................................................................................17

2.4 Switching Step-down Regulator ......................................................................................................................18

3 Functional Description................................................................................................................ 21

3.1 Overview .........................................................................................................................................................21

3.2 Soft Startup .....................................................................................................................................................22

3.3 Output Voltage Setting ....................................................................................................................................22

3.3.1 Logic Programmability ......................................................................................................................22

3.3.2 Serial Programmability......................................................................................................................24

3.3.3 Output Voltage—AnyVoltage™ Technology.....................................................................................26

3.4 Thermal Shutdown ..........................................................................................................................................28

3.5 Under Voltage Lockout (UVLO) ......................................................................................................................28

3.6 Input Over Voltage Protection (OVP) ..............................................................................................................29

3.7 Power Good (PG)............................................................................................................................................29

3.8 Hiccup Current Limit........................................................................................................................................30

4 Functional Characteristics ......................................................................................................... 31

4.1 Startup Waveforms .........................................................................................................................................31

4.2 Switching Waveforms......................................................................................................................................32

4.3 Load Transient Waveforms .............................................................................................................................34

4.3.1 Step-Down Regulator .......................................................................................................................34

5 Typical Characteristics ...............................................................................................................37

5.1 Efficiency.........................................................................................................................................................37

5.2 Load Regulation ..............................................................................................................................................38

5.3 RDS (ON) Resistance .....................................................................................................................................39

5.4 IC Case and Inductor Temperature.................................................................................................................40

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5.5 Input Voltage ...................................................................................................................................................42

5.5.1 Step-Down Regulator .......................................................................................................................43

5.6 Temperature....................................................................................................................................................45

5.6.1 Step-Down Regulator .......................................................................................................................47

6 Applications Information ............................................................................................................ 49

6.1 PC Board Layout Considerations and Guidelines...........................................................................................49

6.1.1 PC Board Layout Examples..............................................................................................................51

6.2 Bill of Materials................................................................................................................................................53

7 Mechanical Drawings ..................................................................................................................55

7.1 Mechanical Drawings ......................................................................................................................................55

7.2 Mechanical Dimensions ..................................................................................................................................56

7.3 Typical Pad Layout Dimensions......................................................................................................................57

7.3.1 Recommended Solder Pad Layout ...................................................................................................57

8 Part Order Numbering/Package Marking ..................................................................................59

8.1 Part Order Numbering Scheme.......................................................................................................................59

8.2 Part Ordering Options .....................................................................................................................................59

8.3 Package Marking ............................................................................................................................................60

A Revision History .......................................................................................................................... 61

List of Figures

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List of Figures

Figure 1: 12V to 1.2V/3.0A Converter................................................................................................................3

1 Signal Description ........................................................................................................................... 11

Figure 2: 4mm x 3mm FCQFN-18 Pin Diagram (Top View) ............................................................................11

2 Electrical Specifications ................................................................................................................. 15

3 Functional Description.................................................................................................................... 21

Figure 3: Block Diagram ..................................................................................................................................21

Figure 4: Soft Startup (1.0V, 1.5V, 2.5V, 3.3V, 5.0V) ......................................................................................22

Figure 5: Serial Programmability......................................................................................................................24

Figure 6: Startup and Soft Startup Sequences ................................................................................................27

Figure 7: VSET = 2.5V and PSET = -5% .........................................................................................................27

Figure 8: UVLO and OVP Waveforms .............................................................................................................29

Figure 9: Power Good Operating Waveform....................................................................................................29

Figure 10: Hiccup Period ...................................................................................................................................30

4 Functional Characteristics.............................................................................................................. 31

Figure 11: Startup Using the EN Pin .................................................................................................................31

Figure 12: Power Off Using the EN Pin .............................................................................................................31

Figure 13: Soft Start...........................................................................................................................................31

Figure 14: Hot Plug ............................................................................................................................................31

Figure 15: PWM Mode—2x22µF ......................................................................................................................32

Figure 16: PWM Mode—4x22µF .......................................................................................................................32

Figure 17: DCM Mode .......................................................................................................................................32

Figure 18: DCM Mode—Zoom...........................................................................................................................32

Figure 19: PWM Output Ripple Voltage ............................................................................................................33

Figure 20: Fast Load Rise Time ........................................................................................................................34

Figure 21: Slow Load Rise Time........................................................................................................................34

Figure 22: Fast Load Fall Times .......................................................................................................................34

Figure 23: Slow Load Fall Time .........................................................................................................................34

Figure 24: Load Transient Response.................................................................................................................35

Figure 25: Double-Pulsed Load Response ........................................................................................................35

Figure 26: Load Transient Response.................................................................................................................35

Figure 27: Double-Pulsed Load Response ........................................................................................................35

5 Typical Characteristics ................................................................................................................... 37

Figure 28: Efficiency vs. Output Current ............................................................................................................37

Figure 29: Efficiency vs. Output Current in Log Scale .......................................................................................37

Figure 30: Output Voltage vs. Output Current ...................................................................................................38

Figure 31: Resistance vs. Input Voltage ............................................................................................................39

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Figure 32: Resistance vs. Temperature.............................................................................................................39

Figure 33: Input Current vs. Output Current ......................................................................................................40

Figure 34: IC Case Temperature vs. Output Current.........................................................................................40

Figure 35: Inductor Temperature vs. Output Current.........................................................................................41

Figure 36: Supply Current vs. Input Voltage ......................................................................................................42

Figure 37: Shutdown Supply Current vs. Input Voltage .....................................................................................42

Figure 38: Enable Threshold vs. Input Voltage..................................................................................................42

Figure 39: Output Voltage vs. Input Voltage ......................................................................................................43

Figure 40: Efficiency vs. Input Voltage...............................................................................................................43

Figure 41: Load Regulation vs. Input Voltage....................................................................................................43

Figure 42: Frequency vs. Input Voltage .............................................................................................................43

Figure 43: Average Output Current Limit vs. Input Voltage ...............................................................................44

Figure 44: Supply Current vs. Temperature.......................................................................................................45

Figure 45: UVLO Threshold vs. Temperature....................................................................................................45

Figure 46: OVP Threshold vs. Temperature ......................................................................................................45

Figure 47: Enable Threshold vs. Temperature ..................................................................................................45

Figure 48: Shutdown Supply Current vs. Temperature......................................................................................46

Figure 49: Output Voltage vs. Temperature.......................................................................................................47

Figure 50: Efficiency vs. Temperature ...............................................................................................................47

Figure 51: Line Regulation vs. Temperature......................................................................................................47

Figure 52: Load Regulation vs. Temperature ....................................................................................................47

Figure 53: Frequency vs. Temperature..............................................................................................................48

Figure 54: Average Output Current Limit vs. Temperature................................................................................48

6 Applications Information ................................................................................................................ 49

Figure 55: PCB Layout Schematic.....................................................................................................................50

Figure 56: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale) ........................................................51

Figure 57: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale)...................................................52

7 Mechanical Drawings ...................................................................................................................... 55

Figure 58: 4mm x 3mm 18-Pin FCQFN Mechanical Drawing............................................................................55

Figure 59: 4mm x 3mm FCQFN-18 Land Pattern (mm).....................................................................................57

8 Part Order Numbering/Package Marking....................................................................................... 59

Figure 60: Sample Part Number ........................................................................................................................59

Figure 61: Package Marking and Pin 1 location ................................................................................................60

A Revision History ............................................................................................................................... 61

List of Tables

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List of Tables

1 Signal Description ............................................................................................................................ 11

Table 1: Pin Type Definitions..........................................................................................................................12

Table 2: Pin Description..................................................................................................................................12

2 Electrical Specifications ..................................................................................................................15

Table 3: Absolute Maximum Ratings ..............................................................................................................15

Table 4: Recommended Operating Conditions...............................................................................................16

Table 5: Electrical Characteristics ..................................................................................................................17

Table 6: Switching Step-down Regulator........................................................................................................18

3 Functional Description..................................................................................................................... 21

Table 7: Output Voltage Rise Time.................................................................................................................22

Table 8: VSET and PSET Logic Programming...............................................................................................23

Table 9: Data Field Default Values .................................................................................................................25

Table 10: Data Field Default Values .................................................................................................................25

Table 11: VSET and PSET Programming for 5% Resistors .............................................................................26

Table 12: VSET and PSET Programming Steps ..............................................................................................28

4 Functional Characteristics...............................................................................................................31

5 Typical Characteristics .................................................................................................................... 37

6 Applications Information .................................................................................................................49

Table 13: 88PH845 BOM..................................................................................................................................53

7 Mechanical Drawings .......................................................................................................................55

Table 14: 4mm x 3mm 18-Pin FCQFN Dimensions..........................................................................................56

8 Part Order Numbering/Package Marking........................................................................................59

Table 15: Part Ordering Options.......................................................................................................................59

A Revision History ............................................................................................................................... 61

Table 16: Revision History................................................................................................................................61

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Signal Description

Pin Configurations

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1Signal Description

1.1 Pin Configurations

Figure 2: 4mm x 3mm FCQFN-18 Pin Diagram (Top View)

12 SGND

14 SFB

15 VSET

VCC

SVIN

VDD

VBS

PGNDVIN SW

PSETPG PWM

VIN

11 SW

10 PGND

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1.2 Pin Type Definitions

Table 1: Pin Type Definitions

Pin Type Description

I Input only

O Output only

S Supply

NC Not Connected

GND Ground

Table 2: Pin Description

Pin No. Pin Name Pin Type Pin Function

1 VCC S Internal 5V Regulator Output

The internal control circuitry is powered from this voltage. This is a no

connect pin. Do not connect an external load to this source.

2 SVIN S Internal LDO Power Supply Input

Power supply input for the internal LDO for generating VCC and VDD.

Decouple with a 4.7µF ceramic capacitor to PGND.

3 VDD S Internal 5V Regulator Output

VDD supplies the boot-strap circuitry and internal MOSFET driver.

Do not connect an external load to this source.

4 VBS S Boot-Strap Voltage Node

Supply to the topside floating driver. Place a 0.047 µF ceramic

capacitor as close as possible to the VBS and SW pins.

5, 8, 11 SW O Switching Node

Internal top power MOSFET source. Connects to the output inductor.

6, 7 VIN S Power Input Voltage

Internal top power MOSFET drain. Connect a ceramic decoupling

capacitor between each VIN and PGND and position it as close as

possible to the device.

9, 10 PGND GND Power Ground

Connect to the (-) terminal of the input capacitors.

12 SGND GND Signal Ground

Must be routed separately from the PGND and connected to the (-)

terminal of the output capacitor.

13 EN I Enable

Logic high (≥2.0V) enables the regulator and logic low (≤0.8V) disables

the regulator. SW pin is high impedance when Enable is logic low.

Signal Description

Pin Type Definitions

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14 SFB I Switching Regulator Feedback

Senses the output voltage of the switching regulator.

15 VSET I Voltage Set

• Used for selecting the output voltage level, when it is connected to

SGND or VCC in conjunction with PSET connected to SGND or

VCC. See Table 8, VSET and PSET Logic Programming, on

page 23 for information.

• Connect to an external resistor to ground to set the output voltage

of the step-down switching regulator. See Table 11, VSET and

PSET Programming for 5% Resistors, on page 26 for resistor

values and Output Voltage Setting section. The total capacitance

across this pin and SGND should be equal to 25 pF or less. Use

resistor values with a tolerance of 5% or better.

• Do not float this pin.

16 PSET I Percent Set

• Used for selecting the output voltage level, when it is connected to

SGND or VCC in conjunction with VSET connected to SGND or

VCC. See Table 8, VSET and PSET Logic Programming, on

page 23 for information.

• Connect to an external resistor to ground to set the output voltage

of the step-down switching regulator. See Table 11, VSET and

PSET Programming for 5% Resistors, on page 26 for resistor

values and Output Voltage Setting section. Use resistor values with

a tolerance of 5% or better.

• Do not float this pin.

17 PWM I Operation Mode Control Input

• Connect the PWM pin to VCC to allow forced PWM operation.

Connect the PWM pin to SGND to allow SKIP operation mode at

light load.

• It also serves as a serial data input when it is connected to a

programming device. The input data to this pin is used to program

the output voltage (see Section 3.3.2, Serial Programmability,

on page 24). Do not share this pin with other serial interface

pins.

• Do not float this pin.

18 PG O Power Good (active high)

Open-drain output that indicates the status of the output voltage. An

external 100 kΩ pull-up resistor is connected between the PG pin and

VOUT

. The output is pulled to ground when the output voltage is not

within the specified tolerance and a 25µs falling edge deglitch delay

prevents tripping of the power good comparator due to high frequency

noise.

Table 2: Pin Description (Continued)

Pin No. Pin Name Pin Type Pin Function

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Electrical Specifications

Absolute Maximum Ratings

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2Electrical Specifications

2.1 Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings1

Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

1. Exceeding the absolute maximum rating may damage the device.

Parameter Range Units

VIN to PGND -0.3 to 18.0 V

VSW to PGND2

2. Capable of -1.0V to (VIN +0.3) for less than 50nS.

-0.3 to (VIN + 0.3) V

VSFB to SGND -0.3 to 6.0 V

VCC to SGND -0.3 to minimum (VIN + 0.3, 5.5) V

VDD to PGND -0.3 to minimum (VIN + 0.3, 5.5) V

VSET , VPSET to SGND -0.3 to (VCC + 0.3) V

VPWM to SGND -0.3 to (VCC + 0.3) V

VEN to SGND -0.3 to 16.0 V

VPG to SGND -0.3 to (VIN + 0.3) V

VBS to PGND3

3. During normal operation, VBS is periodically boosted to (VIN + VDD). However, do not externally force the VBS pin to

more than (VDD + 0.3V).

-0.3 to (VIN + 5.5) V

PGND to SGND -0.3 to +0.3 V

VIN to VSVIN -0.3 to +0.3 V

Operating Ambient Temperature Range4

4. Specifications over the -40°C to 85°C operating temperature ranges are assured by design, characterization, and

correlation with statistical process controls.

-40 to 85 °C

Maximum Junction Temperature 150 °C

Storage Temperature Range -65 to 150 °C

Lead Temperature (soldering, 10s) 300 °C

ESD Rating5 Human Body Model

5. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.

2.0 kV

ESD Rating Machine Model 200 V

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2.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions1

Symbol Parameter Min Typ Max Units

VIN Input Voltage 4.5 15.7 V

θJA Package Thermal Resistance261.5 °C/W

θJC 25.6 °C/W

TJMAX Maximum Operating Junction Temperature 125 °C

1. This device is not guaranteed to function outside the specified operating range.

2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board.

Electrical Specifications

Electrical Characteristics

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2.3 Electrical Characteristics

Table 5: Electrical Characteristics

The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10µF, C2 = C3

= 10µF, C4 = C5 = 22µF, C6 = 0.047µF, C7 = C8 = 4.7µF, L1 = 6.9µH, TA = 25 °C. Bold values indicate -40oC≤TA≤85oC.

Symbol Parameter Conditions Min Typ Max Units

VIN Input Voltage Range 4.5 12 15.7 V

IQTotal Quiescent Current No Load, VPWM = 0V 2.65 4 mA

ISVIN Shutdown Supply Current VEN = 0V 10 20 µA

VUVLO Under Voltage Lockout High Threshold, VIN increasing 4.4 4.5 V

Low Threshold, VIN decreasing 4.0 4.1

VOVP Over Voltage Lockout High Threshold, VIN increasing 16.7 17.5 V

Low Threshold, VIN decreasing 15.7 16.2

IEN EN Input Current VEN = 0V 0.1 1 µA

VEN = 12V 1.5 5

IPWM PWM Input Current VPWM = 5V 1.5 5 µA

VPWM = 0V 0.1 1

VIH EN and PWM Input Voltage

Threshold

2.0 V

VIL 0.4

TOTS Over-Temperature Thermal

Shutdown

TJ increasing (disables regulator) 150 °C

TJ decreasing (enables regulator) 100

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2.4 Switching Step-down Regulator

Table 6: Switching Step-down Regulator

The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10µF, C2 = C3

= 10µF, C4 = C5 = 22µF, C6 = 0.047µF, C7 = C8 = 4.7µF, L1 = 6.9µH, TA = 25 °C. Bold values indicate -40oC≤TA≤85oC.

Symbol Parameter Conditions Min Typ Max Unit

VOUT Output Voltage RVSET = 11k, PWM mode, ILOAD

= 300mA

1.000 V

TA=25C-3+3%

Over Temperature -4 +4 %

RVSET = 18k, PWM mode, ILOAD

= 300mA

1.200 V

TA=25C -2.5 +2.5 %

Over Temperature -3 +3 %

RVSET = 30k, PWM mode, ILOAD

= 300mA

1.500 V

TA=25C -2.5 +2.5 %

Over Temperature -3 +3 %

RVSET = 51k, PWM mode, ILOAD

= 300mA

1.800 V

TA=25C -2.5 +2.5 %

Over Temperature -3 +3 %

Electrical Specifications

Switching Step-down Regulator

May 27, 2009, 3.0 Document Classification: Proprietary Page 19

RVSET = 100k, PWM mode, ILOAD

= 300mA

2.500 V

VVSET = SGND, VPSET = SGND,

PWM mode, ILOAD = 300mA

TA=25C-2+2%

Over Temperature -3 +3 %

RVSET = 160k, PWM mode, ILOAD

= 300mA

3.000 V

VVSET = SGND, VPSET = VCC,

PWM mode, ILOAD = 300mA

TA=25C-2+2%

Over Temperature -3 +3 %

RVSET = 270k, PWM mode, ILOAD

= 300mA

3.300 V

VVSET = VCC, VPSET = SGND,

PWM mode, ILOAD = 300mA

TA=25C-2+2%

Over Temperature -3 +3 %

RVSET = 470k, PWM mode, ILOAD

= 300mA

5.000 V

VVSET = VCC, VPSET = VCC, PWM

mode, ILOAD = 300mA

TA=25C-2+2%

Over Temperature -3 +3 %

Table 6: Switching Step-down Regulator

The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10µF, C2 = C3

= 10µF, C4 = C5 = 22µF, C6 = 0.047µF, C7 = C8 = 4.7µF, L1 = 6.9µH, TA = 25 °C. Bold values indicate -40oC≤TA≤85oC.

Symbol Parameter Conditions Min Typ Max Unit

88PH845

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Percentage Set RPSET = 11k -10 %

RPSET = 18k -7.5

RPSET = 30k -5

RPSET = 51k -2.5

RPSET = 0k 0

RPSET = 100k 2.5

RPSET = 160k 5

RPSET = 270k 7.5

RPSET = 470k 10

VLNREG Output Voltage Line

Regulation

VIN = 8.0V to 14V

VOUT = 5.0V

ILOAD = IOUT(MAX) / 2

0.02 %

VLDREG Output Voltage Load

Regulation

VIN = 12V

VOUT = 5.0V

ILOAD = IOUT(MAX) / 4 to IOUT(MAX)

0.05 %

fSW Switching Frequency 500 kHz

DMAX Maximum Duty Cycle 95 %

ILIM Minimum Peak Switch Current

Limit

4.5 A

RDSON_HS High Side Switch On

Resistance

70 100 mΩ

RDSON_LS Low Side Switch On

Resistance

35 50 mΩ

VPGTH Power Good (PG) Threshold

Voltage

VOUT ≥ 1.35V VOUT

× 90%

VOUT ≤ 1.32V VOUT –

130mV

VPGL PG Output Low Voltage ISINK = 1 mA, VEN = 12V 0.4 V

tDEGLITCH Deglitch125 µs

tDELAY PG Delay 160 µs

1. See Figure 9 for reference.

Table 6: Switching Step-down Regulator

The following applies unless otherwise noted: Refer to schematic shown in Figure 1. VIN = VEN = 12V, C1 = 0.10µF, C2 = C3

= 10µF, C4 = C5 = 22µF, C6 = 0.047µF, C7 = C8 = 4.7µF, L1 = 6.9µH, TA = 25 °C. Bold values indicate -40oC≤TA≤85oC.

Symbol Parameter Conditions Min Typ Max Unit

Functional Description

Overview

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3Functional Description

3.1 Overview

The 88PH845 device incorporates a control architecture that minimizes the number of external

passive components, improves efficiency, and provides fast transient response. A non-linear control

algorithm is able to detect and react to severe load changes in less than 100 ns with no external

compensation components. Other features include under and over voltage lockout, over

temperature shutdown, power good detection, skip or forced Pulse Width Modulation (PWM)

operation, and cycle-by-cycle current limiting.

The output voltage is set by using logic control, serial interface, or external resistors. External

resistors connected to the VSET and PSET pins are measured once before startup. These two

resistors provide up to 72 output voltage options from 0.9V to 5.5V. These external resistors can be

eliminated by tying the VSET and PSET pin to VCC or GND, generating 2.5V, 3.0V, 3.3V, or 5.0V.

Some applications require voltage margining, which forces the output voltage a percentage above

and below its nominal value. In this case, the serial interface can be used to change the output ±0%,

±2.5%, ±5.0%, ±7.5%, ±10% or any one of the 72 voltage options.

Figure 3 shows an overall block diagram.

Figure 3: Block Diagram

OSCILLATOR

RESISTOR

SENSING

CIRCUITRY

DSP PWM

CONTROL

ANALOG-

DIGITAL

CONVERTER

SFB

PSET

VSET

C4-C5

R2R3

PGND

RESISTOR

NETWORK

Serial

Data

Interface

PWM

PGood

Vout

VBS

Vin

12V

FAULT

BAND-GAP

VOLTAGE

REFERENCE

OFF

SGND

THERMAL

SHUTDOWN

150°C

UNDER-

VOLTAGE

LOCKOUT

Vout

VDD

INTERNAL CIRCUITRY

POWER SUPPLY

C1–C3

VIN

VCC SVIN

Current

Sense

LDO

VDD

Current

Sense

DCM

PWM

88PH845

Datasheet

Page 22 Document Classification: Proprietary May 27, 2009, 3.0

3.2 Soft Startup

The 88PH845 controls the rise time of the output voltage, thereby dramatically reducing the inrush

current. The rise time is independent of output capacitance and load current (Figure 4).

3.3 Output Voltage Setting

3.3.1 Logic Programmability

The output voltage of the step-down switching regulator can be programmed for the standard output

voltages by connecting VSET and PSET pins to SGND and/or VCC (Table 8). This method

eliminates the use of external resistors to set the output voltage.

Table 7: Output Voltage Rise Time

Output Voltage(V) Rise Time (ms)

1.0 2.5

1.2 3

1.5 4.5

1.8 5

2.5 5

3.0 5

3.3 5

5.0 5

Figure 4: Soft Startup (1.0V, 1.5V, 2.5V, 3.3V, 5.0V)

VOUT

1V/DIV

1ms/DIV

Functional Description

Output Voltage Setting

May 27, 2009, 3.0 Document Classification: Proprietary Page 23

Table 8: VSET and PSET Logic Programming

VVSET VPSET VOUT

SGND SGND 2.5V

SGND VCC 3.0V

VCC SGND 3.3V

VCC VCC 5.0V

88PH845

Datasheet

Page 24 Document Classification: Proprietary May 27, 2009, 3.0

3.3.2 Serial Programmability

The output voltage of the step-down switching regulator can also be programmed by using 18-bit

serial data into the PWM pin.

Warning: Do not share the PWM pin with other serial interface pins.

Figure 5: Serial Programmability

BIT2

"1"

Pulse

"0"

pulse

"0"

pulse

"0"

pulse

"0"

pulse

"0"

pulse

"1"

Pulse

"1"

Pulse

"1"

Pulse

"1"

Pulse

DATA FIELD

D7 D6 D5 D4 D3 D2 D1 D0

The period of a pulse is 1 μs ±200 ns

HIGH

> V

Low

< V

HIGH

LOW

For "1" pulse, the high is 0.75 μs ±150 ns and the low

period is 0.25 μs ±50 ns

For "0" pulse, the high is 0.25 μs ±50 ns and the low

period is 0.75 μs ±150 ns

LOW

HIGH

The write operation:

1) Each write sequence needs 18 pulses to complete.

2) During a non-write operation, the input needs to be at V

LOW

(<V

3) In between two successive write operations, the PWM input needs to be at V

LOW

(<V

)

for a minimum of 10 μs.

Write

sequence

Write

sequence

Low for at least 10 μs

WRITE MODE

"1" pulse

"0" pulse

BIT7 BIT6 BIT5 BIT4 BIT3 BIT1 BIT0

Address

Chip

Select

Start Stop

Functional Description

Output Voltage Setting

May 27, 2009, 3.0 Document Classification: Proprietary Page 25

The first 4 bits (MSB) of the data field are used to select the output voltage where the second 4 bits

(LSB) of the data field are used to trim the output voltage (percent of output voltage). Table 9 shows

the default value for the data field.

The value for position 7 and 3 of the register will enable use of either logic or serial output voltage

programmability. Bit value of "0" for positions 7 and 3 will enable the resistor/logic programmability

and the output voltage will be set according to Section 3.3.1, Logic Programmability . A bit value of 1

enables serial programmability.

Table 10 shows the output voltage and percent set.

All combinations of the VSET (shown above) can be used with all combinations of the PSET (shown

above) to provide maximum flexibility in output voltage selection.

Table 9: Data Field Default Values

Description Voltage Set Percent Set

Default Value 00100100

Table 10: Data Field Default Values

VSET VOUT (V) PSET Percent Set

1 0 0 0 1.0 1 0 0 0 -10%

1 0 0 1 1.2 1 0 0 1 -7.5%

1 0 1 0 1.5 1 0 1 0 -5.0%

1 0 1 1 1.8 1 0 1 1 -2.5%

1 1 0 0 2.5 1 1 0 0 +2.5%

1 1 0 1 3.0 1 1 0 1 +5.0%

1 1 1 0 3.3 1 1 1 0 +7.5%

1 1 1 1 5.0 1 1 1 1 +10%

88PH845

Datasheet

Page 26 Document Classification: Proprietary May 27, 2009, 3.0

3.3.3 Output Voltage—AnyVoltage™ Technology

The output voltage of the step-down switching regulator is programmed by using Ta b l e 11 to select

resistor values for the VSET and PSET pins. The VSET pin sets the output voltage, and the PSET

pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 100kΩ

resistor is selected for the VSET pin, and an 11kΩ resistor is selected for the PSET pin. The 100kΩ

resistor sets the output voltage to 2.5V and the 11 kΩ resistor trims the set voltage by -10%.

Using a VSET resistor value greater than 619kΩ or less than 7.68kΩ disables the step-down

switching regulator and sets the SW pin to high impedance. If the VSET resistor value is outside the

5% tolerance, the output can be either higher or lower than the set voltage.

Using resistor values greater than 619kΩ or less than 7.68kΩ for the PSET pin does not affect the

set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor,

the percent value is either higher or lower if the PSET resistor's value is outside the 5% tolerance.

The VSET and PSET resistors are read once during startup before the output voltage is turned on.

After the output voltage is turned on, the output voltage can be changed to different values using the

serial programming interface. Otherwise to configure the output to a different voltage, power has to

recycle or the device must turn OFF and back ON using the enable pin.

Figure 6 shows the startup waveforms of the 88PH845. Once the input voltage (VIN) is above the

Under Voltage Lockout (UVLO) Upper Threshold (UTH), the VSET and PSET pins become active.

Current is first sourced out of the PSET pin and then the VSET pin, in exponentially increasing steps.

After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V

reference. If the VSET voltage is below internal reference voltage, then the current source proceeds

to the next set. Once the VSET voltage is above the internal reference voltage the sequence stops

and the output voltage (VOUT) is allowed to turn-on.

Figure 7 shows the VSET and PSET waveform for VSET = 2.5V and PSET = -5% output. The

88PH845 keeps track of the number of many steps required to determine the appropriate output

voltage. Table 12 provides the number of steps necessary for each output voltage option. Using a

VSET resistor of 100kΩ requires the current source to step five times, and a PSET resistor of 30kΩ

requires seven steps.

Table 11: VSET and PSET Programming for 5% Resistors

PSET

-10% -7.50% -5.00% -2.50% 2.50% 5.00% 7.50% 10%

11k 18k 30k 51k GND 100k 160k 270k 470k

VSET

11k 0.900 0.925 0.950 0.975 1.00 1.025 1.050 1.075 1.100

18k 1.080 1.110 1.140 1.170 1.20 1.230 1.260 1.290 1.320

30k 1.350 1.388 1.425 1.463 1.50 1.538 1.575 1.613 1.650

51k 1.620 1.665 1.710 1.755 1.80 1.845 1.890 1.935 1.980

100k 2.250 2.313 2.375 2.438 2.50 2.563 2.625 2.688 2.750

160k 2.700 2.775 2.850 2.925 3.00 3.075 3.150 3.225 3.300

270k 2.970 3.053 3.135 3.218 3.30 3.383 3.465 3.548 3.630

470k 4.500 4.625 4.750 4.875 5.00 5.125 5.250 5.375 5.500

Functional Description

Output Voltage Setting

May 27, 2009, 3.0 Document Classification: Proprietary Page 27

Figure 6: Startup and Soft Startup Sequences

VIN

VOUT

VVSET

VPSET

5V/DIV

2V/DIV

5ms/DIV

Figure 7: VSET = 2.5V and PSET = -5%

VVSET

VPSET

500 mV/DIV

200µs/DIV

88PH845

Datasheet

Page 28 Document Classification: Proprietary May 27, 2009, 3.0

The 88PH845 provide an innovative technique to set the output voltage. During startup they read the

value of external resistors, which are located outside the regulator's feedback loop. By placing the

output voltage programming resistor outside the regulator's feedback loop, its tolerance does not

affect the accuracy of the output voltage. In conventional designs, adjustable regulators use 1%

resistors to set the output voltage. However, these resistors are located inside the feedback loop,

introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial

accuracy of 3%. Whereas, the 88PH845 initial accuracy is 2% for any output voltages.

The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The

output voltage can potentially be programmed to the lower output voltage if there is contamination,

which introduces excessive leakage current on the VSET and PSET pin, especially for a RVSET and

RPSET of 470 kΩ. The parasitic resistance on these nodes must be greater than 3 MΩ, and the stray

capacitance must be less than 25pF. Otherwise, a 5.0V output can potentially end up at 3.3V.

3.4 Thermal Shutdown

When the junction temperature of the 88PH845 exceeds OTS high threshold, the thermal shutdown

circuitry disables the step-down regulator. The step-down switching regulator is enabled when the

junction temperature is decreased to OTS low threshold.

3.5 Under Voltage Lockout (UVLO)

The Under Voltage Lockout (UVLO) feature insures that both internal MOSFETs have adequate

voltage levels to operate properly. When the input voltage drops below UVLO low threshold, both

MOSFETs remain off until the input rises above UVLO high threshold. See section 2.3 for the UVLO

low and high threshold voltages.

Table 12: VSET and PSET Programming Steps

Step VOUT (V) RVSET (kΩ)Step PSET (%) RPSET (kΩ)

1Table 8 0V or VCC 1 Tab l e 8 0V or VCC

2 5.0 470 2 +10 470

3 3.3 270 3 +7.5 270

4 3.0 160 4 +5.0 160

5 2.5 100 5 +2.5 100

61.8516-2.551

71.5307-5.030

81.2188-7.518

9 1.0 11 9 -10 11

Functional Description

Input Over Voltage Protection (OVP)

May 27, 2009, 3.0 Document Classification: Proprietary Page 29

3.6 Input Over Voltage Protection (OVP)

The Over Voltage Protection (OVP) feature uses a comparator to guard against transient

overshoots, as well as other serious conditions, that may damage the device. When the input

voltage is above OVP high threshold both internal N-channel MOSFETs are turned off until the input

voltage drops below OVP low threshold. See section 2.3 for the OVP low and high threshold

voltages.

3.7 Power Good (PG)

The Power Good (PG) pin is an active-high, open-drain output. The output is held low when the

output voltage of the step-down regulator is below the threshold. When the output voltage is above

the threshold for more than tDELAY (160µs typical), the power good signal goes high. Setting the

output voltage greater than 1.32V, the threshold voltage is 0.9% * VOUT (typical). Setting the output

voltage less than 1.32V, the threshold voltage is VOUT - 130mV (typical). A built-in tDEGLITCH (25µs

typical) delay is incorporated to prevent nuisance tripping.

Figure 8: UVLO and OVP Waveforms

OVP_HTH

UVLO_HTH

UVLO_LTH

OVP_LTH

BUCK Output Disable

BUCK Output Enable

VIN

Figure 9: Power Good Operating Waveform

DELAY

DEGLITCH

< t

DEGLITCH

PG _PULLUP

× I

PGL

PG_TH

88PH845

Datasheet

Page 30 Document Classification: Proprietary May 27, 2009, 3.0

3.8 Hiccup Current Limit

The “Hiccup” short-circuit protection is an unique feature among switching regulators. Hiccup mode

offers extra protection against over-current situations since it limits the average current to the load,

reducing power dissipation and case temperature of the device. When the current-sense circuit sees

an over-current condition together with a low output voltage condition (Vout < 0.4V typical), the

88PH845 device shuts off for about 12ms and then tries to startup again (see Figure 10). If the

over-load condition is removed, the device will startup normally; otherwise, the device will see

another over-current event and shut off again, repeating the cycle.

Figure 10: Hiccup Period

VSW

IOUT

5.0V/DIV

5.0A/DIV

10 ms/DIV

Functional Characteristics

S tar tup Waveform s

May 27, 2009, 3.0 Document Classification: Proprietary Page 31

4Functional Characteristics

Note: Unless otherwise specified, all scope pictures were taken using test circuit shown in Figure 1

in this datasheet. TA = 25°C

4.1 Startup Waveforms

When the input voltage rises above the UVLO’s upper threshold, there is a delay (6ms typical)

before the step-down regulator’s output voltage powers on.

VEN

VOUT

Figure 11: Startup Using the EN Pin

5V/DIV

2V/DIV

VEN

VOUT

Figure 12: Power Off Using the EN Pin

5V/DIV

2V/DIV

2ms/DIV 2ms/DIV

VIN = 12V ILOAD = 10mA VIN = 12V ILOAD = 10mA

VOUT = 5V VOUT = 5V

VIN

VOUT

VPG

Figure 13: Soft Start

5V/DIV

VIN

VOUT

VPG

Figure 14: Hot Plug

5V/DIV

10ms/DIV 10ms/DIV

VIN = 12V ILOAD = No load VIN = 12V ILOAD = No load

VOUT = 5V VOUT = 5V

88PH845

Datasheet

Page 32 Document Classification: Proprietary May 27, 2009, 3.0

4.2 Switching Waveforms

Note: For repeatability of measuring output ripple (VOUT(P-P)) for the BUCK regulator, the standard

test procedure limits the scope bandwidth to 20MHz and uses a coax cable with very short leads

terminated into 50Ω. The coax leads must be routed away from the switching node as much as

possible.

VSW

IIND

VOUT

VIN

Figure 15: PWM Mode—2x22µF

10V/DIV

2A/DIV

50 mV/DIV

VSW

IIND

VOUT

VIN

Figure 16: PWM Mode—4x22µF

10V/DIV

2A/DIV

50 mV/DIV

1µs/DIV 1µs/DIV

CIN = 2x22µF VIN(P-P) = 65.0mV CIN = 4x22µF VIN(P-P) = 33.4mV

VIN = 12V IIND(P-P) = 1.11A VIN = 12V IIND(P-P) = 1.13A

VOUT = 5V IIND(PK) = 3.57A VOUT = 5V IIND(PK) = 3.59A

IOUT = 3A Frequency = 507kHz IOUT = 3A Frequency = 510kHz

VOUT(P-P) = 30mV (Note) VOUT(P-P) = 28mV (Note)

VSW

VOUT

IIND

Figure 17: DCM Mode

10V/DIV

50 mV/DIV

1A/DIV

VSW

VOUT

IIND

Figure 18: DCM Mode—Zoom

10V/DIV

50 mV/DIV

1A/DIV

2µs/DIV 1µs/DIV

VIN = 12V VOUT(P-P) = 55mV (Note) VIN = 12V IOUT = 24mA

VOUT = 5V IIND(PK) = 0.76A VOUT = 5V Ringing Frequency = 3.5MHz

IOUT = 24mA Frequency = 263kHz

Functional Characteristics

Switching Waveforms

May 27, 2009, 3.0 Document Classification: Proprietary Page 33

VOUT

Figure 19: PWM Output Ripple Voltage

20mV/DIV

100ms/DIV

VIN = 12V IOUT = 3A

VOUT = 5V VOUT(P-P) = 40mV (Note)

88PH845

Datasheet

Page 34 Document Classification: Proprietary May 27, 2009, 3.0

4.3 Load Transient Waveforms

4.3.1 Step-Down Regulator

VSW

VOUT

ILOAD

IIND

Figure 20: Fast Load Rise Time

10V/DIV

200mV/DIV

2A/DIV

VSW

VOUT

ILOAD

IIND

Figure 21: Slow Load Rise Time

10V/DIV

200mV/DIV

2A/DIV

5µs/DIV 5µs/DIV

VIN = 12V COUT = 2x22µF VIN = 12V COUT = 2x22µF

VOUT = 5V tRISE = 27A/µs VOUT = 5V tRISE = 4A/µs

IOUT = 1A to 3A IOUT = 1A to 3A

VSW

VOUT

ILOAD

IIND

Figure 22: Fast Load Fall Times

10V/DIV

200mV/DIV

2A/DIV

VSW

VOUT

ILOAD

IIND

Figure 23: Slow Load Fall Time

10V/DIV

200mV/DIV

2A/DIV

5µs/DIV 5µs/DIV

VIN = 12V COUT = 2x22µF VIN = 12V COUT = 2x22µF

VOUT= 5V tFALL = 185A/µs VOUT = 5V tFALL = 4.2A/µs

IOUT = 3A to 1A IOUT = 3A to 1A

Functional Characteristics

Load Transient Waveforms

May 27, 2009, 3.0 Document Classification: Proprietary Page 35

VOUT

ILOAD

Figure 24: Load Transient Response

200mV/DIV

2A/DIV

VOUT

ILOAD

Figure 25: Double-Pulsed Load

Response

200mV/DIV

2A/DIV

20µs/DIV 20µs/DIV

VIN = 12V ILOAD = 1A to 3A VIN = 12V ILOAD = 1A to 3A

VOUT = 5V tRISE = 30A/µs VOUT = 5V tRISE = 30A/µs

COUT = 2x22µF tFALL = 200A/µs COUT = 2x22µF tFALL = 200A/µs

VOUT

ILOAD

Figure 26: Load Transient Response

200mV/DIV

2A/DIV

VOUT

ILOAD

Figure 27: Double-Pulsed Load

Response

200mV/DIV

2A/DIV

20µs/DIV 20µs/DIV

VIN = 12V ILOAD = 1A to 3A VIN = 12V ILOAD = 1A to 3A

VOUT = 5V tRISE = 60A/µs VOUT = 5V tRISE = 60A/µs

COUT = 4x22µF tFALL = 150A/µs COUT = 4x22 µF tFALL = 150A/µs

88PH845

Datasheet

Page 36 Document Classification: Proprietary May 27, 2009, 3.0

THIS PAGE INTENTIONALLY LEFT BLANK

Typical Characteristics

Efficiency

May 27, 2009, 3.0 Document Classification: Proprietary Page 37

5Typical Characteristics

Unless otherwise noted, the following typical scope photographs were taken using test circuit shown

in Figure 1 at TA = 25C.

5.1 Efficiency

Figure 28: Efficiency vs. Output Current

Figure 29: Efficiency vs. Output Current in Log Scale

Efficiency vs. Output Current (DCM Mode)

Vin = 12V

100

0123

Output Current (A)

Efficiency (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Efficiency vs. Output Current (PWM Mode)

Vin = 12V

100

0123

Output Current (A)

Efficiency (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Efficiency vs. Output Current (DCM Mode)

Vin = 12V

100

0.01 0.1 1 10

Output Current (A)

Efficie ncy (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Efficiency vs. Output Current (PWM Mode)

Vin = 12V

100

0.01 0.1 1 10

Output Current (A)

Efficiency (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

88PH845

Datasheet

Page 38 Document Classification: Proprietary May 27, 2009, 3.0

5.2 Load Regulation

Figure 30: Output Voltage vs. Output Current

Output Voltage vs. Output Current (PWM Mode)

Vout = 1V

0.97

0.98

0.99

1.00

1.01

1.02

1.03

0123

Output Current (A)

Output Voltage (V)

Output Voltage vs. Output Current (PWM Mode)

Vout = 2.5V

2.43

2.45

2.48

2.50

2.53

2.55

2.58

0123

Output Current (A)

Output Voltage (V)

12V

Vin:

12V

Vin:

Typical Characteristics

RDS (ON) Resistance

May 27, 2009, 3.0 Document Classification: Proprietary Page 39

5.3 RDS (ON) Resistance

Figure 31: Resistance vs. Input Voltage

Figure 32: Resistance vs. Temperature

TOP Switch

Resistance vs. Input Voltage

0.050

0.060

0.070

0.080

0.090

9 1011121314

Input Voltage (V)

Resistance (Ω)

TA = 25ºC

BOTTOM Switch

Resistance vs. Input Voltage

0.010

0.020

0.030

0.040

0.050

9 1011121314

Input Voltage (V)

Resistance (Ω)

TA = 25ºC

TOP Switch

Resistance vs. Temperature

0.040

0.050

0.060

0.070

0.080

0.090

0.100

-40-200 20406080

Temperature (ºC)

Resistance (Ω)

Vin = 8V

Vin = 14V

BOTTOM Switch

Resistance vs. Temperature

0.000

0.010

0.020

0.030

0.040

0.050

-40 -20 0 20 40 60 80

Temperature (ºC)

Resistance (Ω)

Vin = 8V

Vin = 14V

88PH845

Datasheet

Page 40 Document Classification: Proprietary May 27, 2009, 3.0

5.4 IC Case and Inductor Temperature

The following data was taken using a 1.4 square inch PCB 1 oz. copper and L = 6.9µH. Actual

results depend upon the size of the PCB proximity to other heat emitting components.

Figure 33: Input Current vs. Output Current

Figure 34: IC Case Temperature vs. Output Current

Input Current vs . Output Current

Vin = 9V, TA = 25C

0.0

0.5

1.0

1.5

2.0

00.511.522.53

Output Current (A)

Input Current (A)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Input Current vs . Output Current

Vin = 12V, TA = 25C

0.0

0.5

1.0

1.5

00.511.522.53

Output Current (A)

Input Current (A)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

IC Case Temperature vs . Output Current

Vin = 9V, TA = 25C

0 0.5 1 1.5 2 2 .5 3

Output Current (A)

Temperature (°C)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

IC Case Temperature vs . Output Current

Vin = 12V, TA = 25C

0 0.5 1 1.5 2 2.5 3

Output Current (A)

Temperature (°C )

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Typical Characteristics

IC Case and Inductor Temperature

May 27, 2009, 3.0 Document Classification: Proprietary Page 41

Figure 35: Inductor Temperature vs. Output Current

Inductor Temperature vs . Output Current

Vin = 9V, TA = 25C

00.511.522.53

Output Current (A)

Temperature (°C)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Inductor Temperature vs . Output Current

Vin = 12V, TA = 25C

0 0.5 1 1.5 2 2.5 3

Output Current (A)

Temperature (°C )

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

88PH845

Datasheet

Page 42 Document Classification: Proprietary May 27, 2009, 3.0

5.5 Input Voltage

Figure 36: Supply Current vs. Input

Voltage

Figure 37: Shutdown Supply Current vs.

Input Voltage

IOUT = No Load; VPFM = 0V IOUT = No Load; VEN = 0V

Figure 38: Enable Threshold vs. Input Voltage

IOUT = 10mA

Supply Current vs. Input Voltage

PFM Mode

2.5

2.6

2.7

2.8

2.9

9.0 10.0 11.0 12.0 13.0 14.0

Input Voltage (V)

Current (mA)

Supply Current vs. Input Voltage

PFM Mode

2.5

2.6

2.7

2.8

2.9

9.0 10.0 11.0 12.0 13.0 14.0

Input Voltage (V)

Current (mA)

EN Threshold vs. Input Voltage

1.45

1.50

1.55

1.60

1.65

9 1011121314

Input Voltage (V)

Threshold (V)

UTH-Enable

LTH-Disable

Typical Characteristics

Input Voltage

May 27, 2009, 3.0 Document Classification: Proprietary Page 43

5.5.1 Step-Down Regulator

Figure 39: Output Voltage vs. Input Voltage Figure 40: Efficiency vs. Input Voltage

IOUT = 750mA VOUT = 5V; IOUT = 1.5A

Figure 41: Load Regulation vs. Input

Voltage

Figure 42: Frequency vs. Input Voltage

VOUT = 5V; IOUT = 750mA - 3A VOUT = 5V; IOUT = 1.5A

Output Voltage vs. Input Voltage

4.90

4.95

5.00

5.05

5.10

9.0 10.0 11.0 12.0 13.0 14.0

Input Voltage (V)

Voltage (V)

Efficiency vs. Input Voltage

90%

93%

95%

98%

100%

9.0 10.0 11.0 12.0 13.0 14.0

Input Voltage (V)

Efficiency

Load Regulation vs. Input Voltage

-0.20%

-0.10%

0.00%

0.10%

0.20%

91011121314

Input Voltage (V)

Regulation

Frequency vs. Input Voltage

450

475

500

525

550

9 1011121314

Input Voltage (V)

Frequency (kHz)

88PH845

Datasheet

Page 44 Document Classification: Proprietary May 27, 2009, 3.0

Figure 43: Average Output Current Limit vs. Input Voltage

VIN = 12V

verage Output Current Limit vs. Input

Voltage

3.0

3.5

4.0

4.5

5.0

9 1011121314

Input Voltage (V)

Current (A)

Typical Characteristics

Temperature

May 27, 2009, 3.0 Document Classification: Proprietary Page 45

5.6 Temperature

Figure 44: Supply Current vs. Temperature Figure 45: UVLO Threshold vs.

Temperature

IOUT = No Load; VPFM = 0V IOUT = 10mA

Figure 46: OVP Threshold vs. Temperature Figure 47: Enable Threshold vs.

Temperature

IOUT = 10mA IOUT = 10mA

Supply Current vs. Temperature

PFM Mode

-40-20 0 20406080

Temperature (°C)

Current (mA)

UVLO Thresholds vs. Temperature

4.2

4.4

4.6

4.8

-40 -20 0 20 40 60 80

Temperature (°C)

Voltage (V)

UTH

LTH

OVP Thresholds vs. Temperature

-40 -20 0 20 40 60 80

Temperature (°C)

Voltage (V)

HTH

LTH

Enable Threshold vs. Temperature

1.2

1.4

1.6

1.8

-40-200 20406080

Temperature (°C)

Threshold (V)

UTH - Enable

LTH - Disable

88PH845

Datasheet

Page 46 Document Classification: Proprietary May 27, 2009, 3.0

Figure 48: Shutdown Supply Current vs.

Temperature

IOUT = No Load; VEN = 0V

Shutdown Supply Current vs.Temperature

-40-20 0 20406080

Temperature (°C)

Current (uA)

Typical Characteristics

Temperature

May 27, 2009, 3.0 Document Classification: Proprietary Page 47

5.6.1 Step-Down Regulator

Figure 49: Output Voltage vs. Temperature Figure 50: Efficiency vs. Temperature

VIN = 12V; IOUT = 750mA VIN = 12V; VOUT = 5V; IOUT = 1.5A

Figure 51: Line Regulation vs.

Temperature

Figure 52: Load Regulation vs.

Temperature

VIN = 8V to 14V; VOUT = 5V; IOUT = 1.5A VIN = 12V; VOUT = 5V; IOUT = 750mA - 3A

Output Voltage vs. Temperature

4.90

4.95

5.00

5.05

5.10

-40-20 0 20406080

Temperature (°C)

Voltage (V)

Buck Efficiency vs. Temperature

90%

93%

95%

98%

100%

-40-200 20406080

Temperature (°C)

Efficienc

Buck Line Regulation vs. Temperature

-0.20%

-0.10%

0.00%

0.10%

0.20%

-40 -20 0 20 40 60 80

Temperature (°C)

Regulation

Buck Load Regulation vs. Temperature

-0.20%

-0.10%

0.00%

0.10%

0.20%

-40-200 20406080

Temperature (°C)

Regulation

88PH845

Datasheet

Page 48 Document Classification: Proprietary May 27, 2009, 3.0

Figure 53: Frequency vs. Temperature Figure 54: Average Output Current Limit

vs. Temperature

VIN = 12V; VOUT = 5V; IOUT = 1.5A VIN = 12V

Frequency vs. Temperature

450

475

500

525

550

-40-200 20406080

Temperature (°C)

Frequency (kHz)

Average Output Current Limit vs. Temperature

3.0

3.5

4.0

4.5

5.0

-40-200 20406080

Temperature (°C)

Current (A)

Applications Information

PC Board Layout Considerations and Guid el ines

May 27, 2009, 3.0 Document Classification: Proprietary Page 49

6Applications Information

6.1 PC Board Layout Considerations and Guidelines

1. Copy the layout in Figure 56 and Figure 57 as much as possible, and use the recommended

BOM in Section 6.2, Bill of Materials, on page 53. Contact the factory if substitutions are made.

2. Do not layout the inductor first. The input capacitor placement is the most critical for proper

operation. The AC current circulating through the input capacitor (C1) is a square wave with rise

and fall times of 8 ns and slew rates as high as 300 A/µs. At these fast slew rates, stray PCB

inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt.

Therefore, the input capacitor (C1) must be placed as close to the VIN and PGND pins with as

short and wide trace as possible. Also, the VIN and PGND traces must be placed on the top

layer. This will isolate the fast AC currents from interfering with the analog ground plane.

3. The 88PH845 have two internal grounds, analog (SGND) and power (PGND). The analog

ground ties to all the noise sensitive signals while the power ground ties to the higher current

power paths. Noise on an analog ground can cause problems with the IC's internal control and

bias signals. For this reason, separate analog and power ground traces are recommended. The

signal ground is connected to the power ground at one point, which is PGND at pin 10.

4. Connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor.

A back-to-back placing of bypass capacitors is recommended for best results. See Figure 56.

5. Keep the switching node (SW) away from the feedback pins and all sensitive signal nodes,

minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a

right angle.

6. Try not to route analog or digital lines in close proximity to the power supply, especially the SW

node. If this cannot be avoided, shield these lines with a power plane placed between the SW

node and the signal lines.

7. Do not replace the Ceramic input or output capacitors with Tantalum capacitors!

8. Place any type of capacitor in parallel with the input capacitor as long as the Ceramic input

capacitor is placed next to the device. If Tantalum input capacitor is used, it must be rated for

switching regulator applications and the operating voltage needs to be derated by 50%.

9. Place any type of capacitor in parallel with the output capacitor.

10. Replace the Ceramic output capacitors with low-ESR capacitors like the POSCAP from SANYO

as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide

the lowest noise and smallest foot print solution.

11. Use planes for the input and output power to maintain good voltage filtering and to keep power

losses low.

12. If there is not enough space for a power plane for the input supply, then the input supply trace

must be at least 3/8 inch wide.

13. If there is not enough space for a power plane for the output supplies, then place the output as

close to the load as possible with a trace of at least 3/8 inch wide.

14. Review the recommended solder pad layout and notes (see Section 7.3.1, Recommended

Solder Pad Layout, on page 57).

15. The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of

cleaning flux residues from beneath the QFN package.

Warning: To avoid noise and abnormal operating behavior, follow these layout recommendations.

88PH845

Datasheet

Page 50 Document Classification: Proprietary May 27, 2009, 3.0

Figure 55: PCB Layout Schematic

I Cin

LP1

I Cout

LP2

LP1

4.7 uF /25 V

VIN

22 uF/6. 3V

VCC

22 uF/6. 3V

100 K

PWM

VSET

VOUT

VDD EN

VOUT

VBS

0 Ohm

53.6 K

10uF/25V

0 .047 uF/25 V

10uF/25V

VBS

PGND 10

VDD

PGND

EN 13

SVIN

VCC

VIN

SW 11

SGND 12

SFB 14

VSET 15

PSET 16

PWM 17

PG 18

88PH845

0.1 uF /25 V

PSE T

6.9uH

VIN

4. 7uF/25 V

Caution: Do not float Pin 13 and Pin 17.

Applications Information

PC Board Layout Considerations and Guid el ines

May 27, 2009, 3.0 Document Classification: Proprietary Page 51

6.1.1 PC Board Layout Examples

Actual board size = 900 mil x 830 mil

Total copper layers = 2

Figure 56: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale)

88PH845

Datasheet

Page 52 Document Classification: Proprietary May 27, 2009, 3.0

Figure 57: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale)

Applications Information

Bill of Materials

May 27, 2009, 3.0 Document Classification: Proprietary Page 53

6.2 Bill of Materials

Table 13: 88PH845 BOM

Item Qty Ref Manufacturer Part

Number Manufacturer Description

1 1 U1 88PH845 Marvell 12V Step-Down Regulator

2 1 C1 TMK105BJ104KV-F Taiyo Yuden CAP CER .10µF 25V X5R 0402

3 1 C7 C2012X5R1E475K TDK Corporation CAP CER 4.7µF 25V X5R 0805

4 1 C8 C2012X5R1E475K TDK Corporation CAP CER 4.7µF 25V X5R 0805

GRM32DR61E106KA12L Murata CAP CER 10µF 25V 10% X5R 1210

6C3

GRM21BR60J226ME39L Murata CAP CER 22µF 6.3V X5R 0805 20%

8C5

9 1 C6 06033C473KAT2A AVX Corporation CAP CER .047µF 10% 25V X7R 0603

10 1 L1 FDV0840-6R9M TOKO FDV0840 Series, 6.9µH, 4.5A, 41mΩ (max),

H=4mm, L=9.4mm, W=8.7mm

11 1 R1 ERJ-3GEYJ104V Panasonic—ECG RES 100KΩ 1/10W 5% 0603 SMD

12 1 R2 RC0603JR-070RL Yageo America RES 0.0Ω 1/10W 5% 0603 SMD

13 1 R3 ERJ-3EKF5362V Panasonic—ECG RES 53.6KΩ 1/10W 1% 0603 SMD

88PH845

Datasheet

Page 54 Document Classification: Proprietary May 27, 2009, 3.0

THIS PAGE INTENTIONALLY LEFT BLANK

Mechanical Drawings

May 28, 2009, 3.0 Document Classification: Proprietary Page 55

7Mechanical Drawings

7.1 Mechanical Drawings

Figure 58: 4mm x 3mm 18-Pin FCQFN Mechanical Drawing

INDEX AREA

(D / 2 x E/2 )

Termina l Tip

(D/2xE/2)

INDEX AREA

BOTTOM VIEW

17XL

PLANE

SEATING

18Xb

SIDE VIEW

TOP VIEW

''A''

DETAIL 'A'

88PH845

Datasheet

Page 56 Document Classification: Proprietary May 28, 2009, 3.0

7.2 Mechanical Dimensions

Table 14: 4mm x 3mm 18-Pin FCQFN Dimensions

Symbol Dimension in mm Dimension in inch

MIN NOM MAX MIN NOM MAX

A 0.90 1.00 0.035 0.039

A1 0.00 0.02 0.05 0.000 0.001 0.002

A3 0.20 REF 0.008 REF

b 0.20 0.25 0.30 0.008 0.010 0.012

D 2.90 3.00 3.10 0.114 0.118 0.122

E 3.90 4.00 4.10 0.153 0.157 0.161

e 0.50 BSC 0.020 BSC

L 0.40 0.50 0.60 0.012 0.016 0.020

aaa 0.15 0.006

bbb 0.10 0.004

ccc 0.10 0.004

Notes:

Dimensioning and tolerancing conform to ASME Y14.5M-1994

Drawing not to scale

Dimensions are in Millimeters

Terminal #1 identifier and terminal numbering convension

Pin 1 (0.6mm) is longer than the other pins (0.5mm)

Mechanical Drawings

Typical Pad Layout Dimensions

May 28, 2009, 3.0 Document Classification: Proprietary Page 57

7.3 Typical Pad Layout Dimensions

7.3.1 Recommended Solder Pad Layout

Figure 59: 4mm x 3mm FCQFN-18 Land Pattern (mm)

3.00

0.50

Package

Outline

4.30

QFN Lead with

Non-Solder Mask Defined Terminal

0.051 mm

2.0 mils

0.25 mm

Pad

0.25 mm

0.148 mm

SM Pad Pad

0.75

0.65

3.30

0.25

4x3 FCQFN-18

Land Pattern (mm)

Notes:

Top view

The “1” indicates Pin 1 location

Drawing not to scale

Oversize solder mask by 4 mils over pad size (2 mil annular ring)

0.148mm solder mask between pads

Tolerance ±0.05mm

Pin 1 (0.6mm) is longer than the other pins (0.5mm)

88PH845

Datasheet

Page 58 Document Classification: Proprietary May 28, 2009, 3.0

THIS PAGE INTENTIONALLY LEFT BLANK

Part Order Numbering/Package Marking

Part Order Numbering Scheme

May 27, 2009, 3.0 Document Classification: Proprietary Page 59

8Part Order Numbering/Package Marking

8.1 Part Order Numbering Scheme

Figure 60 shows the part order numbering scheme. Refer to a Marvell Field Application Engineer

(FAE) or sales representative for further information when ordering parts.

8.2 Part Ordering Options

The standard ordering part numbers for the respective solutions are as follows:

Figure 60: Sample Part Number

–B1–NFB1C000–xxxx

Part number

Package code

Environmental code

1 = RoHS 6/6 compliant

2 = Green compliant

Temperature code

C = Commercial

I = Industrial

Custom code (optional)

88PH845

Custom code

Table 15: Part Ordering Options

Package Type Part Order (booking) Number

18-pin QFN 4mm x 3mm 88PH845-B1-NFB1C000

18-pin QFN 4mm x 3mm 88PH845-B1-NFB1C000-T (Tape and Reel)

88PH845

Datasheet

Page 60 Document Classification: Proprietary May 27, 2009, 3.0

8.3 Package Marking

Figure 61 shows a sample package marking and pin 1 location.

Figure 61: Package Marking and Pin 1 location

00B1P

YWW$$

Marvell logo and partial part number

Date code and lot traceability code

Y = year

WW = work week

$$ = Lot traceability code

Power code, revision, assembly house code

00 = power code

B1 = custom code

P = assembly house code

Note: The above example is not drawn to scale. Location of markings are approximate.

Pin 1 location

May 27, 2009, 3.0 Document Classification: Proprietary Page 61

ARevision History

Table 16: Revision History

Document Type Document Revision

Rev. D

1. Update schematic (Fig 1) and in the Application Section.

2. Update BOM.

3. Update layout recommendations.

4. Edit Soft Startup section 3.2.

Marvell. Moving Forward Faster

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

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