MOSTEK. Z80 INTERFACING TECHNIQUES FOR DYNAMIC RAM Application Note INTRODUCTION Since the introduction of second generation micro- processors, there has been a steady increase in the need for larger RAM memory for microcomputer systems. This need for larger RAM memory is due in part to the availability of higher level languages such as PL/M, PL/Z, FORTRAN, BASIC and COBOL. Until now, when faced with the need to add memory to a microcomputer system, most designers have chosen static memories such as the 2102 1Kx1 or possibly one of the new 4Kx1 static memories. However, aS most mini or mainframe memory de- signers have learned, 16-pin dynamic memories are often the best overall choice for reliability, low power, performance, and board density. This same philo- sophy is true for a microcomputer system. Why then have microcomputer designers been reluctant to use dynamic memory in their system? The most important reason is that second generation micro- processors such as the 8080 and 6800 do not provide the necessary signals to easily interface dynamic memories into a microcomputer system. Today, with the introduction of the Z80, a true third generation microprocessor, not only can a micro- computer designer increase system throughput by the use of more powerful instructions, but he can also easily interface either static or dynamic memo- ries into the microcomputer systern. This application note provides specific examples of how to inter- face 16-pin dynamic memories to the Z80. OPERATION OF 16-PIN DYNAMIC MEMORIES The 16-pin dynamic memory concept, pioneered by MOSTEK, uses a unique address multiplexing tech- nique which allows memories as large as 16, 384 bits x 1 to be packaged in a 16-pin package. For example the MK4027 (4,096x1 dynamic MOS RAM) and the MK4116 (16,384x1 dynamic MOS RAM) both use address multiplexing to load the address bits into memory. The MK4027 needs 12 address bits to select 1 out of 4,096 locations, while the MK4116 requires 14 bits to select 1 out of 16,384. The internal memo- ries of the MK4027 and MK4116 can be thought of as a matrix. The MK4027 matrix can be thought of as 64x64, and the MK4116 as 128x128. To select a particular location, a row and column address is supplied to the memory. For the MK4027, address bits Ag-Ag are the row address, and bits Ag-Ay1 are the column addresses. For the MK4116, address bits Ag-Ag are the row address, and A7-A43 are the column address. The row and column addresses are strobed into the memory by two negative going clocks called Row Address Strobe (RAS) and Column Address Strobe (CAS). By the use of RAS and CAS, the address bits are latched into the memory for access to the desired memory ocation. PANO ee Rss Dynamic memories store their data in the form of a charge on a small capacitor. In order for the dyna- mic memory to retain valid data, this charge must be periodically restored. The process by which data is restored in a dynamic memory is known as re- freshing. A refresh cycle is performed on a row of data each time a read or write cycle is performed on any bit within the given row. A row consists of 64 locations for the MK4027 and 128 locations for the MK4116. The refresh period for the MK4027 and the MK4116 is 2ms which means that the memory will retain a row of data for 2ms without a refresh. Therefore, to refresh all rows within 2ms, a refresh cycle must be executed every 32us (2ms+64) for the MK4027 and 16us (2ms~+ 128) for the MK4116. To ensure that every row within a given memory is refreshed within the specified time, a refresh row address counter must be implemented either in ex- ternal hardware or as an internal CPU function as in the Z80. (Discussed in more detail under Z80 Refresh Control and Timing.) The refresh row address counter should be incremented each time that a refresh cycle is executed. When a refresh is performed, all RAMs in the system should be loaded with the refresh row address, For the MK4027 and the MK4116, a refresh cycle consists of loading the refresh row address on the address lines and then generating a RAS for all RAMs in the system. This is known as a RAS only refresh. The row that was addressed wiil be refreshed in each memory. The RAS only refresh prevents a conflict between the outputs of all the RAMs by disabling the output on the MK4116, and maintaining the output state from the previous memory cycle on the MK4027. Z80 TIMING AND MEMORY CONTROL SIGNALS The Z80 was designed to make the job of interfacing X39to dynamic memories easier. One of the reasons the Z80 makes dynamic memory interfacing easier is because of the number of memory contro! signals that are available to the designer. The Z80 control signals associated with memory operations are: MEMORY REQUEST (MREQ) - Memory request signal indicating that the address bus holds a valid memory address for a memory read, memory write, or memory refresh cycle. READ (RD) - Read signal indicating that the CPU wants to read data from memory or an [/O device. The addressed 1/O device or memory should use this signal to gate data onto the CPU data bus. WRITE (WR) - Write signal indicating that the CPU data bus hold valid data to be stored in the addressed memory or I/O device. REFRESH (RFSH) - Refresh signal indicates that the lower 7 bits of the address bus contain a refresh address for dynamic memories and the current MREQ signal should be used to generate a refresh cycle for all dynamic memories in the system. Figures 1a, 1b, and 1c show the timing relationships of the control signals, address bus, data bus and system clock . By using these timing diagrams, a set of equations can be derived to show the worst where: t, = Clock period DL@(mp) = MREG delay from falling edge of clock. 's@(D) = Data setup time to rising edge of clock during op code fetch cycle. let: te = 400ns; to, Biy~y = 100ns; tsq = 50ns then: taccess OP CODE = 450ns (2) taccESS MEMORY READ = 4(tc/2) toL&mir) tgplD) where: tc = Clock period tpLimr) = MREO delay from falling edge of clock tsBp) = Data Setup time to falling edge of clock fet: tg = 400ns; tp_ (MR) = 100ns; ts (:p) G = 6Ons then: taccESS MEMORY READ = 640ns The access times computed in equations 1 and 2 are overall worst case access times required by the CPU. The overall access times must include all TTL buffer delays and the access time for the memory device. For example, a typical dynamic memory design would have the following characteristics, (see Figure 2). The example in Figure 2 shows an overall access time of 336ns. This would more than satisfy the 450ns required for the op code fetch and the 640ns required for a memory read. case access times needed for dynamic memories with cpu REO buffer delay.............. 12ns (8T97) the Z80 operating at 2.5MHz. Memory gating and timing delays............. 40ns The access time needed for the op code fetch cycle Memory device access time .. . . 250ns (MK4027/4116-4) and the memory read cycle can be computed by Memory data bus buffer delay.......... 17ns (8T28) equations 1 and 2. CPU data bus buffer delay............. 17ns (8T28) (1) tacCEss OP CODE 3{te/2)-tDLB (mr) *S@(D) 336ns OP CODE FETCH TIMING Figure 1a. TI T2 T3 Ta pae 400ns m fF \ Ff \_F AQ~AIS x VALID MEMORY ADDRESS Xx Vance RES X 100 ns MREQ 7; \ pee +W(MRL) 360ns 1160ns tw(MRA) XY RFSH 00-07 450n8 VO pe access op code a le-SOns 13(D) po x40MEMORY READ TIMING Figure 1b. TY T2 T3 400ns ~~ tC fo \ AO AIS Xx VALID MEMORY ADDRESS AO-AI5 X o OO ns * tDL9 (MR) 3 $ REG 4 MREQ ra vd Q A DO-D7 = taccess memory read 640ns MEMORY WRITE TIMING Figure 1c. "| Te T3 | AO-AI5 VALID MEMORY ADDRESS AQ-AIS Xx 1O0ns wm +DL & (MR) wREQO f[. 90ns > ~ 1DL o (wR) WR +w(WRL) / 200ns S J *D(D) ht 360ns -1> DO-D7 DATA OUT Z80 REFRESH CONTROL AND TIMING One of the most important features provided by the Z80 for interfacing to dynamic memories is the execution of a refresh cycle every time an op code fetch cycle is performed. By placing the refresh cycle in the op code fetch, the Z80 does not have to allo- cate time in the form of wait states or by stretching the clock to perform the refresh cycle. In other words, the refresh cycle is totally trans- parent to the CPU and does not decrease the system throughput (see Figure 1a). The refresh cycle is transparent to the CPU because, once the op code has been fetched from mernory during states T4 and T9, the memory would normally be idle during states T3 and Tq. Therefore, by placing the refresh in the Tg and Tg states of the op code fetch, no time is lost for refre- shing dynamic memory. The critical timing parameters involving the Z80 and dynamic memories during the refresh cycle are: tw(MRH) and tw(mRL)- The parameter known as tw(MRH) refers to the time that MREQ is high during the op code fetch between the fetch of the op code and the refresh cycle. This time is known as precharge for dynamic memories and is necessary to allow certain internal nodes of the RAM to be charged-up for another memory cycle. The equation for the minimum ty (MRH) time period is: (3) tw(MRH) = tw(@ H) + tf 30 where: tw( H) is clock pulse width high tg is clock fall time let: tw( H) = 180ns; ty = 10ns then: tW(MRH) = 160ns (min) A tw(MRH) Of 160ns is more than adequate to meet the worst case precharge times for most dynamic RAMs. For example, the MK4027-4 and the MK4116-4 require a 120ns precharge.The other refresh cycle parameter of importance to dynamic RAMs is tw(mRt), (the time that MREQ is low during the refresh cycle). This time is important because MREQ is used to directly generate RAS. The equation for the minimum time period is: (4) tW(MRL) = te40 where: te is the clock period let: te = 400ns then: tw(MRL) = 360ns A 360ns twimRL) exceeds the 250ns min RAS time required for the MK4027-4 and the MK4116-4. By controlling the .refresh internally with the Z80, the designer must be aware of one limitation. The limitation is that to refresh memory properly, the Z80 CPU must be able to execute op codes since the refresh cycle occurs during the op code fetch. The following conditions cause the execution of op codes to be inhibited, and will destroy the contents of dynamic memory. (1) Prolonged reset > 1ms (2) Prolonged wait state operation > 1ms (3) Prolonged bus acknowledge (DMA) > 1ms (4) clock of < 1.216 MHz for 16K RAMs < .608 MHz for 4K RAMs The clocks rate in number 4 are based on the 280 continually executing the worst case instruction which is an EX (SP), HL that executes in 19 T states. Therefore, by operating the Z80 at or above these clocks frequencies, the user is ensured that the dynamic memories in the system will be refreshed properly. Remember to refresh memory properly, the Z80 must be able to execute op codes! DELAY FOR A TYPICAL MEMORY SYSTEM Figure 2. MK4027-4/MK4116-4 250ns ACCESS 40ns lans MRE 5 TIMING RAS LOGIC z80 8197 CPU CAS OtN = DOUT DO-07 [70s l7ns qo @ S c m m a D uw ww at28 st2a SUPPORT CIRCUITS FOR DYNAMIC MEMORY INTERFACE Two support circuits are necessary to ensure reliable operation of dynamic memory with the 280. The first of these circuits is an address latch shown in Figure 3. The latch is used to hold addresses A12- A15 while MREQ is active. This action is necessary because the Z80 does not ensure the validity of the address bus at the end of the op code fetch (see Figure 4). This action does not directly affect dy- namic memories because they latch addresses inter- nally. The problem comes from the address decoder which generates RAS. If the address lines which drive the decoder are allowed to change while MREQ is iow, then a glitch can occur on the RAS line or lines (if more than one row of RAMs are used) which may have the effect of destroying one row of data. The second support circuit is used to generate a power on and short manual reset pulse. Recall from the discussion under 280 Timing and Memory Con- X42ADDRESS LATCH Figure 3. 7475 Alz > 1g -h_+ a2 Als. >_-_____-_{2p 2Q p-_______- a3 A14 >| 3Qp____________. aig Als >4p 4Q HR 5 PU bsd 3 2 < 2 > a RAS TIMING WITH AND WITHOUT ADDRESS LATCH Figure 4. MREG \ OP CODE FETCH / \ REFRESH ADDRESS/ X VALID MEMORY 4sODRESS X VALID REFRESH ADDRESS XxX RAS WITHOUT ADDRESS LATCH ___> "RAS WITH ADDRESS LATCHtrol Signals that one of the conditions that will cause dynamic memory to be destroyed is a reset pulse of duration greater than Ims. The circuit shown in Figure 5a can be used to generate a short reset pulse from either a push button or an external source. Additionally the manual reset is synchronized to the start of an M1 cycle so that the reset will not the manual reset, the circuit will also generate a power on reset. if it is not necessary that the contents of the dynamic memory be preserved, then the reset circuit shown in Figure 5b may be used to generate a manual or power on reset, fall during the middle of a memory cycle. Along with MANUAL AND POWER-ON RESET CIRCUIT +5 +5 Figure Sa. +5 \OK |OK |oOOpf j ee yt | Tt d Se 8 ~ a >_______{> ck ox a 3 | De RESET +5 R 74132 7404 7474 74121 EXTERNAL RESET 74 | T" pf +5 MANUAL AND POWER-ON RESET CIRCUIT Figure 5b. tOK CPU RESET 10k EXTERNAL 220 RESET X44DESIGN EXAMPLE NO. 1 SCHEMATIC DIAGRAM Figure 6. TAR | JINIVNAG suondo ssduunf 104 Z pue | sajqe| a2ag siv bly ely zy AS+ ei 265118 aw sv liv (8) vv v- 91D IW 40 Eno-amrnon q2 ao y-L20b IN X45DESIGN EXAMPLES FOR 280 TO DYNAMIC MEMORY INTERFACING THE To illustrate the interface between the Z80 and dynamic memory, two design examples are presented. Example number 1 is for a 4K/16Kx8 memory and the example number 2 is a 16K/64Kx8 memory. Design Example Number 1: 4 /16Kx8 Memory This design example describes a 4K/16Kx8 memory that is best suited for a small single board Z80 based microcomputer system. The memory devices used in the example are the MK4027 (4,096x1 MOS Dyna- mic RAM) and the MK4116 (16,384x1 MOS Dyna- mic RAM). A very important feature of this design is the ease in which the memory can be expanded from a 4Kx8 to a 16Kx8 memory. This is made possible by the use of jumper options which con- figure the memory for either the MK4027 or the MK4116. See Table 1 and 2 for jumper options. Figure 6 shows the schematic diagram for the 4K/16Kx8 memory. A timing diagram for the Z80 control signals and memory control signals is shown in Figure 7. The operation of the circuit may be described as follows: RAS is generated by NANDing MREQ with RFSH + ADDRESS DECODE. RFSH is generated directly from the Z80 while address decode comes from the 74LSI38 decoder. Address decode indicates that the address on the bus falls within the memory boundaries of the memory. If an op code fetch or memory read is being executed the 81LS97 output buffer will be enabled at approxi- mately the same time as RAS is generated for the memory array. The output buffer is enabled only during an op code fetch or memory read when ADDRESS DECODE, MREQ, and RD are all low. The switch multiplexer signal (MUX) is generated on the rising edge of after MREQ has gone low during an op code fetch, memory read or memory write. After MUX is generated and the address multiplexers switch from the row address to column address, CAS will be generated. CAS comes from one of the outputs of the multiplexer and is delayed by two gate clelays to ensure that the proper column address set-up time will be achieved. Once RAS and CAS have been generated for the memory array, the memory will then access the desired focation for a read or write operation. 7404 22ns __ __ Generate RAS from MREO 7400 15ns 63ns RAS to rising edge of 74874 10ns to MUX 748197 16ns 7404 22ns Generate CAS from MUX 7404 15ns tcac 165ns CAS access time 81LS97 22ns Output buffer delay 349ns Worst case access DESIGN EXAMPLE NO. 1 MEMORY TIMING Figure 7. 400ns 00ns MREQ fF VS S Ne REFRESH _ I-37 RAS. Ls rm 63ns > 1Ons MUX _+_/ | 52ns OP CODE FETCH / 37ns 160ns 360ns oo DATA BUS p VALID {ee )}-The worst case access time required by the CPU for the op code fetch is 450ns (from equation 1); therefore, the circuit exceeds the required access time by 101ns (worst case). The circuit shown in Figure 6 provides excellent performance when used as a small on board memory. The memory size should be held at eight devices because there is not sufficient timing margin to allow the interface circuit to drive a jJarger memory array. Design Example Number 2: 16Kx8 Memory This design example describes a 16K /64Kx8 memory which is best suited for a 280 based microcomputer system where a large amount of RAM is desired. The memory devices used in this example are the same as for the first example, the MK4027 and the MK4116. Again as with the first example, the memory may be expanded from a 16Kx8 to a G4Kx8 by reconfiguring jumpers. See Table 3 and 4 for jumper options. Figure 8. shows the schematic diagram for the 16K/ 64K memory. A timing diagram is shown in Figure 9. The operation of the circuit can be described as follows: RAS is generated by NANDing MREQ with ADDRESS DECODE (from the two 74LS!38s) + RFSH. Only one row of RAMs will receive a RAS during an op code fetch, memory read or memory write. However, a RAS wil! be generated for all rows within the array during a refresh cycle. MREQ is inverted and fed into a TTL compatible delay line to generate MUX and CAS. (This particular approach differs from the method used in example number 1 in that all memory timing is referenced to MREQ, whereas the circuit in example number 1 bases its memory timing from both MREQ and the clock. Both methods offer good results, however, the TTL delay line approach offers the best control over the memory timing.) MUX is generated 65ns later and is used to switch the 74157 multiplexers from the row to the column address. The 65ns delay was chosen to allow adequate margin for the row address hold time tray. At 110ns, CAS is generated from the delay line and NANDed with RFSH, which inhibits a CAS during refresh cycle. After CAS is applied to the memory, the desired location is then accessed. A worst case access timing analysis for the circuit shown in Figure 8 can be computed as follows: 74LS14 22ns Generate RAS from MREQ 74LS00 15ns delay line 50ns MUX from RAS delay line 45ns CAS delay from MUX 7400 20ns tcac 165ns Access time from CAS 8833 30ns Output buffer delay 347ns The required access time from the CPU is 450ns (from equation 1). This leaves 103ns of margin for additional CPU buffers on the control and address lines. This particular circuit offers excellent results for an application which requires a large amount of RAM memory. As mentioned earlier, the memory timing used in this example offers the best control over the memory timing and would be ideally suited for an application which required direct memory access (DMA). 4K x 8 CONFIGURATION(MK4027) JUMPER Table 1 CONNECT: J13 to J14 Connect: any CONNECT: J14 to J15 ADDRESS CONNECT 4 re ADDRESS CONNECT 0000-0F FF J17 to $25 Oto J10 8000-8F FF J17 to J25 1000-1 FFF J18 to J25 111 to J12 9000-9F FF J18 to J25 2000-2F FF J19 to J25 A000-AFFF J19 to J25 3000-3F FF J20 to J25 BO00-BFFF J20 to J25 4000-4F FF J21 to J25 C000-CF FF J21 to J25 5000-5FFF J22 to J25 DO00-DF FF J22 to J25 6000-6F FF J23 to J25 E000-EFFF J23 to J25 7000-7F FF J24 to J25 FOO0-F FFF J24 to J25 16K x 8 CONFIGURATION (MK4116) JUMPER CONNECTIONS Table 2 CONNECT: J1 to J2 ADDRESS CONNECT J4 to J5 J8 toJ11 0-3F FF J17 to J25 J10 to J13 4000-7 FFF J18 to J25 J12 to J16 8000-BFFF J19 to J25 J14 to J16 C000-FFFF J20 to J25 xX47 Oe AE le RAMS16K x 8 CONFIGURATION (MK4027) Table 3 CONNECT: Ji to J3 J5 to J6 J7 to J8 J9 to J10 J11 to S12 J13 to J14 ADDRESS: 0-3F FF ADDRESS: 4000-7F FF ADDRESS: 8000-BFFF ADDRESS: CO00-F FFF CONNECT: J24 to J25 CONNECT: J16 to J17 CONNECT: J40 to J41 CONNECT: J32 to J33 J26 to J27 J18 to J19 J42 to J43 J34 to J35 J28 to J29 J20 to J21 J44 to J43 J36 to J37 J30 to J31 J22 to J23 J46 to J47 J38 to J39 64K x 8 CONFIGURATION (MK4116) Table 4 CONNECT: Ji to J2 ADDRESS: 0-FFFF J4 to J5 CONNECT: J32 to J33 J8 to J11 J34 to J35 J10 to J13 J36 to J37 J12 to J15 J38 to J39 J14 to J15 SYSTEM PERFORMANCE CHARACTERISTICS Table 5 The system characteristics for the preceeding design examples are shown in Table 5. EXAMPLE # MEMORY CAPACITY MEMORY ACCESS POWER REQUIREMENTS 1 4K/16Kx8 349ns max. +12V @ 0.0250 A max. +5V @ 0.422 A max.* -5V @ 0.030 A max. 2 16K/64Kx8 347ns max. *A\l power requirements are max.; operating temperature oc to 70C ambient, max +12V current computed with Z80 executing continuous op code fetch cycles from RAM at 1.6 Ms intervals. +12V @ 0.600 A max. +5V @ 0.550 A max. * -5V @ 0.030 A max. X48DESIGN EXAMPLE NO. 2 SCHEMATIC DIAGRAM Figure 8, OUTPUT BUFFER DISABLE vA bs) Q = <q 2 Ss a) RFSH 74L$00 MREQ bo ol be MEMORY ARRAY 32 DEVICES 16k x8 (MK 4027-4) 64k x 8 (MK 4116 -4) b3 TTL anc O14 COMPATIBLE CAS ba DELAY LINE DIS bs 005 DI6 006 DI7 DO7 CS (A6) 65ns lo 06 D7 v3 2y 3Y 4Y 74157 WV o2y 3Y 4y s 74157 aaa TALsl4 T4Lsi4 40 A? sOAl 48 A2 AQ AZ AlO A4 All AS Al2 AG AID) AIM AIS FOR JUMPER OPTIONS SEE TABLES 3 AND 4DESIGN EXAMPLE NO. 2 MEMORY TIMING Figure 9. 900ns 7 JF \ f/f sf \_S/ > Pens / REFRESH 37ns - 360ns fr 100ns MREQ \ OP CODE FETCH >| 37ns RAS t ] | 5Ons MUX t 65ns CAS l 195ns |< DATA BUS TT { x SATA 347s >| PRINTED CIRCUIT LAYOUT One of the most important parts of a dynamic memory design is the printed circuit layout. Figure 10 illustrates a recommended layout for 32 devices. A very important factor in the P.C. layout is the power distribution. Proper power distribution on the Vpp and Vpp supply lines is necessary because of the transient current characteristics which dynamic memories exhibit. To achieve proper power distri- bution, Vpp, VgB, Vcc and ground should be laid out in a grid to help minimize the power distribution impedance. Along with good power distribution, adequate capacitive bypassing for each device in the memory array is necessary. In addition to the in- dividual by-passing capacitors, it is recommended that each supply (VBB, VGC and Vpp) be bypassed with an electrolytic capacitor 20uF. By using good power distribution techniques and using the recommended number of bypassing capa- citors, the designer an minimize the amount of noise in the memory array. Other layout considerations are the placement of signal tines. Lines such as address, chip select, column address strobe, and write should be bussed together as rows; then, bus all rows together at one end of the array. Intercon- nection between rows should be avoided. Row address strobe lines should be bussed together as a row, then connected to the appropriate RAS driver. TTL drivers for the memory array signals should be located as close as possible to the array to help minimize signal noise. For a large memory array such as the one shown in design example number 2, series terminating resistors should be used to minimize the amount of negative undershoot. These resistors should be used on the address lines, CAS and WRITE, and have values between 20 Qtoa33 Q. The layout for a 32 device array can be put in a 5 x 5" area on a two sided printed circuit board. X50SUGGESTED P. C. LAYOUT FOR MK4027 or MK4116 Figure 10. . aA es JINVYNAG X514MHz Z80 DYNAMIC MEMORY CONSIDERATIONS INTERFACE A 4MHz Z80 is available for the microcomputer de- signer who needs higher system throughput. Consid- erations which must be faced by the designer when interfacing the 4MHz Z80 to dynamic memory are the need for memories with faster access times and for providing minimum RAM precharge time. The access times required for dynamic memory inter- faced to a 4MHz 280 can be computed from equa- tions 1 and 2 under Z80 Timing and Memory Control Signals. Access time for op code fetch for 4MHz Z80, let: tc = 250ns; tDL@ (mR) = 75n5; tee (D) = 35ns then: tacCESS OP CODE = 265ns Access time for memory read for 4MHz Z80, let: c = 250ns; tp L&(mr) = 75ns; tq (D)7 5Ons then: taccESS MEMORY READ = 375ns The problem of faster access times can be solved by using 200ns memories such as the MK4027-3 or MK4116-3. Depending on the number of buffer delays in the system, the designer may have to use 150ns memories such as the MK 4027-2 or MK 4116-2. The most critical problem that exists when inter- facing dynamic memory to the 4MHz 280 is the RAM precharge time (trp). This parameter is called tw(MRH) on the 280 and. can be computed by the following equation. (4) tw(RH) = tw(@H) * tf-20ns let: tw(@H) = 110ns; tg = Sns shen: tw(MRH) = 95ns A tw(MRH) Of 95ns will not meet the minimum pre- charge time of the MK4027-2 or MK4116-2 which is 100ns. The MK4027-3 and MK4116-3 require a 120ns precharge. Figure 11 shows a circuit that will lengthen the tyw(MRH) Pulse from 95ns to a mini- mum of 126ns while only inserting one gate delay into the access timing chain. Figure 12 shows the timing for the circuit of Figure 11. The operation of the circuit in Figure 11 can be explained as follows: The D flip flops are held in a reset condition until MREO goes to its active state. After MREQ goes active, on the next positive clock edge, the D input of U1 and U2 will be transferred to the outputs of the flip flops. Output OA will go high if M1 was high when clocked U1. Output QB will go low on the next positive going clock edge, which will cause the output of U3 to go low and force the output of U4, which is RAS, high. The flip flops will be reset when MREO goes inactive. The circuit shown in Figure 11 will give a minimum of 126ns precharge for dynamic memories, with the Z80 operating at 4MHz. The 126ns tyy(MRH)} is com- puted as follows. 110ns 5ns 20ns -9ns tw( H) - clock pulse width high (min) te - clock full time (min) oLgime) - MREQ delay (min) 74874 delay (min) 126ns_ tw(MRH) modified (min) 4MHz Z80 PRECHARGE EXTENDER FOR DYNAMIC MEMORIES Figure 11 +5 +5 S QA MI D a 0 g > > ck cK 74874 9 a8 R Re ! | MRE Y Q > 4 | D> ADDRESS DECODE + RF SH X52TIMING DIAGRAM FOR 4MHz Z80 PRECHARGE EXTENDER Figure 12 Ty Te 250ns Ons masns ) 20ns MREQ t Ons OP CODE FETCH 126 ns PRECHARGE REFRESH APPENDIX MEMORY TEST ROUTINE This section is intended to give the microcomputer designer a memory diagnostic suitable for testing memory systems such as the ones shown in Section vi The routine is a modified address storage test with an incrementing pattern. A complete test requires 25649 passes, which will execute in less than 4 minutes for a 16Kx8 memory. If an error occurs, the program will store the pattern in location 2CH and the address of the error at locations 2DH and 2EH. The program is set up to test memory starting at loca- tion 2FH up to the end of the block of memory defined by the bytes located at OCH and ODH. The test may be set up to start at any location by modifying locations 03H - 04H and 11H - 12H with the starting address that is desired. MXRTS LISTING PAGE 0001 Loc OBJ CIDE STMT SOURCE STATEMENT 0001 ;TRANSLATED FROM DEC 1976 INTERFACE MAGAZINE 0002 3 0003 ;THIS IS A MOOIFIED ADDRESS STORAGE TEST WITH AN 0004 s;INCRENENTING PAITERN 0005 3; 0006 5256 PASSES MUST BE EXECUTED BEFORE THE MEMORY IS 9007 ;COMPLETELY TESTED. 0008 ; 0009 ;IF AN ERROR OCCURS, THE PATTERN WILL BE STORED 0010 ;AT LOCATION 002C'H AND THE ADDRESS OF: THE 0011 ;ERROR LOCATION WILL BE STORED AT '002D'H AND 0012 ;'OO2E'H. 0013 > X--53 RAMS YQ 2 ca Fa > a)MEMORY TEST ROUTINE (Contd.) 0014 ;THE CONTENTS OF LOCATIONS *OOOC'H AND *001D'H 0015 ;SHOULD BE SELECTED ACCORDING TO THE FOLLOWINGS 0016 ;MEMORY SIZE TO BE TESTED 0017 ; 0018 ;TOP OF MEMORY TO 0019 ;BE TESTED VALUE OF EFAGE 0020 ; 0021 ; 4K 10H 0022 3; 8K *20H 0023 ; 16K "GOTH 0024 3; 32K "BOTH 0025 ; 48K *COtH 0026 ; 64K "REH 0027 ; 0028 ;THE PROGRAM IS SET UP TO START TESTING AT 0029 ;LOCATION 'OO2F'H. THE STARTING ADDRESS FOR THE 0030 ;TEST CAN BE MODIFIED BY CHANGING LOCATIONS 0031 3'0003-0004'H AND '9011-0012H. 0032 3; 0033 ;TEST TIME FOR A 16K X 8 MEMORY IS APPROX. 4 MIN 0034 ; 0000 0035 ORG OOOOH 9000 0600 0036 LD 3,0 >CLEAR B PATRN MODIFIER 0037 ;LOAD UP MEMORY 0002 212F09 0038 LOOP: LD HL,START ;GET STARTING ADDP 0005 7D 0039 FILL: LD Ayu ,;LOW BYTE TO ACCH 0006 AC 0040 XOR E +XOR WITH HIGH BYTE 0007 A8 0041 XOR B 3XOR WITH PATTERN 0008 77 0042 LD (HL),A ;STCRE IN ADDR 0009 23 0043 INC HL sINCRENENT ADDR OO0A 7c oo4u4 LD A,H ;LOAD HIGH BYTE OF ADDR 000B FE10 0045 cP EPAGE ;COMPARE WITH STOF ADDR oo00D 20500 0046 JP NZ,FILL :NOT DONE,GO BACK 0047 ;READ AND CHECK TEST DATE 9010 2712F00 O0us LD HL,START ;GET STARTING ADDR 0013 7D 0049 TEST: LD A/L 3LOAD LOW BYTE oo14 Ac 0050 XOR 8 3XOR WITH HIGH BYTE 0015 Aa 0051 XOR B +XOR WITH MODIFIER 0016 BE 0052 ce CHL) ;COMPARE WITH MEMCRY LOC 0017 225090 0053 JP NZ,FXIT sERROR EXIT OO1A 23 0054 INC KL ;UPDATE MEMORY ADDRESS 901B 7 0055 LD A,H 3LOAD HIGH BYTE 901C FE10 0056 cP EPAGE ;COMPARE WITH STOP ADDR OO1E C21300 0057 JP NZ,TEST +LOOP BACK 0021 04 0058 INC B ;UPDATE MODIFIER MXRTS LISTING PAGE 0002 Loc OBJ CODE STMT SOURCE STATEMENT 9022 39209 0059 JP LOOP 3RST WITH NEW MODIFIER 0060 ;ERROR EXIT 9025 222009 Q061 FXIT: LD CBYTE),HL ;SAVE ERROR ADDRESS 3028 322C00 0062 LD CPATRN),A ;SAVE BAD PATTERN 002B 76 0063 HALT sFLAG OFERATOR 002C 0064 PATRN: DEFS 1 992D 0965 BYTE: DEFS 2 002F 2F00 0066 START: DEFW S$ 0068 EPAGE: zQU 39H ;SET UP FOR 4K TEST 0069 END