IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET DESCRIPTION: FEATURES: * * * * * * * * * IDT54/74FCT273T/AT/CT The FCT273T is an octal D flip-flop built using an advanced dual metal CMOS technology. The FCT273T has eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop's O output. All outputs will be forced low independently of Clock or Data inputs by a low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Std., A, and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: - Industrial: SOIC, SSOP, QSOP - Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP Q D Q D CP CP RD Q D CP RD Q D Q D CP RD RD Q D CP CP RD Q D CP RD Q D CP RD RD MR O0 O1 O2 O3 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES O4 O5 O6 O7 JUNE 2002 1 (c) 2002 Integrated Device Technology, Inc. DSC-2568/2 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES O0 2 19 O7 D0 3 18 D7 D1 4 D1 4 17 D6 O1 O1 5 16 O6 O2 6 15 D2 7 D3 O3 2 1 19 O2 6 16 O6 O5 D2 7 15 O5 14 D5 D3 8 14 D5 8 13 D4 9 12 O4 10 11 CP 9 10 12 13 LCC TOP VIEW PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS(1) Description 11 D4 D6 O4 17 CP 5 GND D7 CERDIP/ SOIC/ SSOP/ QSOP TOP VIEW Symbol 20 18 O3 GND 3 O7 VCC VCC 20 MR 1 O0 INDEX MR D0 PIN CONFIGURATION Max Unit Pin Names VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7 V Dx Data Inputs VTERM(3) Terminal Voltage with Respect to GND Description -0.5 to VCC+0.5 V MR Master Reset (Active LOW) TSTG Storage Temperature -65 to +150 C CP Clock Pulse Input (Active Rising Edge) IOUT DC Output Current -60 to +120 mA Ox Data Outputs NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. FUNCTION TABLE(1) CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. CIN Input Capacitance VIN = 0V 6 10 pF Output Capacitance VOUT = 0V 8 12 pF MR L Inputs CP X Dx X Outputs Ox L Load "1" Load "0" L H h l H L NOTE: 1. H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don't Care = LOW-to-HIGH Clock Transition Unit COUT Operating Mode Reset (Clear) NOTE: 1. This parameter is measured at characterization but not tested. 2 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10% Symbol Test Conditions(1) Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 -- -- V VIL Input LOW Level Guaranteed Logic LOW Level -- -- 0.8 V IIH Input HIGH Current(4) VCC = Max. VI = 2.7V -- -- 1 A IIL Input LOW Current(4) VCC = Max. VI = 0.5V -- -- 1 II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) -- -- 1 A VIK Clamp Diode Voltage VCC = Min., IIN = -18mA -- -0.7 -1.2 V -60 2.4 -120 3.3 -225 -- mA 2 3 -- -- 0.3 0.5 V -- 200 -- mV -- 0.01 1 mA IOS VOH Parameter Short Circuit Current Output HIGH Voltage VOL Output LOW Voltage VH Input Hysteresis ICC Quiescent Power Supply Current VCC = Max., VO = VCC = Min VIN = VIH or VIL GND(3) IOH = -6mA MIL IOH = -8mA IND IOH = -12mA MIL IOH = -15mA IND IOL = 32mA MIL IOL = 48mA IND VCC = Min VIN = VIH or VIL -- VCC = Max. VIN = GND or VCC V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 3 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Test Conditions(1) Symbol Parameter ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open MR = VCC One Input Toggling 50% Duty Cycle Total Power Supply Current(6) VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle MR = VCC One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle MR = VCC Eight Bits Toggling fi = 2.5MHz 50% Duty Cycle IC Min. Typ.(2) Max. Unit -- 0.5 2 mA VIN = VCC VIN = GND -- 0.15 0.25 mA/ MHz VIN = VCC VIN = GND -- 1.5 3.5 mA VIN = 3.4V VIN = GND -- 2 5.5 VIN = VCC VIN = GND -- 3.8 7.3(5) VIN = 3.4V VIN = GND -- 6 16.3(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL Symbol tPLH tPHL tPLH tPHL tSU tH tW tW tREM Parameter Propagation Delay CP to Ox Propagation Delay MR to Ox Set-up Time HIGH or LOW Dx to CP Hold Time HIGH or LOW Dx to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Condition(1) CL = 50pF RL = 500 74FCT273AT Min.(2) Max. 2 7.2 74FCT273CT Min.(2) Max. 2 5.8 Unit ns 2 7.2 2 6.1 ns 2 -- 2 -- ns 1.5 -- 1.5 -- ns 6 6 2 -- -- -- 6 6 2 -- -- -- ns ns ns SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY Symbol tPLH tPHL tPLH tPHL tSU tH tW tW tREM Parameter Propagation Delay CP to Ox Propagation Delay MR to Ox Set-up Time HIGH or LOW Dx to CP Hold Time HIGH or LOW Dx to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Condition(1) CL = 50pF RL = 500 54FCT273T Min.(2) Max. 2 15 54FCT273AT Min.(2) Max. 2 8.3 54FCT273CT Min.(2) Max. 2 6.5 Unit ns 2 15 2 8.3 2 6.8 ns 3.5 -- 2 -- 2 -- ns 2 -- 1.5 -- 1.5 -- ns 7 7 5 -- -- -- 6 6 2.5 -- -- -- 6 6 2.5 -- -- -- ns ns ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 5 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500 V OUT VIN Pulse Generator D.U.T . 50pF RT 500 Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL Octal link Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V 3V 1.5V 0V tREM tSU LOW-HIGH-LOW PULSE tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 3V 1.5V 0V tH 1.5V 1.5V Octal link Pulse Width Octal link Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V CONTROL INPUT OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Octal link SWITCH CLOSED tPZH SWITCH OPEN 0V tPLZ tPZL VOH 1.5V VOL 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V Octal link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 6 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX IDT XX FCT Temp. Range Device Type XX Package X Process CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Blank B Industrial MIL-STD-883, Class B SO PY Q Industrial Options Small Outline IC Shink Small Outline Package Quarter-size Small Outline Package D L Military Options CERDIP Leadless Chip Carrier 273T 273AT 273CT Octal D Flip-Flop with Master Reset 54 74 - 55C to +125C - 40C to +85C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: logichelp@idt.com (408) 654-6459