MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
1JUNE 2002MILITARY AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2002 Integrated Device Technology, Inc. DSC-2568/2
FEATURES:
• Std., A, and C grades
• Low input and output leakage ≤≤
≤≤
≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
–VOH = 3.3V (typ.)
–VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
• Power off disable outputs permit "live insertion"
• Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT273T/AT/CT
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
DESCRIPTION:
The FCT273T is an octal D flip-flop built using an advanced dual metal
CMOS technology. The FCT273T has eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one set-
up time before the low-to-high clock transition, is transferred to the corre-
sponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by
a low voltage level on the MR input. The device is useful for applications
where the true output only is required and the Clock and Master Reset are
common to all storage elements.
D
CP
Q
RD
D0
O0
D
CP
Q
RD
D1
O1
D
CP
Q
RD
D2
O2
D
CP
Q
RD
D3
O3
D
CP
Q
RD
D4
O4
D
CP
Q
RD
D5
O5
D
CP
Q
RD
D6
O6
D
CP
Q
RD
D7
O7
CP
MR
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
2
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
PIN CONFIGURATION
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Pin Names Description
Dx Data Inputs
MR Master Reset (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
Ox Data Outputs
PIN DESCRIPTION
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
COUT Output Capacitance VOUT = 0V 8 12 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
LCC
TOP VIEW
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
FUNCTION TABLE(1)
Inputs Outputs
Operating Mode MR CP Dx Ox
Reset (Clear) L X X L
Load "1" L ↑hH
Load "0" H ↑lL
2
3
1
16
15
14
11
19
18
20
17
13
12
5
6
7
4
8
9
10
D1
O0
D0
VCC
O1
D3
O2
D2
O3
GND
O7
O6
D7
D6
O5
O4
D5
D4
CP
MR
1
23
4
5
7
9
6
810 11 12 13 14
15
16
17
18
1920
O6
D7
D6
O5
D5
D
0
O
0
O
3
GND
CP
O
4
D
4
MR
V
CC
O
7
INDEX
D1
O1
D3
O2
D2
NOTE:
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑ = LOW-to-HIGH Clock Transition
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
3
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1µA
IIL Input LOW Current(4) VCC = Max. VI = 0.5V — — ±1
IIInput HIGH Current(4) VCC = Max., VI = VCC (Max.) — — ±1µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 –225 mA
VOH Output HIGH Voltage VCC = Min IOH = –6mA MIL 2.4 3.3 —
VIN = VIH or VIL IOH = –8mA IND V
IOH = –12mA MIL 2 3 —
IOH = –15mA IND
VOL Output LOW Voltage VCC = Min IOL = 32mA MIL — 0.3 0.5 V
VIN = VIH or VIL IOL = 48mA IND
VHInput Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max. — 0.01 1 mA
VIN = GND or VCC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4 . The test limit for this parameter is ±5µA at TA = –55°C.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
4
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current VCC = Max. — 0.5 2 mA
TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply VCC = Max. VIN = VCC — 0.15 0.25 mA/
Current(4) Outputs Open VIN = GND M Hz
MR = VCC
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 1.5 3.5 mA
Outputs Open VIN = GND
fCP = 10MHz
50% Duty Cycle
MR = VCC VIN = 3.4V — 2 5.5
One Bit Toggling VIN = GND
fi = 5MHz
50% Duty Cycle
VCC = Max. VIN = VCC — 3.8 7.3(5)
Outputs Open VIN = GND
fCP = 10MHz
50% Duty Cycle
MR = VCC VIN = 3.4V — 6 16.3(5)
Eight Bits Toggling VIN = GND
fi = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
74FCT273AT 74FCT273CT
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 2 7.2 2 5.8 ns
tPHL CP to Ox RL = 500Ω
tPLH Propagation Delay 2 7.2 2 6.1 ns
tPHL MR to Ox
tSU Set-up Time HIGH or LOW 2 — 2 — n s
Dx to CP
tHHold Time HIGH or LOW 1.5 — 1.5 — ns
Dx to CP
tWCP Pulse Width HIGH or LOW 6 — 6 — ns
tWMR Pulse Width LOW 6 — 6 — ns
tREM Recovery Time MR to CP 2 — 2 — ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
54FCT273T 54FCT273AT 54FCT273CT
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 2 15 2 8.3 2 6.5 ns
tPHL CP to Ox RL = 500Ω
tPLH Propagation Delay 2 1 5 2 8.3 2 6.8 ns
tPHL MR to Ox
tSU Set-up Time HIGH or LOW 3 . 5 — 2 — 2 — ns
Dx to CP
tHHold Time HIGH or LOW 2 — 1.5 — 1.5 — ns
Dx to CP
tWCP Pulse Width HIGH or LOW 7 — 6 — 6 — ns
tWMR Pulse Width LOW 7 — 6 — 6 — ns
tREM Recovery Time MR to CP 5 — 2.5 — 2.5 — ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
6
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
Pulse
Generator
RT
D.U.T
.
VCC
VIN
CL
VOUT
50pF 500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CO NTROL
tSU tH
tREM
tSU tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
7
ORDERING INFORMATION
IDT XX
Temp. Range XXXX
Device Type XX
Package X
Process
SO
PY
Q
Industrial Options
Small Outline IC
Shink Small Outline Package
Quarter-size Small Outline Package
Octal D Flip-Flop with Master Reset
54
74 – 55°C to +125°C
– 40°C to +85°C
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
BIndustrial
MIL-STD-883, Class B
FCT
273T
273AT
273CT
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
