NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
DABiC-5 32-Bit Serial Input Latched Sink Drivers
A6832
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
Date of status change: November 1, 2010
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Last T ime Buy
▪ Thermal printheads
▪ Multiplexed LED displays
▪ Incandescent lamps
12
13
14
15
16
17
10
11
9
8
7
27
26
25
24
23
22
21
28
20
19
18
35
34
33
32
31
36
37
38
39
29
2
1
44
43
42
3
4
5
6
40
41
30
Description
Intended originally to drive thermal printheads, the A6832 has
been optimized for low output-saturation voltage, high-speed
operation, and pin configurations that are the most convenient
for the tight space requirements of high-resolution printheads.
These integrated circuits can also be used to drive multiplexed
LED displays or incandescent lamps at up to 125 mA peak
current. The combination of bipolar and MOS technologies
gives the A6832 arrays an interface flexibility beyond the reach
of standard buffers and power driver circuits.
The devices each have 32 bipolar NPN open-collector saturated
drivers, a CMOS data latch for each of the drivers, two 16-bit
CMOS shift registers, and CMOS control circuitry. The high-
speed CMOS shift registers and latches allow operation with
most microprocessor-based systems. Use of these drivers with
TTL may require input pull-up resistors to ensure an input logic
high. MOS serial data outputs permit cascading for interface
applications requiring additional drive lines.
The A6832 is supplied in a 44-lead plastic leaded chip carrier,
for surface-mount applications requiring minimum area. These
devices are lead (Pb) free, with 100% matte tin plated
leadframes.
26185.110G
Features and Benefits
▪ 3.3 to 5 V logic supply range
▪ To 10 MHz data input rate
▪ Schmitt trigger inputs for improved noise immunity
▪ Low-power CMOS logic and latches
▪ 40 V current sink outputs
▪ Low saturation voltage
▪ –40°C operation available
DABiC-5 32-Bit Serial Input Latched Sink Drivers
Package: 44-pin PLCC (suffix EP)
Applications:
Functional Block Diagram
Not to scale
A6832
32-BIT S HIFT R E GIS TE R
LATCHES
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
V
DD
SERIAL DATA
OUT
MOS
BIPOLAR
OUT OUT OUT OUT OUT OUT
12330 31 32
GROUND
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6832
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Logic Supply Voltage VDD 7V
Input Voltage Range VIN
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static-electrical
charges.
–0.3 to VDD + 0.3 V
Output Voltage VOUT 40 V
Continuous Output Current IOUT 125 mA
Package Power Dissipation PDSee Allowable Power Dissipation chart. – –
Operating Ambient Temperature TA
Range E –40 to 85 ºC
Range S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Selection Guide
Part Number Packing Operating Temperature (ºC) Package
A6832EEPTR-T 450 pieces per reel –20 to 85 44-pin PLCC
A6832SEPTR-T 450 pieces per reel –40 to +85
50 75 100 125 15
0
PACKAGE POWER DISSIPATION (W)
AMBIENT TEMPERATURE
(
º C
)
25
4.0
3.0
3.5
0.5
0
2.5
2.0
1.5
1.0
4.5
A6832EP, R = 54 °C/W
θJA
A6832EP, R = 30 °C/W
θJA
Allowable Power Dissipation, PD*
*Additional thermal information is available on the Allegro Web site.
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6832
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V
Characteristic Symbol Test Conditions
Vdd = 3.3 V Vdd = 5 V
Units
Min. Typ. Max. Min. Typ. Max.
Output Leakage Current ICEX VOUT = 40 V – – 10 – – 10 μA
Collector–Emitter
Saturation Voltage VCE(SAT)
IOUT = 50 mA – – 275 – – 275 mV
IOUT = 100 mA – – 550 – – 550 mV
Input Voltage VIN(1) 2.2 – – 3.3 – – V
VIN(0) – – 1.1 – – 1.7 V
Input Current IIN(1) VIN = VDD – < 0.01 1.0 – < 0.01 1.0 μA
IIN(0) VIN = 0 V – < –0.01 –1.0 – < –0.01 –1.0 μA
Serial Data Output Voltage VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V
VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V
Maximum Clock Fre-
quency2fc10 – – 10 – – MHz
Logic Supply Current IDD(1) One output on, IOUT = 100 mA – – 6.0 – – 6.0 mA
IDD(0) All outputs off – – 100 – – 100 μA
Output Enable-to-Output
Delay
tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs
ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs
Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs
tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs
Output Fall Time tfVCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs
Output Rise Time trVCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs
Clock-to-Serial Data Out Delay tp(CH-SQX) IOUT = ±200 μA – 50 – – 50 – ns
1Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin.
2Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed.
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Serial Shift Register Contents Serial Latch Contents Output Output Contents
Data Clock Data Strobe Enable
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INInput I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNHP
1P2P3... PN-1 PN
X X X ... X X L H H H ... H H
Truth Table
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6832
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Timing Requirements and Specifi cations
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT ENABLE
OUT
N
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A B
D E
HIGH = ALL OUTPUTS ENABLED
p(S T H-QL)
t
p(C H-S Q X )
t
DATA
p(S T H-QH)
t
OUTPUT ENABLE
OUT
N
DATA
10%
50%
dis (B Q )
t
en(BQ)
t
LOW = ALL OUTPUTS BLANKED (DISABLED)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specifi ed maximum clock frequency.
Serial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
Key Description Symbol Time (ns)
A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25
B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25
C Clock Pulse Width tw(CH) 50
D Time Between Clock Activation and Strobe tsu(C) 100
E Strobe Pulse Width tw(STH) 50
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6832
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
1
4
5
6
18
19
20
21
22
23
24
25
26
27
28 40
41
42
43
44
2
3
7
8
9
10
11
12
13
14
15
16
17
OUT
NC
STROBE
1
GROUND
SERIAL
DATA IN
LOGIC
SUPPLY
CLOCK
SERIAL
DATA OUT
OUTPUT
ENABLE
NC
OUT32
38
39
37
36
35
34
33
32
31
30
29
OUT31
OUT21
NC
OUT13
OUT16
NC
OUT17
OUT20
NC
VDD
32
SHIFT REGISTER
LATCHES
SHIFT REGISTER
LATCHES
OUT12
OUT2
Pin-out Diagram
Typical Input Circuit Typical Output Driver
IN
VDD
OUT
VDD
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6832
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package EP, 44-pin PLCC
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2003-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
2144
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
For Reference Only
(reference JEDEC MS-018 AC)
Dimensions in millimeters
C
SEATING
PLANE
0.51
4.57 MAX
16.59 ±0.08
16.59 ±0.08
7.75 ±0.36
7.75 ±0.36
7.75 ±0.367.75 ±0.36
C0.10
44X
0.74 ±0.08
17.53 ±0.13
17.53 ±0.13
1.27
0.43 ±0.10
