KS32P6632-LC/TX SOLID DISK CONTROLLER 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW Samsung's KS32P6632-LC/TX is NAND flash memory controller which can control flash memories as solid state disk. It provides PC Card ATA/IDE interface, host transfer rates up to 20.0MB/S and flash memory transfer rates up to 10MB/S. KS32P6632-LC/TX can control flash memory maximum 32 pieces if use the external buffer and decoder. The device is designed using 0.5-um CMOS process, haused in 144-LQFP(LC)/100-TQFP(TX) package. It can support the error correction code(ECC) function to detect and correct errors automatically. An outstanding feature of the KS32P6632-LC/TX flash disk controller is its CPU core: the ARM7TDMI 16/32-bit RISC processor, designed by Advanced RISC Machine(ARM),Ltd. The ARM core is a low-power, generalpurpose, microprocessor macro-cell that was developed for use in application-specific and customer-specific intergrated circuit. Its simple, elegant, and fully static design is particularly suitable for cost and power sensitive applications. -- PA Card-ATA/True IDE/CompactFlash compatible host interface -- Automatic sensing of PC Card ATA and 68-pin IDE -- Included 256-byte CIS RAM -- Support the five PC Card ATA addressing modes -- Host data transfer rate: 20 MB/S -- Flash data transfer rate: 10 MB/S -- Host Interface bus width: 8/16-bit Access -- Flash Interface bus width: 8-bit Access -- Support 3 power save mode: stop/idle/active -- Support up to 32 flash memories -- Support 32-Mbit, 64-Mbit, 128-Mbit and 256-Mbit NAND flash memory made by Samsung -- Auto power down function -- 1-bit ECC function -- Available 100-pin TQFP and 144-pin LQFP -- Operating Voltage: 3.3 V to 5.0 V 1-1 PRODUCT OVERVIEW KS32P6632-LC/TX SOLID DISK CONTROLLER FEATURES Microprocessor Architecture Interrupts * 16/32-bit RISC architecture * 8 interrupt sources * Efficient and powerful ARM7TDMI CPU core * Normal or fast interrupt modes (IRQ, FIQ) * Cost-effective JTAG based debug solution Programmable Timer System Manager * * 1-channel 16-bit programmable timer 512-Kbyte virtually addressable memory space Power Consumption ( @3.3 V ) * Support 8-bit external bus for SRAM/ROM * Active Mode: 30mA (TYP), 40mA (MAX) * Programmable external memory access time * Idle Mode: 20mA * Included 32-Kbytes internal ROM (OTP) * Stop Mode: 30uA * Included 6-Kbytes internal SRAM PC Card-ATA/IDE Interface DMA Controller * Built in 256-Bytes SRAM for CIS * Two-channel, general-purpose DMA controller * Support memory and I/O addressing mode * Memory to memory, PCMCIA to/from memory data transfers without CPU intervention * Support True IDE mode * 1-bit ECC * Support for 8/16/32-bit data transfers * Increment or decrement of source or destination address Operating Voltage Range * 3.3 V to 5.0 V Cache Operating Frequency * 1-Kbyte instruction cache * * Direct map configuration * Cache can be controlled by software 1-2 Up to 20MHz Package Type * 144-pin LQFP * 100-pin TQFP KS32P6632-LC/TX SOLID DISK CONTROLLER PRODUCT OVERVIEW BLOCK DIAGRAM Local Bus ARM7TDMI CPU CORE (20 MHz) Instruction Cache (1-KB) Bus Router Address Decoder DMA0 PAMCIA/ ATA DMA1 CIS (256B) Interrupt Controller Timer S-Bus System Manager Bus Interface Bus Arbitration System Bus Controller Memory Controller (ROM/SRAM) SRAM (6-KB) OTPROM (32-KB) Figure 1-1. Block Diagram 1-3 KS32P6632-LC/TX SOLID DISK CONTROLLER 2 PIN INFORMATION PIN INFORMATION CONTROLLER PACKAGE DRAWING VDD5 VDETO FDB1 FDB2 FDB3 VDD6 FDB4 FDB5 FDB6 FDB7 GND4 Xin Xout GND5 FCE0 FCE1 FCE2 FCE3 FCE4 FCE5 FCE6 FWP FPWR CTEST XTEST 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 VDD7 FCE7 FCE8 FCE9 TDO nTRST TEST1 TEST2 GND6 TDI TMS TCK GND7 XDB10 XDB9 XDB8 XDB2 XDB1 XDB0 PVDD2 XIOIS16 XSTSCHG XDASP XREG XINPACK 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 KS32P6632-TX 100-TQFP (Top View) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 FDB0 GND3 FALE0 FCLE0 FRE0 FWE0 FRDY0 VDD4 FALE1 FCLE1 FRE1 GND2 FVPP XDB3 XDB4 XDB5 XDB6 XDB7 PVDD1 XDB11 XDB12 XDB13 XDB14 XDB15 VDD3 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND1 XCE2 XCE1 XADR10 XOE XIORD XIOWR XADR9 XADR8 VDD2 XWE XRDY XADR7 XADR6 XDAR5 nRESET XADR4 XADR3 XADR2 XADR1 XADR0 VDD1 XDS XRESET XWAIT Figure 2-1. KS32P6632-TX Pin Assignment 2-1 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER VDD5 ADDR10 VDETO FDB1 FDB9 FDB2 FDB10 FDB3 FDB11 VDD6 FDB4 FDB12 FDB5 FDB13 FDB6 FDB14 FDB7 FDB15 GND4 Xin Xout GND5 ADDR11 FCE0 ADDR12 FCE1 ADDR13 FCE2 FCE3 FCE4 FCE5 FCE6 FWP FPWR CTEST XTEST 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 VDD7 FCE7 ADDR16 FCE8 ADDR15 FCE9 ADDR14 TDO DATA7 nTRST DATA6 TEST1 DATA5 TEST2 DATA4 GND6 DATA3 TDI DATA2 TMS DATA1 TCK DATA0 GND7 XDB10 XDB9 XDB8 XDB2 XDB1 XDB0 PVDD2 XIOIS16 XSTSCHG XDASP XREG XINPACK 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 KS32P6632-LC 144-LQFP (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FWE1 GND1 FRDY1 XCE2 XCE1 XADR10 XOE XP56 XIORD XP55 XIOWR XADR9 nWE XADR8 nOE VDD2 XWE nSCS XRDY nRCS XADR7 CMODE XADR6 SW1 XDAR5 SW0 nRESET XADR4 XADR3 XADR2 XADR1 XADR0 VDD1 XDS XRESET XWAIT Figure 2-2. KS32P6632-LC Pin Assignment 2-2 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FDB8 FDB0 GND3 ADDR9 FALE0 ADDR8 FCLE0 ADDR7 FRE0 ADDR6 FWE0 ADDR5 FRDY0 VDD4 ADDR4 FALE1 ADDR3 FCLE1 ADDR2 FRE1 ADDR1 GND2 ADDR0 FVPP XDB3 XDB4 XDB5 XDB6 XDB7 PVDD1 XDB11 XDB12 XDB13 XDB14 XDB15 VDD3 KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION CONTROLLER PIN ASSIGNMENTS AND PIN TYPE Table 2-1. Controller Pin Assignments and Pin Type for 144-LQFP Pin Number Signal Name Pin Type I/O Type Function 1 XWAIT O O1 Wait of PCMCIA 2 XRESET I I1 Reset of PCMCIA 3 XDS I I9 Device select for IDE 4 VDD1 - - System power 5 XADR0 I I1 Address bus of PCMCIA 6 XADR1 I I1 Address bus of PCMCIA 7 XADR2 I I1 Address bus of PCMCIA 8 XADR3 I I1 Address bus of PCMCIA 9 XADR4 I I1 Address bus of PCMCIA 10 nRESET I I3 System power reset 11 SW0 I I6 Dip switch input for firmware. Select the number of flash memory chip (0: 20ea, 1: 32ea) 12 XADR5 I I1 Address bus of PCMCIA 13 SW1 I I6 Dip switch input for firmware. ROM selection 0: Internal ROM (OTP) 1: External ROM 14 XADR6 I I1 Address bus of PCMCIA 15 CMODE I I6 Interrupt enable/disable for CPU 16 XADR7 I I1 Address bus of PCMCIA 17 nRCS O O4 External ROM chip select 18 XRDY O B1 Ready(IREQ) of PCMCIA (Use tri-output only, not input) 19 nSCS I/O O4 External SRAM chip select 20 XWE I I2 Write enable of PCMCIA 21 VDD2 - - System power 22 nOE O O4 Out enable for external memory 23 XADR8 I I1 Address bus of PCMCIA 24 nWE O O6 Write enable for external memory 25 XADR9 I I1 Address bus of PCMCIA 26 XIOWR I I2 IOWR of PCMCIA 27 XP55 I I8 Input for Inverter 28 XIORD I I2 IORD of PCMCIA 29 XP56 O O3 Output for inverter 30 XOE I I2 Output enable of PCMCIA 2-3 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-1. Controller Pin Assignments and Pin Type for 144-LQFP (Continued) Pin Number 2-4 Signal Name Pin Type I/O Type Function 31 XADR10 I I1 Address bus of PCMCIA 32 XCE1 I I2 Card enable1 of PCMCIA 33 XCE2 I I2 Card enable2 of PCMCIA 34 FRDY1 I I5 Ready signal of flash chips of flash bus1 35 GND1 - - Ground 36 FWE1 O O5 37 VDD3 - - 38 XDB15 I/O B10 Data bus of PCMCIA 39 XDB14 I/O B10 Data bus of PCMCIA 40 XDB13 I/O B10 Data bus of PCMCIA 41 XDB12 I/O B10 Data bus of PCMCIA 42 XDB11 I/O B10 Data bus of PCMCIA 43 PVDD1 - - 44 XDB7 I/O B10 Data bus of PCMCIA 45 XDB6 I/O B10 Data bus of PCMCIA 46 XDB5 I/O B10 Data bus of PCMCIA 47 XDB4 I/O B10 Data bus of PCMCIA 48 XDB3 I/O B10 Data bus of PCMCIA 49 FVPP - - 50 ADDR0 O O4 51 GND2 - - 52 ADDR1 O O4 Address bus for external memory 53 FRE1 I/O B9 Read enable flash chips of flash bus1 54 ADDR2 O O4 Address bus for external memory 55 FCLE1 I/O B5 Command latch enable of flash chips of flash bus1 56 ADDR3 O O4 Address bus for external memory 57 FALE1 I/O B5 Address latch enable of flash chips of flash bus1 58 ADDR4 O O4 Address bus for external memory 59 VDD4 - - 60 FRDY0 I/O B5 Ready signal of flash chips of flash bus1 61 ADDR5 O O4 Address bus for external memory 62 FWE0 I/O B9 Write enable of flash chips of flash bus0 63 ADDR6 O O4 Address bus for external memory Write enable of flash chips of flash bus1 System power PCMCIA power High voltage power for internal OTP Address bus for external memory Ground System power KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION Table 2-1. Controller Pin Assignments and Pin Type for 144-LQFP (Continued) Pin Number Signal Name Pin Type I/O Type Function 64 FRE0 I/O B9 Read enable flash chips of flash bus 0 65 ADDR7 O O4 Address bus for external memory 66 FCLE0 I/O B5 Command latch enable of flash chips of flash bus 0 67 ADDR8 O O4 Address bus for external memory 68 FALE0 I/O B5 Address latch enable of flash chips of flash bus 0 69 ADDR9 O O4 Address bus for external memory 70 GND3 - - 71 FDB0 I/O B7 I/O of flash chips of flash bus 0,1 72 FDB8 I/O B7 I/O of flash chips of flash bus 0,1 73 VDD5 - - 74 ADDR10 O O4 Address bus for external memory 75 VDETO O O2 Voltage detect output 76 FDB1 I/O B7 I/O of flash chips of flash bus 0,1 77 FDB9 I/O B7 I/O of flash chips of flash bus 0,1 78 FDB2 I/O B7 I/O of flash chips of flash bus 0,1 79 FDB10 I/O B7 I/O of flash chips of flash bus 0,1 80 FDB3 I/O B7 I/O of flash chips of flash bus 0,1 81 FDB11 I/O B7 I/O of flash chips of flash bus 0,1 82 VDD6 - - 83 FDB4 I/O B7 I/O of flash chips of flash bus 0,1 84 FDB12 I/O B7 I/O of flash chips of flash bus 0,1 85 FDB5 I/O B7 I/O of flash chips of flash bus 0,1 86 FDB13 I/O B7 I/O of flash chips of flash bus 0,1 87 FDB6 I/O B7 I/O of flash chips of flash bus 0,1 88 FDB14 I/O B7 I/O of flash chips of flash bus 0,1 89 FDB7 I/O B7 I/O of flash chips of flash bus 0,1 90 FDB15 I/O B7 I/O of flash chips of flash bus 0,1 91 GND4 - - 92 XI - OC Input clock 93 XO - OC Output clock 94 GND5 - - 95 ADDR11 O O4 Address bus for external memory 96 FCE0 I/O B3 Chip enable 0 of flash chips of flash bus 0,1 Ground System power System power Ground Ground 2-5 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-1. Controller Pin Assignments and Pin Type for 144-LQFP (Continued) Pin Number 2-6 Signal Name Pin Type I/O Type Function 97 ADDR12 O O4 Address bus for external memory 98 FCE1 I/O B3 Chip enable 1 of flash chips of flash bus 0,1 99 ADDR13 O O4 Address bus for external memory 100 FCE2 I/O B3 Chip enable 2 of flash chips of flash bus 0,1 101 FCE3 I/O B3 Chip enable 3 of flash chips of flash bus 0,1 102 FCE4 I/O B3 Chip enable 4 of flash chips of flash bus 0,1 103 FCE5 I/O B3 Chip enable 5 of flash chips of flash bus 0,1 104 FCE6 I/O B3 Chip enable 6 of flash chips of flash bus 0,1 105 FWP I/O B5 Write protect of flash chips of flash bus 0,1 106 FPWR O O2 Power control signal for flash memory 107 CTEST I I4 Core test mode select signal 108 XTEST I I4 Test input for test mode 109 VDD7 - - System power 110 FCE7 I/O B3 Chip enable 7 of flash chips of flash bus 0,1 111 ADDR16 O O4 Address bus for external memory 112 FCE8 I/O B3 Chip enable 8 of flash chips of flash bus 0,1 113 ADDR15 O O4 Address bus for external memory 114 FCE9 I/O B3 Chip enable 9 of flash chips of flash bus 0,1 115 ADDR14 O O4 Address bus for external memory 116 TDO I/O B2 Test data output for JTAG 117 DATA7 I/O B8 Data bus for external memory 118 nTRST I I4 Test reset for JTAG 119 DATA6 I/O B8 Data bus for external memory 120 TEST1 I I4 OTP mode select signal 1 121 DATA5 I/O B8 Data bus for external memory 122 TEST2 I I4 OTP mode select signal 2 123 DATA4 I/O B8 Data bus for external memory 124 GND6 - - 125 DATA3 I/O B8 Data bus for external memory 126 TDI I I4 Test data input for JTAG 127 DATA2 I/O B8 Data bus for external memory 128 TMS I I4 Test mode select for JTAG 129 DATA1 I/O B8 Data bus for external memory Ground KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION Table 2-1. Controller Pin Assignments and Pin Type for 144-LQFP (Continued) Pin Number Signal Name Pin Type I/O Type Function I I4 Test clock for JTAG Data bus for external memory 130 TCK 131 DATA0 I/O B8 132 GND7 - - 133 XDB10 I/O B10 Data bus of PCMCIA 134 XDB9 I/O B10 Data bus of PCMCIA 135 XDB8 I/O B10 Data bus of PCMCIA 136 XDB2 I/O B10 Data bus of PCMCIA 137 XDB1 I/O B10 Data bus of PCMCIA 138 XDB0 I/O B10 Data bus of PCMCIA 139 PVDD2 - - 140 XIOIS16 I/O B1 IOIS16 of PCMCIA 141 XSTSCHG I/O B1 STSCHG of PCMCIA 142 XDASP I/O B4 DASP for IDE 143 XREG I I2 REG of PCMCIA 144 XINPACK O O1 INPACK of PCMCIA Ground PCMCIA power 2-7 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-2. Controller Pin Assignments and Pin Type for 100-TQFP Pin Number 2-8 Signal Name Pin Type I/O Type Function 1 XWAIT O O1 Wait of PCMCIA 2 XRESET I I1 Reset of PCMCIA 3 XDS I I9 Device select for IDE 4 VDD1 - - System power 5 XADR0 I I1 Address bus of PCMCIA 6 XADR1 I I1 Address bus of PCMCIA 7 XADR2 I I1 Address bus of PCMCIA 8 XADR3 I I1 Address bus of PCMCIA 9 XADR4 I I1 Address bus of PCMCIA 10 nRESET I I3 System power reset 11 XADR5 I I1 Address bus of PCMCIA 12 XADR6 I I1 Address bus of PCMCIA 13 XADR7 I I1 Address bus of PCMCIA 14 XRDY I/O B1 Ready (IREQ) of PCMCIA (Use tri-output only, not input) 15 XWE I I2 Write enable of PCMCIA 16 VDD2 - - System power 17 XADR8 I I1 Address bus of PCMCIA 18 XADR9 I I1 Address bus of PCMCIA 19 XIOWR I I2 IOWR of PCMCIA 20 XIORD I I2 IORD of PCMCIA 21 XOE I I2 Output enable of PCMCIA 22 XADR10 I I1 Address bus of PCMCIA 23 XCE1 I I2 Card enable1 of PCMCIA 24 XCE2 I I2 Card enable2 of PCMCIA 25 GND1 - - Ground 26 VDD3 - - System power 27 XDB15 I/O B10 Data bus of PCMCIA 28 XDB14 I/O B10 Data bus of PCMCIA 29 XDB13 I/O B10 Data bus of PCMCIA 30 XDB12 I/O B10 Data bus of PCMCIA 31 XDB11 I/O B10 Data bus of PCMCIA 32 PVDD1 - - PCMCIA power KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION Table 2-2. Controller Pin Assignments and Pin Type for 100-TQFP (Continued) Pin Number Signal Name Pin Type I/O Type Function 33 XDB7 I/O B10 Data bus of PCMCIA 34 XDB6 I/O B10 Data bus of PCMCIA 35 XDB5 I/O B10 Data bus of PCMCIA 36 XDB4 I/O B10 Data bus of PCMCIA 37 XDB3 I/O B10 Data bus of PCMCIA 38 FVPP - - High voltage power for OTP 39 GND2 - - Ground 40 FRE1 I/O B9 Read enable flash chips of flash bus1 41 FCLE1 I/O B5 Command latch enable of flash chips of flash bus1 42 FALE1 I/O B5 Address latch enable of flash chips of flash bus1 43 VDD4 - - 44 FRDY0 I/O B5 Ready signal of flash chips of flash bus 0 45 FWE0 I/O B9 Write enable of flash chips of flash bus 0 46 FRE0 I/O B9 Read enable flash chips of flash bus 0 47 FCLE0 I/O B5 Command latch enable of flash chips of flash bus 1 48 FALE0 I/O B5 Address latch enable of flash chips of flash bus 1 49 GND3 - - 50 FDB0 I/O B7 51 VDD5 - - 52 VDETO O O2 Voltage detect output 53 FDB1 I/O B7 I/O of flash chips of flash bus 0,1 54 FDB2 I/O B7 I/O of flash chips of flash bus 0,1 55 FDB3 I/O B7 I/O of flash chips of flash bus 0,1 56 VDD6 - - 57 FDB4 I/O B7 I/O of flash chips of flash bus 0,1 58 FDB5 I/O B7 I/O of flash chips of flash bus 0,1 59 FDB6 I/O B7 I/O of flash chips of flash bus 0,1 60 FDB7 I/O B7 I/O of flash chips of flash bus 0,1 61 GND4 - - 62 XI - OC Input clock 63 XO - OC Output clock 64 GND5 - - 65 FCE0 I/O B3 System power Ground I/O of flash chips of flash bus 0,1 System power System power Ground Ground Chip enable 0 of flash chips of flash bus 0,1 2-9 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-2. Controller Pin Assignments and Pin Type for 100-TQFP (Continued) Pin Number 2-10 Signal Name Pin Type I/O Type Function 66 FCE1 I/O B3 Chip enable 1 of flash chips of flash bus 0,1 67 FCE2 I/O B3 Chip enable 2 of flash chips of flash bus 0,1 68 FCE3 I/O B3 Chip enable 3 of flash chips of flash bus 0,1 69 FCE4 I/O B3 Chip enable 4 of flash chips of flash bus 0,1 70 FCE5 I/O B3 Chip enable 5 of flash chips of flash bus 0,1 71 FCE6 I/O B3 Chip enable 6 of flash chips of flash bus 0,1 72 FWP I/O B5 Write protect of flash chips of flash bus 0,1 73 FPWR O O2 Power control signal for flash memory 74 CTEST I I4 Core test mode select signal 75 XTEST I I4 Test input for test mode 76 VDD7 - - System power 77 FCE7 I/O B3 Chip enable 7 of flash chips of flash bus 0,1 78 FCE8 I/O B3 Chip enable 8 of flash chips of flash bus 0,1 79 FCE9 I/O B3 Chip enable 9 of flash chips of flash bus 0,1 80 TDO I/O B2 Test data output for JTAG 81 nTRST I I4 Test reset for JTAG 82 TEST1 I I4 OTP mode select signal 1 83 TEST2 I I4 OTP mode select signal 2 84 GND6 - - Ground 85 TDI I I4 Test data input for JTAG 86 TMS I I4 Test mode select for JTAG 87 TCK I I4 Test clock for JTAG 88 GND7 - - Ground 89 XDB10 I/O B10 Data bus of PCMCIA 90 XDB9 I/O B10 Data bus of PCMCIA 91 XDB8 I/O B10 Data bus of PCMCIA 92 XDB2 I/O B10 Data bus of PCMCIA 93 XDB1 I/O B10 Data bus of PCMCIA 94 XDB0 I/O B10 Data bus of PCMCIA 95 PVDD2 - - 96 XIOIS16 I/O B1 IOIS16 of PCMCIA 97 XSTSCHG I/O B1 STSCHG of PCMCIA 98 XDASP I/O B4 DASP for IDE 99 XREG I I2 REG of PCMCIA 100 XINPACK O O1 INPACK of PCMCIA PCMCIA power KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION Table 2-3. I/O Type Description I/O Type Pad Type Description I1 PVIL3 3.3V/5.0V TTL schmitt trigger level PCMCIA LIN input buffer I2 PVILU3 3.3V/5.0V TTL schmitt trigger level PCMCIA LIN input buffer with pull-up register I3 PIS CMOS schmitt trigger level input buffer I4 PIC CMOS level input buffer I5 PICU CMOS level input buffer with pull-up register I6 PICD CMOS level input buffer with pull-down register I8 PVIC3 3.3V/5.0V CMOS level input buffer I9 PVICU3 3.3V/5.0V CMOS level input buffer with pull-up resister O1 PVOB43 3.3V/5.0V 4mA PCMCIA output buffer without SRC O2 POD4 4mA open drain output buffer O3 POB4 4mA normal output buffer O4 POB4SM 4mA normal output buffer with medium slew-rate control O5 POB16SM 16mA normal output buffer with medium slew-rate control O6 POB12 12mA normal output buffer B1 PVBTT43 3.3V/5.0V 4mA PCMCIA LIN bi-directional buffer without SRC B2 PBCT4 CMOS level input buffer and 4mA tri-state output buffer B3 PBCT4SM CMOS level input buffer and 4mA tri-state output buffer with medium slew-rate control B4 PBCUT4SM CMOS level input buffer with pull-up register and 4mA tri-state output buffer with medium slew-rate control B5 PBCT8SM CMOS level input buffer and 8mA tri-state output buffer with medium slew-rate control B6 PBCUT8SM CMOS level input buffer with pull-up register and 8mA tri-state output buffer with medium slew-rate control B7 PBCDT8 CMOS level input buffer with pull-down register and 8mA tri-state output buffer B8 PBSDT4SM CMOS schmitt trigger level input buffer with pull-down register and 4mA tri-state output buffer with medium slew-rate control B9 PBCT16SM CMOS level input buffer and 16mA tri-state output buffer with medium slew-rate control B10 PVBTT83 3.3V/5.0V 8mA PCMCIA LIN bi-directional buffer without SRC OC PSOSCM26 Oscillator cell with enable and register 2-11 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER PIN DESCRIPTION FOR HOST INTERFACE Table 2-4. Pin Description for Host Interface Signal Name 100-Pin Number 144-Pin Number XARD0 5 5 XARD1 6 6 XARD2 7 7 XARD3 8 8 XARD4 9 9 XARD5 11 12 XARD6 12 14 XARD7 13 16 XARD8 17 23 XARD9 18 25 XARD10 22 31 XDB0 94 138 XDB1 93 137 XDB2 92 136 XDB3 37 48 XDB4 36 47 XDB5 35 46 XDB6 34 45 XDB7 33 44 XDB8 91 135 XDB9 90 134 XDB10 89 133 XDB11 31 42 XDB12 30 41 XDB13 29 40 XDB14 28 39 XDB15 27 38 XREG 99 143 I/O Description ADDRESS BUS[10:0]: These address lines along with the -REG signal are used to select the following: The I/O port address registers within the PC Storage Card, the memory mapped port address registers within the PC Storage Card, a byte in the Card's information structure and its configuration control and status registers. I This signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A[2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. DATA BUS[15:0]: These lines carry the Data, Commands and Status information between the host and the controller. XDB0 is the LSB of the even byte of the word. XDB8 is the LSB of the odd byte of the word. This signal is the same as the PC Card memory mode signal in PC Card I/O mode. I/O In True IDE mode, all Task File operations occur in byte mode on the low order bus XDB0-XDB7 while all data transfers are 16 bit using XDB0-XDB15. ATTRIBUTE MEMORY AREA SELECTION: This signal is used during memory cycles to distinguish between common memory and register (Attribute) memory accesses. High for Common memory, low for attribute memory. I The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In True IDE mode, this input signal is not used and should be connected to VCC by the host. 2-12 KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION Table 2-4. Pin Description for Host Interface (Continued) Signal Name XCE1 XCE2 100-Pin Number 144-Pin Number I/O Description 23 24 32 33 I CARD ENABLE: These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multi-plexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on XDB0-XDB7. See tables 3-7,3-8,4-3 and 4-4. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE mode, CS0 is the chip select for the task file registers while CS1 is used to select the alternate status register and the device control register. XOE 21 30 I OUTPUT ENABLE: This is an output enable strobe generated by the host interface. It is used to read data from the PC Card in memory mode and to read the CIS and configuration registers. In PC Card I/O mode, this signal is used to read the CIS and configuration registers. To enable True IDE mode this input should be grounded by the host. XWE 15 20 I WRITE ENABLE: This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode, this input signal is not used and should be connected to VCC by the host. XWAIT 1 1 O WAIT: The -WAIT signal is driven low by the PC Card to signal the host to delay completion of a memory or I/O cycle that is in progress. IORDY: In True IDE mode, this output signal may be used as IORDY. 2-13 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-4. Pin Description for Host Interface (Continued) Signal Name XIOIS16 100-Pin Number 144-Pin Number I/O Description 96 140 I/O I/O PORT IS 16 BITS: Memory mode -- The PC Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O operation - When the PC Card is configured for I/O operation pin 24 is used for the -I/O selected is 16-Bit Port (-IOIS16) function. A low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. In True IDE mode, this output signal is asserted low when this device is expecting a word data transfer cycle. XINPACK 100 144 O INPUT PORT ACKNOWLEDGE: This signal is not used in memory mode. The Input acknowledge signal is asserted by the PC Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the PC Card and the CPU. In True IDE mode, this output signal is not used and should be connected at the host. XRDY 14 18 O READY/BUSY: In memory mode, this signal is set high when the PC Card is ready to accept a new data transfer operation and held low when the card is busy. The host memory card socket must provide a pull-up resistor. At power up and at reset, the RDY/-BSY signal is held low (busy) until the PC Card has completed its power up or reset function. No access of any type should be made to the PC Card during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true: The PC Card has been powered up with RESET continuously disconnected or asserted. I/O operation - After the PC Card has been configured for I/O operation, this signal is used as Interrupt request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE mode, this signal is the active high Interrupt request to the host. 2-14 KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION Table 2-4. Pin Description for Host Interface (Continued) Signal Name XIORD 100-Pin Number 144-Pin Number I/O 20 28 I Description I/O READ: This signal is not used in memory mode. This is an I/O read strobe generated by the host. This signal gates I/O data onto the bus from the PC Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has the same function as in PC Card I/O Mode. XIOWR 19 26 I I/O WRITE: This signal is not used in memory mode. The I/O write strobe pulse is used to clock I/O data on the card data bus into the PC Card controller registers when the PC Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In True IDE mode, this signal has the same function as in PC Card I/O Mode. XSTSCHG 97 141 I/O STATUS CHANGED: This signal is asserted high as the BVD1 signal since a battery is not used with this product. This signal is asserted low to alert the host to changes in the RDY/-BSY and write protect states, while the I/O interface is configured. Its use is controlled by the Card config and status In the True IDE mode, this input / output is the pass diagnostic signal in the Master / Slave handshake protocol. XDS 3 3 I CARD SELECT: In True IDE mode, this signal is used for configure this device as a master or slave. When it is grounded , the device is configured as a master. When this signal is open, the device is configured as a slave. In I/O and memory mode, this signal is not used. XRESET 2 2 I RESET: When the pin is high, this signal resets the PC Card. The PC Card is reset only at Power up if this pin is left high or open from power-up. The PC Card is also reset when the soft reset bit in the Card Configuration Option Register is set. In the True IDE mode, this input pin is the active low hardware reset from the host. 2-15 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-4. Pin Description for Host Interface (Continued) Signal Name XDASP 100-Pin Number 144-Pin Number I/O 98 142 I/O Description This output line is always driven to a high state in memory mode since a battery is not required for this product. This output line is always driven to a high state in I/O mode since this product does not support the audio function. In the True IDE mode, this input/output is the disk active/slave present signal in the Master/Slave handshake protocol. XP55 - 27 I Input for inverter XP56 - 29 O Output for inverter VDETO 52 75 O Voltage detect output 1: more than 3.6 V (Typ.) 0: less than 3.6 V (Typ.) XTEST 75 108 I Test input for test mode 2-16 KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION PIN ASSIGNMENT FOR FLASH MEMORY INTERFACE Table 2-5. Pin Description for Flash Memory Interface Signal Name 100-Pin Number 144-Pin Number I/O FDB0 50 71 FDB1 53 76 FDB2 54 78 FDB3 55 80 FDB4 57 83 FDB5 58 85 FDB6 59 87 FDB7 60 89 FDB8 - 72 FDB9 - 77 FDB10 - 79 FDB11 - 81 FDB12 - 84 FDB13 - 86 FDB14 - 88 FDB15 - 90 FRDY0 44 60 I/O FRDY1 - 34 I FALE0 48 68 I/O FALE1 42 57 I/O FCLE0 47 66 I/O FCLE1 41 55 I/O FRE0 46 64 I/O FRE1 40 53 I/O FWE0 45 62 I/O FWE1 - 36 O Description FLASH DATA BUS[15:0]: These lines are 16-bit data lines to/from the flash memory chip. I/O FLASH READY 0/1: The signal is used for indicate to the controller, which flash memory is ready to accept a command. FDB0-FDB7 are controlled by FRDY0 signal, FDB8-FDB15 are controlled by FRDY1. FLASH ADDRESS LATCH ENABLE 0/1: When this signal is asserted the controller can send an address to the flash memory by asserting of FWE pin. FDB0-FDB7 are controlled by FALE0 signal, FDB8-FDB15 are controlled by FALE1. FLASH COMMAND LATCH ENABLE 0/1: When this signal is asserted, a command can be to the flash memory. FDB0-FDB7 are controlled by FCLE0 signal, FDB8-FDB15 are controlled by FCLE1. FLASH READ ENABLE 0/1: This signal is asserted to enable the reading of data from the flash memory. FDB0-FDB7 are controlled by FRE0 signal, FDB8-FDB15 are controlled by FRE1. FALSH WRITE ENABLE 0/1: When this signal is asserted , the controller can write data to the flash memory. FDB0-FDB7 are controlled by FWE0 signal, FDB8-FDB15 are controlled by FWE1. 2-17 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-5. Pin Description for Flash Memory Interface (Continued) Signal Name 100-Pin Number 144-Pin Number FCE0 65 96 FCE1 66 98 FCE2 67 100 FCE3 68 101 FCE4 69 102 FCE5 70 103 FCE6 71 104 FCE7 77 110 FCE8 78 112 FCE9 79 114 FWP 72 105 I/O Write protect of flash chips of flash bus 0, 1 FPWR 73 106 O Power control signal for flash memory 1: Sleep mode 0: Active mode 2-18 I/O Description FLASH CHIP ENABLE [9:0]: These lines are flash memory enable signal. I/O KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION PIN ASSIGNMENT FOR EXTERNAL MEMORY CONTROL Table 2-6. Pin Description for External Memory Interface Signal Name 100-Pin Number 144-Pin Number I/O Description ADDR0 - 50 ADDR1 - 52 ADDR2 - 54 ADDR3 - 56 ADDR4 - 58 ADDR5 - 61 ADDR6 - 63 ADDR7 - 65 ADDR8 - 67 ADDR9 - 69 ADDR10 - 74 ADDR11 - 95 ADDR12 - 97 ADDR13 - 99 ADDR14 - 115 ADDR15 - 113 ADDR16 - 111 DATA0 - 131 DATA1 - 129 DATA2 - 127 DATA3 - 125 DATA4 - 123 DATA5 - 121 DATA6 - 119 DATA7 - 117 nRCS - 17 O EXTERNAL ROM CHIP SELECT: When this signal is asserted(low active) , the controller can access the external ROM device. nSCS - 19 O EXTERNAL SRAM CHIP SELECT: When this signal is asserted(low active) , the controller can access the external SRAM device. nOE - 22 O OUTPUT ENABLE: This signal is data output enable signal. When an external memory access for ROM/SRAM occurs, this signal controls the output enable port of the specific device. nWE - 24 O WRITE ENABLE: When an external memory device access for SRAM/ROM occurs, this signal control the write enable port of the specific device. EXTERNAL MEMORY ADDRESS BUS [16:0]: These signals are address bus to access external memory device as SRAM or ROM. O EXTERNAL MEMORY DATA BUS [7:0]: These signals are data bus to access external memory device as SRAM or ROM. I/O 2-19 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 2-6. Pin Description for External Memory Interface (Continued) Signal Name 100-Pin Number 144-Pin Number I/O TCK 87 130 I TEST CLOCK: The KS32P6632 contains internally in-circuit emulation block for debugger mode which use standard JTAG protocol. When the controller go into debugger mode, this signal is provided from external debugger tool. TMS 86 128 I TEST MODE SELECT: In the debugger mode, this signal select test mode. This pin should be held to "1', when do not use the JTAG block. TDI 85 126 I TEST DATA INPUT: In the debugger mode, this signal is used for carry data. from external debugger tool to the controller. nTRST 81 118 I TEST RESET: This signal should be sustained LOW first at the begging of normal operation. TDO 80 116 I/O TEST DATA OUTPUT: In the debugger mode, this signal is used for carry data. from the controller to external debugger tool. XI 62 92 OC INPUT CLOCK: This signal is system input clock. XO 63 93 OC OUTPUT CLOCK: This signal is system output clock. nRESET 10 10 I RESET: This pin is system power on reset . A low input will stop all operation within the controller. SW1 - 13 I ROM SELECTION: This pin is used for select ROM. When this signal set "1", the controller access external ROM. When this pin is "0", the controller access internal ROM. SW0 - 11 I FLASH NUMBER OF SELECTION: Basically flash memory can be connected up to 20. But if use the external buffer on pc card , flash memory can be connected up to 32. This signal is used for select number of flash. When this signal is high, can be connected up to 32. In the case of low, can be connected up to 20. CTEST 74 107 I CORE TEST: This signal is used for test CPU (ARM7TDMI) core. When this signal is low (0), the controller operate normal mode. When it is high (1), operate CPU test mode. It should be tied to GND. CMODE - 15 I INTERRUPT ENABLE: This signal is used for control interrupt signal of CPU, when the signal is set (1), interrupt signal of CPU can be enabled. When this signal is cleared (0), interrupt signal can be disabled. It should be tied to GND. TEST1 82 120 I TEST2 83 122 MODE SELECT: These signals are used for select OTP mode. When TEST1 and TEST2 are low, the controller operate normal mode. To operate the OTP mode, TEST1 and TEST2 signal should be set to low and high. The others setting mode are reserved for chip maker. 2-20 Description KS32P6632-LC/TX SOLID DISK CONTROLLER PIN INFORMATION POWER PIN ASSIGNMENT Table 2-7. Pin Description for Power Signal Signal Name 100-Pin Number 144-Pin Number I/O Description VDD 4,16,26,43,51,56,76 4,21,37,59,73,82,109 - System power supply voltage ( 3.3 V or 5.0 V) PVDD 32,95 43,139 - PCMCIA power supply voltage (3.3 V or 5.0 V) FVPP 38 49 - High voltage power for internal OTP (12.5 V). It should be tied to GND in the normal operation mode. GND 25,39,49,61,64,84,88 35,51,70,91,94,124,132 - Ground 2-21 PIN INFORMATION KS32P6632-LC/TX SOLID DISK CONTROLLER NOTES 9-22 KS32P6632-LC/TX SOLID DISK CONTROLLER 3 INTERFACE BUS TIMING INTERFACE BUS TIMMING There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card Standard. The PC Card conforms to the timing in that reference document. ATTRIBUTE MEMORY READ TIMING SPECIFICATION The attribute memory read time is defined as 300 ns. Detailed timing specifications are shown in Table 3-1. Table 3-1. Attribute Memory Read Timing Parameter Symbol IEEE Symbol 300 ns Min. ns Max. ns Read Cycle Time tc (R) TAVAV 300 Address Access Time ta (A) TAVQV 300 Card Enable Access Time ta (CE) TELQV 300 Output Enable Access Time ta (OE) TGLQV 150 Output Disable Time from CE tdis (CE) TEHQZ 100 Output Disable Time from OE tdis (OE) TGHQZ 100 Address Setup Time tsu (A) tAVWL 30 Output Enable Time from CE ten (CE) tELQNZ 5 Output Enable Time from OE ten (OE) tGLQNZ 5 Data Valid from Address Change tv (A) tAXQX 0 NOTE: All times are in nanosecond. Dout signifies data provided by the PC Card to the system. The -CE signal or both the -OE signal & the -WE signal must be de-asserted between consecutive cycle operation. 3-1 INTERFACE BUS TIMING KS32P6632-LC/TX SOLID DISK CONTROLLER tc (R) An ta (A) -REG tsu (A) tv (A) ta (CE) -CE ten (CE) tdis (CE) ta (OE) -OE ten (OE) Dout Figure 3-1. Attribute Memory Read Timing Diagram 3-2 tdis (OE) KS32P6632-LC/TX SOLID DISK CONTROLLER INTERFACE BUS TIMING ATTRIBUTE MEMORY WRITE TIMING SPECIFICATION The attribute memory write time is defined as 250 ns. Detailed timing specifications are shown in Table 3-2. NOTE A host cannot write to CIS. This timing is specified only for the write to Configuration Register. Table 3-2. Attribute Memory Write Timing Parameter Symbol IEEE Symbol 250 ns Min. ns Write Cycle Time tc (W) tAVAV 250 Write Pulse Width tw (WE) tWLWH 150 Address Setup Time tsu (A) tAVWL 30 Write Recovery Time trec (WE) tWMAX 30 Data Setup Time for WE tsu (D-WEH) tDVWH 80 Data Hold Time th (D) tWMDX 30 Max. ns NOTE: All times are in nanosecond. Din signifies data provided by the system to the PC Card. tc (W) -REG An tsu (A) trec (WE) tw (WE) -WE tsu (D-WEH) th (D) -CE -OE Dout Data In Valid Figure 3-2. Attribute Memory Write Timing Diagram 3-3 INTERFACE BUS TIMING KS32P6632-LC/TX SOLID DISK CONTROLLER COMMON MEMORY READ TIMING SPECIFICATION Table 3-3. Common Memory Read Timing Parameter Symbol IEEE Symbol Min. ns Max. ns Output Enable Access Time ta (OE) tGLQV 125 Output Disable Time from OE tdis (OE) tGHQZ 100 Address Setup Time tsu (A) tAVGL 30 Address Hold Time th (A) tGHAX 20 CE Setup before OE tsu (CE) tELGL 0 CE Hold following OE th (CE) tGHEH 20 Wait Delay Falling from OE tv (WT-OE) tGLWTV 35 Data Setup for Wait Release tv (WT) tQVWTH 0 Wait Width Time tw (WT) tWTLWTH 350 NOTE: The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Dout signifies data provided by the PC Card to the system. The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. An tsu (A) th (A) -REG -CE th (CE) tsu (CE) tdis (CE) ta (OE) -OE tw (WT) -WAIT tdis (OE) tv (WT-OE) tv (WT) Dout Figure 3-3. Common Memory Read Timing Diagram 3-4 KS32P6632-LC/TX SOLID DISK CONTROLLER INTERFACE BUS TIMING COMMON MEMORY WRITE TIMING SPECIFICATION Table 3-4. Common Memory Write Timing Parameter Symbol IEEE Symbol Min ns. Data Setup before WE tsu (D-WEH) tDVWH 80 Data Hold following WE th (D) tlWMDX 30 WE Pulse Width tw (WE) tWLWH 150 Address Setup Time tsu (A) tAVWL 30 CE Setup before WE tsu (CE) tELWL 0 Write recovery Time trec (WE) tWMAX 30 Address Hold Time th (A) tGHAX 20 CE Hold following WE th (CE) tGHEH 20 Wait Delay Falling from WE tv (WT-WE) tWLWTV WE High from Wait Release tv (WT) tWTHWH Wait Width Time tw (WT) tWTLWTH Max ns. 35 0 350 NOTE: The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Din signifies data provided by the system to the PC Card. The -WAIT signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. An tsu (A) th (A) -REG th (CE) tsu (CE) -CE trec (WE) tw (WE) -WE tw (WT) -WAIT tv (WT-WE) Din tv (WT) tsu (D-WEH) th (D) Din Valid Figure 3-4. Common Memory Write Timing Diagram 3-5 INTERFACE BUS TIMING KS32P6632-LC/TX SOLID DISK CONTROLLER I/O INPUT (READ) TIMING SPECIFICATION Table 3-5. I/O Read Timing Parameter Symbol IEEE Symbol Min ns. Max ns. Data Delay after IORD td (IORD) tlGLQV 100 Data Hold following IORD th (IORD) tlGHQX 0 IORD Width Time tw (IORD) tlGLIGH 165 Address Setup before IORD tsuA (IORD) tAVIGL 70 Address Hold following IORD thA (IORD) tlGHAX 20 CE Setup before IORD tsuCE (IORD) tELIGL 5 CE Hold following IORD thCE (IORD) tlGHEH 20 REG Setup before IORD tsuREG (IORD) tRGLIGL 5 REG Hold following IORD thREG (IORD) tlGHRGH 0 INPACK Delay Falling from IORD tdfINPACK (IORD) tlGLIAL 0 INPACK Delay Rising from IORD tdrINPACK (IORD) tlGHIAH 45 IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35 Wait Delay Falling from IORD tdWT (IORD) tlGLWTL 35 Data Delay from Wait Rising td (WT) tWTHQV 0 Wait Width Time tw (WT) tWTLWTH 45 350 NOTE: The maximum load on -WAIT, -INPACK and -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IORD high is 0nsec, but minimum -IORD width must still be met. Dout signifies data provided by the PC Card to the system. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. 3-6 KS32P6632-LC/TX SOLID DISK CONTROLLER INTERFACE BUS TIMING An tsu (IORD) thA (IORD) -REG tsuREG (IORD) thRE (IORD) -CE tsuCE (IORD) thCE (IORD) twIORD -IORD -INPACK tdrINPACK (IORD) tdfIOIS16 (ADR) tdfINPACK (IORD) tdrIOIS16 (ADR) td (IORD) -IOIS16 -WAIT td (WT) tdWT (IORD) tw (WT) th (IORD) Dout Figure 3-5. I/O Read Timing Diagram 3-7 INTERFACE BUS TIMING KS32P6632-LC/TX SOLID DISK CONTROLLER I/O OUTPUT (WRITE) TIMING SPECIFICATION Table 3-6. I/O Write Timing Parameter Symbol IEEE Symbol Min. ns Max. ns Data Setup before IOWR tsu (IOWR) tDVIWH 60 Data Hold following IOWR th (IOWR) tlWHDX 30 IOWR Width Time tw (IOWR) tlWLIWH 165 Address Setup before IOWR tsuA (IOWR) tAVIWL 70 Address Hold following IOWR thA (IOWR) tlWHAX 20 CE Setup before IOWR tsuCE (IOWR) tELIWL 5 CE Hold following IOWR thCE (IOWR) tlWHEH 20 REG Setup before IOWR tsuREG (IOWR) tRGLIWL 5 REG Hold following IOWR thREG (IOWR) tlWHRGH 0 IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35 Wait Delay Falling from IOWR tdWT (IOWR) tlWLWTL 35 IOWR high from Wait high tdrIOWR (WT) tWTJIWH Wait Width Time tw (WT) tWTLWTH 0 350 NOTE: The maximum load on -WAIT, -INPACK, and -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met. Din signifies data provided by the system to the PC Card. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. 3-8 KS32P6632-LC/TX SOLID DISK CONTROLLER INTERFACE BUS TIMING An tsu (IOWR) thA (IOWR) -REG tsuREG (IOWR) thRE (IOWR) -CE tsuCE (IOWR) thCE (IOWR) twIORD -IOWR tdfIOIS16 (ADR) tdrIOIS16 (ADR) s tsu (IOWR) -IOIS16 tw (WT) -WAIT tdWT (IOWR) tdrIOWR (WT) th (IOWR) Din Figure 3-6. I/O Write Timing Diagram 3-9 INTERFACE BUS TIMING KS32P6632-LC/TX SOLID DISK CONTROLLER IDE MODE I/O INPUT(READ) TIMING SPECIFICATION Table 3-7. IDE Mode I/O Read Timing Parameter Symbol IEEE Symbol Min. ns Max. ns Data Delay after IORD td (IORD) tlGLQV 100 Data Hold following IORD th (IORD) tlGHQX 0 IORD Width Time tw (IORD) tlGLIGH 165 Address Setup before IORD tsuA (IORD) tAVIGL 70 Address Hold following IORD thA (IORD) tlGHAX 20 CE Setup before IORD tsuCE (IORD) tELIGL 5 CE Hold following IORD thCE (IORD) tlGHEH 20 IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35 NOTE: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT high to -IORD high is 0nsec, but minimum -IORD width must still be met. Dout signifies data provided by the PC Card to the system. An tsu (IORD) -CE thA (IORD) tsuCE (IORD) thCE (IORD) twIORD -IORD td (IORD) tdrIOIS16 (ADR) -IOIS16 tdfIOIS16 (ADR) th (IORD) Dout Figure 3-7. IDE Mode I/O Read Timing Diagram 3-10 KS32P6632-LC/TX SOLID DISK CONTROLLER INTERFACE BUS TIMING IDE MODE I/O OUTPUT (WRITE) TIMING SPECIFICATION Table 3-8. IDE Mode I/O Write Timing Parameter Symbol IEEE Symbol Min. ns Max. ns Data Setup before IOWR tsu(IOWR) tDVIWH 60 Data Hold following IOWR th(IOWR) tlWHDX 30 IOWR Width Time twI(OWR) tlWLIWH 165 Address Setup before IOWR tsuA(IOWR) tAVIWL 70 Address Hold following IOWR thA(IOWR) tlWHAX 20 CE Setup before IOWR tsuCE(IOWR) tELIWL 5 CE Hold following IOWR thCE(IOWR) tlWHEH 20 IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35 NOTE: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met. Din signifies data provided by the system to the PC Card. An tsu (IOWR) -CE thA (IOWR) tsuCE (IOWR) thCE (IOWR) twIOWR -IOWR tdrIOIS16 (ADR) -IOIS16 tdfIOIS16 (ADR) tsu (IOWR) th (IOWR) Din Figure 3-8. I/O Write Timing Diagram 3-11 INTERFACE BUS TIMING KS32P6632-LC/TX SOLID DISK CONTROLLER NOTES 3-12 KS32P6632-LC/TX SOLID DISK CONTROLLER 4 CARD CONFIGURATION CARD CONFIGURATION The PC Cards are identified by appropriate information in the Card Information Structure (CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, these registers provide a method for accessing status information about the PC Card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate use in I/O cards. Table 4-1. Registers and Memory Space Decoding -CE2 -CE1 -REG -OE -WE A10 A9 A8-A4 A3 A2 A1 A0 SELECTED SPACE 1 1 x x x x x xx x x x x Standby x 0 0 0 1 x 1 xx x x x 0 Configuration Registers Read 1 0 1 0 1 x x xx x x x x Common Memory Read(8bit D7-D0) 0 1 1 0 1 x x xx x x x x Common Memory Read(8bit D15-D8) 0 0 1 0 1 x x xx x x x 0 Common Memory Read(16bit D15-D0) x 0 0 1 0 x 1 xx x x x 0 Configuration Registers Write 1 0 1 1 0 x x xx x x x x Common Memory Write(8bit D7-D0) 0 1 1 1 0 x x xx x x x x Common Memory Write(8bit D15-D8) 0 0 1 1 0 x x xx x x x 0 Common Memory Write(16bit D15-D0) x 0 0 0 1 0 0 xx x x x 0 Card Information Structure Read 1 0 0 1 0 0 0 xx x x x 0 Invalid Access (CIS Write) 1 0 0 0 1 x x xx x x x 1 Invalid Access (Odd Attribute Read) 1 0 0 1 0 x x xx x x x 1 Invalid Access (Odd Attribute Write) 0 1 0 0 1 x x xx x x x x Invalid Access (Odd Attribute Read) 0 1 0 1 0 x x xx x x x x Invalid Access (Odd Attribute Write) 4-1 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Table 4-2. Configuration Registers Decoding -CE2 -CE1 -REG -OE -WE A10 A9 A8-A4 A3 A2 A1 A0 SELECTED SPACE x 0 0 0 1 0 1 00 0 0 0 0 Configuration Option Reg Read x 0 0 1 0 0 1 00 0 0 0 0 Configuration Option Reg Write x 0 0 0 1 0 1 00 0 0 1 0 Card Status Register Read x 0 0 1 0 0 1 00 0 0 1 0 Card Status Register Write x 0 0 0 1 0 1 00 0 1 0 0 Pin Replacement Register Read x 0 0 1 0 0 1 00 0 1 0 0 Pin Replacement Register Write x 0 0 0 1 0 1 00 0 1 1 0 Socket and Copy Register Read x 0 0 1 0 0 1 00 0 1 1 0 Socket and Copy Register Write NOTE: The location of the card configuration registers should always be read from the cis since these locations may vary in future products. No writes should be performed to the PC card attribute memory except to the card configuration register addresses. All other attribute memory locations are reserved. 4-2 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION ATTRIBUTE MEMORY FUNCTION Attribute memory is a space where PC Card identification and configuration information are stored, and is limited to 8-bit wide accesses only at even addresses. The card configuration registers are also located here. For the attribute memory read function, signals -REG and -OE must be active and -WE inactive during the cycle. As in the main memory read functions, the signals -CE1 and -CE2 control the even-byte and odd-byte address, but only the even-byte data is valid during the attribute memory access. Refer to table 4-3 below for signal states and bus validity for the attribute memory function. Table 4-3. Attribute Memory Function Function Mode -REG -CE2 -CE1 A9 A0 -OE -WE D15-D8 D7-D0 Standby Mode x H H x x x x High Z High Z Read Byte Access CIS (8 bits) L H L L L L H High Z Even Byte Write Byte Access CIS (8 bits) (invalid) L H L L L H L Don't Care Even Byte Read Byte Access Configuration (8 bits) L H L H L L H High Z Even Byte Write Byte Access Configuration (8 bits) L H L H L H L Don't Care Even Byte Read Word Access CIS (16 bits) L L L L x L H Not Valid Even Byte Write Word Access CIS (16 bits) (invalid) L L L L x H L Don't Care Even Byte Read Word Access Configuration (16 bits) L L L H x L H Not Valid Even Byte Write Word Access Configuration (16 bits) L L L H x H L Don't Care Even Byte NOTE: The -CE signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations. 4-3 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER CONFIGURATION OPTION REGISTER ADDRESS 200H IN ATTRIBUTE MEMORY The Configuration Option Register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the PC Card. Operation D7 D6 D5 D4 D3 D2 D1 D0 R/W SRESET LevIREQ Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 SRESET Soft Reset - Setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the PC Card in the reset state. Setting this bit to one (1) is equivalent to assertion of the +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the PC Card in the same un-configured, Reset state as following power-up and hardware reset. This bit is set to zero (0) by power-up and hardware reset. Using the PCMCIA Soft Reset is considered a hardware reset by the ATA commands. Contrast with software reset in the Device Control Register. LevIREQ This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when pulse mode is selected. Set to zero (0) by reset. Conf5-Conf0 Configuration Index. Set to zero (0) by reset. It's used to select operation mode of the PC Card as shown below. NOTE: Conf5 and Conf4 are reserved and must be written as zero (0) Table 4-4. Card Configurations Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 0 0 0 0 0 0 Memory Mapped 0 0 0 0 0 1 I/O Mapped, Any 16byte system decoded boundary 0 0 0 0 1 0 I/O Mapped, 1F0-1F7/3F6-3F7 0 0 0 0 1 1 I/O Mapped, 170-177/376-377 4-4 Disk Card Mode KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION CARD CONFIGURATION AND STATUS REGISTER ADDRESS 202H IN ATTRIBUTE MEMORY The Card Configuration and Status Register contains information about the Card's condition. Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Changed SigChg IOis8 0 0 PwrDwn Int 0 Write 0 SigChg IOis8 0 0 PwrDwn 0 0 Changed Indicates that one or both of the Pin Replacement register CRdy, or CWProt bits are set to one (1). When the Changed bit is set, -STSCHG Pin 46 is held low if the SigChg bit is a One (1) and the PC Card is configured for the I/O interface. SigChg This bit is set and reset by the host to enable and disable a state-change signal from the Status Register, the Changed bit control pin 46 the Changed Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46 (-STSCHG) signal will be held high while the PC Card is configured for I/O. IOis8 The host sets this bit to a one (1) if the PC Card is to be configured in an 8 bit I/O Mode. The PC Card is always configured for both 8- and 16-bit I/O, so this bit is ignored. PwrDwn This bit indicates whether the host requests the PC Card to be in the power saving or active mode. When the bit is one (1), the PC Card enters a power down mode. When zero (0), the host is requesting the PC Card to enter the active mode. The PCMCIA Rdy/-Bsy value becomes BUSY when this bit is changed. Rdy/-Bsy will not become Ready until the power state requested has been entered. The PC Card automatically powers down when it is idle and powers back up when it receives a command. Int This bit represents the internal state of the interrupt request. This value is available whether or not I/O interface has been configured. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero (0). 4-5 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER PIN REPLACEMENT REGISTER ADDRESS 204H IN ATTRIBUTE MEMORY Operation D7 D6 D5 D4 D3 D2 D1 D0 Read 0 0 CRdy/-Bsy CWProt 0 0 Rdy/-Bsy WProt Write 0 0 CRdy/-Bsy CWProt 0 0 MRdy/-Bsy MWProt CRdy/-Bsy This bit is set to one (1) when the bit RRdy/-Bsy changes state. This bit can also be written by the host. CWProt This bit is set to one (1) when the RWprot changes state. This bit may also be written by the host. Rdy/-Bsy This bit is used to determine the internal state of the Rdy/-Bsy signal. This bit may be used to determine the state of the Ready/-Busy as this pin has been reallocated for use as Interrupt Request on an I/O card. When written, this bit acts as a mask for writing the corresponding bit CRdy/-Bsy. WProt This bit is always zero (0) since the PC Card does not have a Write Protect switch. When written, this bit acts as a mask for writing the corresponding bit CWProt. MRdy/-Bsy This bit acts as a mask for writing the corresponding bit CRdy/-Bsy. MWProt This bit when written acts as a mask for writing the corresponding bit CWProt. Table 4-5. Pin Replacement Changed Bit/Mask Bit Values Initial Value Written by Host Final Command of (C) Status "C" Bit "M" Bit "C" Bit 0 x 0 0 Unchanged 1 x 0 1 Unchanged x 0 1 0 Cleared by Host x 1 1 1 Set by Host 4-6 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION SOCKET AND COPY REGISTER ADDRESS 206H IN ATTRIBUTE MEMORY This register contains additional configuration information. This register is always written by the system before writing the card's Configuration Index Register. Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Reserved 0 0 Drive# 0 0 0 0 Write 0 0 0 Drive# x x x x Reserved This bit is reserved for future standardization. This bit must be set to zero (0) by the software when the register is written. Drive # This bit indicates the drive number of the card for twin card configuration. The socket number is ignored by the PC Card. 4-7 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER I/O TRANSFER FUNCTION I/O FUNCTION The I/O transfer to or from the PC Card can be either 8 or 16 bits. When a 16-bit accessible port is addressed, the signal -IOIS16 is asserted by the PC Card. Otherwise, the -IOIS16 signal is de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the PC Card, the system must generate a pair of 8-bit references to access the word's even byte and odd byte. The PC Card permits both 8 and 16 bit accesses to all of its I/O addresses, so -IOIS16 is asserted for all addresses to which the PC Card responds. The PC Card may request the host to extend the length of an input cycle until data is ready by asserting the -WAIT signal at the start of the cycle. Table 4-6. I/O Function Function Mode -REG -CE2 -CE1 A0 -IORD -IOWR D15-D8 D7-D0 Standby Mode x H H x x x High Z High Z Byte Input Access (8 bits) L H L L L H High Z Even Byte L H L H L H High Z Odd Byte L H L L H L Don't Care Even Byte L H L H H L Don't Card Odd Byte Word Input Access (16 bits) L L L L L H Odd Byte Even Byte Word Output Access (16 bits) L L L L H L Odd Byte Even Byte I/O Read Inhibit H x x x L H Don't Care Don't Care I/O Write Inhibit H x x x H L High Z High Z High Byte Inout Only (8 bits) L L H x L H Odd Byte High Z High Byte Output Only (8 bits) L L H x H L Odd Byte Don't Care Byte Output Access (8 bits) 4-8 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION COMMON MEMORY TRANSFER FUNCTION COMMON MEMORY FUNCTION The common memory transfer to or from the PC Card can be either 8 or 16 bits. The PC Card permits both 8 and 16 bit accesses to all of its common memory addresses. The PC Card may request the host to extend the length of a memory write cycle or extend the length of a memory read cycle until data is ready by asserting the -WAIT signal at the start of the cycle. Table 4-7. Common Memory Function Function Mode -REG -CE2 -CE1 A0 -OE -WE Standby Mode x H H x x x High Z High Z Byte Read Access (8 bits) H H L L L H High Z Even Byte H H L H L H High Z Odd Byte H H L L H L Don't Care Even Byte H H L H H L Don't Care Odd Byte Word Read Access (16 bits) H L L x L H Odd Byte Even Byte Word Write Access (16 bits) H L L x H L Odd Byte Even Byte Odd Byte Read Only (8 bits) H L H x L H Odd Byte High Z Odd Byte Write Only (8 bits) H L H x H L Odd Byte Don't Care Byte Write Access (8 bits) D15-D8 D7-D0 4-9 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER IDE MODE I/O TRANSFER FUNCTION IDE I/O FUNCTION The PC Card can be configured in a True IDE Mode of operation. The PC Card is configured in this mode only when the -OE input signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. In this mode no Memory or Attribute Registers are accessible to the host. NOTE Removing and reinserting the PC Card while the host computer's power is on will reconfigure the PC Card to PC Card ATA mode from the original True IDE Mode. To configure the PC Card in True IDE Mode, the 50-pin socket must be power cycled with the PC Card inserted and -OE (output enable) asserted. The following table defines the function of the operations for the True IDE Mode. Table 4-8. IDE Mode I/O Function Function Mode -CE2 -CE1 A2-A0 -IORD -IOWR Invalid Mode L L x x x High Z High Z Standby Mode H H x x x High Z High Z Task File Write H L 1-7h H L Don't Care Data In Task File Read H L 1-7h L H High Z Data Out Data Register Write H L 0 H L Odd Byte in Even Byte in Data Register Read H L 0 L H Odd Byte out Even Byte out Control Register Write L H 6h H L Don't Care Control In All Status Read L H 6h L H High Z Status Out 4-10 D15-D8 D7-D0 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION ATA DRIVE REGISTER SET DEFINITION AND PROTOCOL The PC Card can be configured as a high performance I/O device through: a. Standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary); 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). b. Any system decoded 16 byte I/O block using any available IRQ. c. Memory space. The communication to or from the PC Card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four register mapping methods. The following is a detailed description of these methods: Table 4-9. I/O Configurations Standard Configurations Config Index I/O or Memory Address Drive # Description 0&8 Memory 0-Fh, 400-7FFh 0 Memory Mapped 1&9 I/O xx0-xxFh 0 I/O Mapped 16 Contiguous Registers 2 & Ah I/O 1F0-1F7h, 3F6-3F7h 0 Primary I/O Mapped Drive 0 2 &Ah I/O 1F0-1F7h, 3F6-3F7h 1 Primary I/O Mapped Drive 1 3 & Bh I/O 170-177h, 376-377h 0 Secondary I/O Mapped Drive 0 3 & Bh I/O 170-177h, 376-377h 1 Secondary I/O Mapped Drive 1 NOTE: Refer to Twin Card implementation. 4-11 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER I/O PRIMARY AND SECONDARY ADDRESS CONFIGURATIONS Table 4-10. Primary and Secondary I/O Decoding -REG A9-A4 A3 A2 A1 A0 -IORD=0 -IOWR=0 0 1F(17)h 0 0 0 0 1F(17)h 0 0 0 1F(17)h 0 0 1F(17)h 0 Notes 0 Even RD Data Even WR Data 1,2 0 1 Error Register Features 1 0 1 0 Sector Count Sector Count 0 0 1 1 Sector No. Sector No. 1F(17)h 0 1 0 0 Cylinder Low Cylinder Low 0 1F(17)h 0 1 0 1 Cylinder High Cylinder High 0 1F(17)h 0 1 1 0 Select Card/Head Select Card/Head 0 1F(17)h 0 1 1 1 Status Command 0 3F(37)h 0 1 1 0 Alt Status Drive Control 0 3F(37)h 0 1 1 1 Drive Address Reserved NOTES: 1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don't Care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers which lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. 2. A byte accesses to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 3. Address lines which are not indicated are ignored by the PC Card for accessing all the registers in this table. 4-12 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION CONFIGURATIONS I/O MAPPED ADDRESSING When the system decodes a contiguous block of I/O registers to select the PC Card, the registers are accessed in the block of I/O space decoded by the system as follows: Table 4-11. Contiguous I/O Decoding -REG A3 A2 A1 A0 Offset -IORD=0 -IOWR=0 Notes 0 0 0 0 0 0 Even RD Data Even WR Data 1 0 0 0 0 1 1 Error Features 2 0 0 0 1 0 2 Sector Count Sector Count 0 0 0 1 1 3 Sector No. Sector No. 0 0 1 0 0 4 Cylinder Low Cylinder Low 0 0 1 0 1 5 Cylinder High Cylinder High 0 0 1 1 0 6 Select Card/Head Select Card/Head 0 0 1 1 1 7 Status Command 0 1 0 0 0 8 Dup. Even RD Data Dup. Even WR Data 2 0 1 0 0 1 9 Dup. Odd RD Data Dup. Odd WR Data 2 0 1 1 0 1 Dh Dup. Error Dup. Feature 2 0 1 1 1 0 Eh Alt Status Device Ctl 0 1 1 1 1 Fh Drive Address Reserved NOTES: 1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don't Care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Address lines which are not indicated are ignored by the PC Card for accessing all the registers in this table. 4-13 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER MEMORY MAPPED ADDRESSING When the PC Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows: Table 4-12. Memory Mapped Decoding -REG A10 A9-A4 A3 A2 A1 A0 Offset -IORD=0 -IOWR=0 1 0 x 0 0 0 0 1 0 x 0 0 0 1 0 x 0 0 1 0 x 0 1 0 x 1 0 1 Notes 0 Even RD Data Even WR Data 1 1 1 Error Features 2 1 0 2 Sector Count Sector Count 0 1 1 3 Sector No. Sector No. 0 1 0 0 4 Cylinder Low Cylinder Low x 0 1 0 1 5 Cylinder High Cylinder High 0 x 0 1 1 0 6 Select Card/Head Select Card/Head 1 0 x 0 1 1 1 7 Status Command 1 0 x 1 0 0 0 8 Dup. Even RD Data Dup. Even WR Data 2 1 0 x 1 0 0 1 9 Dup. Odd RD Data Dup. Odd WR Data 2 1 0 x 1 1 0 1 Dh Dup. Error Dup. Feature 2 1 0 x 1 1 1 0 Eh Alt Status Device Ctl 1 0 x 1 1 1 1 Fh Drive Address Reserved 1 1 x x x x 0 8 Even RD Data Even WR Data 3 1 1 x x x x 1 9 Odd RD Data Odd WR Data 3 NOTES: 1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1Kbyte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the PC Card. A word access to address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus. 4-14 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION TRUE IDE MODE ADDRESSING When the PC Card is configured in the True IDE Mode, the I/O decoding is as follows: Table 4-13. True IDE Mode I/O Decoding -CE2 -CE1 A2 A1 A0 -IORD=0 -IOWR=0 1 0 0 0 0 Even RD Data Even WR Data 1 0 0 0 1 Error Features 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector No. Sector No. 1 0 1 0 0 Cylinder Low Cylinder Low 1 0 1 0 1 Cylinder High Cylinder High 1 0 1 1 0 Select Card/Head Select Card/Head 1 0 1 1 1 Status Command 0 1 1 1 0 Alt Status Device Control 0 1 1 1 1 Drive Address Reserved Notes 4-15 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER ATA REGISTERS The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the "task file." NOTE In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset address may be accessed at its normal address and also the corresponding even address (normal address -1) using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16is high (not asserted) and an I/O cycle is being performed. DATA REGISTER (ADDRESS -1F0[170]; OFFSET 0,8,9): The Data Register is a 16bit register, and it used to transfer data blocks between the PC Card data buffer and the Host. This register overlaps the Error Register. The table below describes the combinations of data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte access modes and operations. See the PCMCIA PC Card Standard Release 3.0 for definitions of the Card Accessing Modes for I/O and Memory cycles. NOTE Because of the overlapped register, access to the 1f1h, 171h or offset 1 are not defined for word (-CE2 = 0 and -CE1 = 0) operations. These accesses are treated as accesses to the Word Data Register. The duplicated registers at offsets 8,9 and Dh have no restrictions on the operations that can be performed by the socket. Data Register -CE2 -CE1 A0 Offset Data Bus Word Data Register 0 0 x 0,8,9 D15-D0 Even Data Register 1 0 0 0,8 D7-D0 Odd Data Register 1 0 1 9 D7-D0 Odd Data Register 0 1 x 8,9 D15-D8 Error / Feature Register 1 0 1 1,Dh D7-D0 Error / Feature Register 0 1 x 1 D15-D8 Error / Feature Register 0 0 x Dh D15-D8 4-16 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION ERROR REGISTER (ADDRESS -1F1[171]; OFFSET 1, DH READ ONLY) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: D7 D6 D5 D4 D3 D2 D1 D0 BBK UNC 0 IDNF 0 ABRT 0 AMNF This register is also accessed on data bits D15 -D8 during a write operation to offset 0 with -CE2 low and -CE1 high. Bit 7 (BBK) This bit is set when a Bad Block is detected. This bit is set when Error on drive 1 (True IDE). Bit 6 (UNC) This bit is set when an Uncorrectable Read Error is encountered. Bit 5 This bit is 0. Bit 4 (IDNF) The requested sector ID is in error or cannot be found. This bit is 0. Bit 3 This bit is 0. Bit 2 (Abort) Abort=1 This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition (Write Fault, Invalid Parameter, etc) or when an invalid command has been issued. Bit 1 This bit is 0. Bit 0 (AMNF) This bit is set in case of a general error. (DMA transfer Error) 4-17 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER FEATURE REGISTER (ADDRESS -1F1[171]; OFFSET 1, DH WRITE ONLY): This register provides information regarding features of the PC Card that the host can utilize. This register is also accessed on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high. SECTOR COUNT REGISTER (ADDRESS -1F2[172]; OFFSET 2): This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the PC Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request SECTOR NUMBER (LBA 7-0) REGISTER (ADDRESS -1F3[173]; OFFSET 3): This register contains starting sector number or bits 7-0 of the Logical Block Address (LBA) for any PC Card data access for the subsequent command. CYLINDER LOW (LBA 15-8) REGISTER (ADDRESS -1F4[174]; OFFSET 4): This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address. CYLINDER HIGH (LBA 23-16) REGISTER (ADDRESS -1F5[175]; OFFSET 5): This register contains the high order 8 bits of the starting cylinder address or bits 23-16 of the Logical Block Address. 4-18 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION DRIVE/HEAD (LBA 27-24) REGISTER (ADDRESS -1F6[176]; OFFSET 6): The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defines as follows: D7 D6 D5 D4 D3 D2 D1 D0 1 LBA 1 DRV HS3 HS2 HS1 HS0 Bit 7 This bit is set to 1. Bit 6 (LBA) LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA = 1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: A7-LBA0: Sector Number Register D7-D0. LBA15-LBA8: Cylinder Low Register D7-D0. LBA23-LBA16: Cylinder High Register D7-D0. LBA27-LBA24: Drive/Head Register HS3-HS0. Bit 5 his bit is set to 1. Bit 4 (DRV) DRV is the drive number. When DRV 0, drive (card) 0 is selected. When DRV = 1,drive (card) 1 is selected. The PC Card is set to be Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register. Bit 3 (HS3) When operating in the Cylinder, Head, Sector mode, this is bit3 of the head number. It is Bit 27 in the Logical Block Address mode. Bit 2 (HS2) When operating in the Cylinder, Head, Sector mode, this is bit2 of the head number. It is Bit 26 in the Logical Block Address mode. Bit 1 (HS1) When operating in the Cylinder, Head, Sector mode, this is bit1 of the head number. It is Bit 25 in the Logical Block Address mode. Bit 0 (HS0) When operating in the Cylinder, Head, Sector mode, this is bit0 of the head number. It is Bit 24 in the Logical Block Address mode. 4-19 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER STATUS & ALTERNATE STATUS REGISTER (ADDRESS -1F7[177]&3F6[376]; OFFSET 7, EH): These registers return the PC Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits is described as follows: D7 D6 D5 D4 D3 D2 D1 D0 BUSY RDY DWF DSC DRQ CORR 0 ERR Bit 7 (BUSY) The busy bit is set when the PC Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. Bit 6 (RDY) RDY indicates whether the device is capable of performing PC Card operations. This bit is cleared at power up and remains cleared until the PC Card is ready to accept a command. Bit 5 (DWF) This bit, if set, indicates a write fault has occurred. Bit 4 (DSC) This bit is set when the PC Card is ready. This bit is cleared at power up. Bit 3 (DRQ) The Data Request is set when the PC Card required and that information be transferred either to or from the host through the Data register. Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. Bit 1 This bit is always set to 0. Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. 4-20 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION DEVICE CONTROL REGISTER (ADDRESS -3F6[376]; OFFSET EH): This register is used to control the PC Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows: D7 D6 D5 D4 D3 D2 D1 D0 x x x x 1 SW Rst -IEn 0 Bit 7 This bit is an X (don't care). Bit 6 This bit is an X (don't care). Bit 5 This bit is an X (don't care). Bit 4 This bit is an X (don't care). Bit 3 This bit is ignored by the PC Card. Bit 2 (SW Rst) This bit set to 1 in order to force the PC Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers (4.3.2-to 4.3.5) as hardware Reset does. The Card remains in Reset until this bit is reset to "0". Bit 1 The Interrupt Enable bit enables interrupts when the bit is 0 (-IEn=0), interrupts from the PC Card are disable. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 1 at power on and Reset. Bit 0 This bit ignored by the PC Card. 4-21 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER CARD (DRIVE) ADDRESS REGISTER (ADDRESS -3F7[377]; OFFSET FH): This register is provided for compatibility with the AT disk drive interface. It is recommended that this register nit be mapped into the host's I/O space because of potential conflicts on Bit 7. The bits are defined as follow: D7 D6 D5 D4 D3 D2 D1 D0 x -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0 Bit 7 This bit is unknown. NOTES: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the PC Card. Following are some possible solutions to this problem for the PCMCIA implementation: 1. Locate the PC Card at a non -conflicting address, i.e. Secondary address (377h) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2. Do not install a Floppy and a PC Card in the system at the same time. 3. Implement a socket adapter which can be programmed to (conditionally) tri-state D7 of I/O address 3F7h/377h when a PC Card is installed and conversely to tri-state D6-D0 of I/O address 3F7h/377h when a floppy controller is installed. 4. Do not use the PC Card's Drive Address register. This may be accomplished by either If possible, program the host adapter to enable only I/O address 1F0h-1F7h, 3F6h (or 170-177h, 176h) to the PC Card or If provided use an additional Primary/Secondary configuration in the PC Card which does not respond to accesses to I/O location 3F7h and 377h with either of these implementation, the host software must not attempt to use information in the Drive Address Register. Bit 6 (-WTG) This bit is 0 when a write operation is in progress, otherwise, it is 1. Bit 5 (-HS3) This bit is the negation of bit 3 in the Drive/Head register. Bit 4 (-HS2) This bit is the negation of bit 2 in the Drive/Head register. Bit 3 (-HS1) This bit is the negation of bit 1 in the Drive/Head register. Bit 2 (-HS0) This bit is the negation of bit 0 in the Drive/Head register. Bit 1 (-nDS1) This bit is 0 when drive 1 is active and selected. Bit 0 (-nDS0) This bit is 0 when the drive 0 is active and selected. 4-22 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION ATA COMMAND DESCRIPTION This section defines the software requirements and the format of the commands the host sends to the CompactFlash Storage Cards or PC Cards are issued to the CompactFlash Storage Card or PC Card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. The manner in which a command is accepted varies. There are three classes (see Table 4-15) of command acceptance, all dependent on the host not issuing commands unless the CompactFlash Storage Card or PC Card is not busy (BSY=0). All commands listed in this specification shall be implemented. Commands can be implemented as "no operation" to meet this requirement. 1. Upon receipt of a Class 1 command, the CompactFlash Storage Card or PC Card sets BSY within 400nsec. 2. Upon receipt of a Class 2 command, the CompactFlash Storage Card or PC Card sets BSY within 400nsec, sets up the sector buffer for a write operation, sets DRQ within 700 msec, and clears BSY within 400 nsec of setting DRQ. 3. Upon receipt of a Class 3 command, the CompactFlash Storage Card or PC Card sets BSY within 400nsec, sets up the sector buffer for a write operation, sets DRQ within 20 msec (assuming nore-assignments), and clears BSY within 400 nsec of setting DRQ. 4-23 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER ATA COMMAND SET Table 4-15 summarizes the ATA command set with the paragraphs that follow describing the individual commands and the task file for each. Table 4-15. ATA Command Set Class 4-24 Command Code FR SC SN CY DH LBA 1 Check Power Mode E5h or 98h - - - - D - 1 Execute Drive Diagnostic 90h - - - - D - 1 Erase Sector(s) C0h - Y Y Y Y Y 2 Format Track 50h - Y - Y Y Y 1 Identify Drive ECh - - - - D - 1 Idle E3h or 97h - Y - - D - 1 Idle Immediate E1h or 95h - - - - D - 1 Initialize Drive Parameters 91h - Y - - Y - 1 Read Buffer E4h - - - - D - 1 Read Long Sector 22h or 23h - - Y Y Y Y 1 Read Multiple C4h - Y Y Y Y Y 1 Read Sector(s) 21h or 21h - Y Y Y Y Y 1 Read Verify Sector(s) 40h or 41h - Y Y Y Y Y 1 Recalibrate 1Xh - - - - D - 1 Request Sense 03h - - - - D - 1 Seek 7Xh - - Y Y Y Y 1 Set Features EFh Y - - - D - KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Table 4-15. ATA Command Set (Continued) Class Command Code FR SC SN CY DH LBA 1 Set Multiple Mode C6h - Y - - - - 1 Set Sleep Mode E6h or 99h - - - - D - 1 Stand By E2h or 96h - - - - D - 1 Stand By Immediate E0h or 94h - - - - D - 1 Translate Sector 87h - Y Y Y Y Y 1 Wear Level F5h - - - - Y - 2 Write Buffer E8h - - - - D - 2 Write Long Sector 32h or 33h - - Y Y Y Y 3 Write Multiple C5h - Y Y Y Y Y 3 Write Multiple w/o Erase CDh - Y Y Y Y Y 2 Write Sector(s) 30h or 31h - Y Y Y Y Y 2 Write Sector(s) w/o Erase 38h - Y Y Y Y Y 3 Write Verify 3Ch - Y Y Y Y Y Definitions: FR = Features Register, SC = Sector Count Register, SN = Sector Number Register, CY = Cylinder Registers, DH = Card/Drive/Head Register, LBA = Logical Block Address Mode Supported (see command descriptions for use). Y - The register contains a valid parameter for this command. For the Drive/Head Register Y means both the CompactFlash Storage Card or PC Card and head parameters are used; D - only the CompactFlash Storage Card or PC Card parameter is valid and not the head parameter. 4-25 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Check Power Mode - 98h or E5h Bit-> 7 6 5 4 Command (7) 3 2 1 0 98H or E5H C/D/H (6) x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command checks the power mode. If the CompactFlash Storage Card or PC Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage Card or PC Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt. If the CompactFlash Storage Card or PC Card is in Idle mode, the CompactFlash Storage Card or PC Card sets BSY, sets the Sector Count Register to FFh, clears BSY and generates an interrupt. Execute Drive Diagnostic - 90h Bit-> 7 6 5 4 2 1 0 90H Command (7) C/D/H (6) 3 x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command performs the internal diagnostic tests implemented by the CompactFlash Storage Card or PC Card. If in PCMCIA configuration this command runs only on the CompactFlash Storage Card or PC Card which is addressed by the Drive/Head register when the diagnostic command is issued. This is because PCMCIA card interface does not allows for direct inter-drive communication (such as the ATA PDIAG and DASP signals). If in True IDE Mode the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with status for both devices. The Diagnostic codes shown in Table 4-16 are returned in the Error Register at the end of the command. 4-26 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Table 4-16. Diagnostic Codes Code Error Type 01h No Error Detect 02h Formatter Device Error 03h Sector Buffer Error 04h ECC Circuitry Error 05h Controlling Microprocessor Error 8Xh Slave Error in True IDE Mode Erase Sector(s) - C0h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 LBA 1 Drive Head (LBA27-24) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Feature (1) 0 C0H Cylinder High (5) Sec Count (2) 1 Sector Counter x This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write Multiple without Erase command. There is no data transfer associated with this command but a Write Fault error status can occur. 4-27 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Format Track - 50h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 50H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) x (LBA 7-0) Sec Count (2) Count (LBA Mode Only) Feature (1) x This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFh or 00h). To remain host backward compatible, the CompactFlash Storage Card or PC Card expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the CompactFlash Storage Card or PC Card. If LBA=1 then the number of sectors to format is taken from the Sec Cnt register (0=256). The use of this command is not recommended. Identify Drive - ECh Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 ECH x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x The Identify Drive command enables the host to receive parameter information from the CompactFlash Storage Card or PC Card. This command has the same protocol as the Read Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table 4-17. All reserved bits or words are zero. Table 4-17 is the definition for each field in the Identify Drive Information. 4-28 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Table 4-17. Identify Drive Information Word Address Default Value Total Bytes Data Field Type Information 0 848Ah 2 General configuration bit-significant information 1 XXXXh 2 Default number of cylinders 2 0000h 2 Reserved 3 00XXh 2 Default number of heads 4 XXXXh 2 Number of unformatted bytes per track 5 XXXXh 2 Number of unformatted bytes per track 6 XXXXh 2 Default number of sectors per track 7-8 XXXXh 4 Number of sectors per card (Word7=MSW, Word8=LSW) 9 XXXXh 2 Vendor Unique 10-19 aaaa 20 Serial number in ASCII (Right Justified) 20 XXXXh 2 Buffer Type 21 XXXXh 2 Buffer size in 512 byte increments 22 0004h 2 # of ECC bytes passed in Read/Write Long Command 23-26 aaaa 8 Firmware revision in ASCII. Big Endian Byte Order in Word 27-46 aaaa 40 Model number in ASCII (Left justified) Big Endian Order in Word 47 XXXXh 2 Maximum number of sectors in read/write multiple command 48 0000h 2 Double word not supported 49 XX00h 2 capabilities 50 0000h 2 Reserved 51 0X00h 2 PIO data transfer cycle timing mode 52 0000h 2 DMA data transfer cycle timing mode 53 0001h 2 Translation parameters are valid 54 XXXXh 2 Current numbers of cylinders 55 XXXXh 2 Current numbers of heads 56 XXXXh 2 Current numbers per track 57-58 XXXXh 4 Current capacity in sectors (LBAs) (Word 57=LSW, Word 58= MSW) 59 010Xh 2 Multiple sector setting 60-61 XXXXh 4 Total number of sectors addressable in LBA Mode 62-127 0000h 138 Reserved 128-159 0000h 64 Vendor unique bytes 160-255 0000h 192 Reserved 4-29 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Idle - 97h or E3h Bit-> 7 6 5 Command (7) 4 3 2 1 0 97H or 23H C/D/H (6) x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) Timer Counter (5 msec increments) Feature (1) x This command causes the CompactFlash Storage Card or PC Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. Note that this time base (5msec) is different from the ATA specification. Idle Immediate - 97h or E1h Bit-> 7 6 Command (7) C/D/H (6) 5 4 3 2 1 0 97H or E1 x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command causes the CompactFlash Storage Card or PC Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. 4-30 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Initialize Drive Parameters - 91h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 91H x 0 x Drive Max Head (No. of heads-1) Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) Number of Sectors Feature (1) x This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by this command. Read Buffer - E4h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 E4H x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card or PC Card sector buffer. This command has the same protocol as the Read Sector(s) command. 4-31 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Read Multiple - C4h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Feature (1) 0 C4H Cylinder High (5) Sec Count (2) 1 Sector Counter x The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = (sector count) - modulo (block count). If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. 4-32 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Read Long Sector - 22h or 23h Bit-> 7 6 5 Command (7) C/D/H (6) 4 3 2 1 0 22H or 23H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Sec Count (2) x Feature (1) x The Read Long command performs similarly to the Read Sector(s) command except that it returns 516 bytes of data instead of 512 bytes. During a Read Long command, the CompactFlash Storage Card or PC Card does not check the ECC bytes to determine if there has been a data error. Only single sector read long operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 4 bytes of ECC data transferred in byte mode. This command has the same protocol as the Read Sector(s) command. Use of this command is not recommended. Read Sector(s) - 20h or 21h Bit-> 7 6 5 Command (7) C/D/H (6) 4 3 2 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Feature (1) 0 20H or 21H Cylinder High (5) Sec Count (2) 1 Sector Counter x This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and after each sector of data (except the last one) has been read by the host, the CompactFlash Storage Card or PC Card sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 bytes of data from the buffer. At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. 4-33 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Read Verify Sector(s) - 40h or 41h Bit-> 7 6 5 Command (7) C/D/H (6) 4 3 2 1 0 40H or 41H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Sec Count (2) Sector Counter Feature (1) x This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the CompactFlash Storage Card or PC Card sets BSY. When the requested sectors have been verified, the CompactFlash Storage Card or PC Card clears BSY and generates an interrupt. Upon command completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified. Recalibrate - 1Xh Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 1xH 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command is effectively a NOP command to the CompactFlash Storage Card or PC Card and is provided for compatibility purposes. 4-34 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Request Sense - 03h Bit-> 7 6 4 5 3 Command (7) C/D/H (6) 2 1 0 03H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command requests extended error information for the previous command. Table 4-18 defines the valid extended error codes for the CompactFlash Storage Card or PC Card Series product. The extended error code is returned to the host in the Error Register. Table 4-18. Extended Error Codes Extended Error Code Description 00h No error detected 01h Self test OK (No error) 09h Miscellaneous error 20h Invalid command 21h Invalid address (Request head or sector invalid) 2Fh Address overflow 35h, 36h Supply or generated voltage out of tolerance 11h Uncorrectable ECC error 18h Corrected ECC error 05h, 30-34h, 37h, 3Eh Self test or diagnostic failed 10h, 14h ID not found 3Ah Spare sectors exhausted 1Fh Data transfer error/abort command 0Ch, 38h, 3Bh, 3Ch, 3Fh Corrupted media format 03h Write/Erase failed 4-35 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Seek - 7Xh Bit-> 7 6 5 4 3 Command (7) C/D/H (6) 2 1 0 7XH 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) x (LBA 7-0) Sec Count (2) x Feature (1) x This command is effectively a NOP command to the CompactFlash Storage Card or PC Card although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. Set Features - EFh Bit-> 7 6 5 4 3 Command (7) C/D/H (6) 4-36 2 1 EFH x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) Config Feature (1) Feature 0 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Table 4-19. Features Supported Feature Operation 01h Enable 8-bit data transfer. 55h Disable read look ahead. 66h Disable power on reset(POR) establishment of defaults at soft reset. 69h NOP-Accepted for backward compatibility. 81h Disable 8-bit data transfer. 96h NOP-Accepted for backward compatibility. 97h Accepted for backward compatibility. Use of this features is not recommended. 9Ah Set the host current source capability. Allows tradeoff between current drawn and read/write speed BBh 4 bytes of data apply on read/write long command. CCh Enable power on reset(POR) establishment of default at soft reset Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the This command is used by the host to establish or select certain features. Table 5-10 defines all features that are supported. 01h feature command is issued all data transfers will occur on the low order D7-D0 data bus and the IOIS16 signal will not be asserted for data register accesses. Features 55h and BBh are the default features for the CompactFlash Storage Card or PC Card; thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons. Feature code 9Ah enables the host to configure the card to best meet the host system power requirements. The host sets a value in the Sector Count register that is equal to one-fourth of the desired maximum average current (in mA) that the card should consume. For example, if the Sector Count register is set to 6, the card would be configured to provide the best possible performance without exceeding 24 mA. Upon completion of the command, the card responds to the host with the range of values supported by the card. The minimum value is set in the Cylinder Low register, and the maximum value is set in the Cylinder Hi register. The default value, after a power on reset, is to operate at the highest performance and therefore the highest current mode. The card will accept values outside this programmable range, but will operate either at the lowest power or highest performance as appropriate. Features 66h and CCh can be used to enable and disable whether the Power On Reset (POR) Defaults will be set when a soft reset occurs. The default setting is to revert to the POR defaults when a soft reset occurs. 4-37 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Set Multiple Mode - C6h Bit-> 7 6 5 4 Command (7) 3 2 1 0 C6H C/D/H (6) x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) Sector Count Feature (1) x This command enables the CompactFlash Storage Card or PC Card to perform Read and Write Multiple operations and establishes the block count for these commands. The Sector Count Register is loaded with the number of sectors per block. Upon receipt of the command, the CompactFlash Storage Card or PC Card sets BSY to 1 and checks the Sector Count Register. If the Sector Count Register contains a valid value and the block count is supported, the value is loaded for all subsequent Read Multiple and Write Multiple commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and Read Multiple and Write Multiple commands are disabled. If the Sector Count Register contains 0 when the command is issued, Read and Write Multiple commands are disabled. At power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write Multiple disabled. Set Sleep Mode- 99h or E6h Bit-> 7 6 Command (7) C/D/H (6) 5 4 3 2 1 0 99H or E6 x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command causes the CompactFlash Storage Card or PC Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 5 milliseconds. Note that this time base (5 msec) is different from the ATA Specification. 4-38 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Standby - 96h or E2h Bit-> 7 6 5 Command (7) 4 3 2 1 0 96H or E2H C/D/H (6) x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command causes the CompactFlash Storage Card or PC Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). Standby Immediate - 94h or E0h Bit-> 7 6 Command (7) C/D/H (6) 5 4 3 2 1 0 94H or E0H x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x This command causes the CompactFlash Storage Card or PC Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). 4-39 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Translate Sector - 87h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 87H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Sec Count (2) x Feature (1) x This command allows the host a method of determining the exact number of times a user sector has been erased and programmed. The controller responds with a 512 byte buffer of information containing the desired cylinder, head and sector, including its Logical Address, and the Hot Count, if available, for that sector. Table 4-20 represents the information in the buffer. Please note that this command is unique to the CompactFlash Storage Card or PC Card. Table 4-20. Translate Sector Information Address Information 00h-01h Cylinder MSB(00), Cylinder LSB(01) 02h Head 03h Sector 04h-06h LBA MSB(04) - LSB(06) 07h-12h Reserved 13h Erase flag(FFh) = Erased; 00h = not Erased 14h-17h Reserved 18h-1Ah Hot count MSB(18) - LSB(1A) 1Bh-1FFh Reserved NOTE: A value of 0 indicates Hot Count is not supported. 4-40 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Wear Level - F5h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 F5H x x x Drive Flag Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) Completion Status Feature (1) x This command is effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with an 00h indicating Wear Level is not needed. Write Buffer - E8h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 E8H x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) x Feature (1) x The Write Buffer command enables the host to overwrite contents of the CompactFlash Storage Card or PC Card's sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 bytes. 4-41 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Write Long Sector - 32h or 33h Bit-> 7 6 5 Command (7) C/D/H (6) 4 3 2 1 0 32H or 33H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number Sec Count (2) x Feature (1) x This command is similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. Only single sector Write Long operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 4 bytes of ECC transferred in byte mode. Because of the unique nature of the solid-state CompactFlash Storage Card, the four bytes of ECC transferred by the host may be used by the CompactFlash Storage Card or PC Card. The CompactFlash Storage Card or PC Card may discard these four bytes and write the sector with valid ECC data. This command has the same protocol as the Write Sector(s) command. Use of this command is not recommended. 4-42 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Write Multiple Command - C5h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 1 0 C5H x LBA x Drive Head Cylinder High (5) Cylinder High Cylinder Low (4) Cylinder Low Sec Number (3) Sector Number Sec Count (2) Sector Counter Feature (1) 2 x NOTE: The current revision of the CompactFlash Storage Card or PC Card only supports a block count of 1 as indicated in the Identify Drive Command information. This command is provided for compatibility with future products which may support a larger block count. This command is similar to the Write Sectors command. The CompactFlash Storage Card or PC Card sets BSY within 400 nsec of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = sector count (modulo sector/block). If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write Multiple commands are disabled, the Write Multiple operation will be rejected with an aborted command error. Errors encountered during Write Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count Register contains the residual number of sectors that need to be transferred for successful completion of the command e.g. each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count Register contains 6 and the address is that of the third sector. 4-43 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Write Multiple without Erase - CDh Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 CDH x LBA x Drive Head Cylinder High (5) Cylinder High Cylinder Low (4) Cylinder Low Sec Number (3) Sector Number Sec Count (2) Sector Counter Feature (1) x This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. Write Sector(s) - 30h or 31h Bit-> 7 6 5 Command (7) C/D/H (6) 4 3 2 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Feature (1) 0 30H or 31H Cylinder High (5) Sec Count (2) 1 Sector Counter x This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the CompactFlash Storage Card or PC Card sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. 4-44 KS32P6632-LC/TX SOLID DISK CONTROLLER CARD CONFIGURATION Write Sector(s) without Erase - 38h Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 38H 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (5) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Sec Count (2) Sector Counter Feature (1) x This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. This command has the same protocol as the Write Sector(s) command. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. If the sector is not preerased with the Erase Sector(s) command, a normal write sector operation will occur. Write Verify - 3Ch Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 LBA 1 Drive Head (LBA 27-24) Cylinder High (LBA 23-16) Cylinder Low (4) Cylinder Low (LBA 15-8) Sec Number (3) Sector Number (LBA 7-0) Feature (1) 0 3CH Cylinder High (5) Sec Count (2) 1 Sector Counter x This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write Sector(s) command. 4-45 CARD CONFIGURATION KS32P6632-LC/TX SOLID DISK CONTROLLER Vender Unique ATA Command KS32P6632-LX/TC support the nine vender unique commands together with standard ATA commands. Table 4-21 summarizes vender unique command set. Table 4-21. Vendor unique command Command Name Description Physical Read Read from physical page on flash memory Physical Write Write data to physical page on flash memory Physical Block Erase Erase physical block on flash memory Set SG Control Table Set SG control table for initializing flash memory Flash Initialize Executing flash memory initializing Change Information CIS/DID Changing data of CIS/DID Get Flash Information Getting flash memory information. (Structure of block number and page number) Get Firmware Revision Getting firmware revision Get Flash ID Information Getting flash information of maker ID and device ID 4-46 KS32P6632-LC/TX SOLID DISK CONTROLLER 5 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, KS32P6632 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- Recommended operating conditions -- Thermal characteristics 5-1 ELECTRICAL DATA KS32P6632-LC/TX SOLID DISK CONTROLLER Table 5-1. Absolute Maximum Ratings Symbol Parameter VDD Supply voltage VIN Input voltage I IN DC input current TSTG Storage temperature Ratings Unit - 0.3 to + 7.0 V - 0.3 to VDD + 0.3 V - 10 mA - 40 to + 125 C Table 5-2. Recommended Operating Conditions Symbol VDD Parameter DC supply voltage Ta Ratings Unit 5V 4.75 to + 5.25 V 3.3 V 3.0 to 3.6 V - 40 to + 85 C Value Unit 57 C /W Storage temperature Table 5-3. Thermal Characteristics Symbol ja 5-2 Parameter Thermal impedance - junction to ambient plastic 144-pin LQFP KS32P6632-LC/TX SOLID DISK CONTROLLER ELECTRICAL DATA Table 5-4. D.C. Electrical Characteristics (TA = 0 to 70 C, VDD = 3.3 V 0.3 V) Symbol Parameter Conditions VIH High level input voltage CMOS VIL Low level input voltage CMOS VT Switching threshold CMOS VT+ Switching trigger, positivegoing threshold CMOS VT- Switching trigger, negativegoing threshold CMOS IIH High level input current Input buffer Low level input current Input buffer VOL High level output voltage Low level output voltage Max 1.4 1.0 VIN = VSS Type 4 (1) IOH = -4 mA Type 4 (2) IOH = -8 mA Type 4 (3) IOH = -16 mA Type 4 (1) IOH = 4 mA Type 4 (2) IOH = 8 mA Type 4 (3) IOH = 16 mA 10 30 -10 -160 V V -10 10 V V 2.0 VIN = VDD Unit V 1.0 Input buffer with pull-up VOH Typ 2.0 Input buffer with pull-up IIL Min 60 10 -30 uA uA -10 2.4 V 0.4 V 10 uA 40 mA IOZ Tri-state output leakage current VOUT = VSS or VDD IDD Maximum operating current VDD = 5.0 V, f MCLK = 20 MHz Iidle Idle current 20 mA Ids Stop current 30 uA -10 30 NOTES: 1. 4 mA drive output PAD. 2. 8 mA drive output PAD. 3. 16 mA drive output PAD. 5-3 ELECTRICAL DATA KS32P6632-LC/TX SOLID DISK CONTROLLER Table 5-4. D.C. Electrical Characteristics (TA = 0 to 70 C, VDD = 5 V 5 %) Symbol VIH VIL VT VT+ VT- IIH Parameter High level input voltage Low level input voltage Switching threshold Switching trigger, positivegoing threshold Switching trigger, negativegoing threshold High level input current Conditions CMOS 3.5 TTL 2.0 Low level input current VOL High level output voltage Low level output voltage V TTL 0.8 CMOS 2.5 TTL 1.4 4.0 TTL 2.0 CMOS 1.0 TTL 0.8 VIN = VDD Input buffer -10 10 VIN = VSS -10 -100 Type 4 (1) IOH = -4 mA Type 4 (2) IOH = -8 mA Type 4 (3) IOH = -16 mA Type 4 (1) IOH = 4 mA Type 4 (2) IOH = 8 mA Type 4 (3) IOH = 16 mA uA 100 10 -50 V V 10 50 V V CMOS Input buffer Unit uA -10 2.4 V 0.4 V 10 uA 70 mA IOZ Tri-state output leakage current VOUT = VSS or VDD IDD Maximum operating current VDD = 5.0 V, f MCLK = 20 MHz Iidle Idle current 35 mA Ids Stop current 60 uA NOTES: 1. 4 mA drive output PAD. 2. 8 mA drive output PAD. 3. 16 mA drive output PAD. 5-4 Max 1.5 Input buffer with pull-up VOH Typ CMOS Input buffer with pull-up IIL Min -10 60 KS32P6632-LC/TX SOLID DISK CONTROLLER 7 APPLICATION NOTE APPLICATION NOTE FLASH MEMORY CONNECTION FRDY0 FCLE0 FALE0 FWE0 FRE0 FCE0 FCE1 Flash 0 Flash 1 Flash 2 Flash 9 FCE2 ... FCE9 FDB[7:0] Figure 7-1. Case of Using the KS32P6632-TX (100-pin) 7-1 APPLICATION NOTE KS32P6632-LC/TX SOLID DISK CONTROLLER Flash 10 Flash 11 Flash 12 FRDY1 FRDY0 FCLE1 FCLE0 FALE1 FALE0 FWE1 FWE0 FRE1 FRE0 Flash 0 Flash 2 FDB[15:8] FDB[7:0] Flash 9 Flash 19 FCE0 SW0 FCE1 FCE2 ... FCE9 Figure 7-2. Case of Using the KS32P6632-LC (20ea Connection) 7-2 Flash 1 KS32P6632-LC/TX SOLID DISK CONTROLLER Fce3 Fce2 Fce1 Fce0 Controller APPLICATION NOTE Decoder (138) Decoder (138) 0 0 Flash 19 Flash 7 19 Flash 19 Flash Flash 19 Flash 7 19 Flash 19 Flash Buffer (245) FD[7:0] FBDIR (FCE4) FRE0 FRE0x (FCE5) FWE0 FWE0x (FCE6) R/B0 ALE0 CLE0 sw0 0 0 Flash 19 Flash 7 1919 Flash Flash FD[15:8] Flash 19 Flash 7 1919 Flash Flash Buffer (245) FRE1 FRE1x (FCE7) FWE0 FWE1x (FCE8) R/B1 ALE1 CLE1 Figure 7-3. Case of Using the KS32P6632-LC (32ea Connection) 7-3 APPLICATION NOTE KS32P6632-LC/TX SOLID DISK CONTROLLER EXTERNAL ROM AND RAM CONNECTION RCE RWE ROE ROM_CS Ncs1 Controller RE WE Ncs1 RE cs2 EXT RAM A16-0 D7-0 EXT ROM A16-0 RAB0-16 RD0-7 sw1 Figure 7-4. External ROM and RAM Connection 7-4 WE D7-0 KS32P6632-LC/TX SOLID DISK CONTROLLER APPLICATION NOTE CF SCHEMATIC 7-5 APPLICATION NOTE PC CARD SCHEMATIC 7-6 KS32P6632-LC/TX SOLID DISK CONTROLLER KS32P6632-LC/TX SOLID DISK CONTROLLER 6 MECHANICAL DATA MECHANICAL DATA OVERVIEW The KS32P6632-LC/TX disk controller is available in a 100-pin TQFP package (Samsung part number 100TQFP-1414) and a 144-LQFP package (Samsung part number 144-LQFP-2020). 16.00 BSC 0-7 14.00 BSC 14.00 BSC + 0.073 - 0.037 0.08 MAX 100-TQFP-1414 0.45-0.75 16.00 BSC 0.127 #100 #1 + 0.07 0.20 - 0.03 0.50 0.05-0.15 (1.00) 1.00 0.05 1.20 MAX NOTE: Dimensions are in millimeters. Figure 6-1. 100-TQFP-1414 Package Dimensions 6-1 ELECTRICAL DATA KS32P6632-LC/TX SOLID DISK CONTROLLER 22.00 BSC 0-7 20.00 BSC 20.00 BSC 0.08 MAX 144-LQFP-2020 0.60 0.15 22.00 BSC 0.09-0.20 #144 #1 0.17-0.27 0.50 BSC 0.05-0.15 (1.25) 1.40 0.05 1.60 MAX NOTE: Dimensions are in millimeters. Figure 6-2. 144-LQFP-2020 Package Dimensions 6-2 KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND 1. VENDOR UNIQUE COMMAND Bit-> 7 6 5 4 3 Command (7) 2 1 0 EFH C/D/H (6) x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) Config Feature (1) Feature A Vendor unique command is setting F0h as Feature REGISTER of a SET FEATURE COMMAND, and is executed. Moreover, each Vendor unique command is processed with the setting value of Config. Set Features Command(EFh) ConfigFeature Value = F0h Config Value Command Name Description C0 Physical Read Read from physical page on flash memory. C1 Physical Write Write data to physical page on flash memory. C2 Physical Block Erase Erase physical block on flash memory. C3 Set SG Control Table Set SG Control Table for initializing Flash Memory C4 Flash initialize Executing Flash Memory initializing. C5 Change Information CIS/IDI Changing Data of CIS/IDI. C6 Get Flash Information Getting flash Memory information. (Structure of Block number and Page number.) C7 Get Firmware Revision Getting Firmware Revision. C8 Get Flash ID Information Getting flash information of Maker ID and Device ID. 1 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER 1.1 PHYSICAL READ SECTOR Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 EFH x Drive x Cylinder High (5) Page No High Cylinder Low (4) Page No Low Sec Number (3) Chip No (0-31) Sec Count(2) C0h Feature (1) F0h Features code F0h enables the host to configure the card to test card function. The host sets a value C0h in the Sector Count register that is permission physical sector access. The Physical Read Sector command performs similarly to the Read Sector(s) command except that it returns 528 bytes from physical sector (flash page). During a Physical Read Sector command, the PC Card does not check the ECC bytes to determine if there has been a data error. Only single sector Read long operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 16 bytes of spare data transferred in byte mode. This command has the same protocol as the Read Sector(s) command. Use of this command is Developer's test. -- Input parameter Cylinder High Low = The page address within a memory chip. (0- ) Sector Number = Memory chip number. (0-31) -- The output parameter at the time of a normal end Status Register = 50h -- The output parameter at the time of an unusual end. An address is too large. Status Register = 51h Error Register = 10h (ID Not Found) 2 KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND 1.2 PHYSICAL WRITE SECTOR Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 EFH x Drive x Cylinder High (5) Page No High Cylinder Low (4) Page No Low Sec Number (3) Chip No (0-31) Sec Count(2) Ch Feature (1) F0h The Physical Write Sector command performs similarly to the Write Sector(s) command except that it writes 528 bytes of data instead of 512 bytes. During a Physical Write Sector command, the PC Card does not check the ECC bytes to determine if there has been a data error. Only single page Write operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 16 bytes of spare data transferred in byte mode. This command has the same protocol as the write Sector(s) command. Use of this command is Developer's test. -- Input parameter Cylinder High Low = The page address within a memory chip. (0- ) Sector Number = Memory chip number. (0-31) -- The output parameter at the time of a normal end Status Register = 50h -- The output parameter at the time of an unusual end. An address is too large. Status Register = 51h Error Register = 10h (ID Not Found) -- Write fault. Status Register = 71h (Write fault) Error Register = 80h (Bad Block Detected) 3 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER 1.3 PHYSICAL ERASE BLOCK Bit-> 7 6 5 4 Command (7) 3 2 1 0 EFH C/D/H (6) x Drive x Cylinder High (5) Block No High Cylinder Low (4) Block No Low Sec Number (3) Chip No (0-31,FFh) Sec Count (2) Ch Feature (1) F0h CF which a command was taken in does elimination toward physical Block of the specified chip Number. It is the erase of only one block. A Sec Number of FFh requests all block Erase. Block No is Block Address in a tip simple substance. 1.4 SET SG (SECTOR GROUP) CONTROL TABLE Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 EFH x Drive x Cylinder High (5) The number of link blocks Cylinder Low (4) The number of spared part blocks Sec Number (3) The number of updated part blocks Sec Count (2) C3h Feature (1) F0h A garbage collection is performed. This Command must be executed before Initialize Flash Memory Command. 4 KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND 1.5 INITIALIZE FLASH MEMORY Bit-> 7 6 5 4 Command (7) 3 2 1 0 EFH C/D/H (6) x Drive x Cylinder High (5) x Cylinder Low (4) Number of mounted Flash Memory Sec Number (3) Erase Flash Switch Sec Count(2) C4h Feature (1) F0h This command checks all flash memory, and after then, write information of control. The blank check of all the mounting flash memories is done, and Write/Read/Compare/Erase is done, and writing a control table are made (initialization to do after mounting). Sec Number: When This Value is FFh, Erase block of all the mounting flash memories. NOTE: Before this Command execution, all blocks must be erased. After this Command execution, it must execute the Write CIS/IDI Command (Change Card Information). Error return value (Sec Number) Error Value Description 00h Normalcy End: it is Sec Number =00h. 01h All flash chip is not recognized by ID read command. 02h Block 0 or Block 1 erase check error. 03h Block 0 or Block 1 write/read check error. 04h CIS/IDI Write page error 05h Link info writes error or SG ctbl (The table of control information) build up error. 5 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER 1.6 CHANGE CARD INFORMATION Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 EFH x Drive x Cylinder High (5) Interleave Mode Cylinder Low (4) FAT Analysis Mode Sec Number (3) x Sec Count (2) C5h Feature (1) F0h This command change card information. As for doing action, writing of CIS/IDI and Flash Information to page of the fixation, others is the same protocol as Write Sector Command the elimination of the fixed block. But Flash information currently written in is inherited, without updating. Format of writes data (format) Byte Description 0-255 CIS(Vendor Unique) 256-511 Drive Identify Information(Vendor Unique) Special specification (note) Specification Set Register Function Interleave Cylinder High 2F:Enable, 1Fh:Disable FAT Analysis Cylinder Low FA:Enable, F0h:Disable Data of Special specification are written on Flash memory (1Byte). That location is Page No.1 of Block No.0. Data after 2 byte is invalid. Default is Disable (FFh). NOTE: This specification is not supported now. 6 KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND 1.7 GET FLASH CHIP INFORMATION Bit-> 7 6 5 4 Command (7) 3 2 1 0 EFH C/D/H (6) x Drive Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) C6h Feature (1) F0h This command checks connecting flash chip information. The PC Card sets Sector Number Register to Page number per block, Cylinder Low Register to Block number LSB, Cylinder High Register to Block number MSB. 1.8 GET FIRMWARE INFORMATION Bit-> 7 6 5 4 Command (7) C/D/H (6) 3 2 1 0 EFH x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) C7h Feature (1) F0h This command checks the Firmware Revision. The PC Card sets Sector Number Register to firmware version. Firmware Revision A.B Return parameter: Sector Number = Firmware Revision Byte (A). Cylinder Low = Firmware Revision Byte (B). 7 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER 1.9 GET FLASH ID INFORMATION Bit-> 7 6 Command (7) C/D/H (6) 5 4 3 2 1 0 EFH x Drive x Cylinder High (5) x Cylinder Low (4) x Sec Number (3) x Sec Count (2) C8h Feature (1) F0h This command checks connecting flash chip information. The PC Card sets Sector Number Register to mounting chip number, Cylinder Low Register to maker ID, Cylinder High Register to device ID. 8 KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND 2. CARD INFORMATION STRUCTURE (DEFAULT) CIS Description (BASIC) Attribute Offset Data 000h 01h 002h 03 004h D9 7 6 5 4 3 2 1 0 CISTPL_DEVICE Device Type Code Dh =I/O W Speed 1 1h Description of Contents CIS Function Device Info Tuple Tuple Code Link is 3bytes Link to next tuple I/O device, No Write Protects, Device Speed=250ns Device ID WPS, Speed 006h 01 Device Size 2Kbyte of address Space Device size 008h FF List End Marker End of Devices End Maker 00Ah 18 CISTPL_JEDEC_C JEDEC ID Common Mem Tuple Code 00Ch 02 Link is 2 bytes Link to next tuple 00Eh DF PCMCIA Manufacture's ID 010h 01 PCMCIA Code for PC Card-ATA No Vpp Required 012h 20 CISTPL_MANFID 014h 04 016h 07 018h C0 01Ah 01 01Ch 01 01Eh 21 020h 02 022h 04 IC Card Function Code 024h 01 R0 026h 22 CISTPL_FUNCE 028h 02 02Ah 01 02Ch 01 Byte 1,JEDEC ID of Device 1 Second Byte of JEDEC ID Byte 2,JEDEC ID Tiple Code Link is 4bytes PC Card manufacturer's Code Link Length TPLMID_MANF TPLMID_MANF Manufacturer information TPLMID_CARD TPLMID_CARD CISTPL_FUNCID R0 R0 R0 R0 R0 R0 P1 Function ID Tuple Tuple Code Link is 2bytes Link to next tuple Fixed DISK Function TPLFID_FUNCTION Attempt installation at Post P: Install at POST R: Reserved Function Extension Tuple Tuple Code Link is 2bytes Link to next tuple Disk Function Extension Tuple Type Disk Device interface TPLFE_TYPE Interface Type Code PC Card-ATA interface TPLFE_DATA 9 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER CIS Description (Cont.) Attribute Offset Data 02Eh 22 030h 03 032h 02 034h 7 6 5 4 3 2 1 0 CISTPL_FUNCE Description of Contents CIS Function Function Extension Tuple Tuple Code Link is 3bytes Link to next tuple Disk Function Extension Tuple Type PCMCIA-ATA Extension tuple Extension Tuple Type for Disk 04 R0 R0 R0 R0 U0 S1 Silicon Drive V:0 No Vpp Required S: Silicon/Rotating U: ID Drive not Mfg/SN Unique R: Reserved TPLFE_DATA 036h 07 R 0 I 0 E 0 N 0 P3 0 P2 1 Sleep, stand by, Idle Mode Supported. P0: Sleep Mode Supported P1: Standby Mode Supported P2: Idle Mode Supported P3: Drive Auto Power Control not supported N: All Primary & secondary I/O addressing E: Index bit Not Emulated I: Twin IOIS16 Data Reg TPLFE_DATA 038h 1A CISTPL_CONF Configuration Tuple Tuple Code 03Ah 05 Link is 5bytes Link to next tuple 03Ch 01 Size of Field RFSZ: Reserved Field TPCC_SZ V 0 P1 1 RFSZ RMSZ RASZ 00 0000 01 P0 1 RMSZ: Reg Mask RASZ: Base Address 03Eh 03 TPCC_LAST Entry Index 03h Last entry of Configuration table 040h 00 TPCC_RADR Configuration Registers are located at 200h Location of Config Registers 042h 02 TPCC_RADR 044h 0F R0 4 Configuration Registers are present I: Configuration Index C: Configuration &Status P: Pin Replacement S: Socket and Copy R: Reserved for future TPCC_RMSK 046h 1B CISTPL_CONF Configuration Entry Tuple Tuple Code 048h 08 Link is 8bytes Link to next tuple 10 R0 R0 R0 S1 P1 C1 I1 KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND CIS Description (Cont.) Attribute Offset Data 7 6 5 04Ah C0 I1 D1 04Ch C0 W 1 R1 04Eh A1 M1 4 2 1 0 Configuration Index 0 P0 MS 01 Interface Type 0 IR 0 IO 0 T0 AI 0 SI 0 HV 0 P 01 TPCE_INDEX Memory Only Interface 0 Bvd & Wprot not used, Ready/Busy & Wait used for Memory Cycle B: Battery Volt Detects P: Write Protect R: Ready/Busy W: Wait used for Memory Cycle TPCE_IF Vcc-power-description structure only P: Power info type T: Timing info present IO: I/O port info present IR: Interrupt info present MS: Mem space info type M: Misc info bytes present TPCE_FS Nominal operating supply voltage. NV: Nominal Voltage LV: Minimum Voltage HV: Maximum Voltage SI: Static Current AI: Average Current PI: Peak Current DI: Power Down Current Power Parameters for Vcc Vcc Nominal is 5 Volts Vcc Nominal Value 052h 55 X0 054h 08 Length in 256 bytes pages(lsb) Length of Mem Space is 2KB TPCE_MS Length LSB 056h 00 Length in 256 bytes pages(msb) Start at 0 on card TPCE_MS Length MSB 058h 20 X0 Power Down T: Twin Cards Allowed A: Audio Supported RO: Read only Mode P:Power-Down Supported R: Reserved X: More Misc Fields Byte TPCE_MI Configuration Entry Tuple Tuple Code Link is 10bytes Link to next tuple 05Ch 0A R0 P1 CISTPL_CONF 5h=1V R0 0 A0 Twin 1 N V 1 Memory Mapped I/O D: default Configuration I: Interface Byte Follows R 0 Ah=5.0 LV 0 CIS Function 01 1B PI 0 B0 Description of Contents 050h 05Ah DI 0 3 11 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER CIS Description (Cont.) Attribute Offset Data 7 6 05Eh C1 I1 D1 Configuration Index 1 I/O Mapped Contiguous 16registers configuration D: default Configuration I: interface Byte Follows 060h 41 W 0 R1 P0 072h 99 M1 074h 01 R0 076h 55 X0 078h 64 R0 S1 E1 07Ah F0 S1 P1 L1 M1 V0 B0 I0 07Ch FF 71 61 51 41 31 21 11 07Eh 080h FF 20 082h 1B 084h 0C 12 F1 X0 5 MS1 DI 0 PI 0 4 3 2 R0 D1 P1 CISTPL_CONF 0 Description of Contents B0 Interface Type 1 I/O interface (1), Bvd & Wprotect not used, Rdy/Bsy active ,Wait not used for memory access IR 0 IO 0 T0 Vcc power-description structure only AI 0 SI 0 HV 0 Ah=5.0 E1 1 P01 LV 0 NV 1 Power Parameters for Vcc Vcc Nominal is 5 Volts Vcc Nominal Value Supports 8/16bit I/O access TPCE_IO N0 IRQ Sharing S: share Logic Active P: Pulse IRQ Supported L: Level IRQ Supported M: Bit Mask of IRQ V: Vender Specific signal B: Bus Error signal I: I/O check signal N: Non Mask able IRQ TPCE_IR 01 IRQ Levels to be routed 07 recommended TPCE_IR IRQ Levels to be routed 815 recommended TPCE_IR Power Down Supported T: Twin Cards Allowed A: Audio Supported RO: Read only Mode P:Power-Down Supported R: Reserved X: More Misc Fields Byte TPCE_MI Configuration Entry Tuple Tuple Code Link is 12bytes Link to next tuple 5h=1V R O0 B1 A0 A1 91 T 0 TPCE_INDEX Nominal operating supply voltage. IO AddeLine 4 C1 CIS Function 81 Mask Extension Mask Extension KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND CIS Description (Cont.) Attribute Offset Data 7 6 5 086h 82 I1 D0 088h 41 W 0 R1 08Ah 18 M0 4 EA P0 B0 MS R1 S1 2 1 0 Configuration Index 2 IR 1 0 08Ch 3 E1 Interface Type 1 IO 1 T0 P 0 IO AddeLines Ah=10 08Eh 61 LS AS 1 2 Number I/O range 1 Description of Contents AT Fixed Disk Primary I/O Address Configuration D: default Configuration I: interface Byte Follows TPCE_INDEX I/O mapped Contiguous 16 registers configuration TPCE_IF Vcc power-description structure only TPCE_FS Supports both 8/16bit I/O accesses. TPCE_IO Number of Range 2 byte; Size of each address2 byte Size of each Length 1 byte AS: Size of address 0: No address present 1: 8-bit Addresses 2: 16-bit Addresses 3: 32-bit Addresses LS: Size of Length 0: No Length Present 1: 8-bit Addresses 2: 16-bit Addresses 3: 32-bit Addresses I/O Range Format Description 090h F0 1st I/O Base Address(lsb) First I/O Range base is 092h 01 1st I/O Base Address(msb) 1F0h 094h 07 1st I/O Range Length-1 8byte total 1F0-1F7h 096h F6 2nd I/O Base Address(lsb) 2nd I/O Range base is 098h 03 2ndI/O Base Address(msb) 3F6h 09Ah 01 2nd I/O Range Length-1 2byte total 3F6-3F7h 09Ch EE S1 09Eh 1B CISTPL_CONF P1 L1 M0 V1 B1 I1 N0 CIS Function IRQ Sharing Logic Active Pulse & Level mode interrupts Supported IREQ 0-15 S: share Logic Active P: Pulse IRQ Supported L: Level IRQ Supported M: Bit Mask of IRQ V: Vender Specific signal B: Bus Error signal I: I/O check signal N: Non Mask able IRQ TPCE_IR Configuration Entry Tuple Tuple Code 13 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER CIS Description (Cont.) Attribute Offset Data 7 6 5 0A0h 0C 0A2h 83 I1 D0 0A4h 41 W 0 R1 0A6h 18 M0 4 EA P0 B0 MS R1 S1 2 1 0 Configuration Index 3 IR 1 0 0A8h 3 E1 Interface Type 1 IO 1 T0 61 AS 1 2 Link to next tuple AT Fixed Disk Secondary I/O Address configuration D: default Configuration I: interface Byte Follows TPCE_INDEX I/O interface(1) Bvd ,wPrrrot: No use Ready Active Wait not used for Memory Cycle TPCE_IF TPCE_FS 0 IO AddeLines LS Num I/O range 1 Supports both 8/16bit I/O accesses. Number of Range 2byte; Size of each address2byte Size of each Length 1byte AS: Size of address 0: No address present 1: 8-bit Addresses 2: 16-bit Addresses 3: 32-bit Addresses LS: Size of Length 0: No Length Present 1: 8-bit Addresses 2: 16-bit Addresses 3: 32-bit Addresses 0ACh 70 1st I/O Base Address(lsb) First I/O Range base is 0AEh 01 1st I/O Base Address(msb) 170h 0B0h 07 1st I/O Range Length-1 8byte total 170-177h 0B2h 76 2nd I/O Base Address(lsb) 2nd I/O Range base is 0B4h 03 2ndI/O Base Address(msb) 376h 0B6h 01 2nd I/O Range Length-1 2byte total 376-377h 14 CIS Function Link is 12bytes P Ah=10 0AAh Description of Contents TPCE_IO KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND CIS Description (Cont.) Attribute Offset Data 7 6 5 4 3 2 1 0 P1 L1 M0 V1 B1 I1 N0 0B8h EE S1 0BAh 15 CISTPL_VER_1 0BCh 1D 0BEh 04 0C0h Description of Contents CIS Function IRQ Sharing Logic Active Pulse & Level mode nterrupts Supported IREQ 0-15 S: share Logic Active P: Pulse IRQ Supported L: Level IRQ Supported M: Bit Mask of IRQ V: Vender Specific signal B: Bus Error signal I: I/O check signal N: Non Mask able IRQ TPCE_IR Level 1 version Tuple Code Link is 29 bytes Link to next tuple TPPLV_MAJOR PCMCIA 2.0/JEIDA 4.1 Major Version 01 TPPLV_MINOR PCMCIA 2.0/JEIDA 4.1 Minor Version 0C2h 53 ASCII Manufac String 0C4h 45 0C6h 49 0C8h 4B 0CAh 4F 0CCh 20 0CEh 45 0D0h 50 0D2h 53 0D4h 4F 0D6h 4E 0D8h 00 End of Manufacture 0DAh 53 ASCII Product Name Str 0DCh 45 0DEh 41 0E0h 54 0E2h 41 0E4h 2D 0E6h 31 0E8h 30 String 1 Null terminator Info String2 15 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER CIS Description (Cont.) Attribute Offset Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function 0EAh 4D 0ECh 00 End of Manufacture 0EEh 31 ASCII Product Name Str 0F0h 2E - 0F2h 30 0 0F4h 00 End of CIS Revision Number Null terminator 0F6h FF End of List Marker FFh List terminator 0F8h 14 CISTPL_NO_LINK 0FAh 00 No Bytes Following Link Length is 0 Bytes Link to Next Tuple 0FCh FF End of CIS Tuple Chain End of CIS Tuple Code 16 Null terminator 1 Info String3 Tuple Code KS32P6632-LQ/TQ SOLID DISK CONTROLLER VENDOR UNIQUE COMMAND 3. EXAMPLE TEST OF PRODUCTION Modules check. Set feature Command code C4 Check Flash Memory. (Initialize Flash Memory) Initialization Table. (Initialize Flash Memory) Managed table creation. (Initialize Flash Memory) Set feature Command code C5 Write CIS/IDIFLASH. (Change Information) Card check. (function) Physical Disk Format ATAINITDOS Set Parameter Logical Disk Format FORMATDOS FAT16,FAT32,NTFS etc. Read/Write check SCANDISKDOS NOTE ATAINIT is a Card Wizard utility that create a DOS partition on the FlashDisk card. ATAINIT program (the System Soft Corp FDISK utility). 4. LOAD OF CIS (CARD INFORMATION STRUCTURE) AND IDI (DRIVE IDENTIFY DATA) -- The foundations of CIS are defined as the firmware of ARM7TDMI. (Definition of only 5V power supply.) -- When effective data as CIS does not have data in head Block of a flash or flash is not mounted, data defined as the firmware is loaded as CIS. -- When there is CIS developed to the flash (after CIS and IDI are written), its data become effective, and CIS is read from a flash. -- IDI is not defined in first stage. -- The write of CIS/IDI and the code of rewriting are put on the first page of first block of a flash, and access to other blocks is not performed (management TBL etc. is not changed). -- CIS/IDI needs to be rewritten with the specification of a card. -- Concept figure (CIS/IDI Load action). 17 VENDOR UNIQUE COMMAND KS32P6632-LQ/TQ SOLID DISK CONTROLLER NOTES 18 PRODUCT OVERVIEW KS32P6632-LC/TX SOLID DISK CONTROLLER SYSTEM CONFIGURATION Flash Memory (32 Mbit, 64 Mbit, 128 Mbit, 256 Mbit) PCMIA-ATA Interface Flash Memory Controller KS32C6632-LC/TX 3.3 V Regulator Figure 1-2. System Configuration Example 1-4