Freescale Semiconductor Data Sheet: Technical Data Document Number: PXR40 Rev. 1, 09/2011 PXR40 PXR40 Microcontroller Data Sheet * Dual issue, 32-bit CPU core complex (e200z7) - Compliant with the Power Architecture embedded category - 16 KB I-Cache and 16 KB D-Cache - Includes an instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction - Includes signal processing extension (SPE2) instruction support for digital signal processing (DSP) and single-precision floating point operations * 4 MB on-chip flash - Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation * 256 KB on-chip general-purpose SRAM including 32 KB of standby RAM * Two direct memory access controller (eDMA2) blocks - One supporting 64 channels - One supporting 32 channels * Interrupt controller (INTC) * Frequency modulated phase-locked loop (FMPLL) * Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters * External bus interface (EBI) for calibration and application development (not available on all packages) * System integration unit (SIU) * Error correction status module (ECSM) * Boot assist module (BAM) supports serial bootload via CAN or SCI * Two second-generation enhanced time processor units (eTPU2) that share code and data RAM. - 32 standard channels per eTPU2 - 24 KB code RAM - 6 KB parameter (data) RAM * Enhanced modular input output system supporting 32 unified channels (eMIOS) with each channel capable of (c) Freescale Semiconductor, Inc., 2011. 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TEPBGA-416 27mm x 27mm * * * * * * * * single action, double action, pulse width modulation (PWM) and modulus counter operation Four enhanced queued analog-to-digital converters (eQADC) - Support for 64 analog channels - Includes one absolute reference ADC channel - Includes eight decimation filters Four deserial serial peripheral interface (SPI) modules Three enhanced serial communication interface (UART) modules Four controller area network (CAN) modules Dual-channel FlexRay controller Nexus development interface (NDI) per IEEE-ISTO 5001-2003/5001-2008 standard Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1) On-chip voltage regulator controller regulates supply voltage down to 1.2 V for core logic Table of Contents 1 2 3 4 5 PXR40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 PXR40 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 416-ball TEPBGA pin assignments. . . . . . . . . . . . . . . . .6 Signal properties and muxing . . . . . . . . . . . . . . . . . . . . . . . . .11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .53 5.2.1 General notes for specifications at maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3 EMI (Electromagnetic Interference) characteristics . . .55 5.4 ESD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5.5 PMC/POR/LVI electrical specifications . . . . . . . . . . . . .56 5.6 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .59 5.6.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.3 Power sequencing and POR dependent on VDDA60 5.7 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .61 5.7.1 I/O pad current specifications . . . . . . . . . . . . . .64 5.7.2 I/O pad VDD33 current specifications . . . . . . . . .64 5.7.3 LVDS pad specifications . . . . . . . . . . . . . . . . . .65 5.8 Oscillator and FMPLL electrical characteristics . . . . . .66 5.9 6 7 8 9 eQADC electrical characteristics . . . . . . . . . . . . . . . . . 5.9.1 ADC internal resource measurements . . . . . . . 5.10 C90 flash memory electrical characteristics . . . . . . . . 5.11 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.2 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 5.12 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.1 Generic timing diagrams . . . . . . . . . . . . . . . . . 5.12.2 Reset and configuration pin timing . . . . . . . . . . 5.12.3 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 5.12.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.5 External Bus Interface (EBI) timing . . . . . . . . . 5.12.6 External interrupt timing (IRQ pin) . . . . . . . . . . 5.12.7 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.8 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.9 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 69 71 73 73 74 77 77 78 78 81 84 88 88 89 90 96 96 97 97 99 99 PXR40 Microcontroller Data Sheet, Rev. 1 2 Freescale Semiconductor PXR40 features 1 PXR40 features Table 1 displays the PXR40 feature set. Table 1. PXR40 feature set Feature Core SIMD VLE Cache Non-maskable interrupt (NMI) MMU MPU XBAR Windowing software watchdog Nexus SRAM Flash Flash fetch accelerator External bus Calibration bus DMA DMA Nexus Serial UART_A UART_B UART_C Microsecond bus uplink CAN CAN_A CAN_B CAN_C CAN_D CAN_E SPI SPI_A SPI_B SPI_C SPI_D FlexRay Ethernet System timers eMIOS eTPU eTPU_A eTPU_B PXR40 e200z7 Yes Yes 32 KB (16 KB Instruction/16 KB Data) NMI & Critical Interrupt 64 entry Yes 5x5 Yes 3+ 256 KB 4 MB 4 x 256 bit (first 1 MB of memory is 4 x 128; last 3 MB are 4 x 256) Yes 16 bit non-muxed 32 bit muxed 96 channel Class 3 3 Yes Yes Yes Yes 4 64 message buffers 64 message buffers 64 message buffers 64 message buffers No 4 Yes Yes Yes Yes Yes No 4 PIT chan 4 SWT 1 Watchdog 32 channel 64 channel Yes (eTPU2) Yes (eTPU2) PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 3 PXR40 features Table 1. PXR40 feature set (continued) Feature Code memory Data memory Interrupt controller ADC eQADC_A eQADC_B Temperature sensor Variable gain amp. Decimation filter Sensor diagnostics PLL VRC Supplies Low Power Modes PXR40 24 KB 6 KB 448 64 channel Yes Yes Yes Yes Yes (8 on eQADC_B) Yes FM Yes 5V Stop Mode Slow Mode Note: 3.3 V is required for certain IO segments only during debug/development (e.g., Nexus 3 trace and bus) PXR40 Microcontroller Data Sheet, Rev. 1 4 Freescale Semiconductor PXR40 block diagram 2 PXR40 block diagram Figure 1 shows a top-level block diagram of the PXR40 microcontrollers. PXR40 Block Diagram System Integration Data and Instruction System Debug SPE2 JTAG 2 x eDMA 64- and 32-ch Osc/PLL Interrupt Controller e200z7 Superscalar CPU FlexRayTM Controller Nexus IEEE ISTO 5001TM-2003 Crossbar Switch (XBAR) Memory Protection Unit (MPU) PBRIDGE A 256 KB SRAM w/ECC (32 KB S/B) 4 MB Flash w/ECC PBRIDGE B Main Memory System SIU Communications Timed I/O System eMIOS 32-ch Boot Assist Module (BAM) eTPU2 32-ch 6K Data 24K Code RAM eTPU2 32-ch ADC - Analog-to-digital converter ADCi - ADC interface AIPS - Peripheral I/O bridge AMux - Analog multiplexer CAN - Controller area network DECFIL- Decimation filter EBI - External bus interface ECSM - Error correction status module eDMA2 - Enhanced direct memory access eMIOS - Enhanced modular I/O system eQADC - Enhanced queued A/D converter module eTPU2 - Enhanced time processing unit 2 4x CAN 3x UART/ LIN MMU MPU PBRIDGE S/B SIU SPE2 SPI SRAM UART/LIN VLE 4x SPI 4x Dec Fil 64-ch QUAD ADCi - Memory management unit - Memory protection unit - Peripheral I/O bridge - Stand-by - System integration unit - Signal processing engine 2 - Serial peripheral interface controller - General-purpose static RAM - Universal asynchronous receiver/transmitter/ local interconnect network - Variable length instruction encoding Figure 1. Block diagram PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 5 Pin assignments 3 Pin assignments The figures in this section show the primary pin function. For the full signal properties and muxing table, see Table 4. 3.1 416-ball TEPBGA pin assignments Figure 2 shows the 416-ball TEPBGA pin assignments in one figure. The same information is shown in Figure 3 through Figure 6. 1 A VSS 2 3 4 VDD RSTOUT ANA0 5 6 ANA4 ANA8 ANA11 ANA15 VDDA_A0 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 25 14 AN32 AN36 VDDA_B0 REF- VRL_B VRH_B ANB7 BYPCB1 ANB11 ANB14 ANB17 ANB21 ANB23 AN24 AN27 AN29 AN33 VDDA_B1 VSSA_B0 REF- ANB6 BYPCB ANB8 ANB10 ANB15 ANB18 ANB22 VDD TEST ANA1 ANA5 REF- ANA10 ANA14 VDDA_A1 VSSA_A1 BYPCA C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 AN26 AN30 AN34 AN37 AN38 ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA7 ANA12 ANA16 ANA18 ANA20 ANA22 AN25 AN31 AN35 AN39 ANB1 ANB2 ANB3 ANB9 ANB13 ANB20 B VDDEH1 VSS 24 13 AN28 REF- VRL_A VRH_A BYPCA1 VSS 26 VSS A VSS TCRCLKC B ETPUC0 ETPUC1 C VSS VDDEH7 ETPUC2 ETPUC3 D VDDEH7 ETPUC4 ETPUC5 ETPUC6 E E ETPUA23 ETPUA24 ETPUA25 ETPUA26 ETPUC7 ETPUC8 ETPUC9 ETPUC10 F F ETPUA19 ETPUA20 ETPUA21 ETPUA22 PXR40 416-ball TEPBGA G ETPUA15 ETPUA16 ETPUA17 ETPUA18 ETPUC11 ETPUC12 ETPUC13 ETPUC14 G (as viewed from top through the package) H ETPUA11 ETPUA12 ETPUA14 ETPUA13 ETPUC15 ETPUC16 ETPUC17 ETPUC18 H J ETPUA7 ETPUA8 ETPUA9 ETPUA10 ETPUC19 ETPUC20 ETPUC21 ETPUC22 J K ETPUA3 ETPUA4 ETPUA5 ETPUA6 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC23 ETPUC24 ETPUC25 ETPUC26 K L TCRCLKA ETPUA0 ETPUA1 ETPUA2 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC29 ETPUC30 L M VDD33_1 TXDA VSS VSS VSS VSS VSS VSS VSS VSS ETPUC31 ETPUB15 ETPUB14 VDDEH7 M BOOT- N RXDB CFG1 WKPCFG VDD VDDE2 VSS VSS VSS VSS VSS VSS VSS VDDEH6 ETPUB11 ETPUB12 ETPUB13 N P TXDB PLLCFG1 PLLCFG2 VDDEH1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB7 ETPUB8 ETPUB9 ETPUB10 P R JCOMP RESET PLLCFG0 RDY VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB3 ETPUB4 ETPUB5 ETPUB6 R RXDA VSTBY T VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS TCRCLKB ETPUB0 ETPUB1 ETPUB2 T U EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB19 ETPUB18 ETPUB17 ETPUB16 U V MDO2 MDO3 MDO4 MDO5 ETPUB26 ETPUB22 ETPUB21 ETPUB20 V W MDO6 MDO7 MDO8 VDDE2 REGSEL ETPUB25 ETPUB24 ETPUB23 W Y MDO9 MDO10 MDO11 MDO15 ETPUB29 ETPUB28 ETPUB27 REGCTL Y AA MDO12 MDO13 MDO14 VDD33_2 VDD33_3 ETPUB30 VDDREG VSSSYN AA TDO TCK TMS VDD TDI VDD VSS AD ENGCLK VDD VSS AB AC VDDE2 AE VDD AF VSS 1 VSS VDD ETPUB31 VSSFL EXTAL AB VDDE2 PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 VDD FR_A_ FR_B_ EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC TX TX PCSA5 SOUTA SCKA PCSB0 PCSB3 EMIOS2 FR_A_ FR_B_ PCSA4 PCSA0 PCSA3 SCKB RX RX FR_A_ FR_B_ VDDE2 TX_EN TX_EN VDDEH3 PCSB5 2 3 EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1 4 5 6 SINA 7 SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0 VSS RXDC PCSC3 SINC VDD VDDEH6 XTAL AC VSS PCSC2 PCSC5 VDD VDDSYN AD VSS VDD AE PCSB2 SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 VSS AF 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 2. PXR40 416-ball TEPBGA (full diagram) PXR40 Microcontroller Data Sheet, Rev. 1 6 Freescale Semiconductor Pin assignments A 1 2 3 4 5 6 7 VSS VDD RSTOUT ANA0 ANA4 ANA8 ANA11 ANA15 VDDA_A0 VSS VDD TEST ANA1 ANA5 ANA10 VSS VDD ANA2 ANA6 VSS VDD ANA3 B VDDEH1 C ETPUA30 ETPUA31 D ETPUA27 ETPUA28 ETPUA29 8 9 10 11 12 13 REFBYPCA1 VRL_A VRH_A AN28 A ANA14 VDDA_A1 VSSA_A1 REFBYPCA AN24 AN27 B ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 AN26 C ANA7 ANA12 ANA16 ANA18 ANA20 ANA22 AN25 D E ETPUA23 ETPUA24 ETPUA25 ETPUA26 E F ETPUA19 ETPUA20 ETPUA21 ETPUA22 F PXR40 416-ball TEPBGA G ETPUA15 ETPUA16 ETPUA17 ETPUA18 G (as viewed from top through the package) (1 of 4) H ETPUA11 ETPUA12 ETPUA14 ETPUA13 H J ETPUA7 ETPUA8 ETPUA9 ETPUA10 J K ETPUA3 ETPUA4 ETPUA5 ETPUA6 VSS VSS VSS VSS K L TCRCLKA ETPUA0 ETPUA1 ETPUA2 VSS VSS VSS VSS L M VDD33_1 VSTBY VSS VSS VSS VSS M VDD VDDE2 VSS VSS VSS N 10 11 12 13 N TXDA RXDA RXDB BOOTCFG1 WKPCFG 1 2 3 4 5 6 7 8 9 Figure 3. PXR40 416-ball TEPBGA (1 of 4) PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 7 Pin assignments 14 15 16 17 18 19 20 21 22 23 24 25 26 A AN32 AN36 VDDA_B0 REFBYPCB1 VRL_B VRH_B ANB7 ANB11 ANB14 ANB17 ANB21 ANB23 VSS B AN29 AN33 VDDA_B1 VSSA_B0 REFBYPCB ANB6 ANB8 ANB10 ANB15 ANB18 ANB22 VSS C AN30 AN34 AN37 AN38 ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS D AN31 AN35 AN39 ANB1 ANB2 ANB3 ANB9 ANB13 ANB20 VSS A TCRCLKC B ETPUC0 ETPUC1 C VDDEH7 ETPUC2 ETPUC3 D E VDDEH7 ETPUC4 ETPUC5 ETPUC6 E F ETPUC7 ETPUC8 ETPUC9 ETPUC10 F PXR40 416-ball TEPBGA G ETPUC11 ETPUC12 ETPUC13 ETPUC14 G (as viewed from top through the package) (2 of 4) H ETPUC15 ETPUC16 ETPUC17 ETPUC18 H J ETPUC19 ETPUC20 ETPUC21 ETPUC22 J K VSS VSS VSS VSS ETPUC23 ETPUC24 ETPUC25 ETPUC26 K L VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC29 ETPUC30 L M VSS VSS VSS VSS ETPUC31 ETPUB15 ETPUB14 VDDEH7 M N VSS VSS VSS VSS VDDEH6 ETPUB11 ETPUB12 ETPUB13 N 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 4. PXR40 416-ball TEPBGA (2 of 4) PXR40 Microcontroller Data Sheet, Rev. 1 8 Freescale Semiconductor Pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 PLLCFG1 PLLCFG2 VDDEH1 VDDE2 VDDE2 VSS VSS P RDY VDDE2 VDDE2 VSS VSS R P TXDB R JCOMP RESET PLLCFG0 T VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VDDE2 VSS T U EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VDDE2 VSS U V MDO2 MDO3 MDO4 MDO5 V W MDO6 MDO7 MDO8 VDDE2 W Y MDO9 MDO10 MDO11 MDO15 AA MDO12 MDO13 MDO14 VDD33_2 AB TDO TCK TMS VDD AC VDDE2 TDI VDD VSS VDD VSS PXR40 416-ball TEPBGA AD ENGCLK Y (as viewed from top through the package) (3 of 4) AA AB VDDE2 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 FR_A_TX FR_B_TX PCSA5 SOUTA SCKA PCSB0 PCSA0 PCSA3 SCKB SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 AE EMIOS1 EMIOS4 EMIOS7 EMIOS11 AF AE VDD VSS AF VSS VDDE2 FR_A_ TX_EN FR_B_ TX_EN VDDEH3 PCSB5 SINA PCSB2 SOUTB 1 2 3 4 5 6 7 8 9 FR_A_RX FR_B_RX PCSA4 PCSB3 10 VDD EMIOS8 AC PCSA1 EMIOS2 EMIOS5 EMIOS9 AD 11 12 13 Figure 5. PXR40 416-ball TEPBGA (3 of 4) PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 9 Pin assignments 14 15 16 17 18 19 20 21 22 23 24 25 26 P VSS VSS VSS VSS ETPUB7 ETPUB8 ETPUB9 ETPUB10 P R VSS VSS VSS VSS ETPUB3 ETPUB4 ETPUB5 ETPUB6 R T VSS VSS VSS VSS TCRCLKB ETPUB0 ETPUB1 ETPUB2 T U VSS VSS VSS VSS ETPUB19 ETPUB18 ETPUB17 ETPUB16 U V ETPUB26 ETPUB22 ETPUB21 ETPUB20 V W REGSEL ETPUB25 ETPUB24 ETPUB23 W PXR40 416-ball TEPBGA Y ETPUB29 ETPUB28 ETPUB27 REGCTL Y (as viewed from top through the package) (4 of 4) VDD33_3 ETPUB30 VDDREG VSSSYN AA AA AB VDD AC EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1 AD EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC AE EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0 AF EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 14 15 16 17 18 19 20 21 ETPUB31 VSSFL VSS VDD VDDEH6 RXDC PCSC3 VSS VDD SINC PCSC2 PCSC5 VSS TXDC PCSC4 VDDEH5 22 23 24 25 EXTAL AB XTAL AC VDDSYN AD VDD AE VSS AF 26 Figure 6. PXR40 416-ball TEPBGA (4 of 4) PXR40 Microcontroller Data Sheet, Rev. 1 10 Freescale Semiconductor Signal properties and muxing 4 Signal properties and muxing Table 2 shows the signals properties for each pin on the PXR40. For each port pin that has an associated SIU_PCRn register to control its pin properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 7. Table 2. Signal Properties Summary Primary Functions are listed First GPIO/ PCR1 113 Signal Name2 P/ F/ G TCRCLKA_IRQ7_GPIO113 P Function3 Function Summary I/O Pad Type 5V M TCRCLKA eTPU A TCR clock I I Secondary Functions are alternate functions A1 IRQ7 External interrupt request A2 -- -- -- GPIO Functions are listed Last G GPIO113 GPIO I/O Function not implemented on this device Figure 7. Supported functions example PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 11 12 Voltage6 Function Summary Pad Type5 Function4 Direction Signal Name2 P/A/G3 GPIO/PCR1 Table 2. Signal Properties and Muxing Summary State during RESET7 I MH VDDEH1 --/Up --/Up L1 MH VDDEH1 --/WKPCFG --/WKPCFG L2 MH VDDEH1 --/WKPCFG --/WKPCFG L3 MH VDDEH1 --/WKPCFG --/WKPCFG L4 MH VDDEH1 --/WKPCFG --/WKPCFG K1 MH VDDEH1 --/WKPCFG --/WKPCFG K2 State after RESET8 Package Location (416) eTPU_A 113 PXR40 Microcontroller Data Sheet, Rev. 1 114 115 116 117 Freescale Semiconductor 118 TCRCLKA_IRQ7_ GPIO113 ETPUA0_ETPUA12_ GPIO114 ETPUA1_ETPUA13_ GPIO115 ETPUA2_ETPUA14_ GPIO116 ETPUA3_ETPUA15_ GPIO117 ETPUA4_ETPUA16_ GPIO118 P TCRCLKA eTPU A TCR clock A1 IRQ7 External interrupt request I A2 -- -- -- G GPIO113 GPIO I/O P ETPUA0 eTPU A channel I/O A1 ETPUA12 eTPU A channel (output only) O A2 -- -- -- G GPIO114 GPIO I/O P ETPUA1 eTPU A channel I/O A1 ETPUA13 eTPU A channel (output only) O A2 -- -- -- G GPIO115 GPIO I/O P ETPUA2 eTPU A channel I/O A1 ETPUA14 eTPU A channel (output only) O A2 -- -- -- G GPIO116 GPIO I/O P ETPUA3 eTPU A channel I/O A1 ETPUA15 eTPU A channel (output only) O A2 -- -- -- G GPIO117 GPIO I/O P ETPUA4 eTPU A channel I/O A1 ETPUA16 eTPU A channel (output only) O A2 -- -- -- G GPIO118 GPIO I/O 122 123 124 ETPUA7_ETPUA19_ GPIO121 ETPUA8_ETPUA20_ GPIO122 ETPUA9_ETPUA21_ GPIO123 ETPUA10_ETPUA22_ GPIO124 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 121 ETPUA6_ETPUA18_ GPIO120 Function Summary Pad Type5 120 ETPUA5_ETPUA17_ GPIO119 Function4 Direction 119 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH1 --/WKPCFG --/WKPCFG K3 MH VDDEH1 --/WKPCFG --/WKPCFG K4 MH VDDEH1 --/WKPCFG --/WKPCFG J1 MH VDDEH1 --/WKPCFG --/WKPCFG J2 MH VDDEH1 --/WKPCFG --/WKPCFG J3 MH VDDEH1 --/WKPCFG --/WKPCFG J4 P ETPUA5 eTPU A channel A1 ETPUA17 eTPU A channel (output only) O A2 -- -- -- G GPIO119 GPIO I/O P ETPUA6 eTPU A channel I/O A1 ETPUA18 eTPU A channel (output only) O A2 -- -- -- G GPIO120 GPIO I/O P ETPUA7 eTPU A channel I/O A1 ETPUA19 eTPU A channel (output only) O A2 -- -- -- G GPIO121 GPIO I/O P ETPUA8 eTPU A channel I/O A1 ETPUA20 eTPU A channel (output only) O A2 -- -- -- G GPIO122 GPIO I/O P ETPUA9 eTPU A channel I/O A1 ETPUA21 eTPU A channel (output only) O A2 -- -- -- G GPIO123 GPIO I/O P ETPUA10 eTPU A channel I/O A1 ETPUA22 eTPU A channel (output only) O A2 -- -- -- G GPIO124 GPIO I/O State after RESET8 Package Location (416) 13 128 129 Freescale Semiconductor 130 ETPUA13_PCSB3_ GPIO127 ETPUA14_PCSB4_ GPIO128 ETPUA15_PCSB5_ GPIO129 ETPUA16_PCSD1_ GPIO130 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 127 ETPUA12_PCSB1_ GPIO126 Function Summary Pad Type5 126 ETPUA11_ETPUA23_ GPIO125 Function4 Direction 125 Signal Name2 P/A/G3 GPIO/PCR1 14 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH1 --/WKPCFG --/WKPCFG H1 MH VDDEH1 --/WKPCFG --/WKPCFG H2 MH VDDEH1 --/WKPCFG --/WKPCFG H4 MH VDDEH1 --/WKPCFG --/WKPCFG H3 MH VDDEH1 --/WKPCFG --/WKPCFG G1 MH VDDEH1 --/WKPCFG --/WKPCFG G2 P ETPUA11 eTPU A channel A1 ETPUA23 eTPU A channel (output only) O A2 -- -- -- G GPIO125 GPIO I/O P ETPUA12 eTPU A channel I/O A1 PCSB1 DSPI B peripheral chip select O A2 -- -- -- G GPIO126 GPIO I/O P ETPUA13 eTPU A channel I/O A1 PCSB3 DSPI B peripheral chip select O A2 -- -- -- G GPIO127 GPIO I/O P ETPUA14 eTPU A channel I/O A1 PCSB4 DSPI B peripheral chip select O A2 -- -- -- G GPIO128 GPIO I/O P ETPUA15 eTPU A channel I/O A1 PCSB5 DSPI B peripheral chip select O A2 -- -- -- G GPIO129 GPIO I/O P ETPUA16 eTPU A channel I/O A1 PCSD1 DSPI D peripheral chip select O A2 -- -- -- G GPIO130 GPIO I/O State after RESET8 Package Location (416) 134 135 136 ETPUA19_PCSD4_ GPIO133 ETPUA20_IRQ8_ GPIO134 ETPUA21_IRQ9_ GPIO135 ETPUA22_IRQ10_ GPIO136 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 133 ETPUA18_PCSD3_ GPIO132 Function Summary Pad Type5 132 ETPUA17_PCSD2_ GPIO131 Function4 Direction 131 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH1 --/WKPCFG --/WKPCFG G3 MH VDDEH1 --/WKPCFG --/WKPCFG G4 MH VDDEH1 --/WKPCFG --/WKPCFG F1 MH VDDEH1 --/WKPCFG --/WKPCFG F2 MH VDDEH1 --/WKPCFG --/WKPCFG F3 MH VDDEH1 --/WKPCFG --/WKPCFG F4 P ETPUA17 eTPU A channel A1 PCSD2 DSPI D peripheral chip select O A2 -- -- -- G GPIO131 GPIO I/O P ETPUA18 eTPU A channel I/O A1 PCSD3 DSPI D peripheral chip select O A2 -- -- -- G GPIO132 GPIO I/O P ETPUA19 eTPU A channel I/O A1 PCSD4 DSPI D peripheral chip select O A2 -- -- -- G GPIO133 GPIO I/O P ETPUA20 eTPU A channel I/O A1 IRQ8 External interrupt request A2 -- -- -- G GPIO134 GPIO I/O P ETPUA21 eTPU A channel I/O A1 IRQ9 External interrupt request A2 -- -- -- G GPIO135 GPIO I/O P ETPUA22 eTPU A channel I/O A1 IRQ10 External interrupt request A2 -- -- -- G GPIO136 GPIO I/O State after RESET8 Package Location (416) I I I 15 140 141 Freescale Semiconductor 142 ETPUA25_IRQ13_ GPIO139 ETPUA26_IRQ14_ GPIO140 ETPUA27_IRQ15_ GPIO141 ETPUA28_PCSC1_ GPIO142 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 139 ETPUA24_IRQ12_ GPIO138 Function Summary Pad Type5 138 ETPUA23_IRQ11_ GPIO137 Function4 Direction 137 Signal Name2 P/A/G3 GPIO/PCR1 16 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH1 --/WKPCFG --/WKPCFG E1 MH VDDEH1 --/WKPCFG --/WKPCFG E2 MH VDDEH1 --/WKPCFG --/WKPCFG E3 MH VDDEH1 --/WKPCFG --/WKPCFG E4 MH VDDEH1 --/WKPCFG --/WKPCFG D1 MH VDDEH1 --/WKPCFG --/WKPCFG D2 P ETPUA23 eTPU A channel A1 IRQ11 External interrupt request A2 -- -- -- G GPIO137 GPIO I/O P ETPUA24 eTPU A channel I/O A1 IRQ12 External interrupt request A2 -- -- -- G GPIO138 GPIO I/O P ETPUA25 eTPU A channel I/O A1 IRQ13 External interrupt request A2 -- -- -- G GPIO139 GPIO I/O P ETPUA26 eTPU A channel I/O A1 IRQ14 External interrupt request A2 -- -- -- G GPIO140 GPIO I/O P ETPUA27 eTPU A channel I/O A1 IRQ15 External interrupt request A2 -- -- -- G GPIO141 GPIO I/O P ETPUA28 eTPU A channel I/O A1 PCSC1 DSPI C peripheral chip select O A2 -- -- -- G GPIO142 GPIO I/O State after RESET8 Package Location (416) I I I I I ETPUA31_PCSC4_ GPIO145 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 145 ETPUA30_PCSC3_ GPIO144 Function Summary Pad Type5 144 ETPUA29_PCSC2_ GPIO143 Function4 Direction 143 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH1 --/WKPCFG --/WKPCFG D3 MH VDDEH1 --/WKPCFG --/WKPCFG C1 MH VDDEH1 --/WKPCFG --/WKPCFG C2 MH VDDEH6 --/Up --/Up T23 MH VDDEH6 --/WKPCFG --/WKPCFG T24 MH VDDEH6 --/WKPCFG --/WKPCFG T25 P ETPUA29 eTPU A channel A1 PCSC2 DSPI C peripheral chip select O A2 -- -- -- G GPIO143 GPIO I/O P ETPUA30 eTPU A channel I/O A1 PCSC3 DSPI C peripheral chip select O A2 -- -- -- G GPIO144 GPIO I/O P ETPUA31 eTPU A channel I/O A1 PCSC4 DSPI C peripheral chip select O A2 -- -- -- G GPIO145 GPIO I/O State after RESET8 Package Location (416) eTPU_B 146 147 148 TCRCLKB_IRQ6_ GPIO146 ETPUB0_ETPUB16_ GPIO147 ETPUB1_ETPUB17_ GPIO148 17 P TCRCLKB eTPU B TCR clock I A1 IRQ6 External interrupt request I A2 -- -- -- G GPIO146 GPIO I/O P ETPUB0 eTPU B channel I/O A1 ETPUB16 eTPU B channel (output only) O A2 -- -- -- G GPIO147 GPIO I/O P ETPUB1 eTPU B channel I/O A1 ETPUB17 eTPU B channel (output only) O A2 -- -- -- G GPIO148 GPIO I/O 152 153 Freescale Semiconductor 154 ETPUB4_ETPUB20_ GPIO151 ETPUB5_ETPUB21_ GPIO152 ETPUB6_ETPUB22_ GPIO153 ETPUB7_ETPUB23_ GPIO154 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 151 ETPUB3_ETPUB19_ GPIO150 Function Summary Pad Type5 150 ETPUB2_ETPUB18_ GPIO149 Function4 Direction 149 Signal Name2 P/A/G3 GPIO/PCR1 18 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH6 --/WKPCFG --/WKPCFG T26 MH VDDEH6 --/WKPCFG --/WKPCFG R23 MH VDDEH6 --/WKPCFG --/WKPCFG R24 MH VDDEH6 --/WKPCFG --/WKPCFG R25 MH VDDEH6 --/WKPCFG --/WKPCFG R26 MH VDDEH6 --/WKPCFG --/WKPCFG P23 P ETPUB2 eTPU B channel A1 ETPUB18 eTPU B channel (output only) O A2 -- -- -- G GPIO149 GPIO I/O P ETPUB3 eTPU B channel I/O A1 ETPUB19 eTPU B channel (output only) O A2 -- -- -- G GPIO150 GPIO I/O P ETPUB4 eTPU B channel I/O A1 ETPUB20 eTPU B channel (output only) O A2 -- -- -- G GPIO151 GPIO I/O P ETPUB5 eTPU B channel I/O A1 ETPUB21 eTPU B channel (output only) O A2 -- -- -- G GPIO152 GPIO I/O P ETPUB6 eTPU B channel I/O A1 ETPUB22 eTPU B channel (output only) O A2 -- -- -- G GPIO153 GPIO I/O P ETPUB7 eTPU B channel I/O A1 ETPUB23 eTPU B channel (output only) O A2 -- -- -- G GPIO154 GPIO I/O State after RESET8 Package Location (416) 158 159 160 ETPUB10_ETPUB26_ GPIO157 ETPUB11_ETPUB27_ GPIO158 ETPUB12_ETPUB28_ GPIO159 ETPUB13_ETPUB29_ GPIO160 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 157 ETPUB9_ETPUB25_ GPIO156 Function Summary Pad Type5 156 ETPUB8_ETPUB24_ GPIO155 Function4 Direction 155 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH6 --/WKPCFG --/WKPCFG P24 MH VDDEH6 --/WKPCFG --/WKPCFG P25 MH VDDEH6 --/WKPCFG --/WKPCFG P26 MH VDDEH6 --/WKPCFG --/WKPCFG N24 MH VDDEH6 --/WKPCFG --/WKPCFG N25 MH VDDEH6 --/WKPCFG --/WKPCFG N26 P ETPUB8 eTPU B channel A1 ETPUB24 eTPU B channel (output only) O A2 -- -- -- G GPIO155 GPIO I/O P ETPUB9 eTPU B channel I/O A1 ETPUB25 eTPU B channel (output only) O A2 -- -- -- G GPIO156 GPIO I/O P ETPUB10 eTPU B channel I/O A1 ETPUB26 eTPU B channel (output only) O A2 -- -- -- G GPIO157 GPIO I/O P ETPUB11 eTPU B channel I/O A1 ETPUB27 eTPU B channel (output only) O A2 -- -- -- G GPIO158 GPIO I/O P ETPUB12 eTPU B channel I/O A1 ETPUB28 eTPU B channel (output only) O A2 -- -- -- G GPIO159 GPIO I/O P ETPUB13 eTPU B channel I/O A1 ETPUB29 eTPU B channel (output only) O A2 -- -- -- G GPIO160 GPIO I/O State after RESET8 Package Location (416) 19 164 165 Freescale Semiconductor 166 ETPUB16_PCSA1_ GPIO163 ETPUB17_PCSA2_ GPIO164 ETPUB18_PCSA3_ GPIO165 ETPUB19_PCSA4_ GPIO166 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 163 ETPUB15_ETPUB31_ GPIO162 Function Summary Pad Type5 162 ETPUB14_ETPUB30_ GPIO161 Function4 Direction 161 Signal Name2 P/A/G3 GPIO/PCR1 20 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH6 --/WKPCFG --/WKPCFG M25 MH VDDEH6 --/WKPCFG --/WKPCFG M24 MH VDDEH6 --/WKPCFG --/WKPCFG U26 MH VDDEH6 --/WKPCFG --/WKPCFG U25 MH VDDEH6 --/WKPCFG --/WKPCFG U24 MH VDDEH6 --/WKPCFG --/WKPCFG U23 P ETPUB14 eTPU B channel A1 ETPUB30 eTPU B channel (output only) O A2 -- -- -- G GPIO161 GPIO I/O P ETPUB15 eTPU B channel I/O A1 ETPUB31 eTPU B channel (output only) O A2 -- -- -- G GPIO162 GPIO I/O P ETPUB16 eTPU B channel I/O A1 PCSA1 DSPI A peripheral chip select O A2 -- -- -- G GPIO163 GPIO I/O P ETPUB17 eTPU B channel I/O A1 PCSA2 DSPI A peripheral chip select O A2 -- -- -- G GPIO164 GPIO I/O P ETPUB18 eTPU B channel I/O A1 PCSA3 DSPI A peripheral chip select O A2 -- -- -- G GPIO165 GPIO I/O P ETPUB19 eTPU B channel I/O A1 PCSA4 DSPI A peripheral chip select O A2 -- -- -- G GPIO166 GPIO I/O State after RESET8 Package Location (416) 170 171 172 ETPUB22_ GPIO169 ETPUB23_ GPIO170 ETPUB24_ GPIO171 ETPUB25_ GPIO172 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 169 ETPUB21_ GPIO168 Function Summary Pad Type5 168 ETPUB20_ GPIO167 Function4 Direction 167 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH6 --/WKPCFG --/WKPCFG V26 MH VDDEH6 --/WKPCFG --/WKPCFG V25 MH VDDEH6 --/WKPCFG --/WKPCFG V24 MH VDDEH6 --/WKPCFG --/WKPCFG W26 MH VDDEH6 --/WKPCFG --/WKPCFG W25 MH VDDEH6 --/WKPCFG --/WKPCFG W24 P ETPUB20 eTPU B channel A1 -- -- -- A2 -- -- -- G GPIO167 GPIO I/O P ETPUB21 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO168 GPIO I/O P ETPUB22 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO169 GPIO I/O P ETPUB23 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO170 GPIO I/O P ETPUB24 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO171 GPIO I/O P ETPUB25 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO172 GPIO I/O State after RESET8 Package Location (416) 21 176 177 Freescale Semiconductor 178 ETPUB28_ GPIO175 ETPUB29_ GPIO176 ETPUB30_ GPIO177 ETPUB31_ GPIO178 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 175 ETPUB27_ GPIO174 Function Summary Pad Type5 174 ETPUB26_ GPIO173 Function4 Direction 173 Signal Name2 P/A/G3 GPIO/PCR1 22 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH6 --/WKPCFG --/WKPCFG V23 MH VDDEH6 --/WKPCFG --/WKPCFG Y25 MH VDDEH6 --/WKPCFG --/WKPCFG Y24 MH VDDEH6 --/WKPCFG --/WKPCFG Y23 MH VDDEH6 --/WKPCFG --/WKPCFG AA24 MH VDDEH6 --/WKPCFG --/WKPCFG AB24 P ETPUB26 eTPU B channel A1 -- -- -- A2 -- -- -- G GPIO173 GPIO I/O P ETPUB27 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO174 GPIO I/O P ETPUB28 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO175 GPIO I/O P ETPUB29 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO176 GPIO I/O P ETPUB30 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO177 GPIO I/O P ETPUB31 eTPU B channel I/O A1 -- -- -- A2 -- -- -- G GPIO178 GPIO I/O State after RESET8 Package Location (416) Voltage6 Function Summary Pad Type5 Function4 Direction Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 -- MH VDDEH7 --/Up --/Up B26 MH VDDEH7 --/WKPCFG --/WKPCFG C25 MH VDDEH7 --/WKPCFG --/WKPCFG C26 MH VDDEH7 --/WKPCFG --/WKPCFG D25 MH VDDEH7 --/WKPCFG --/WKPCFG D26 MH VDDEH7 --/WKPCFG --/WKPCFG E24 State after RESET8 Package Location (416) GPIO, IRQ, FlexRay 440 PXR40 Microcontroller Data Sheet, Rev. 1 441 442 443 444 445 TCRCLKC_ GPIO4409 ETPUC0_ GPIO4419 ETPUC1_ GPIO4429 ETPUC2_ GPIO4439 ETPUC3_ GPIO4449 ETPUC4_ GPIO4459 23 P -- -- A1 -- -- -- A2 -- -- -- G GPIO440 GPIO I/O P -- -- -- A1 -- -- -- A2 -- -- -- G GPIO441 GPIO I/O P -- -- -- A1 -- -- -- A2 -- -- -- G GPIO442 GPIO I/O P -- -- -- A1 -- -- -- A2 -- -- -- G GPIO443 GPIO I/O P -- -- -- A1 -- -- -- A2 -- -- -- G GPIO444 GPIO I/O P -- -- -- A1 -- -- -- A2 -- -- -- G GPIO445 GPIO I/O 449 450 Freescale Semiconductor 451 ETPUC7_ GPIO4489 ETPUC8_ GPIO4499 ETPUC9_IRQ0_ GPIO4509 ETPUC10__IRQ1_ GPIO4519 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 448 ETPUC6_ GPIO4479 Function Summary Pad Type5 447 ETPUC5_ GPIO4469 Function4 Direction 446 Signal Name2 P/A/G3 GPIO/PCR1 24 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH7 --/WKPCFG --/WKPCFG E25 MH VDDEH7 --/WKPCFG --/WKPCFG E26 MH VDDEH7 --/WKPCFG --/WKPCFG F23 MH VDDEH7 --/WKPCFG --/WKPCFG F24 MH VDDEH7 --/WKPCFG --/WKPCFG F25 MH VDDEH7 --/WKPCFG --/WKPCFG F26 P -- -- A1 -- -- -- A2 -- -- -- G GPIO446 GPIO I/O P -- -- I/O A1 -- -- -- A2 -- -- -- G GPIO447 GPIO I/O P -- -- I/O A1 -- -- -- A2 -- -- -- G GPIO448 GPIO I/O P -- -- I/O A1 -- -- -- A2 -- -- -- G GPIO449 GPIO I/O P -- -- -- A1 IRQ0 External interrupt request A2 -- -- -- G GPIO450 GPIO I/O P -- -- -- A1 IRQ1 External interrupt request A2 -- -- -- G GPIO451 GPIO I/O State after RESET8 Package Location (416) I I 455 456 457 ETPUC13_3_IRQ4_ GPIO4549 ETPUC14_4_IRQ5_ GPIO4559 ETPUC15__ GPIO4569 ETPUC16_FR_A_TX_ GPIO4579 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 454 ETPUC12_IRQ3_ GPIO4539 Function Summary Pad Type5 453 ETPUC11_IRQ2_ GPIO4529 Function4 Direction 452 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 -- MH VDDEH7 --/WKPCFG --/WKPCFG G23 MH VDDEH7 --/WKPCFG --/WKPCFG G24 MH VDDEH7 --/WKPCFG --/WKPCFG G25 MH VDDEH7 --/WKPCFG --/WKPCFG G26 MH VDDEH7 --/WKPCFG --/WKPCFG H23 MH VDDEH7 --/WKPCFG --/WKPCFG H24 P -- -- A1 IRQ2 External interrupt request A2 -- -- -- G GPIO452 GPIO I/O P -- -- -- A1 IRQ3 External interrupt request A2 -- -- -- G GPIO453 GPIO I/O P -- -- -- A1 IRQ4 External interrupt request A2 -- -- -- G GPIO454 GPIO I/O P -- -- -- A1 IRQ5 External interrupt request A2 -- -- -- G GPIO455 GPIO I/O P -- -- -- A1 -- -- -- A2 -- -- -- G GPIO456 GPIO I/O P -- -- -- A1 FR_A_TX FlexRay A transfer O A2 -- -- -- G GPIO457 GPIO I/O State after RESET8 Package Location (416) I I I I 25 461 462 Freescale Semiconductor 463 ETPUC19_TXDA_ GPIO4609 ETPUC20_RXDA _ GPIO4619 ETPUC21_TXDB_ GPIO4629 ETPUC22_RXDB_ GPIO4639 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 460 ETPUC18_FR_A_TX_EN_ GPIO4599 Function Summary Pad Type5 459 ETPUC17_FR_A_RX_ GPIO4589 Function4 Direction 458 Signal Name2 P/A/G3 GPIO/PCR1 26 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 -- MH VDDEH7 --/WKPCFG --/WKPCFG H25 MH VDDEH7 --/WKPCFG --/WKPCFG H26 MH VDDEH7 --/WKPCFG --/WKPCFG J23 MH VDDEH7 --/WKPCFG --/WKPCFG J24 MH VDDEH7 --/WKPCFG --/WKPCFG J25 MH VDDEH7 --/WKPCFG --/WKPCFG J26 P -- -- A1 FR_A_RX FlexRay A receive A2 -- -- -- G GPIO458 GPIO I/O P -- -- -- A1 FR_A_TX_EN FlexRay A transfer enable O A2 -- -- -- G GPIO459 GPIO I/O P -- -- -- A1 TXDA eSCI A transmit O A2 -- -- -- G GPIO460 GPIO I/O P -- -- -- A1 RXDA eSCI A receive A2 -- -- -- G GPIO461 GPIO I/O P -- -- -- A1 TXDB eSCI B transmit O A2 -- -- -- G GPIO462 GPIO I/O P -- -- -- A1 RXDB eSCI B receive A2 -- -- -- G GPIO463 GPIO I/O State after RESET8 Package Location (416) I I I 467 468 ETPUC25_PCSD3_ GPIO4669 ETPUC26_PCSD2_ GPIO4679 ETPUC27_PCSD1_ GPIO4689 Voltage6 466 ETPUC24_PCSD4_ GPIO4659 Function Summary Pad Type5 PXR40 Microcontroller Data Sheet, Rev. 1 465 ETPUC23_PCSD5_ GPIO4649 Function4 Direction 464 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 -- MH VDDEH7 --/WKPCFG --/WKPCFG K23 MH VDDEH7 --/WKPCFG --/WKPCFG K24 MH VDDEH7 --/WKPCFG --/WKPCFG K25 MH VDDEH7 --/WKPCFG --/WKPCFG K26 MH VDDEH7 --/WKPCFG --/WKPCFG L23 P -- -- A1 PCSD5 DSPI D peripheral chip select O A2 MAA0 ADC A Mux Address 0 O A3 MAB0 ADC B Mux Address 0 O G GPIO464 GPIO I/O P -- -- -- A1 PCSD4 DSPI D peripheral chip select O A2 MAA1 ADC A Mux Address 1 O A4 MAB1 ADC B Mux Address 1 O G GPIO465 GPIO I/O P -- -- -- A1 PCSD3 DSPI D peripheral chip select O A2 MAA2 ADC A Mux Address 2 O A3 MAB2 ADC B Mux Address 2 O G GPIO466 GPIO I/O P -- -- -- A1 PCSD2 DSPI D peripheral chip select O A2 -- -- -- G GPIO467 GPIO I/O P -- -- -- A1 PCSD1 DSPI D peripheral chip select O A2 -- -- -- G GPIO468 GPIO I/O State after RESET8 Package Location (416) 27 472 ETPUC30_SOUTD_ GPIO4719 ETPUC31_SIND_ GPIO4729 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 471 ETPUC29_SCKD_ GPIO4709 Function Summary Pad Type5 470 ETPUC28_PCSD0_ GPIO4699 Function4 Direction 469 Signal Name2 P/A/G3 GPIO/PCR1 28 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 -- MH VDDEH7 --/WKPCFG --/WKPCFG L24 MH VDDEH7 --/WKPCFG --/WKPCFG L25 MH VDDEH7 --/WKPCFG --/WKPCFG L26 MH VDDEH7 --/WKPCFG --/WKPCFG M23 MH VDDEH4 --/WKPCFG --/WKPCFG AE10 MH VDDEH4 --/WKPCFG --/WKPCFG AF10 P -- -- A1 PCSD0 DSPI D peripheral chip select I/O A2 -- -- -- G GPIO469 GPIO I/O P -- -- -- A1 SCKD DSPI D clock I/O A2 -- -- -- G GPIO470 GPIO I/O P -- -- -- A1 SOUTD DSPI D data output O A2 -- -- -- G GPIO471 GPIO I/O P -- -- -- A1 SIND DSPI D data input A2 -- -- -- G GPIO472 GPIO I/O State after RESET8 Package Location (416) I eMIOS 179 Freescale Semiconductor 180 EMIOS0_ETPUA0_ GPIO179 EMIOS1_ETPUA1_ GPIO180 P EMIOS0 eMIOS channel I/O A1 ETPUA0 eTPU A channel O A2 -- -- -- G GPIO179 GPIO I/O P EMIOS1 eMIOS channel I/O A1 ETPUA1 eTPU A channel O A2 -- -- -- G GPIO180 GPIO I/O 184 185 186 EMIOS4_ETPUA4_ GPIO183 EMIOS5_ETPUA5_ GPIO184 EMIOS6_ETPUA6_ GPIO185 EMIOS7_ETPUA7_ GPIO186 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 183 EMIOS3_ETPUA3_ GPIO182 Function Summary Pad Type5 182 EMIOS2_ETPUA2_ GPIO181 Function4 Direction 181 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH4 --/WKPCFG --/WKPCFG AD11 MH VDDEH4 --/WKPCFG --/WKPCFG AE11 MH VDDEH4 --/WKPCFG --/WKPCFG AF11 MH VDDEH4 --/WKPCFG --/WKPCFG AD12 MH VDDEH4 --/WKPCFG --/WKPCFG AE12 MH VDDEH4 --/WKPCFG --/WKPCFG AF12 P EMIOS2 eMIOS channel A1 ETPUA2 eTPU A channel O A2 -- -- -- G GPIO181 GPIO I/O P EMIOS3 eMIOS channel I/O A1 ETPUA3 eTPU A channel O A2 -- -- -- G GPIO182 GPIO I/O P EMIOS4 eMIOS channel I/O A1 ETPUA4 eTPU A channel O A2 -- -- -- G GPIO183 GPIO I/O P EMIOS5 eMIOS channel I/O A1 ETPUA5 eTPU A channel O A2 -- -- -- G GPIO184 GPIO I/O P EMIOS6 eMIOS channel I/O A1 ETPUA6 eTPU A channel O A2 -- -- -- G GPIO185 GPIO I/O P EMIOS7 eMIOS channel I/O A1 ETPUA7 eTPU A channel O A2 -- -- -- G GPIO186 GPIO I/O State after RESET8 Package Location (416) 29 190 191 Freescale Semiconductor 192 EMIOS10_SCKD_ GPIO189 EMIOS11_SIND_ GPIO190 EMIOS12_SOUTC_ GPIO191 EMIOS13_SOUTD_ GPIO192 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 189 EMIOS9_ETPUA9_ GPIO188 Function Summary Pad Type5 188 EMIOS8_ETPUA8_ GPIO187 Function4 Direction 187 Signal Name2 P/A/G3 GPIO/PCR1 30 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH4 --/WKPCFG --/WKPCFG AC13 MH VDDEH4 --/WKPCFG --/WKPCFG AD13 MH VDDEH4 --/WKPCFG --/WKPCFG AE13 MH VDDEH4 --/WKPCFG --/WKPCFG AF13 MH VDDEH4 --/WKPCFG --/WKPCFG AF14 MH VDDEH4 --/WKPCFG --/WKPCFG AE14 P EMIOS8 eMIOS channel A1 ETPUA8 eTPU A channel O A2 -- -- -- G GPIO187 GPIO I/O P EMIOS9 eMIOS channel I/O A1 ETPUA9 eTPU A channel O A2 -- -- -- G GPIO188 GPIO I/O P EMIOS10 eMIOS channel I/O A1 SCKD DSPI D clock O A2 -- -- -- G GPIO189 GPIO I/O P EMIOS11 eMIOS channel I/O A1 SIND DSPI D data input A2 -- -- -- G GPIO190 GPIO I/O P EMIOS12 eMIOS channel O A1 SOUTC DSPI C data output O A2 -- -- -- G GPIO191 GPIO I/O P EMIOS13 eMIOS channel O A1 SOUTD DSPI D data output O A2 -- -- -- G GPIO192 GPIO I/O State after RESET8 Package Location (416) I 196 197 198 EMIOS16_ETPUB0_ GPIO195 EMIOS17_ETPUB1_ GPIO196 EMIOS18_ETPUB2_ GPIO197 EMIOS19_ETPUB3_ GPIO198 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 195 EMIOS15_IRQ1_ GPIO194 Function Summary Pad Type5 194 EMIOS14_IRQ0_ GPIO193 Function4 Direction 193 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O MH VDDEH4 --/WKPCFG --/WKPCFG AC14 MH VDDEH4 --/WKPCFG --/WKPCFG AD14 MH VDDEH4 --/WKPCFG --/WKPCFG AF15 MH VDDEH4 --/WKPCFG --/WKPCFG AE15 MH VDDEH4 --/WKPCFG --/WKPCFG AC15 MH VDDEH4 --/WKPCFG --/WKPCFG AD15 P EMIOS14 eMIOS channel A1 IRQ0 External interrupt request I A2 CNTXD FlexCAN D transmit O G GPIO193 GPIO I/O P EMIOS15 eMIOS channel O A1 IRQ1 External interrupt request I A2 CNRXD FlexCAN D receive I G GPIO194 GPIO I/O P EMIOS16 eMIOS channel I/O A1 ETPUB0 eTPU B channel O A2 FR_DBG[3] FlexRay debug O G GPIO195 GPIO I/O P EMIOS17 eMIOS channel I/O A1 ETPUB1 eTPU B channel O A2 FR_DBG[2] FlexRay debug O G GPIO196 GPIO I/O P EMIOS18 eMIOS channel I/O A1 ETPUB2 eTPU B channel O A2 FR_DBG[1] FlexRay debug O G GPIO197 GPIO I/O P EMIOS19 eMIOS channel I/O A1 ETPUB3 eTPU B channel O A2 FR_DBG[0] FlexRay debug O G GPIO198 GPIO I/O State after RESET8 Package Location (416) 31 202 203 Freescale Semiconductor 204 EMIOS22_ETPUB6_ GPIO201 EMIOS23_ETPUB7_ GPIO202 EMIOS24_PCSB0_ GPIO203 EMIOS25_PCSB1_ GPIO204 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 201 EMIOS21_ETPUB5_ GPIO200 Function Summary Pad Type5 200 EMIOS20_ETPUB4_ GPIO199 Function4 Direction 199 Signal Name2 P/A/G3 GPIO/PCR1 32 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH4 --/WKPCFG --/WKPCFG AF16 MH VDDEH4 --/WKPCFG --/WKPCFG AE16 MH VDDEH4 --/WKPCFG --/WKPCFG AC16 MH VDDEH4 --/WKPCFG --/WKPCFG AD16 MH VDDEH4 --/WKPCFG --/WKPCFG AF17 MH VDDEH4 --/WKPCFG --/WKPCFG AE17 P EMIOS20 eMIOS channel A1 ETPUB4 eTPU B channel O A2 -- -- -- G GPIO199 GPIO I/O P EMIOS21 eMIOS channel I/O A1 ETPUB5 eTPU B channel O A2 -- -- -- G GPIO200 GPIO I/O P EMIOS22 eMIOS channel I/O A1 ETPUB6 eTPU B channel O A2 -- -- -- G GPIO201 GPIO I/O P EMIOS23 eMIOS channel I/O A1 ETPUB7 eTPU B channel O A2 -- -- -- G GPIO202 GPIO I/O P EMIOS24 eMIOS channel I/O A1 PCSB0 DSPI B peripheral chip select I/O A2 -- -- -- G GPIO203 GPIO I/O P EMIOS25 eMIOS channel I/O A1 PCSB1 DSPI B peripheral chip select O A2 -- -- -- G GPIO204 GPIO I/O State after RESET8 Package Location (416) 435 436 437 EMIOS28_PCSC0_ GPIO434 EMIOS29_PCSC1_ GPIO435 EMIOS30_PCSC2_ GPIO436 EMIOS31_PCSC5_ GPIO437 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 434 EMIOS27_PCSB3_ GPIO433 Function Summary Pad Type5 433 EMIOS26_PCSB2_ GPIO432 Function4 Direction 432 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH4 --/WKPCFG --/WKPCFG AD17 MH VDDEH4 --/WKPCFG --/WKPCFG AC17 MH VDDEH4 --/WKPCFG --/WKPCFG AF18 MH VDDEH4 --/WKPCFG --/WKPCFG AE18 MH VDDEH4 --/WKPCFG --/WKPCFG AD18 MH VDDEH4 --/WKPCFG --/WKPCFG AC18 P EMIOS26 eMIOS channel A1 PCSB2 DSPI B peripheral chip select O A2 -- -- -- G GPIO432 GPIO I/O P EMIOS27 eMIOS channel I/O A1 PCSB3 DSPI B peripheral chip select O A2 -- -- -- G GPIO433 GPIO I/O P EMIOS28 eMIOS channel I/O A1 PCSC0 DSPI C peripheral chip select I/O A2 -- -- -- G GPIO434 GPIO I/O P EMIOS29 eMIOS channel I/O A1 PCSC1 DSPI C peripheral chip select O A2 -- -- -- G GPIO435 GPIO I/O P EMIOS30 eMIOS channel I/O A1 PCSC2 DSPI C peripheral chip select O A2 -- -- -- G GPIO436 GPIO I/O P EMIOS31 eMIOS channel I/O A1 PCSC5 DSPI C peripheral chip select O A2 -- -- -- G GPIO437 GPIO I/O 33 eQADC State after RESET8 Package Location (416) Voltage6 State during RESET7 -- ANA0 P ANA010 eQADC A analog input I AE/updown VDDA_A1 ANA0 ANA0 A4 -- ANA1 P ANA110 eQADC A analog input I AE/updown VDDA_A1 ANA1 ANA1 B5 -- ANA2 P ANA210 eQADC A analog input I AE/updown VDDA_A1 ANA2 ANA2 C5 -- ANA3 P ANA310 eQADC A analog input I AE/updown VDDA_A1 ANA3 ANA3 D6 -- ANA4 P ANA410 eQADC A analog input I AE/updown VDDA_A1 ANA4 ANA4 A5 -- ANA5 P ANA510 eQADC A analog input I AE/updown VDDA_A1 ANA5 ANA5 B6 -- ANA6 P ANA610 eQADC A analog input I AE/updown VDDA_A1 ANA6 ANA6 C6 -- ANA7 P ANA710 eQADC A analog input I AE/updown VDDA_A1 ANA7 ANA7 D7 -- ANA8 P ANA8 eQADC A analog input I AE VDDA_A1 ANA8 ANA8 A6 -- ANA9 P ANA9 eQADC A analog input I AE VDDA_A1 ANA9 ANA9 C7 -- ANA10 P ANA10 eQADC A analog input I AE VDDA_A1 ANA10 ANA10 B7 -- ANA11 P ANA11 eQADC A analog input I AE VDDA_A1 ANA11 ANA11 A7 -- ANA12 P ANA12 eQADC A analog input I AE VDDA_A1 ANA12 ANA12 D8 -- ANA13 P ANA13 eQADC A analog input I AE VDDA_A1 ANA13 ANA13 C8 -- ANA14 P ANA14 eQADC A analog input I AE VDDA_A1 ANA14 ANA14 B8 -- ANA15 P ANA15 eQADC A analog input I AE VDDA_A1 ANA15 ANA15 A8 -- ANA16 P ANA16 eQADC A analog input I AE VDDA_A1 ANA16 ANA16 D9 -- ANA17 P ANA17 eQADC A analog input I AE VDDA_A1 ANA17 ANA17 C9 -- ANA18 P ANA18 eQADC A analog input I AE VDDA_A1 ANA18 ANA18 D10 -- ANA19 P ANA19 eQADC A analog input I AE VDDA_A1 ANA19 ANA19 C10 Signal Name2 P/A/G3 Pad Type5 PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor Direction GPIO/PCR1 34 Table 2. Signal Properties and Muxing Summary (continued) Function4 Function Summary State after RESET8 Package Location (416) Voltage6 State during RESET7 -- ANA20 P ANA20 eQADC A analog input I AE VDDA_A1 ANA20 ANA20 D11 -- ANA21 P ANA21 eQADC A analog input I AE VDDA_A1 ANA21 ANA21 C11 -- ANA22 P ANA22 eQADC A analog input I AE VDDA_A1 ANA22 ANA22 D12 -- ANA23 P ANA23 eQADC A analog input I AE VDDA_A1 ANA23 ANA23 C12 -- AN24 P AN24 eQADC A and B shared analog input I AE VDDA_A0 AN24 AN24 B12 -- AN25 P AN25 eQADC A and B shared analog input I AE VDDA_A0 AN25 AN25 D13 -- AN26 P AN26 eQADC A and B shared analog input I AE VDDA_A0 AN26 AN26 C13 -- AN27 P AN27 eQADC A and B shared analog input I AE VDDA_A0 AN27 AN27 B13 -- AN28 P AN28 eQADC A and B shared analog input I AE VDDA_A0 AN28 AN28 A13 -- AN29 P AN29 eQADC A and B shared analog input I AE VDDA_A0 AN29 AN29 B14 -- AN30 P AN30 eQADC A and B shared analog input I AE VDDA_B1 AN30 AN30 C14 -- AN31 P AN31 eQADC A and B shared analog input I AE VDDA_B1 AN31 AN31 D14 -- AN32 P AN32 eQADC A and B shared analog input I AE VDDA_B1 AN32 AN32 A14 -- AN33 P AN33 eQADC A and B shared analog input I AE VDDA_B0 AN33 AN33 B15 -- AN34 P AN34 eQADC A and B shared analog input I AE VDDA_B0 AN34 AN34 C15 -- AN35 P AN35 eQADC A and B shared analog input I AE VDDA_B0 AN35 AN35 D15 -- AN36 P AN36 eQADC A and B shared analog input I AE VDDA_B1 AN36 AN36 A15 -- AN37 P AN37 eQADC A and B shared analog input I AE VDDA_B0 AN37 AN37 C16 -- AN38 P AN38 eQADC A and B shared analog input I AE VDDA_B0 AN38 AN38 C17 -- AN39 P AN39 eQADC A and B shared analog input I AE VDDA_B0 AN39 AN39 D16 -- ANB0 P ANB0 eQADC B analog input I AE/updown VDDA_B0 ANB0 ANB0 C18 -- ANB1 P ANB1 eQADC B analog input I AE/updown VDDA_B0 ANB1 ANB1 D17 -- ANB2 P ANB2 eQADC B analog input I AE/updown VDDA_B0 ANB2 ANB2 D18 Signal Name2 P/A/G3 Pad Type5 PXR40 Microcontroller Data Sheet, Rev. 1 Direction GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) Function4 Function Summary State after RESET8 Package Location (416) 35 Voltage6 State during RESET7 -- ANB3 P ANB3 eQADC B analog input I AE/updown VDDA_B0 ANB3 ANB3 D19 -- ANB4 P ANB4 eQADC B analog input I AE/updown VDDA_B0 ANB4 ANB4 C19 -- ANB5 P ANB5 eQADC B analog input I AE/updown VDDA_B0 ANB5 ANB5 C20 -- ANB6 P ANB6 eQADC B analog input I AE/updown VDDA_B0 ANB6 ANB6 B19 -- ANB7 P ANB7 eQADC B analog input I AE/updown VDDA_B0 ANB7 ANB7 A20 -- ANB8 P ANB8 eQADC B analog input I AE VDDA_B0 ANB8 ANB8 B20 -- ANB9 P ANB9 eQADC B analog input I AE VDDA_B0 ANB9 ANB9 D20 -- ANB10 P ANB10 eQADC B analog input I AE VDDA_B0 ANB10 ANB10 B21 -- ANB11 P ANB11 eQADC B analog input I AE VDDA_B0 ANB11 ANB11 A21 -- ANB12 P ANB12 eQADC B analog input I AE VDDA_B0 ANB12 ANB12 C21 -- ANB13 P ANB13 eQADC B analog input I AE VDDA_B0 ANB13 ANB13 D21 -- ANB14 P ANB14 eQADC B analog input I AE VDDA_B0 ANB14 ANB14 A22 -- ANB15 P ANB15 eQADC B analog input I AE VDDA_B0 ANB15 ANB15 B22 -- ANB16 P ANB16 eQADC B analog input I AE VDDA_B0 ANB16 ANB16 C22 -- ANB17 P ANB17 eQADC B analog input I AE VDDA_B0 ANB17 ANB17 A23 -- ANB18 P ANB18 eQADC B analog input I AE VDDA_B0 ANB18 ANB18 B23 -- ANB19 P ANB19 eQADC B analog input I AE VDDA_B0 ANB19 ANB19 C23 -- ANB20 P ANB20 eQADC B analog input I AE VDDA_B0 ANB20 ANB20 D22 -- ANB21 P ANB21 eQADC B analog input I AE VDDA_B0 ANB21 ANB21 A24 -- ANB22 P ANB22 eQADC B analog input I AE VDDA_B0 ANB22 ANB22 B24 -- ANB23 P ANB23 eQADC B analog input I AE VDDA_B0 ANB23 ANB23 A25 -- VRH_A P VRH_A ADC A Voltage reference high I VDDINT VRH_A VRH_A VRH_A A12 Signal Name2 P/A/G3 Pad Type5 PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor Direction GPIO/PCR1 36 Table 2. Signal Properties and Muxing Summary (continued) Function4 Function Summary State after RESET8 Package Location (416) Voltage6 State during RESET7 -- VRL_A P VRL_A ADC A Voltage reference low I VSSINT VRL_A VRL_A VRL_A A11 -- VRH_B P VRH_B ADC B Voltage reference high I VDDINT VRH_B VRH_B VRH_B A19 -- VRL_B P VRL_B ADC B Voltage reference low I VSSINT VRL_B VRL_B VRL_B A18 -- REFBYPCB P REFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B18 -- REFBYPCA P REFBYPCA ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA REFBYPCA B11 -- VDDA_A0 P VDDA_A Internal logic supply input I VDDE VDDA_A0 VDDA_A0 VDDA_A0 A9 -- VDDA_A1 P VDDA_A Internal logic supply input I VDDE VDDA_A1 VDDA_A1 VDDA_A1 B9 -- REFBYPCA1 P REFBYPCA1 ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA1 REFBYPCA1 A10 -- VSSA_A1 P VSSA_A Ground I VSSE VSSA_A1 VSSA_A1 VSSA_A1 B10 -- VDDA_B0 P VDDA_B Internal logic supply input I VDDE VDDA_B0 VDDA_B0 VDDA_B0 A16 -- VDDA_B1 P VDDA_B Internal logic supply input I VDDE VDDA_B1 VDDA_B1 VDDA_B1 B16 -- VSSA_B0 P VSSA_B Ground I VSSE VSSA_B0 VSSA_B0 VSSA_B0 B17 -- REFBYPCB1 P REFBYPCB1 ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB1 REFBYPCB1 A17 FS VDDE2 --/Up (-/- for Rev.1 of the device) --/Up (-/- for Rev.1 of the device) AD4 FS VDDE2 --/Up (-/- for Rev.1 of the device) --/Up (-/- for Rev.1 of the device) AE3 Signal Name2 P/A/G3 Pad Type5 PXR40 Microcontroller Data Sheet, Rev. 1 Direction GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) Function4 Function Summary State after RESET8 Package Location (416) FlexRay 248 249 FR_A_TX_ GPIO248 FR_A_RX_ GPIO249 P FR_A_TX FlexRay A transfer O A1 -- -- -- A2 -- -- -- G GPIO248 GPIO I/O P FR_A_RX FlexRay A receive A1 -- -- -- A2 -- -- -- G GPIO249 GPIO I/O I 37 253 FR_B_RX_ GPIO252 FR_B_TX_EN_ GPIO253 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 252 FR_B_TX_ GPIO251 Function Summary Pad Type5 251 FR_A_TX_EN_ GPIO250 Function4 Direction 250 Signal Name2 P/A/G3 GPIO/PCR1 38 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O FS VDDE2 --/Up (-/- for Rev.1 of the device) --/Up (-/- for Rev.1 of the device) AF3 FS VDDE2 --/Up (-/- for Rev.1 of the device) --/Up (-/- for Rev.1 of the device) AD5 FS VDDE2 --/Up (-/- for Rev.1 of the device) --/Up (-/- for Rev.1 of the device) AE4 FS VDDE2 --/Up (-/- for Rev.1 of the device) --/Up (-/- for Rev.1 of the device) AF4 MH VDDEH4 --/Up --/Up AF19 MH VDDEH4 --/Up --/Up AE19 P FR_A_TX_EN FlexRay A transfer enable A1 -- -- -- A2 -- -- -- G GPIO250 GPIO I/O P FR_B_TX FlexRay B transfer O A1 -- -- -- A2 -- -- -- G GPIO251 GPIO I/O P FR_B_RX FlexRay B receive A1 -- -- -- A2 -- -- -- G GPIO252 GPIO I/O P FR_B_TX_EN FlexRay B transfer enable O A1 -- -- -- A2 -- -- -- G GPIO253 GPIO I/O I State after RESET8 Package Location (416) FlexCAN 83 Freescale Semiconductor 84 CNTXA_TXDA_ GPIO83 CNRXA_RXDA_ GPIO84 P CNTXA FlexCAN A transmit O A1 TXDA eSCI A transmit O A2 -- -- -- G GPIO83 GPIO I/O P CNRXA FlexCAN A receive I A1 RXDA eSCI A receive I A2 -- -- -- G GPIO84 GPIO I/O 88 246 247 CNTXC_PCSD3_ GPIO87 CNRXC_PCSD4_ GPIO88 CNTXD_ GPIO246 CNRXD_ GPIO247 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 87 CNRXB_PCSC4_ GPIO86 Function Summary Pad Type5 86 CNTXB_PCSC3_ GPIO85 Function4 Direction 85 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O MH VDDEH4 --/Up --/Up AD19 MH VDDEH4 --/Up --/Up AC19 MH VDDEH4 --/Up --/Up AF20 MH VDDEH4 --/Up --/Up AE20 MH VDDEH4 --/Up --/Up AD20 MH VDDEH4 --/Up --/Up AC20 P CNTXB FlexCAN B transmit A1 PCSC3 DSPI C peripheral chip select O A2 -- -- -- G GPIO85 GPIO I/O P CNRXB FlexCAN B receive I A1 PCSC4 DSPI C peripheral chip select O A2 -- -- -- G GPIO86 GPIO I/O P CNTXC FlexCAN C transmit O A1 PCSD3 DSPI D peripheral chip select O A2 -- -- -- G GPIO87 GPIO I/O P CNRXC FlexCAN C receive I A1 PCSD4 DSPI D peripheral chip select O A2 -- -- -- G GPIO88 GPIO I/O P CNTXD FlexCAN D transmit O A1 -- -- -- A2 -- -- -- G GPIO246 GPIO I/O P CNRXD FlexCAN D receive A1 -- -- -- A2 -- -- -- G GPIO247 GPIO I/O I 39 eSCI State after RESET8 Package Location (416) 92 244 Freescale Semiconductor 245 TXDB_PCSD1_ GPIO91 RXDB_PCSD5_ GPIO92 TXDC_ETRIG0_ GPIO244 RXDC_ GPIO245 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 91 RXDA _ GPIO90 Function Summary Pad Type5 90 TXDA_ GPIO89 Function4 Direction 89 Signal Name2 P/A/G3 GPIO/PCR1 40 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O MH VDDEH1 --/Up --/Up M2 MH VDDEH1 --/Up --/Up M3 MH VDDEH1 --/Up --/Up P1 MH VDDEH1 --/Up --/Up N1 MH VDDEH4 --/Up --/Up AF23 MH VDDEH5 --/Up --/Up AD22 P TXDA eSCI A transmit A1 -- -- -- A2 -- -- -- G GPIO89 GPIO I/O P RXDA eSCI A receive A1 -- -- -- A2 -- -- -- G GPIO90 GPIO I P TXDB eSCI B transmit O A1 PCSD1 DSPI D peripheral chip select O A2 -- -- -- G GPIO91 GPIO I/O P RXDB eSCI B receive I A1 PCSD5 DSPI D peripheral chip select O A2 -- -- -- G GPIO92 GPIO I/O P TXDC eSCI C transmit O A1 ETRIG0 eQADC trigger input I A2 -- -- -- G GPIO244 GPIO I/O P RXDC eSCI C receive A1 -- -- -- A2 -- -- -- G GPIO245 GPIO I/O I I State after RESET8 Package Location (416) Voltage6 Function Summary Pad Type5 Function4 Direction Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH3 --/Up --/Up AD8 MH VDDEH3 --/Up --/Up AF7 MH VDDEH3 --/Up --/Up AD7 MH VDDEH3 --/Up --/Up AE6 MH VDDEH3 --/Up --/Up AC6 MH VDDEH3 --/Up --/Up AC7 State after RESET8 Package Location (416) DSPI 93 PXR40 Microcontroller Data Sheet, Rev. 1 94 95 96 97 98 SCKA_PCSC1_ GPIO93 SINA_PCSC2_ GPIO94 SOUTA_PCSC5_ GPIO95 PCSA0_PCSD2_ GPIO96 PCSA1_ GPIO97 PCSA2_ GPIO98 41 P SCKA DSPI A clock A1 PCSC1 DSPI C peripheral chip select O A2 -- -- -- G GPIO93 GPIO I/O P SINA DSPI A data input I A1 PCSC2 DSPI C peripheral chip select O A2 -- -- -- G GPIO94 GPIO I/O P SOUTA DSPI A data output O A1 PCSC5 DSPI C peripheral chip select O A2 -- -- -- G GPIO95 GPIO I/O P PCSA0 DSPI A peripheral chip select I/O A1 PCSD2 DSPI D peripheral chip select O A2 -- -- -- G GPIO96 GPIO I/O P PCSA1 DSPI A peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO97 GPIO I/O P PCSA2 DSPI A peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO98 GPIO I/O 102 103 Freescale Semiconductor 104 PCSA5_ETRIG1_ GPIO101 SCKB_ GPIO102 SINB_ GPIO103 SOUTB_ GPIO104 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 101 PCSA4_ GPIO100 Function Summary Pad Type5 100 PCSA3_ GPIO99 Function4 Direction 99 Signal Name2 P/A/G3 GPIO/PCR1 42 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O MH VDDEH3 --/Up --/Up AE7 MH VDDEH3 --/Up --/Up AE5 MH VDDEH3 --/Up --/Up AD6 MH VDDEH3 --/Up --/Up AE8 MH VDDEH3 --/Up --/Up AE9 MH VDDEH3 --/Up --/Up AF9 P PCSA3 DSPI A peripheral chip select A1 -- -- -- A2 -- -- -- G GPIO99 GPIO I/O P PCSA4 DSPI A peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO100 GPIO I/O P PCSA5 DSPI A peripheral chip select O A1 ETRIG1 eQADC trigger input I A2 -- -- -- G GPIO101 GPIO I/O P SCKB DSPI B clock I/O A1 -- -- -- A2 -- -- -- G GPIO102 GPIO I/O P SINB DSPI B data input A1 -- -- -- A2 -- -- -- G GPIO103 GPIO I/O P SOUTB DSPI B data output O A1 -- -- -- A2 -- -- -- G GPIO104 GPIO I/O I State after RESET8 Package Location (416) 108 109 110 PCSB2_SOUTC_ GPIO107 PCSB3_SINC_ GPIO108 PCSB4_SCKC_ GPIO109 PCSB5_PCSC0_ GPIO110 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 107 PCSB1_PCSD0_ GPIO106 Function Summary Pad Type5 106 PCSB0_PCSD2_ GPIO105 Function4 Direction 105 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH VDDEH3 --/Up --/Up AD9 MH VDDEH3 --/Up --/Up AC9 MH VDDEH3 --/Up --/Up AF8 MH VDDEH3 --/Up --/Up AD10 MH VDDEH3 --/Up --/Up AC8 MH VDDEH3 --/Up --/Up AF6 P PCSB0 DSPI B peripheral chip select A1 PCSD2 DSPI D peripheral chip select O A2 -- -- -- G GPIO105 GPIO I/O P PCSB1 DSPI B peripheral chip select O A1 PCSD0 DSPI D peripheral chip select I/O A2 -- -- -- G GPIO106 GPIO I/O P PCSB2 DSPI B peripheral chip select O A1 SOUTC DSPI C data output O A2 -- -- -- G GPIO107 GPIO I/O P PCSB3 DSPI B peripheral chip select O A1 SINC DSPI C data input I A2 -- -- -- G GPIO108 GPIO I/O P PCSB4 DSPI B peripheral chip select O A1 SCKC DSPI C clock I/O A2 -- -- -- G GPIO109 GPIO I/O P PCSB5 DSPI B peripheral chip select O A1 PCSC0 DSPI C peripheral chip select I/O A2 -- -- -- G GPIO110 GPIO I/O State after RESET8 Package Location (416) 43 238 239 SOUTC_SOUT_C_LVDSP_ GPIO237 PCSC0_SOUT_C_LVDSM_ GPIO238 Freescale Semiconductor PCSC1_ GPIO239 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 237 SINC_SCK_C_LVDSM_ GPIO236 Function Summary Pad Type5 236 SCKC_SCK_C_LVDSP_ GPIO235 Function4 Direction 235 Signal Name2 P/A/G3 GPIO/PCR1 44 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I/O MH+ LVDS VDDEH4 --/Up --/Up AD21 MH+ LVDS VDDEH4 --/Up --/Up AE22 MH+ LVDS VDDEH4 --/Up --/Up AF21 MH+ LVDS VDDEH4 --/Up --/Up AE21 MH VDDEH4 --/Up --/Up AC22 P SCKC DSPI C clock A1 SCK_C_LVDSP LVDS+ downstream signal positive output clock O A2 -- -- -- G GPIO235 GPIO I/O P SINC DSPI C data input I A1 SCK_C_LVDSM LVDS- downstream signal negative output clock O A2 -- -- -- G GPIO236 GPIO I/O P SOUTC DSPI C data output O A1 SOUT_C_LVDSP LVDS+ downstream signal positive output data O A2 -- -- -- G GPIO237 GPIO I/O P PCSC0 DSPI C peripheral chip select I/O A1 SOUT_C_LVDSM LVDS- downstream signal negative output data O A2 -- -- -- G GPIO238 GPIO I/O P PCSC1 DSPI C peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO239 GPIO I/O State after RESET8 Package Location (416) 243 PCSC4_GPIO242 PCSC5_GPIO243 Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 242 PCSC3_GPIO241 Function Summary Pad Type5 241 PCSC2_GPIO240 Function4 Direction 240 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O MH VDDEH5 --/Up --/Up AE23 MH VDDEH5 --/Up --/Up AD23 MH VDDEH5 --/Up --/Up AF24 MH VDDEH5 --/Up --/Up AE24 P PCSC2 DSPI C peripheral chip select A1 -- -- -- A2 -- -- -- G GPIO240 GPIO I/O P PCSC3 DSPI C peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO241 GPIO I/O P PCSC4 DSPI C peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO242 GPIO I/O P PCSC5 DSPI C peripheral chip select O A1 -- -- -- A2 -- -- -- G GPIO243 GPIO I/O State after RESET8 Package Location (416) Reset and Clocks -- RESET P RESET External reset input I MH VDDEH1 RESET/Up RESET/Up R2 230 RSTOUT P RSTOUT External reset output O MH VDDEH1 RSTOUT/Low RSTOUT/ High A3 212 BOOTCFG1_IRQ3_ GPIO212 P BOOTCFG1 Boot configuration I MH VDDEH1 Input/Down N2 A1 IRQ3 External interrupt request I BOOTCFG/ Down A2 -- -- -- G GPIO212 GPIO I/O 45 PLLCFG1_IRQ5_ GPIO209 WKPCFG Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 209 PLLCFG0_IRQ4_ GPIO208 P Function Summary Pad Type5 208 WKPCFG_NMI_ GPIO213 Function4 Direction 213 Signal Name2 P/A/G3 GPIO/PCR1 46 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 I MH VDDEH1 WKPCFG/Up Input/Up N3 MH VDDEH1 PLLCFG/Up Input/Up R3 MH VDDEH1 PLLCFG/Up Input/Up (for Rev2 of the device: --/Up) P2 Weak pull configuration input core11 A1 NMI Critical interrupt to A2 -- -- G GPIO213 GPIO I P PLLCFG0 FMPLL mode configuration input I A1 IRQ4 External interrupt request I A2 -- -- -- G GPIO208 GPIO I/O P PLLCFG1 FMPLL mode configuration input I A1 IRQ5 External interrupt request I A2 SOUTD DSPI D data output O G GPIO209 GPIO I/O State after RESET8 Package Location (416) I -- -- PLLCFG2 P PLLCFG2 FMPLL mode configuration input I MH VDDEH1 PLLCFG/ Down PLLCFG/ Down P3 -- XTAL P XTAL Crystal oscillator output O AE VDD33 XTAL XTAL AC26 -- EXTAL P EXTAL Crystal oscillator input I AE VDD33 EXTAL EXTAL AB26 ENGCLK P ENGCLK EBI engineering clock output Note: EXTCLK (External clock input) selected through SIU register) O F VDDE2 ENGCLK/ Enabled ENGCLK/ Enabled AD1 214 JTAG and Nexus (see footnote12 about resets) Freescale Semiconductor -- EVTI -13 13 227 EVTO (the BAM uses this pin to select if auto baud rate is on or off) - 219 MCKO -13 EVTI Nexus event in I F VDDE2 --/Up EVTI/Up T4 EVTO Nexus event out O F VDDE2 ABS/Up EVTO/HI U1 MCKO Nexus message clock out O F VDDE2 O/Low Disabled14 T2 223 75 76 MDO2_GPIO222 (GPIO function on this pin is only available on Rev.2 of the device) MDO3_GPIO223 (GPIO function on this pin is only available on Rev.2 of the device) MDO4_GPIO75 (GPIO function on this pin is only available on Rev.2 of the device) MDO5_GPIO76 (GPIO function on this pin is only available on Rev.2 of the device) Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 222 MDO1_GPIO221 (GPIO function on this pin is only available on Rev.2 of the device) Function Summary Pad Type5 221 MDO0_GPIO220 (GPIO function on this pin is only available on Rev.2 of the device) Function4 Direction 220 Signal Name2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O F VDDE2 O/Low MDO0/Low U3 F VDDE2 O/Low --/Down U4 F VDDE2 O/Low --/Down V1 F VDDE2 O/Low --/Down V2 F VDDE2 O/Low --/Down V3 F VDDE2 O/Low --/Down V4 -13 MDO015 Nexus message data out A1 -- -- -- A2 -- -- -- G GPIO220 GPIO I/O -13 MDO115 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO221 GPIO I/O -13 MDO215 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO222 GPIO I/O -13 MDO315 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO223 GPIO I/O -13 MDO415 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO75 GPIO I/O -13 MDO515 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO76 GPIO I/O State after RESET8 Package Location (416) 47 80 81 Freescale Semiconductor 82 MDO8_GPIO79 (GPIO function on this pin is only available on Rev.2 of the device) MDO9_GPIO80 (GPIO function on this pin is only available on Rev.2 of the device) MDO10_GPIO81 (GPIO function on this pin is only available on Rev.2 of the device) MDO11_GPIO82 (GPIO function on this pin is only available on Rev.2 of the device) Voltage6 PXR40 Microcontroller Data Sheet, Rev. 1 79 MDO7_GPIO78 (GPIO function on this pin is only available on Rev.2 of the device) Function Summary Pad Type5 78 MDO6_GPIO77 (GPIO function on this pin is only available on Rev.2 of the device) Function4 Direction 77 Signal Name2 P/A/G3 GPIO/PCR1 48 Table 2. Signal Properties and Muxing Summary (continued) State during RESET7 O F VDDE2 O/Low --/Down W1 F VDDE2 O/Low --/Down W2 F VDDE2 O/Low --/Down W3 F VDDE2 O/Low --/Down Y1 F VDDE2 O/Low --/Down Y2 F VDDE2 O/Low --/Down Y3 -13 MDO615 Nexus message data out A1 -- -- -- A2 -- -- -- G GPIO77 GPIO I/O -13 MDO715 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO78 GPIO I/O -13 MDO815 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO79 GPIO I/O -13 MDO915 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO80 GPIO I/O -13 MDO1015 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO81 GPIO I/O -13 MDO1115 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO82 GPIO I/O State after RESET8 Package Location (416) Pad Type5 Voltage6 O F VDDE2 O/Low --/Down AA1 F VDDE2 O/Low --/Down AA2 F VDDE2 O/Low --/Down AA3 F VDDE2 O/Low --/Down Y4 O F VDDE2 O/Low MSEO/HI U2 Nexus message start/end out O F VDDE2 O/Low MSEO/HI T3 RDY Nexus ready output O F VDDE2 O/Low RDY/HI R4 TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down AB2 -13 TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up AC2 TDO -13 TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up AB1 TMS - 13 TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up AB3 - 13 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down R1 P/A/G3 State during RESET7 Signal Name2 Function4 Function Summary -13 MDO1215 Nexus message data out A1 -- -- -- A2 -- -- -- G GPIO231 GPIO I/O -13 MDO1315 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO232 GPIO I/O -13 MDO1415 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO233 GPIO I/O -13 MDO1515 Nexus message data out O A1 -- -- -- A2 -- -- -- G GPIO234 GPIO I/O MSEO0 -13 MSEO015 Nexus message start/end out MSEO1 - 13 MSEO115 RDY -13 -- TCK - 13 -- TDI 231 232 PXR40 Microcontroller Data Sheet, Rev. 1 Direction GPIO/PCR1 Freescale Semiconductor Table 2. Signal Properties and Muxing Summary (continued) 233 234 224 225 226 228 -- -- MDO12_GPIO231 MDO13_GPIO232 MDO14_GPIO233 MDO15_GPIO234 JCOMP State after RESET8 Package Location (416) 49 2 3 4 5 6 Freescale Semiconductor 7 8 Voltage6 State during RESET7 -- TEST -- TEST Test mode select (not for customer use) I F VDDEH1 TEST/Down TEST/Down B4 -- VDDSYN -- VDDSYN Clock synthesizer power input I VDDE VDDSYN VDDSYN VDDSYN AD26 -- VSSSYN -- VSSSYN Clock synthesizer ground input I VSSE VDDSYN VSSSYN VSSSYN AA26 -- VSTBY -- VSTBY SRAM standby power input I VHV VDDEH1 VSTBY VSTBY M4 -- REGSEL -- REGSEL Selects regulator mode (Linear/Switch mode) I AE VDDREG REGSEL REGSEL W23 -- REGCTL -- REGCTL Regulator controller output to base/gate of power transistor O AE VDDREG REGCTL REGCTL Y26 -- VSSFL -- VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL AB25 -- VDDREG -- VDDREG Source voltage for on-chip regulators and Low voltage detect circuits I VDDINT VDDREG VDDREG VDDREG AA25 Signal Name2 P/A/G3 Pad Type5 PXR40 Microcontroller Data Sheet, Rev. 1 1 Direction GPIO/PCR1 50 Table 2. Signal Properties and Muxing Summary (continued) Function4 Function Summary State after RESET8 Package Location (416) The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not have GPIO functionality, this number is the PCR number. The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type. P/A/G stands for Primary/Alternate/GPIO. This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO. Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are designated in the PA field of the SIU_PCRn registers except where explicitly noted. MH = High voltage, medium speed F = Fast speed FS = Fast speed with slew AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad) VHV = Very high voltage VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3-5.0 V (+5%/-10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8-3.3 V (10%) power supply. The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column is: O - output, I - input, Up - weak pull up enabled, Down - weak pulldown enabled, Low - output driven low, High - output driven high, ABS -- Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled. The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 9 Freescale Semiconductor This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C. During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device. 11 NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers. 12 Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO are also dependent on trace (RPM or FPM) being enabled. 13 The Nexus pins don't have a "primary" function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values have no effect on the function of these pins once enabled. 14 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register). 15 Do not connect pin directly to a power supply or ground. 10 PXR40 Microcontroller Data Sheet, Rev. 1 51 Electrical characteristics 5 Electrical characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the PXR40. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. 5.1 Maximum ratings Table 3. Absolute maximum ratings1 Spec Characteristic Symbol Min Max Unit VDD -0.3 2.0 2 V VSTBY -0.3 6.4 3,4 V VDDSYN -0.3 5.3 4,5 V 1 1.2 V Core Supply Voltage 2 SRAM Standby Voltage 3 Clock Synthesizer Voltage 4 I/O Supply Voltage (I/O buffers and predrivers) VDD33 -0.3 5.3 4,5 V 5 Analog Supply Voltage (reference to VSSA6) VDDA7 -0.3 6.4 3,4 V 6 I/O Supply Voltage (fast I/O pads) VDDE -0.3 5.3 4,5 V 3,4 V 7 I/O Supply Voltage (medium I/O pads) VDDEH -0.3 6.4 8 Voltage Regulator Input Supply Voltage VDDREG -0.3 6.4 3,4 V 9 Analog Reference High Voltage (reference to VRL8) VRH9 -0.3 6.4 3,4 V 10 VSS to VSSA8 Differential Voltage VSS - VSSA -0.1 0.1 V 11 VREF Differential Voltage VRH - VRL -0.3 6.4 3,4 V 12 VRL to VSSA Differential Voltage VRL - VSSA -0.3 0.3 V 13 VDD33 to VDDSYN Differential Voltage VDD33 - VDDSYN -0.1 0.1 V 14 VSSSYN to VSS Differential Voltage VSSSYN - VSS -0.1 0.1 V 15 Maximum Digital Input Current 10 (per pin, applies to all digital pins) IMAXD -3 11 3 11 mA 16 Maximum Analog Input Current 12 (per pin, applies to all analog pins) IMAXA -37 3 7,11 mA 17 Maximum Operating Temperature Range 13 - Die Junction Temperature TJ -40.0 150.0 oC 18 Storage Temperature Range Tstg -55.0 150.0 oC 19 Maximum Solder Temperature 14 Pb-free package SnPb package Tsdr -- -- 260.0 245.0 Moisture Sensitivity Level 15 MSL -- 3 20 o C -- PXR40 Microcontroller Data Sheet, Rev. 1 52 Freescale Semiconductor Electrical characteristics 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 2.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining. 3 6.4 V for 10 hours cumulative time, 5.25 V +10% for time remaining. 4 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 5.3 V for 10 hours cumulative time, 3.60 V +10% for time remaining. 6 PXR40 has two analog power supply pins on the pinout: VDDA_A and VDDA_B. 7 PXR40 has two analog ground supply pins on the pinout: VSSA_A and VSSA_B. 8 PXR40 has two analog low reference voltage pins on the pinout: VRL_A and VRL_B. 9 PXR40 has two analog high reference voltage pins on the pinout: VRH_A and VRH_B. 10 Total injection current for all pins must not exceed 25 mA at maximum operating voltage. 11 Injection current of 5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under this stress condition. 12 Total injection current for all analog input pins must not exceed 15 mA. 13 Lifetime operation at these specification limits is not guaranteed. 14 Solder profile per CDF-AEC-Q100. 15 Moisture sensitivity per JEDEC test method A112. 5.2 Thermal characteristics Table 4. Thermal characteristics, 416-pin TEPBGA package1 Characteristic Symbol Value Unit RJA 24 C/W RJA 18 C/W Junction to Ambient (@200 ft./min., Single layer board) RJMA 19 C/W Junction to Ambient (@200 ft./min., Four layer board 2s2p) RJMA 14 C/W RJB 9 C/W RJC 6 C/W JT 2 C/W Junction to Ambient 2,3 Natural Convection (Single layer board) Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) Junction to Board 5 Junction to Case 6 7 Junction to Package Top Natural Convection 1 2 3 4 5 6 7 Thermal characteristics are targets based on simulation that are subject to change per device characterization. This data is PRELIMINARY based on similar package used on other devices. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 53 Electrical characteristics 5.2.1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA * PD) Eqn. 1 where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA Eqn. 2 where: RJA = junction to ambient thermal resistance (oC/W) RJC = junction to case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) Eqn. 3 where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 3081 Zanker Road PXR40 Microcontroller Data Sheet, Rev. 1 54 Freescale Semiconductor Electrical characteristics San Jose, CA 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. * * * C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 5.3 EMI (Electromagnetic Interference) characteristics To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for "radiated emissions." The following tables list the values of the device's radiated emissions operating behaviors. Table 5. EMC radiated emissions operating behaviors: 416 BGA Symbol VRE_TEM VRE_TEM 1 2 3 4 5 Description Radiated emissions, electric field and magnetic field Radiated emissions, electric field and magnetic field fOSC fSYS Frequency band (MHz) Level (max.) VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 C 416 BGA EBI off CLK on FM off 40 MHz crystal 264 MHz (fEBI_CAL = 66 MHz) 0.15-50 26 50-150 30 150-500 34 500-1000 30 IEC and SAE level VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 C 416 BGA EBI off CLK off FM on4 40 MHz crystal 264 MHz (fEBI_CAL = 66 MHz) Conditions Unit Notes dBV 1 I2 -- 1, 3 0.15-50 24 dBV 1 50-150 25 150-500 25 500-1000 21 IEC and SAE level K5 -- 1,3 Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits--TEM/Wideband TEM (GTEM) Cell Method. I = 36 dBV Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits--TEM/Wideband TEM (GTEM) Cell Method. "FM on" = FM depth of 2% K = 30 dBV PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 55 Electrical characteristics 5.4 ESD characteristics Table 6. ESD ratings1,2 Spec Characteristic Symbol Value Unit 1 ESD for Human Body Model (HBM) VHBM 2000 V 2 ESD for Charged Device Model (CDM) VCDM 750 (corners) 500 (other) V 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 5.5 PMC/POR/LVI electrical specifications Note: For ADC internal resource measurements, see Table 18 in Section 5.9.1 ADC internal resource measurements. Table 7. PMC operating conditions Name Parameter Condition Min Typ Max Unit Note VDDREG Supply voltage VDDREG 5V nominal LDO5V / SMPS5V mode 4.5 5 5.5 V 1 VDDREG Supply voltage VDDREG 3V nominal LDO3V mode 3.0 3.3 3.6 V 1 VDD33 Supply voltage VDDSYN / VDD33 3.3V nominal LDO3V mode 3.0 3.3 3.6 V 2 VDD Supply voltage VDD 1.2V nominal -- 1.14 1.2 1.32 V 3 1 Voltage should be higher than maximum VLVDREG to avoid LVD event Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum VLVD33 to avoid LVD event 3 Voltage should be higher than maximum V LVD12 to avoid LVD event 2 NOTE In the following table, "untrimmed" means "at reset" and "trimmed" means "after reset". Table 8. PMC electrical specifications ID Name Parameter 1 VBG Nominal bandgap reference voltage 1a -- Untrimmed bandgap reference voltage 2 VDD12OUT Nominal VRC regulated 1.2V output VDD Min Typ Max Unit 0.608 0.620 0.632 V VBG - 5% VBG VBG + 5% V -- 1.2 -- V PXR40 Microcontroller Data Sheet, Rev. 1 56 Freescale Semiconductor Electrical characteristics Table 8. PMC electrical specifications (continued) ID Name Parameter Min Typ Max Unit 2a -- Untrimmed VRC 1.2V output variation before band gap trim (unloaded) Note: Voltage should be higher than maximum VLVD12 to avoid LVD event VDD12OUT - 8% VDD12OUT VDD12OUT + 17% V 2b -- Trimmed VRC 1.2V output variation after band gap trim (REGCTL load max. 20mA, VDD load max. 1A)1 VDD12OUT - 5% VDD12OUT VDD12OUT + 10% V 2c VSTEPV12 Trimming step VDD12OUT -- 10 -- mV 3 VPORC POR rising VDD 1.2V -- 0.7 -- V 3a -- POR VDD 1.2V variation VPORC - 30% VPORC VPORC + 30% 3b -- POR 1.2V hysteresis -- 75 -- mV 4 VLVD12 Nominal rising LVD 1.2V Note: ~VDD12OUT x 0.87 -- 1.100 -- V 4a -- Untrimmed LVD 1.2V variation before band gap trim Note: Rising VDD VLVD12 - 6% VLVD12 VLVD12 + 6% V 4b -- Trimmed LVD 1.2V variation after band gap trim Rising VDD VLVD12 - 3% VLVD12 VLVD12 + 3% V 4c -- LVD 1.2V Hysteresis 15 20 25 mV 4d VLVDSTEP12 Trimming step LVD 1.2V -- 10 -- mV 5 IREGCTL VRC DC current output on REGCTL -- -- 20 mA 6 -- Voltage regulator 1.2V current consumption VDDREG -- 3 -- mA 7 VDD33OUT Nominal VREG 3.3V output -- 3.3 -- V 7a -- Untrimmed VREG 3.3V output variation before band gap trim (unloaded) Note: Rising VDDSYN VDD33OUT - 6% VDD33OUT VDD33OUT + 10% V 7b -- Trimmed VREG 3.3V output variation after band gap trim (max. load 80mA) VDD33OUT - 5% VDD33OUT VDD33OUT + 10% V 7c VSTEPV33 Trimming step VDDSYN -- 30 -- mV 8 VLVD33 Nominal rising LVD 3.3V Note: ~VDD33OUT x 0.872 -- 2.950 -- V 8a -- Untrimmed LVD 3.3V variation before band gap trim Note: Rising VDDSYN VLVD33 - 5% VLVD33 VLVD33 + 5% V 8b -- Trimmed LVD 3.3V variation after bad gap trim Note: Rising VDDSYN VLVD33 - 3% VLVD33 VLVD33 + 3% V 8c -- LVD 3.3V Hysteresis -- 30 -- mV 8d VLVDSTEP33 Trimming step LVD 3.3V -- 30 -- mV PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 57 Electrical characteristics Table 8. PMC electrical specifications (continued) ID Name Parameter Min Typ Max Unit 9 IDD33 VREG = 4.5 V, max DC output current VREG = 4.25 V, max DC output current, crank condition Note: Max current supplied by VDDSYN that does not cause it to drop below VLVD33 -- -- -- -- 80 40 mA mA 10 -- Voltage regulator 3.3V current consumption VDDREG Note: Except IDD33 -- 2 -- mA 11 VPORREG POR rising on VDDREG -- 2.00 -- V VPORREG + 30% V 11a -- POR VDDREG variation 11b -- POR VDDREG hysteresis -- 250 -- mV 12 Nominal rising LVD VDDREG (LDO3V / LDO5V mode) -- 2.950 -- V VLVDREG VPORREG - 30% VPORREG 12a -- Untrimmed LVD VDDREG variation before band gap trim Note: Rising VDDREG VLVDREG - 5% VLVDREG VLVDREG + 5% V 12b -- Trimmed LVD VDDREG variation after band gap trim Note: Rising VDDREG VLVDREG - 3% VLVDREG VLVDREG + 3% V 12c -- LVD VDDREG Hysteresis (LDO3V / LDO5V mode) -- 30 -- mV 12d VLVDSTEPREG Trimming step LVD VDDREG (LDO3V / LDO5V mode) -- 30 -- mV 13 -- 4.360 -- V VLVDREG Nominal rising LVD VDDREG (SMPS5V mode) 13a -- Untrimmed LVD VDDREG variation before band gap trim Note: Rising VDDREG VLVDREG - 5% VLVDREG VLVDREG + 5% V 13b -- Trimmed LVD VDDREG variation after band gap trim Note: Rising VDDREG VLVDREG - 3% VLVDREG VLVDREG + 3% V 13c -- LVD VDDREG Hysteresis (SMPS5V mode) -- 50 -- mV 13d VLVDSTEPREG Trimming step LVD VDDREG (SMPS5V mode) -- 50 -- mV 14 -- 4.60 -- V VLVDA Nominal rising LVD VDDA 14a -- Untrimmed LVD VDDA variation before band gap trim VLVDA - 5% VLVDA VLVDA + 5% V 14b -- Trimmed LVD VDDA variation after band gap trim VLVDA - 3% VLVDA VLVDA + 3% V 14c -- LVD VDDA Hysteresis -- 150 -- mV PXR40 Microcontroller Data Sheet, Rev. 1 58 Freescale Semiconductor Electrical characteristics Table 8. PMC electrical specifications (continued) ID Name Parameter Min Typ Max Unit 14d VLVDASTEP Trimming step LVD VDDA -- 20 -- mV 15 -- SMPS regulator output resistance Note: Pullup to VDDREG when high, pulldown to VSSREG when low. -- 15 25 Ohm 16 -- SMPS regulator clock frequency (after reset) 1.0 1.5 2.4 MHz -- 1.32 1.4 V -- 1.0 -- A -- -- 0.1 V 17 -- SMPS regulator overshoot at start-up 18 -- SMPS maximum output current 19 2 2 -- Voltage variation on current step (20% to 80% of maximum current with 4 sec constant time) 1 VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 A. When using the recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core voltage is up to 1A. 2 Parameter cannot be tested; this value is based on simulation and characterization. 5.6 Power up/down sequencing There is no power sequencing required among power sources during power up and power down in order to operate within specification as long as the following two rules are met: * * When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG. When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the internal 3.3V regulator. The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH supplies. There is no limit on the fall time for the power supplies. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies according to Table 9 and Table 10. Table 9. Power sequence pin states for MH and AE pads 1 VDD VDD33 VDDE MH Pad MH+LVDS Pads1 AE/up-down Pads High High High Normal operation Normal operation Normal operation -- Low High Pin is tri-stated (output buffer, input buffer, and weak pulls disabled) Outputs driven high Pull-ups enabled, pull-downs disabled Low High Low Output low, pin unpowered Outputs disabled Output low, pin unpowered Low High High Pin is tri-stated (output buffer, input buffer, and weak pulls disabled) Outputs disabled Pull-ups enabled, pull-downs disabled MH+LVDS pads are output-only. PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 59 Electrical characteristics Table 10. Power sequence pin states for F and FS pads 1 5.6.1 VDD VDD33 VDDE F and FS pads low low high Outputs drive high low high -- Outputs Disabled high low low Outputs Disabled high low high Outputs drive high high high low Normal operation - except no drive current and input buffer output is unknown.1 high high high Normal Operation The pad pre-drive circuitry will function normally but since VDDE is unpowered the outputs will not drive high even though the output pmos can be enabled. Power-up If VDDE/VDDEH is powered up first, then a threshold detector tristates all drivers connected to VDDE/VDDEH. There is no limit to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit the characteristics described in the next paragraph. If VDD is powered up first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDD powers up before VDDE/VDDEH must power up. The rise times on the power supplies are to be no faster than 25 V/millisecond. 5.6.2 Power-down If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down before VDDE/VDDEH must power down. If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down. There are no limits on the fall times for the power supplies. 5.6.3 Power sequencing and POR dependent on VDDA During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between VDDA and VDDEH is more than 1 V, the following will result: * * * Triggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created, when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect level. If VDDA is between 0-2 V, powering all the other segments (especially VDDEH1) will not be sufficient to get the part out of reset. Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH - VDDA - 1 V(diode drop)/200 KOhms) up to (VDDEH/2 = VDDA + 1 V). PXR40 Microcontroller Data Sheet, Rev. 1 60 Freescale Semiconductor Electrical characteristics * 5.7 Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor since VDD = 1.32 V max. DC electrical specifications Table 11. DC electrical specifications Spec Characteristic Symbol Min Max Unit 1 Core Supply Voltage (External Regulation) VDD 1.14 1.321,2 V 1a Regulation)3 VDD 1.08 1.32 V 2 Core Supply Voltage (Internal I/O Supply Voltage (fast I/O pads) VDDE 3.0 3.6 1,4 1,5 V 3 I/O Supply Voltage (medium I/O pads) VDDEH 3.0 5.25 V 4 3.3 V I/O Buffer Voltage VDD33 3.0 3.61,4 V VDDA 4.75 5.251,5 V 1.2 V 5 Analog Supply Voltage 6a SRAM Standby Voltage Keep-out Range: 1.2V-2V VSTBY_LOW 0.956 6b SRAM Standby Voltage Keep-out Range: 1.2V-2V VSTBY_HIGH 2 6 V 7 Voltage Regulator Control Input Voltage7 VDDREG 2.78 5.51,5 V 8 Clock Synthesizer Operating Voltage9 VDDSYN 3.0 3.61,4 V 9 Fast I/O Input High Voltage Hysteresis enabled Hysteresis disabled VIH_F VDDE + 0.3 V Fast I/O Input Low Voltage Hysteresis enabled Hysteresis disabled VIL_F Medium I/O Input High Voltage Hysteresis enabled Hysteresis disabled VIH_S Medium I/O Input Low Voltage Hysteresis enabled Hysteresis disabled VIL_S 10 11 12 0.65 x VDDE 0.55 x VDDE V VSS - 0.3 0.35 x VDDE 0.40 x VDDE VDDEH + 0.3 V 0.65 x VDDEH 0.55 x VDDEH V VSS - 0.3 0.35 x VDDEH 0.40 x VDDEH 13 Fast I/O Input Hysteresis VHYS_F 0.1 x VDDE -- V 14 Medium I/O Input Hysteresis VHYS_S 0.1 x VDDEH -- V 15 Analog Input Voltage VINDC VSSA - 0.1 VDDA + 0.1 V VOH_F 0.8 x VDDE -- V VOH_S 0.8 x VDDEH -- V VOL_F -- 0.2 x VDDE V VOL_S -- 0.2 x VDDEH V -- -- -- -- 10 20 30 50 pF pF pF pF 10 16 Fast I/O Output High Voltage 17 Medium I/O Output High Voltage11 18 10 Fast I/O Output Low Voltage 11 19 Medium I/O Output Low Voltage 20 Load Capacitance (Fast I/O)12 DSC(PCR[8:9]) = 0b00 DSC(PCR[8:9]) = 0b01 DSC(PCR[8:9]) = 0b10 DSC(PCR[8:9]) = 0b11 CL PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 61 Electrical characteristics Table 11. DC electrical specifications (continued) Spec Characteristic Symbol Min Max Unit 21 Input Capacitance (Digital Pins) CIN -- 7 pF 22 Input Capacitance (Analog Pins) CIN_A -- 10 pF 24 Operating Current 1.2 V Supplies @ fsys = 264 MHz VDD @1.32 V VSTBY13 @1.2 V and 85oC VSTBY @6.0 V and 85oC IDD IDDSTBY IDDSTBY6 -- -- -- 1.014 0.10 0.15 A mA mA Operating Current 3.3 V Supplies @ fsys = 264 MHz VDD3315 VDDSYN IDD33 IDDSYN -- -- note15 716 mA mA Operating Current 5.0 V Supplies @ fsys = 264 MHz VDDA Analog Reference Supply Current (Transient) VDDREG IDDA IREF IREG -- -- -- 5017 1.0 22 mA mA mA Operating Current VDDE/VDDEH18 Supplies VDDE2 VDDEH1 VDDEH3 VDDEH4 VDDEH5 VDDEH6 VDDEH7 IDD2 IDD1 IDD3 IDD4 IDD5 IDD6 IDD7 -- -- -- -- -- -- -- note18 mA mA mA mA mA mA mA IACT_F 42 158 A 15 35 95 200 A A IINACT_D -2.5 2.5 A IIC -1.0 1.0 mA IINACT_A -250 250 nA -150 150 nA VSS - VSSA -100 100 mV VRL VSSA VSSA + 100 mV VRL - VSSA -100 100 mV VRH VDDA - 100 VDDA mV VRH - VRL 4.75 5.25 V VSSSYN - VSS -100 100 mV TA (TL to TH) -40.0 125.0 C -- -- 25 V/ms 25 26 27 28 29 Fast I/O Weak Pull Up/Down Current19 3.0 V-3.6 V Medium I/O Weak Pull Up/Down 3.0 V-3.6 V 4.5 V-5.5 V 30 I/O Input Leakage Current21 31 DC Injection Current (per pin) 32 Current20 22 Analog Input Current, Channel Off , AN[0:7], AN38, AN39 Analog Input Current, Channel Off, all other analog inputs AN[x] 33 VSS Differential Voltage 34 Analog Reference Low Voltage 35 VRL Differential Voltage 36 Analog Reference High Voltage 37 VREF Differential Voltage 38 VSSSYN to VSS Differential Voltage 39 Operating Temperature Range--Ambient (Packaged) 40 Slew rate on power supply pins IACT_S PXR40 Microcontroller Data Sheet, Rev. 1 62 Freescale Semiconductor Electrical characteristics Table 11. DC electrical specifications (continued) Spec 41 42 Characteristic Weak Pull-Up/Down Resistance23, 200 K Option Weak Pull-Up/Down Resistance 23, 100 K Option Resistance23 43 Weak Pull-Up/Down 44 Pull-Up/Down Resistance Matching Ratios24 (100K/200K) , 5 K Option Symbol Min Max Unit RPUPD200K 130 280 k RPUPD100K 65 140 k RPUPD5K 1.4 7.5 k RPUPDMTCH -2.5 +2.5 % 1 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 3 Assumed with DC load. 4 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 5 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 6 V STBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode. 7 Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with V DDREG = 4.5 V (min). 8 2.7 V minimum operating voltage allowed during vehicle crank for system with V DDREG = 3.0 V (min). Normal operating voltage should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected. 9 Required to be supplied when 3.3 V regulator is disabled. See Section 5.5 PMC/POR/LVI electrical specifications. 10 I OH_F = {16,32,47,77} mA and IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V. This spec is for characterization only. 11 I OH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDE = 4.5 V; IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDE = 3.0 V. These specs are for characterization only. 12 Applies to D_CLKOUT, external bus pins, and Nexus pins. 13 V o STBY current specified at 1.0 V at a junction temperature of 85 C. VSTBY current is 700 A maximum at a junction temperature oC. of 150 14 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization. 900 mA based on transistor count estimate at Worst Case (wcs) process and temperature condition. 15 Power requirements for the V DD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Section 5.7.2 I/O pad VDD33 current specifications, for information on both fast (F, FS) and medium (MH) pads. Also refer to Table 13 for values to calculate power dissipation for specific operation. 16 This value is a target that is subject to change. 17 This value allows a 5 V reference to supply ADC + REF. 18 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Section 5.7.1 I/O pad current specifications, for information on I/O pad power. Also refer to Table 12 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 19 Absolute value of current, measured at V and V . IL IH 20 Absolute value of current, measured at V and V . IL IH 21 Weak pull up/down inactive. Measured at V DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH. 22 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down. See Section 4 Signal properties and muxing. 23 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics 24 Pull-up and pull-down resistances are both enabled and settings are equal. 2 PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 63 Electrical characteristics 5.7.1 I/O pad current specifications The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 12 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 12. The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications. Table 12. VDDE/VDDEH I/O Pad Average DC Current1 Spec Pad Type Symbol Frequency (MHz) Load2 (pF) Voltage (V) Drive/Slew Rate Select Current (mA) 1 Medium IDRV_MH 50 50 5.25 11 16.0 2 20 50 5.25 01 6.3 3 3.0 50 5.25 00 1.1 4 2.0 200 5.25 00 2.4 66 10 3.6 00 6.5 6 66 20 3.6 01 9.4 7 66 30 3.6 10 10.8 8 66 50 3.6 11 33.3 66 50 3.6 11 12.0 50 50 3.6 10 6.2 11 33.33 50 3.6 01 4.0 12 20 50 3.6 00 2.4 13 20 200 3.6 00 8.9 5 9 10 1 2 Fast Fast w/ Slew Control IDRV_FC IDRV_FSR These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only. All loads are lumped. 5.7.2 I/O pad VDD33 current specifications The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be calculated from Table 13 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium pads can be calculated from Table 13 dependent on voltage and independent on the frequency and load on all MH type pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 13. The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications. PXR40 Microcontroller Data Sheet, Rev. 1 64 Freescale Semiconductor Electrical characteristics Table 13. VDD33 Pad Average DC Current1 Spec Pad Type Symbol Frequency (MHz) Load2 (pF) VDD33 (V) VDDE (V) Drive/Slew Rate Select Current (mA) 1 Medium I33_MH -- -- 3.6 5.5 -- 0.0007 2 Fast I33_FC 66 10 3.6 3.6 00 0.92 3 66 20 3.6 3.6 01 1.14 4 66 30 3.6 3.6 10 1.50 5 66 50 3.6 3.6 11 2.19 66 50 3.6 3.6 11 0.74 50 50 3.6 3.6 10 0.52 8 33.33 50 3.6 3.6 00 0.19 9 20 50 3.6 3.6 00 0.19 10 20 200 3.6 3.6 00 0.19 6 Fast w/ Slew Control 7 I33_FSR 1 These are average IDDE for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input pins only for the medium pads. 2 All loads are lumped. 5.7.3 LVDS pad specifications LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI module. Table 14. DSPI LVDS pad specification # Characteristic Min. Value Typ. Value Max. Value Unit -- 50 -- MHz SRC=0b00 or 0b11 150 -- 400 mV SRC=0b01 90 -- 320 SRC=0b10 160 -- 480 VOS -- 1.06 1.2 1.39 V Symbol Condition Data Rate 1 Data Frequency fLVDSCLK -- Driver Specs 2 Differential output voltage VOD 3 Common mode voltage (LVDS), VOS 4 Rise/Fall time TR/TF -- -- 2 -- ns 5 Propagation delay (Low to High) TPLH -- -- 4 -- ns 6 Propagation delay (High to Low) TPHL -- -- 4 -- ns 7 Delay (H/L), sync Mode tPDSYNC -- -- 4 -- ns 8 Delay, Z to Normal (High/Low) TDZ -- -- 500 -- ns PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 65 Electrical characteristics Table 14. DSPI LVDS pad specification (continued) 9 Diff Skew Itphla-tplhbI or Itplhb-tphlaI TSKEW -- -- -- 0.5 ns Termination 10 Trans. Line (differential Zo) -- -- 95 100 105 ohms 11 Temperature -- -- -40 -- 150 C 5.8 Oscillator and FMPLL electrical characteristics Table 15. FMPLL Electrical Specifications1 (VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Spec 1 Characteristic PLL Reference Frequency Range2 (Normal Mode) Crystal Reference (PLLCFG2 = 0b0) Crystal Reference (PLLCFG2 = 0b1) External Reference (PLLCFG2 = 0b0) External Reference (PLLCFG2 = 0b1) Symbol Min Max fref_crystal fref_crystal fref_ext fref_ext 8 16 8 16 20 403 20 40 Unit MHz 2 Loss of Reference Frequency4 fLOR 100 1000 kHz 3 Self Clocked Mode Frequency5 fSCM 4 16 MHz tLPLL -- < 400 s tDC 40 60 % 4 PLL Lock Time6 7 5 Duty Cycle of Reference 6 Frequency un-LOCK Range fUL -4.0 4.0 % fsys 7 Frequency LOCK Range fLCK -2.0 2.0 % fsys CJitter -5 5 %fclkout Cmod 0 4 %fsys Cmod_err -0.25 0.25 %fsys Jitter8, 9 8 D_CLKOUT Period Cycle-to-cycle Jitter Measured at fSYS Max 9 Peak-to-Peak Frequency Modulation Range Limit 10,11 (fsys Max must not be exceeded) 10 FM Depth Tolerance12 11 VCO Frequency fVCO 192 600 MHz 12 Modulation Rate Limits13 fmod 0.400 1 MHz 13 Predivider output frequency range14 fprediv 4 10 MHz 1 All values given are initial design targets and subject to change. Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz. 3 Upper tolerance of less than 1% is allowed on 40MHz crystal. 4 "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. 5 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f LOR. This frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and RFD values have no effect 2 PXR40 Microcontroller Data Sheet, Rev. 1 66 Freescale Semiconductor Electrical characteristics 6 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal startup time. 7 For Flexray operation, duty cycle requirements are higher. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. D_CLKOUT divider set to divide-by-2. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod. 10 Modulation depth selected must not result in fpll value greater than the fpll maximum specified value. 11 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in control register are: 2%, 3%, and 4% peak-to-peak. 12 Depth tolerance is the programmed modulation depth 0.25% of Fsys. Violating the VCO min/max range may prevent the system from exiting reset. 13 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz will result in reduced calibration accuracy. 14 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset. Table 16. Oscillator electrical specifications1 (VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Spec Characteristic Amplitude2 Symbol Min Max Unit 1 Crystal Mode Differential (Min differential voltage between EXTAL and XTAL) Vcrystal_diff_amp | Vextal - Vxtal | > 0.4 V -- V 2 Crystal Mode: Internal Differential Amplifier Noise Rejection Vcrystal_diff_amp_nr -- | Vextal - Vxtal | < 0.2 V V 3 EXTAL Input High Voltage Bypass mode, External Reference VIHEXT ((VDD33/2) + 0.4 V) -- V 4 EXTAL Input Low Voltage Bypass mode, External Reference VILEXT -- (VDD33/2) - 0.4 V V 5 XTAL Current3 IXTAL 1 3 mA 6 Total On-chip stray capacitance on XTAL CS_XTAL -- 1.5 pF 7 Total On-chip stray capacitance on EXTAL CS_EXTAL -- 1.5 pF 8 Crystal manufacturer's recommended capacitive load CL See crystal spec See crystal spec pF 9 Discrete load capacitance to be connected to EXTAL CL_EXTAL -- (2 x CL - CS_EXTAL - CPCB_EXTAL4) pF 10 Discrete load capacitance to be connected to XTAL CL_XTAL -- (2 x CL - CS_XTAL - CPCB_XTAL4) pF 1 All values given are initial design targets and subject to change. This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal - Vxtal 400 mV criterion has to be met for oscillator's comparator to produce output clock. 3 Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 4 CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 2 PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 67 Electrical characteristics 5.9 eQADC electrical characteristics Table 17. eQADC Conversion Specifications (Operating) Spec 6 7 fADCLK 2 16 MHz 2 + 14 128 + 14 2 + 12 128 + 12 2 + 10 128 + 10 CC 3 Stop Mode Recovery Time1 TSR 10 -- s 4 Resolution2 -- 1.25 -- mV INL8 -44 4 4 LSB5 Clock3 ADCLK cycles 5 INL: 8 MHz ADC 6 INL: 16 MHz ADC Clock3 INL16 -84 84 LSB 7 DNL: 8 MHz ADC Clock3 DNL8 -34 34 LSB DNL16 -34 34 LSB LSB 3 DNL: 16 MHz ADC Clock 9 Offset Error without Calibration OFFNC 0 1004 10 Offset Error with Calibration OFFWC -44 44 LSB 11 Full Scale Gain Error without Calibration GAINNC -1204 04 LSB GAINWC 4,6 44,6 LSB Full Scale Gain Error with Calibration 4 -4 13 Non-Disruptive Input Injection Current 7, 8, 9, 10 IINJ -3 3 m 14 Incremental Error due to injection current11, 12 EINJ -44 44 Counts 15 TUE value at 8 MHz 13, 14 (with calibration) TUE8 -44,6 44,6 Counts TUE16 -8 8 Counts DIFFmax DIFFmax2 DIFFmax4 -- -- -- (VRH - VRL)/2 (VRH - VRL)/4 (VRH - VRL)/8 V V V DIFFcmv (VRH - VRL)/2 - 5% (VRH - VRL)/2 + 5% V 18 5 Unit Conversion Cycles Single Ended Conversion Cycles 12 bit resolution Single Ended Conversion Cycles 10 bit resolution Single Ended Conversion Cycles 8 bit resolution Note: Differential conversion (min) is one clock cycle less than the single-ended conversion values listed here. 17 4 Max 2 16 2 Min ADC Clock (ADCLK) Frequency 12 3 Symbol 1 8 1 Characteristic TUE value at 16 MHz 13, 14 (with calibration) 15 Maximum differential voltage (DANx+ - DANx-) or (DANx- - DANx+) PREGAIN set to 1X setting PREGAIN set to 2X setting PREGAIN set to 4X setting Differential input Common mode voltage15 (DANx- + DANx+)/2 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms. At VRH - VRL = 5.12 V, one count = 1.25 mV without using pregain. INL and DNL are tested from VRL + 50 LSB to VRH - 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy (12 bit resolution selected). New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully included. At VRH - VRL = 5.12 V, one LSB = 1.25 mV. The value is valid at 8 MHz, it is 8 counts at 16 Mhz. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions. PXR40 Microcontroller Data Sheet, Rev. 1 68 Freescale Semiconductor Electrical characteristics 8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = -0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pins at injection limits. 11 Performance expected with production silicon. 12 All channels have same 10 k < Rs < 100 kChannel under test has Rs = 10 k, IINJ=IINJMAX,IINJMIN. 13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors. 14 TUE does not apply to differential conversions. 15 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode voltage of the differential signal violates the Differential Input common mode voltage specification. 5.9.1 ADC internal resource measurements Table 18. Power Management Control (PMC) specification Spec Characteristic Symbol Min Typical Max Unit PMC Normal Mode 1 Bandgap 0.62 V ADC0 channel 145 VADC145 -- 0.62 -- V 2 Bandgap 1.2 V ADC0 channel 146 VADC146 -- 1.22 -- V 3 Vreg1p2 Feedback ADC0 channel 147 VADC147 -- VDD / 2.045 -- V 4 LVD 1.2 V ADC0 channel 180 VADC180 -- VDD / 1.774 -- V 5 Vreg3p3 Feedback ADC0 channel 181 VADC181 -- Vreg3p3 / 5.460 -- V 6 LVD 3.3 V ADC0 channel 182 VADC182 -- Vreg3p3 / 4.758 -- V 7 LVD 5.0 V ADC0 channel 183 -- LDO mode -- SMPS mode VADC183 -- -- V VDDREG / 4.758 VDDREG/7.032 PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 69 Electrical characteristics Table 19. Standby RAM regulator electrical specifications Spec Characteristic Symbol Min Typ Max Unit Normal Mode 1 Standby Regulator Output ADC1 channel 194 VADC194 -- 1.2 -- V 2 Standby Source Bias 150 mV to 360 mV (30mV Increment @ vref_sel) ADC1 channel 195 Default Value 150 mV (@vref_sel = 1 1 1) VADC195 150 -- 360 mV 3 Standby Brownout Reference ADC1 channel 195 VADC195 500 -- 850 mV Table 20. ADC band gap reference / LVI electrical specifications Spec Characteristic Symbol Min Typ Max Unit 1 4.75 LVD (from VDDA) ADC1 channel 196 VADC196 -- 4.75 -- V 2 ADC Bandgap ADC0 channel 45 ADC1 channel 45 VADC45 1.171 1.220 1.269 V Table 21. Temperature sensor electrical specifications Spec 1 Characteristic 1 Slope -40 C to 100 C 1.0 C 100 C to 150 C 1.6 C ADC0 channel 128 ADC1 channel 128 2 Accuracy -40 C to 150 C ADC0 channel 128 ADC1 channel 128 Symbol Min Typ Max Unit VSADC1281 -- 5.8 -- mV/ C -- -- -- C 10.0 Slope is the measured voltage change per C. PXR40 Microcontroller Data Sheet, Rev. 1 70 Freescale Semiconductor Electrical characteristics 5.10 C90 flash memory electrical characteristics Table 22. Flash program and erase specifications Spec Characteristic Symbol Min Typ1 Initial Max2 Max3 Unit 1 Double Word (64 bits) Program Time4 tdwprogram -- 38 -- 500 s 2 Page Program Time4,5 tpprogram -- 45 160 500 s 3 16 KB Block Pre-program and Erase Time t16kpperase -- 270 1000 5000 ms 4 64 KB Block Pre-program and Erase Time t64kpperase -- 800 1800 5000 ms 5 128 KB Block Pre-program and Erase Time t128kpperase -- 1500 2600 7500 ms 6 256 KB Block Pre-program and Erase Time t256kpperase -- 3000 5200 15000 ms 1 oC. Typical program and erase times assume nominal supply values and operation at 25 Initial factory condition: 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency. 3 The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 Program times are actual hardware programming times and do not include software overhead. 5 Page size is 128 bits (4 words). 2 Table 23. Flash EEPROM module life Spec Characteristic Symbol Min Typical1 Unit 1 Number of program/erase cycles per block for 16 KB and 64 KB blocks over the operating temperature range (TJ) P/E 100,000 -- cycles 2 Number of program/erase cycles per block for 128 KB and 256 KB blocks over the operating temperature range (TJ) P/E 1,000 100,000 cycles 3 Minimum Data Retention at 85 C ambient temperature2 Blocks with 0-1,000 P/E cycles Blocks with 1,001-10,000 P/E cycles Blocks with 10,001-100,000 P/E cycles 20 10 5 -- -- -- Retention years 1 Typical endurance is evaluated at 25 C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range. Table 24 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 71 Electrical characteristics Table 24. PFCPR1 settings vs. frequency of operation1 Spec Clock Mode Maximum Frequency2 (MHz) Core fsys 264 MHz6 APC = RWSC WWSC 132 MHz6 0b011 Platform fplatf 2 3 4 5 6 IPFEN3 PFLIM4 BFEN5 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 1 Enhanced 2 Enhanced/ 200 MHz Full 100 MHz 0b010 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 3 Legacy 132 MHz 0b100 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 0b111 0b11 0b00 0b00 0b00 0b0 132 MHz Default setting after reset: 1 DPFEN3 Illegal combinations exist. Use entries from the same row in this table. This is the nominal maximum frequency of operation: platform runs at fsys/2 in Enhanced Mode . For maximum flash performance, set to 0b1. For maximum flash performance, set to 0b10. For maximum flash performance, set to 0b1. This is the nominal maximum frequency of operation in Enhanced Mode. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(fsys) + 2% FM and 132 Mhz platform clock (fplatf)+ 2% FM. PXR40 Microcontroller Data Sheet, Rev. 1 72 Freescale Semiconductor Electrical characteristics 5.11 AC specifications 5.11.1 Clocking Figure 8 shows the operating frequency domains of various blocks on PXR40. PLLCFG[0:1] CORE EXTAL SYSDIV X PLL fsys 2 fplatf IPG DIV SEL fperiph SIU_SYSDIV[SYSCLKDIV[0:1]] X = 2, 4, 8, or 16 fetpu ETPU DIV SEL SIU_SYSDIV[BYPASS] X=1 SIU_SYSDIV[IPCLKDIV[0:1]] DIV PLATFORM / BLOCKS / FLASH eTPU / NDEDI febi_cal SIU_ECCR[EBDF[0:1]] Note: tcycsys = 1 / fsys tcyc = 1 / fplatf 2 = divide-by-2 X = divide-by-X, depending on SIU_SYSDIV[BYPASS] and SIU_SYSDIV[SYSCLKDIV]. EBI CAL BUS D_CLKOUT (D_CLKOUT is not available on all packages and cannot be programmed for faster than fsys/2.) Figure 8. PXR40 block operating frequency domain diagram Table 25 shows the operating frequencies of various blocks depending on the device's clocking mode configuration settings (see Table 26 and Table 27 for descriptions of bit settings). Table 25. PXR40 operating frequencies1, 2 fsys fplatf SIU_ECCR [EBDF[0:1]]3 (core) Enhanced 01 11 264 264 132 132 Full 01 11 200 200 Legacy 01 11 132 132 Mode 1 fetpu febi_cal4,5 Unit 132 132 66 33 MHz 100 100 200 200 50 25 MHz 132 132 132 132 66 33 MHz (platform and all blocks (eTPU, eTPU RAM, except eTPU) and NDEDI) The values in the table are specified at: VDD = 1.02 V to 1.32 V VDDE = 3.0 V to 3.6 V VDDEH = 4.5 V to 5.5 V VDD33 and VDDSYN = 3.0 V to 3.6 V TA = TL to TH. PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 73 Electrical characteristics 2 Up to the maximum frequency rating of the device (refer to Table 39). The fsys speed is the nominal maximum frequency. 270 Mhz parts allow for 264 Mhz system clock + 2% FM. 3 See the PXR40 Reference Manual for full description as not all bit combinations are valid. 4 EBI/Calibration bus is not available in all packages. 5 The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block's max allowed frequency of operation. Normally febi_cal = fplatf /2, but can be limited to < fplatf /2 in Full Mode. Table 26. IPCLKDIV settings SIU_SYSDIV [IPCLKDIV[0:1]] Mode 00 Enhanced 01 Full 10 -- 11 Legacy Description CPU frequency is doubled (Max 264Mhz). Platform, peripheral, and eTPU clocks are 1/2 of CPU frequency CPU and eTPU frequency is doubled (Max 200Mhz). Platform and peripheral clocks are 1/2 of CPU frequency. Reserved CPU, eTPU, platform, and peripheral's clocks all run at same speed (Max 132Mhz). Table 27. SYSCLKDIV settings SIU_SYSDIV [SYSCLKDIV[0:1]] 5.11.2 Description 00 Divide by 2. 01 Divide by 4. 10 Divide by 8. 11 Divide by 16. Pad AC specifications Table 28. Pad AC specifications (vddeh = 5.0 V, VDDE = 3.3 V)1 Spec Pad SRC/DSC Out Delay2,4 L H/H L (ns) Rise/Fall3,4 (ns) Load Drive (pF) 1 Medium5 00 152/165 70/74 50 205/220 96/96 200 28/34 12/15 50 52/59 28/31 200 12/12 5.3/5.9 50 32/32 22/22 200 2 3 01 4 5 6 11 PXR40 Microcontroller Data Sheet, Rev. 1 74 Freescale Semiconductor Electrical characteristics Table 28. Pad AC specifications (vddeh = 5.0 V, VDDE = 3.3 V)1 (continued) Spec Pad SRC/DSC 7 Fast6 00 8 Out Delay2,4 L H/H L (ns) 01 20 10 30 10 11 50 Fast with Slew Rate 00 12 13 01 14 15 10 16 17 11 18 3 4 5 6 1.2 9 11 2 Load Drive (pF) 10 2.5 1 Rise/Fall3,4 (ns) 40/40 16/16 50 50/50 21/21 200 13/13 5/5 50 19/19 8/8 200 8/8 2.4/2.4 50 12/12 5/5 200 5/5 1.1/1/1 50 8/8 2.6 2.6 19 Pull Up/Down (3.6 V max) -- -- 7500 50 20 Pull Up/Down (5.25 V max) -- 6000 5000/5000 50 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. This parameter is guaranteed by characterization before qualification rather than 100% tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 29. Derated pad AC specifications (VDDEH = 3.3 V)1 Spec Pad SRC/DSC Out Delay2,3 L H/H L (ns) Rise/Fall4,3 (ns) Load Drive (pF) 1 Medium5 00 200/210 86/86 50 270/285 120/120 200 37/45 15.5/19 50 69/82 38/43 200 18/17 7.6/8.5 50 46/49 30/34 200 2 3 01 4 5 6 1 2 3 4 5 11 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization before qualification rather than 100% tested. Out delay is shown in Figure 9. Add a maximum of one system clock to the output delay for delay with respect to system clock. PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 75 Electrical characteristics VDDEn / 2 VDDEHn / 2 Pad Data Input Rising Edge Output Delay Falling Edge Output Delay VOH Pad Output VOL Figure 9. Pad output delay PXR40 Microcontroller Data Sheet, Rev. 1 76 Freescale Semiconductor Electrical characteristics 5.12 AC timing 5.12.1 Generic timing diagrams The generic timing diagrams in Figure 10 and Figure 11 apply to all I/O pins with pad types F and MH. See 4, Signal properties and muxing, for the pad type for each pin. D_CLKOUT VDDE / 2 A B I/O Outputs VDDEn / 2 VDDEHn / 2 A - Maximum Output Delay Time B - Minimum Output Hold Time Figure 10. Generic output delay/hold timing D_CLKOUT VDDE / 2 B A I/O Inputs VDDEn / 2 VDDEHn / 2 A - Minimum Input Setup Time B - Minimum Input Hold Time Figure 11. Generic input setup/hold timing PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 77 Electrical characteristics 5.12.2 Reset and configuration pin timing Table 30. Reset and configuration pin timing1 Spec 1 Characteristic Symbol Min Max Unit 1 RESET Pulse Width tRPW 10 -- tcyc2 2 RESET Glitch Detect Pulse Width tGPW 2 -- tcyc2 3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 -- tcyc2 4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0 -- tcyc2 Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH. See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking. 2 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG WKPCFG 4 Figure 12. Reset and configuration pin timing 5.12.3 IEEE 1149.1 interface timing Table 31. JTAG pin AC electrical characteristics1 Spec Characteristic Symbol Min Max Unit 1 TCK Cycle Time tJCYC 100 -- ns 2 TCK Clock Pulse Width (Measured at VDDE / 2) tJDC 40 60 ns 3 TCK Rise and Fall Times (40%-70%) tTCKRISE -- 3 ns 4 TMS, TDI Data Setup Time tTMSS, tTDIS 5 -- ns 5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 -- ns 6 TCK Low to TDO Data Valid tTDOV -- 10 ns PXR40 Microcontroller Data Sheet, Rev. 1 78 Freescale Semiconductor Electrical characteristics Table 31. JTAG pin AC electrical characteristics1 (continued) Spec 1 Characteristic Symbol Min Max Unit tTDOI 0 -- ns tTDOHZ -- 20 ns tJCMPPW 100 -- ns 7 TCK Low to TDO Data Invalid 8 TCK Low to TDO High Impedance 9 JCOMP Assertion Time 10 JCOMP Setup Time to TCK Low tJCMPS 40 -- ns 11 TCK Falling Edge to Output Valid tBSDV -- 50 ns 12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ -- 50 ns 13 TCK Falling Edge to Output High Impedance tBSDHZ -- 50 ns 14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 -- ns 15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 -- ns JTAG timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 32 for functional specifications. TCK 2 2 3 1 3 Figure 13. JTAG test clock input timing PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 79 Electrical characteristics TCK 4 5 TMS, TDI 6 8 7 TDO Figure 14. JTAG Test Access Port (TAP) timing TCK 10 JCOMP 9 Figure 15. JTAG JCOMP timing PXR40 Microcontroller Data Sheet, Rev. 1 80 Freescale Semiconductor Electrical characteristics TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 16. JTAG boundary scan timing 5.12.4 Nexus timing Table 32. Nexus debug port timing1 Spec Characteristic Symbol Min Max Unit 1 MCKO Cycle Time tMCYC 22 8 tCYC3 2 MCKO Duty Cycle tMDC 40 60 % 3 MCKO Low to MDO Data Valid4 tMDOV -0.1 0.2 tMCYC 4 MCKO Low to MSEO Data Valid4 tMSEOV -0.1 0.2 tMCYC 5 MCKO Low to EVTO Data Valid4 tEVTOV -0.1 0.2 tMCYC 6 EVTI Pulse Width tEVTIPW 4.0 -- tTCYC3 7 EVTO Pulse Width tEVTOPW 1 -- tMCYC 8 TCK Cycle Time tTCYC 45 -- tCYC3 9 TCK Duty Cycle tTDC 40 60 % PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 81 Electrical characteristics Table 32. Nexus debug port timing1 (continued) Spec Characteristic Symbol Min Max Unit 10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8 -- ns 11 TDI, TMS Data Hold Time TNTDIH, tNTMSH 5 -- ns 12 TCK Low to TDO Data Valid tNTDOV 0 10 ns 13 RDY Valid to MCKO6 -- -- -- -- 1 2 3 4 5 6 All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending on the system frequency, not to exceed maximum Nexus AUX port frequency. See Notes on tcyc on Figure 13 and Table 25 in Section Section 5.11.1 Clocking. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. Lower frequency is required to be fully compliant to standard. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly. 1 2 MCKO 3 4 5 MDO MSEO EVTO Output Data Valid 7 EVTI 6 Figure 17. Nexus timings PXR40 Microcontroller Data Sheet, Rev. 1 82 Freescale Semiconductor Electrical characteristics 8 9 TCK 10 11 TMS, TDI 12 TDO Figure 18. Nexus TCK, TDI, TMS, TDO timing PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 83 Electrical characteristics 5.12.5 External Bus Interface (EBI) timing Table 33. Bus operation timing 1 66 MHz (Ext. Bus Freq)2 3 Spec Characteristic Symbol Unit Notes -- ns Signals are measured at 50% VDDE. Min Max tC 15.2 1 D_CLKOUT Period 2 D_CLKOUT Duty Cycle tCDC 45% 55% tC 3 D_CLKOUT Rise Time tCRT -- --4 ns 4 4 D_CLKOUT Fall Time tCFT -- -- ns 5 D_CLKOUT Posedge to Output Signal Invalid or High Z (Hold Time) tCOH 1.0/1.5 -- ns Hold time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 1.0 ns EBTS = 1: 1.5 ns tCOV -- 7.0/7.5 ns Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 7.0 ns EBTS = 1: 7.5 ns D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3] 6 D_CLKOUT Posedge to Output Signal Valid (Output Delay) D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3] PXR40 Microcontroller Data Sheet, Rev. 1 84 Freescale Semiconductor Electrical characteristics Table 33. Bus operation timing 1 (continued) 66 MHz (Ext. Bus Freq)2 3 Spec 7 Characteristic Symbol Input Signal Valid to D_CLKOUT Posedge (Setup Time) Unit Min Max tCIS 5.0/4.5 -- ns tCIH 1.0 -- ns Input setup time selectable via SIU_ECCR[EBTS] bit: EBTS = 0; 5.0ns EBTS = 1; 4.5ns D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 8 D_CLKOUT Posedge to Input Signal Invalid (Hold Time) Notes D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 1 2 3 4 5 9 D_ALE Pulse Width tAPW 6.5 -- ns The timing is for Asynchronous external memory system. 10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5 -- ns The timing is for Asynchronous external memory system. ALE is measured at 50% of VDDE. EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system clock + 2% FM. Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency. The maximum external bus frequency is 66 MHz. Refer to Fast pad timing in Table 28 and Table 29. ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0 C. 2.0 ns spec applies to temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit. VOH_F VDDE / 2 D_CLKOUT VOL_F 3 2 2 4 1 Figure 19. D_CLKOUT timing PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 85 Electrical characteristics VDDE / 2 D_CLKOUT 6 5 5 Output Bus VDDE / 2 6 5 5 Output Signal VDDE / 2 6 Output Signal VDDE / 2 Figure 20. Synchronous output timing PXR40 Microcontroller Data Sheet, Rev. 1 86 Freescale Semiconductor Electrical characteristics D_CLKOUT VDDE / 2 7 8 Input Bus VDDE / 2 7 8 Input Signal VDDE / 2 Figure 21. Synchronous input timing ipg_clk D_CLKOUT D_ALE D_TS D_ADD/D_DAT DATA ADDR 9 10 Figure 22. ALE signal timing PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 87 Electrical characteristics 5.12.6 External interrupt timing (IRQ pin) Table 34. External interrupt timing1 Spec Characteristic Symbol Min Max Unit 1 IRQ Pulse Width Low tIPWL 3 -- tcyc2 2 IRQ Pulse Width High tIPWH 3 -- tcyc2 3 IRQ Edge to Edge Time3 tICYC 6 -- tcyc2 1 IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. 2 See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking. 3 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 2 1 3 Figure 23. External interrupt timing 5.12.7 eTPU timing Table 35. eTPU timing1 Spec Characteristic Symbol Min Max Unit 1 eTPU Input Channel Pulse Width tICPW 4 -- tcyc2 2 eTPU Output Channel Pulse Width tOCPW 13 -- tcyc2 1 eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00. 2 See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking. 3 This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). PXR40 Microcontroller Data Sheet, Rev. 1 88 Freescale Semiconductor Electrical characteristics eTPU Input and TCRCLK 1 2 eTPU Output Figure 24. eTPU timing 5.12.8 eMIOS timing Table 36. eMIOS timing1 Spec Characteristic Symbol Min Max Unit 1 eMIOS Input Pulse Width tMIPW 4 -- tcyc2 2 eMIOS Output Pulse Width tMOPW 13 -- tcyc2 1 eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2 See Notes on t cyc on Figure 8 and Table 25 in Section 5.11.1 Clocking. 3 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 89 Electrical characteristics eMIOS Input 1 2 eMIOS Output Figure 25. eMIOS timing 5.12.9 DSPI timing Table 37. DSPI timing1 2 Peripheral Bus Freq: 132 MHz Spec Characteristic Symbol Unit Min Max 1 DSPI Cycle Time3, 4 Master (MTFE = 0) Slave (MTFE = 0) Master (MTFE = 1) Slave (MTFE = 1) tSCK tSYS * 2 tSYS*32768*7 ns 2 PCS to SCK Delay5 tCSC 12 -- ns 3 After SCK Delay6 Master mode Slave mode tASC tSYS * 2 tSYS *3 - constraints 7 -- 4 SCK Duty Cycle tSDC 0.33 * tSCK 0.66 * tSCK ns 5 Slave Access Time (SS active to SOUT valid) tA -- 25 ns 6 Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) tDIS -- 25 ns 7 PCSx to PCSS time tPCSC tSYS * 2 tSYS * 7 ns 8 PCSS to PCSx time tPASC tSYS * 2 tSYS * 7 ns ns PXR40 Microcontroller Data Sheet, Rev. 1 90 Freescale Semiconductor Electrical characteristics Table 37. DSPI timing1 2 (continued) Peripheral Bus Freq: 132 MHz Spec Characteristic 9 10 11 12 1 2 3 4 5 6 7 8 Symbol Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) tSUI Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) tHI Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tSUO Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tHO Unit Min Max 20 4 6 20 -- -- -- -- ns ns ns ns -3 7 12 -3 -- -- -- -- ns ns ns ns -- -- -- -- 5 25 13 5 ns ns ns ns -5 2.5 3 -5 -- -- -- -- ns ns ns ns DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM. The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK]. The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC]. For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10. The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol. DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high speed operation. Table 38. DSPI LVDS timing1, 2 Characteristic LVDS Clock to Data/Chip Select Outputs 1 2 Symbol Min Max Unit tLVDSDATA -0.25 x tSCYC +0.25 x tSCYC ns These are typical values that are estimated from simulation. See DSPI LVDS Pad related data in Table 14. PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 91 Electrical characteristics 2 3 PCSx 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT First Data 11 Data Last Data Figure 26. DSPI classic SPI timing -- Master, CPHA = 0 PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN Data First Data 12 SOUT First Data Last Data 11 Data Last Data Figure 27. DSPI classic SPI timing -- Master, CPHA = 1 PXR40 Microcontroller Data Sheet, Rev. 1 92 Freescale Semiconductor Electrical characteristics 3 2 SS 1 4 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 First Data SOUT 9 6 Data Last Data Data Last Data 10 First Data SIN 11 12 Figure 28. DSPI classic SPI timing -- Slave, CPHA = 0 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 SOUT First Data 9 SIN Data Last Data Data Last Data 6 10 First Data Figure 29. DSPI classic SPI timing -- Slave, CPHA = 1 PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 93 Electrical characteristics 3 PCSx 4 1 2 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT 11 First Data Last Data Data Figure 30. DSPI modified transfer format timing -- Master, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Figure 31. DSPI modified transfer format timing -- Master, CPHA = 1 PXR40 Microcontroller Data Sheet, Rev. 1 94 Freescale Semiconductor Electrical characteristics 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) 12 11 5 First Data SOUT Data Last Data 10 9 Data First Data SIN 6 Last Data Figure 32. DSPI modified transfer format timing -- Slave, CPHA = 0 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 6 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data Figure 33. DSPI modified transfer format timing -- Slave, CPHA = 1 7 8 PCSS PCSx Figure 34. DSPI PCS strobe (PCSS) timing PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 95 Ordering information 6 Ordering information 6.1 Orderable parts Figure 35 and Table 39 describe and list the orderable part numbers for the PXR40. M PX R 40 30 V VU 264 R Qualification status Brand Family Class Flash memory size Temperature range Package identifier Operating frequency Tape and reel indicator Qualification status P = Pre-qualification (engineering samples) M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Temperature range V = -40 C to 105 C (ambient) Family D = Display Graphics N = Connectivity/Network R = Performance/Real Time Control S = Safety Package identifier VU = 416 PBGA Operating frequency 1 = 150 MHz 2 = 180 MHz Flash Memory Size 30 = 3 MB 40 = 4 MB Tape and reel status R = Tape and reel (blank) = Trays Note: Not all options are available on all devices. See Table 39 for more information. Figure 35. PXR40 orderable part number description Table 39. PXR40 orderable part number summary Flash/SRAM Package Speed (MHz) MPXR4030VVU264 3 MB / 192 KB 416 PBGA (27 mm x 27 mm) 264 MPXR4040VVU264 4 MB / 256 KB 416 PBGA (27 mm x 27 mm) 264 Part number PXR40 Microcontroller Data Sheet, Rev. 1 96 Freescale Semiconductor Package information 7 Package information 7.1 416-pin package The package drawings of the 416-pin TEPBGA package are shown in Figure 36 and Figure 37. Figure 36. 416 TEPBGA package (1 of 2) PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 97 Package information Figure 37. 416 TEPBGA package (2 of 2) PXR40 Microcontroller Data Sheet, Rev. 1 98 Freescale Semiconductor Product documentation 8 Product documentation This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. The following documents are required for a complete description of the device and are necessary to design properly with the parts: * PXR40 Microprocessor Reference Manual (document number PXR40RM). 9 Revision history Table 40 describes the changes made to this document between revisions. Table 40. Revision history Revision 1 Date Description of Changes September 2011 Initial release: Technical Data PXR40 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 99 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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