Freescale Semiconductor
Data Sheet: Technical Data Document Number: PXR40
Rev. 1, 09/2011
© Freescale Semiconductor, Inc., 2011. All rights reserved.
PXR40
TEPBGA–416
27mm x 27mm
• Dual issue, 32-bit CPU core complex (e200z7)
– Compliant with the Power Architecture embedded
category
– 16 KB I-Cache and 16 KB D-Cache
– Includes an instruction set enhancement allowing
variable length encoding (VLE), optional encoding of
mixed 16-bit and 32-bit instru ctions, for code size
footprint reduction
– Includes signal processing extension (SPE2) instruction
support for digital signal processing (DSP) and
single-precision floatin g point operations
• 4 MB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPRO M emul ation
• 256 KB on-chip general-purpose SRAM including 32 KB
of standby RAM
• Two direct memory access controller (eDMA2) blocks
– One supporting 64 channels
– One supporting 32 channels
• Interrupt controller (INTC)
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• External bus interface (EBI) for calibration and application
development (not available on all packages)
• System integration unit (SIU)
• Error correction status module (ECSM)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Two second-generation enhanced time processor units
(eTPU2) that share code and data RAM.
– 32 standard channels per eTPU2
– 24 KB code RAM
– 6 KB parameter (data) RAM
• Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
single action, double action, pulse width modulation
(PWM) and modulus counter operation
• Four enhanced queued analog-to-digital converters
(eQADC)
– Support for 64 analog channels
– Includes one absolute reference ADC channel
– Includes eight decimation filters
• Four deserial serial peripheral interface (SPI) modules
• Three enhanced serial communication interface (UART)
modules
• Four controller area network (CAN) modules
• Dual-channel FlexRay controller
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003/5001-2008 standard
• Device and board test support per Joint Test Action Group
(JTAG) (IEEE 1149.1)
• On-chip voltage regulator controller regulates supply
voltage down to 1.2 V for core logic
PXR40 Microcontroller Data
Sheet
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor2
Table of Contents
1 PXR40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 PXR40 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 416-ball TEPBGA pin assignments. . . . . . . . . . . . . . . . .6
4 Signal properties and muxing. . . . . . . . . . . . . . . . . . . . . . . . .11
5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .53
5.2.1 General notes for specifications at maximum junction
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3 EMI (Electromagnetic Interference) characteristics . . .55
5.4 ESD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.5 PMC/POR/LVI electrical specifications . . . . . . . . . . . . .56
5.6 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .59
5.6.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.6.2 Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.6.3 Power sequencing and POR dependent on VDDA60
5.7 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . .61
5.7.1 I/O pad current specifications . . . . . . . . . . . . . .64
5.7.2 I/O pad VDD33 current specifications . . . . . . . . .64
5.7.3 LVDS pad specifications . . . . . . . . . . . . . . . . . .65
5.8 Oscillator and FMPLL electrical characteristics . . . . . .66
5.9 eQADC electrical characteristics. . . . . . . . . . . . . . . . . 68
5.9.1 ADC internal resource measurements. . . . . . . 69
5.10 C90 flash memory electrical characteristics . . . . . . . . 71
5.11 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.11.2 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 74
5.12 AC timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.12.1 Generic timing diagrams . . . . . . . . . . . . . . . . . 77
5.12.2 Reset and configuration pin timing. . . . . . . . . . 78
5.12.3 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 78
5.12.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.12.5 External Bus Interface (EBI) timing . . . . . . . . . 84
5.12.6 External interrupt timing (IRQ pin) . . . . . . . . . . 88
5.12.7 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.12.8 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.12.9 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8 Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PXR40 features
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 3
1 PXR40 features
Table 1 displays the PXR40 feature set.
Table 1. PXR40 feature set
Feature PXR40
Core e200z7
SIMD Yes
VLE Yes
Cache 32 KB
(16 KB Instruction/16 KB Data)
Non-maskable interrupt (NMI) NMI & Critical Interrupt
MMU 64 entry
MPU Yes
XBAR 5 × 5
Windowing software watchdog Yes
Nexus 3+
SRAM 256 KB
Flash 4 MB
Flash fetch accelerator 4 × 256 bit
(first 1 MB of memory is 4 × 128; last 3 MB are 4 × 256)
External bus Yes
Calibration bus 16 bit non-muxed
32 bit muxed
DMA 96 channel
DMA Nexus Class 3
Serial 3
UART_A Yes
UART_B Yes
UART_C Yes
Microsecond bus uplink Yes
CAN 4
CAN_A 64 message buffers
CAN_B 64 message buffers
CAN_C 64 message buffers
CAN_D 64 message buffers
CAN_E No
SPI 4
SPI_A Yes
SPI_B Yes
SPI_C Yes
SPI_D Yes
FlexRay Yes
Ethernet No
System timers 4 PIT chan
4 SWT
1 Watchdog
eMIOS 32 channel
eTPU 64 channel
eTPU_A Yes (eTPU2)
eTPU_B Yes (eTPU2)
PXR40 Microcontroller Data Sheet, Rev. 1
PXR40 features
Freescale Semiconductor4
Note: 3.3 V is required for cert ain IO segments only during debug/development (e.g., Nexu s 3 trace and bus)
Code memory 24 KB
Data memory 6 KB
Interrupt controller 448
ADC 64 channel
eQADC_A Yes
eQADC_B Yes
Temperature sensor Yes
Variable gain amp. Yes
Decimation filter Yes (8 on eQADC_B)
Sensor diagnostics Yes
PLL FM
VRC Yes
Supplies 5V
Low Power Modes Stop Mode
Slow Mode
Table 1. PXR40 feature set (continued)
Feature PXR40
PXR40 block diagram
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 5
2 PXR40 block diagram
Figure 1 shows a top-level bloc k diagram of the PXR40 microcontrollers.
Figure 1. Block diagram
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Data and Instruction System
PBRIDGE A
PXR40 Block Diagram
System
Integration
Interrupt
Controller
Osc/PLL
SPE2
Debug
Nexus
JTAG
IEEE
ISTO
5001™-2003
2 x eDMA
64- and
32-ch
e200z7
Superscalar
CPU
PBRIDGE B
256 KB
SRAM
w/ECC
(32 KB S/B)
4MB
Flash
w/ECC
Main Memory System
SIU
Timed I/O System
Boot Assist
Module
(BAM)
6K
Data
24K
Code
RAM
eMIOS
32-ch eTPU2
32-ch eTPU2
32-ch 4 x
CAN 3 x
UART/ 4 x
SPI 4 x
Dec
Fil
64-ch
QUAD
ADCi
Communications
FlexRay™
Controller
ADC – Analog-to-digital converter
ADCi – ADC interface
AIPS – Peripheral I/O bridge
AMux – Analog multiplexer
CAN – Controller area network
DECFIL– Decimation filter
EBI – External bus interface
ECSM – Error correction status module
eDMA2 – Enhanced direct memory access
eMIOS – Enhanced modular I/O system
eQADC– Enhanced queued A/D converter module
eTPU2 – Enhanced time processing unit 2
MMU – Memory management unit
MPU – Memory protection unit
PBRIDGE – Peripheral I/O bridge
S/B – Stand-by
SIU – System integration unit
SPE2 – Signal processing engine 2
SPI – Serial peripheral interface controller
SRAM – General-purpose static RAM
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
VLE – Variable length instruction encoding
LIN
PXR40 Microcontroller Data Sheet, Rev. 1
Pin assignments
Freescale Semiconductor6
3 Pin assignments
The figures in this section show the primary pin function. For the full signal properties and muxing table, see Table 4.
3.1 416-ball TEPBGA pin assignments
Figure 2 shows the 416-ball TEPBGA pin assignments in one fi gure. The same information is shown in Figure 3 through
Figure 6.
Figure 2. PXR40 416-ball TEPBGA (full diagram)
VSSFL
REGCTL
ETPUB26
TDO
MDO15
VDDE2
VDDE2
VDDE2
VSS
12345678910111213141516
VDD RSTOUT ANA0 ANA15
VDDA_A0
VRH_A AN28 AN32 AN36
VDDA_B0
A
VDDEH1 VSS VDD TEST ANA1 ANA5 ANA14
VDDA_A1
REF– AN24 AN27 AN29 AN33
VDDA_B1
B
VSS VDD ANA2 ANA6 ANA13 ANA17 ANA19 ANA21 ANA23 AN26
AN30
AN34 AN37
C
VSS VDD ANA3 ANA12 ANA18 ANA20 AN25 AN31 AN35 AN39
D
E
F
G
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
H
VSSVDDE2 VSS VSS
J
K
L
M
VSS VDDE2 VDD
AC
VSS FR_A_ EMIOS5
AD
VSS FR_A_ EMIOS6
AE
VSS VDDE2 EMIOS7
AF
ANA7
ANA9
ANA4
PXR40 416-ball TEPBGA
(as viewed from top through the package)
VRL_A
VSSA_A1
PCSA1
FR_A_
ANA11ANA8
ETPUA30
ANA16
VDD
PCSA5
ANA10
ANA22
VDDEH4VDDEH3PCSB1PCSB4PCSA2
ETPUA2
VSTBYRXDATXDAVDD33_1
VDDTDIVDDE2
VDDENGCLK FR_B_ EMIOS2PCSB3SCKASOUTA PCSB0
FR_B_ PCSA0PCSA4 EMIOS3EMIOS0SCKBPCSA3 SINB
FR_B_ PCSB5VDDEH3 EMIOS4EMIOS1PCSB2SINA SOUTB
17 18 19 20 21 22 23 24 25 26
VRL_B VRH_B ANB14 ANB17 ANB21 ANB23 VSS
REF– ANB6 ANB10 ANB15 ANB18 ANB22 VSS
ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS
ANB2 ANB9 ANB13 VSS VDDEH7
VDDEH7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
PCSC1 VSS
RXDC PCSC3 VSS VDD VDDSYN
SINC PCSC2 PCSC5 VSS
VDDEH4 TXDC VSS
A
B
C
D
E
F
G
H
J
K
L
M
ANB1
AN38
ANB11ANB7
ANB8
ANB3
XTAL
VDDEH5
VSSA_B0
ANB20
ETPUC7
ETPUB15ETPUB14 VDDEH7
VDD VDDEH6VDDEH5CNRXDCNRXB
SCKCCNTXDCNTXB
PCSC0CNRXCCNRXA
SOUTCCNTXCCNTXA PCSC4
VDD
1234567891011121314151617181920212223242526
WKPCFG VDDN
VDDEH1P
R
T
U
V
W
Y
AA
AB
PLLCFG2
RDY
RXDB
TXDB
PLLCFG0
EVTI
RESETJCOMP
MSEO1MCKOVDDE2
MDO1MDO0MSEO0EVTO
MDO5MDO4MDO3MDO2
VDDE2MDO8MDO7MDO6
MDO11MDO10MDO9
VDD33_2MDO14MDO13MDO12
VDDTMSTCK
VDDEH6 ETPUB11ETPUB12ETPUB13
ETPUB7 ETPUB8 ETPUB9 ETPUB10
ETPUB3 ETPUB4 ETPUB5
ETPUB0 ETPUB1 ETPUB2
ETPUB19
ETPUB20
REGSEL ETPUB25 ETPUB24 ETPUB23
ETPUB29 ETPUB28 ETPUB27
VDD33_3 ETPUB30 VSSSYN
VDD
N
P
R
T
U
V
W
Y
AA
AB
ETPUB18 ETPUB17 ETPUB16
ETPUB21ETPUB22
TCRCLKB
VDDREG
ETPUB31 EXTAL
VSSVDDE2 VSS
VSSVDDE2 VSS
VSSVDDE2
VSSVDDE2 VDDE2 VDDE2
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
AC
AD
AE
AF
ETPUA27
ETPUA23
ETPUA19
ETPUA15
ETPUA11
ETPUA7
ETPUA3
TCRCLKA
ETPUA28
ETPUA24
ETPUA20
ETPUA16
ETPUA12
ETPUA8
ETPUA4
ETPUA31
ETPUA29
ETPUA25
ETPUA21
ETPUA17
ETPUA14
ETPUA9
ETPUA5
ETPUA1
ETPUA26
ETPUA22
ETPUA18
ETPUA13
ETPUA10
ETPUA6
EMIOS8
EMIOS9
EMIOS10
EMIOS11
EMIOS14
EMIOS15
EMIOS13
EMIOS12
EMIOS18
EMIOS19
EMIOS17
EMIOS16
EMIOS22
EMIOS23
EMIOS21
EMIOS20
EMIOS27
EMIOS26
EMIOS25
EMIOS24
EMIOS31
EMIOS30
EMIOS29
EMIOS28
RX
TX_EN TX_EN
RX
TX TX
BYPCA BYPCB
ETPUC11
ETPUC15
ETPUC19
ETPUC23
ETPUC27
ETPUC31
ETPUC8
ETPUC12
ETPUC16
ETPUC20
ETPUC24
ETPUC28
ETPUC9
ETPUC13
ETPUC17
ETPUC21
ETPUC25
ETPUC29
ETPUC10
ETPUC14
ETPUC18
ETPUC22
ETPUC26
ETPUC30
ETPUC4 ETPUC5 ETPUC6
ETPUC3
ETPUC1
TCRCLKC
ETPUC2
ETPUC0
ETPUB6
ETPUA0
VDDE2
BOOT–
CFG1
PLLCFG1
REF–
BYPCA1 REF–
BYPCB1
Pin assignments
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 7
Figure 3. PXR40 416-ball TEPBGA ( 1 of 4)
12345678910111213
12345678910111213
VDD
VSS
TXDA
BOOTCFG1
ETPUA28
ETPUA24
ETPUA20
ETPUA16
ETPUA12
ETPUA8
ETPUA4
ETPUA0
VSS RSTOUT ANA0 ANA15 VDDA_A0 VRH_A AN28
VDDEH1 VDD TEST ANA1 ANA5 ANA14 VDDA_A1
REFBYPCA
AN24 AN27
VSS VDD ANA2 ANA6 ANA13 ANA17 ANA19 ANA21 ANA23 AN26
VSS VDD ANA3 ANA12 ANA18 ANA20 AN25
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVDDE2 VSS VSS
ANA7
ANA9
ANA4 VRL_A
VSSA_A1
ANA11ANA8
ETPUA30
ANA16
ANA10
ANA22
ETPUA2
VSTBYRXDAVDD33_1
WKPCFG VDDRXDB
ETPUA27
ETPUA23
ETPUA19
ETPUA15
ETPUA11
ETPUA7
ETPUA3
TCRCLKA
ETPUA31
ETPUA29
ETPUA25
ETPUA21
ETPUA17
ETPUA14
ETPUA9
ETPUA5
ETPUA1
ETPUA26
ETPUA22
ETPUA18
ETPUA13
ETPUA10
ETPUA6
A
B
E
F
G
H
J
K
L
M
N
C
D
A
B
E
F
G
H
J
K
L
M
N
C
D
PXR40 416-ball TEPBGA
(as view ed from top through the package)
(1 of 4)
REFBYP-
CA1
PXR40 Microcontroller Data Sheet, Rev. 1
Pin assignments
Freescale Semiconductor8
Figure 4. PXR40 416-ball TEPBGA ( 2 of 4)
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
AN32 AN36 VDDA_B0
AN29 AN33 VDDA_B1
AN30 AN34 AN37
AN31 AN35 AN39
VRL_B VRH_B ANB14 ANB17 ANB21 ANB23 VSS
REFBYPCB
ANB6 ANB10 ANB15 ANB18 ANB22 VSS
ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS
ANB2 ANB9 ANB13 VSS VDDEH7
VDDEH7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
ANB1
AN38
ANB11ANB7
ANB8
ANB3
VSSA_B0
ANB20
ETPUC7
ETPUB15 ETPUB14 VDDEH7
VDDEH6 ETPUB11 ETPUB12 ETPUB13
ETPUC11
ETPUC15
ETPUC19
ETPUC23
ETPUC27
ETPUC31
ETPUC8
ETPUC12
ETPUC16
ETPUC20
ETPUC24
ETPUC28
ETPUC9
ETPUC13
ETPUC17
ETPUC21
ETPUC25
ETPUC29
ETPUC10
ETPUC14
ETPUC18
ETPUC22
ETPUC26
ETPUC30
ETPUC4 ETPUC5 ETPUC6
ETPUC3
ETPUC1
TCRCLKC
ETPUC2
ETPUC0
A
B
E
F
G
H
J
K
L
M
N
C
D
A
B
E
F
G
H
J
K
L
M
N
C
D
PXR40 416-ball TEPBGA
(as viewed from top through the package)
(2 of 4)
REFBYP-
CB1
Pin assignments
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 9
Figure 5. PXR40 416-ball TEPBGA ( 3 of 4)
VDDE2
VDDE2
TDO
MDO15
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
VSS
VDDE2
TDI
VDD
PLLCFG1
RESET
MCKO
MSEO0
MDO3
MDO7
MDO10
MDO13
TCK
VSS VDDE2 VDD
VSS EMIOS5
EMIOS6
VSS EMIOS7
PCSA1
VDD
PCSA5
VDDEH4VDDEH3PCSB1PCSB4PCSA2VDDVDDE2
ENGCLK FR_B_TX EMIOS2PCSB3SCKASOUTA PCSB0
FR_B_RX PCSA0PCSA4 EMIOS3EMIOS0SCKBPCSA3 SINB
PCSB5VDDEH3 EMIOS4EMIOS1PCSB2SINA SOUTB
VDDEH1PLLCFG2
RDY
TXDB
PLLCFG0
EVTI
JCOMP
MSEO1VDDE2
MDO1MDO0EVTO
MDO5MDO4MDO2
VDDE2MDO8MDO6
MDO11MDO9
VDD33_2MDO14MDO12
VDDTMS
VSSVDDE2 VSS
VSSVDDE2 VSS
VSSVDDE2
VSSVDDE2 VDDE2 VDDE2
EMIOS8
EMIOS9
EMIOS10
EMIOS11
12345678910111213
12345678910111213
PXR40 416-ball TEPBGA
(as viewed from top through the package)
(3 of 4)
VDDE2
VDDE2
FR_B_
TX_EN
FR_A_TX
FR_A_RX
FR_A_
TX_EN
PXR40 Microcontroller Data Sheet, Rev. 1
Pin assignments
Freescale Semiconductor10
Figure 6. PXR40 416-ball TEPBGA ( 4 of 4)
REGCTL
ETPUB26
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
PCSC1 VSS
RXDC PCSC3 VSS VDD VDDSYN
SINC PCSC2 PCSC5 VSS
VDDEH4 TXDC VSS
XTAL
VDDEH5
VDD VDDEH6VDDEH5CNRXDCNRXB
SCKCCNTXDCNTXB
PCSC0CNRXCCNRXA
SOUTCCNTXCCNTXA PCSC4
VDD
ETPUB7 ETPUB8 ETPUB9 ETPUB10
ETPUB3 ETPUB4 ETPUB5
ETPUB0 ETPUB1 ETPUB2
ETPUB19
ETPUB20
REGSEL ETPUB25 ETPUB24 ETPUB23
ETPUB29 ETPUB28 ETPUB27
VDD33_3 ETPUB30 VSSSYN
VDD
ETPUB18 ETPUB17 ETPUB16
ETPUB21ETPUB22
TCRCLKB
ETPUB31 EXTAL
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
EMIOS14
EMIOS15
EMIOS13
EMIOS12
EMIOS18
EMIOS19
EMIOS17
EMIOS16
EMIOS22
EMIOS23
EMIOS21
EMIOS20
EMIOS27
EMIOS26
EMIOS25
EMIOS24
EMIOS31
EMIOS30
EMIOS29
EMIOS28
ETPUB6
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
PXR40 416-ball TEPBGA
(as viewed from top through the package)
(4 of 4)
VDDREG
VSSFL
Signal properties and muxing
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 11
4 Signal properties and muxing
Table 2 shows the signals properties for each pin on the PXR40. For each port pin that has an associated SIU_PCRn register to
control its pin properties, the supported functions column lists the functions associated with the programming of the
SIU_PCRn[PA ] bit in the order: Primary fun ction (P), Func ti on 2 (F2), Function 3 (F3), and GPIO (G). See Figure 7.
Figure 7. Supported functions example
Primary Functions
Secondary Functions
GPIO Functions are
are listed First
are alternate functions
listed Last
GPIO/
PCR1Signal Name2
P/
F/
GFunction
3Function Summary I/O Pad
Type
113 TCRCLKA_IRQ7_GPIO113 PTCRCLKA eTPU A TCR clock I 5V M
A1 IRQ7 External interrupt request I
A2 ———
GGPIO113 GPIO I/O
Function not implemented on th is device
Table 2. Signal Properties Summary
PXR40 Microcontroller Data Sheet, Rev. 1
12 Freescale Semiconductor
Table 2. Signal Properties and Muxing Summary
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
eTPU_A
113 TCRCLKA_IRQ7_
GPIO113 PTCRCLKA eTPU A TCR clock I MH VDDEH1 —/Up —/Up L1
A1 IRQ7 External interrupt request I
A2 —— —
GGPIO113 GPIO I/O
114 ETPUA0_ETPUA12_
GPIO114 PETPUA0 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG L2
A1 ETPUA12 eTPU A channel (output only) O
A2 —— —
GGPIO114 GPIO I/O
115 ETPUA1_ETPUA13_
GPIO115 PETPUA1 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG L3
A1 ETPUA13 eTPU A channel (output only) O
A2 —— —
GGPIO115 GPIO I/O
116 ETPUA2_ETPUA14_
GPIO116 PETPUA2 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG L4
A1 ETPUA14 eTPU A channel (output only) O
A2 —— —
GGPIO116 GPIO I/O
117 ETPUA3_ETPUA15_
GPIO117 PETPUA3 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K1
A1 ETPUA15 eTPU A channel (output only) O
A2 —— —
GGPIO117 GPIO I/O
118 ETPUA4_ETPUA16_
GPIO118 PETPUA4 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K2
A1 ETPUA16 eTPU A channel (output only) O
A2 —— —
GGPIO118 GPIO I/O
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 13
119 ETPUA5_ETPUA17_
GPIO119 PETPUA5 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K3
A1 ETPUA17 eTPU A channel (output only) O
A2 —— —
GGPIO119 GPIO I/O
120 ETPUA6_ETPUA18_
GPIO120 PETPUA6 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K4
A1 ETPUA18 eTPU A channel (output only) O
A2 —— —
GGPIO120 GPIO I/O
121 ETPUA7_ETPUA19_
GPIO121 PETPUA7 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J1
A1 ETPUA19 eTPU A channel (output only) O
A2 —— —
GGPIO121 GPIO I/O
122 ETPUA8_ETPUA20_
GPIO122 PETPUA8 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J2
A1 ETPUA20 eTPU A channel (output only) O
A2 —— —
GGPIO122 GPIO I/O
123 ETPUA9_ETPUA21_
GPIO123 PETPUA9 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J3
A1 ETPUA21 eTPU A channel (output only) O
A2 —— —
GGPIO123 GPIO I/O
124 ETPUA10_ETPUA22_
GPIO124 PETPUA10 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J4
A1 ETPUA22 eTPU A channel (output only) O
A2 —— —
GGPIO124 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
14 Freescale Semiconductor
125 ETPUA11_ETPUA23_
GPIO125 PETPUA11 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H1
A1 ETPUA23 eTPU A channel (output only) O
A2 —— —
GGPIO125 GPIO I/O
126 ETPUA12_PCSB1_
GPIO126 PETPUA12 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H2
A1 PCSB1 DSPI B peripheral chip select O
A2 —— —
GGPIO126 GPIO I/O
127 ETPUA13_PCSB3_
GPIO127 PETPUA13 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H4
A1 PCSB3 DSPI B peripheral chip select O
A2 —— —
GGPIO127 GPIO I/O
128 ETPUA14_PCSB4_
GPIO128 PETPUA14 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H3
A1 PCSB4 DSPI B peripheral chip select O
A2 —— —
GGPIO128 GPIO I/O
129 ETPUA15_PCSB5_
GPIO129 PETPUA15 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G1
A1 PCSB5 DSPI B peripheral chip select O
A2 —— —
GGPIO129 GPIO I/O
130 ETPUA16_PCSD1_
GPIO130 PETPUA16 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G2
A1 PCSD1 DSPI D peripheral chip select O
A2 —— —
GGPIO130 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 15
131 ETPUA17_PCSD2_
GPIO131 PETPUA17 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G3
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO131 GPIO I/O
132 ETPUA18_PCSD3_
GPIO132 PETPUA18 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G4
A1 PCSD3 DSPI D peripheral chip select O
A2 —— —
GGPIO132 GPIO I/O
133 ETPUA19_PCSD4_
GPIO133 PETPUA19 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F1
A1 PCSD4 DSPI D peripheral chip select O
A2 —— —
GGPIO133 GPIO I/O
134 ETPUA20_IRQ8_
GPIO134 PETPUA20 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F2
A1 IRQ8 External interrupt request I
A2 —— —
GGPIO134 GPIO I/O
135 ETPUA21_IRQ9_
GPIO135 PETPUA21 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F3
A1 IRQ9 External interrupt request I
A2 —— —
GGPIO135 GPIO I/O
136 ETPUA22_IRQ10_
GPIO136 PETPUA22 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F4
A1 IRQ10 External interrupt request I
A2 —— —
GGPIO136 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
16 Freescale Semiconductor
137 ETPUA23_IRQ11_
GPIO137 PETPUA23 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E1
A1 IRQ11 External interrupt request I
A2 —— —
GGPIO137 GPIO I/O
138 ETPUA24_IRQ12_
GPIO138 PETPUA24 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E2
A1 IRQ12 External interrupt request I
A2 —— —
GGPIO138 GPIO I/O
139 ETPUA25_IRQ13_
GPIO139 PETPUA25 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E3
A1 IRQ13 External interrupt request I
A2 —— —
GGPIO139 GPIO I/O
140 ETPUA26_IRQ14_
GPIO140 PETPUA26 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E4
A1 IRQ14 External interrupt request I
A2 —— —
GGPIO140 GPIO I/O
141 ETPUA27_IRQ15_
GPIO141 PETPUA27 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D1
A1 IRQ15 External interrupt request I
A2 —— —
GGPIO141 GPIO I/O
142 ETPUA28_PCSC1_
GPIO142 PETPUA28 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D2
A1 PCSC1 DSPI C peripheral chip select O
A2 —— —
GGPIO142 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 17
143 ETPUA29_PCSC2_
GPIO143 PETPUA29 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D3
A1 PCSC2 DSPI C peripheral chip select O
A2 —— —
GGPIO143 GPIO I/O
144 ETPUA30_PCSC3_
GPIO144 PETPUA30 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C1
A1 PCSC3 DSPI C peripheral chip select O
A2 —— —
GGPIO144 GPIO I/O
145 ETPUA31_PCSC4_
GPIO145 PETPUA31 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C2
A1 PCSC4 DSPI C peripheral chip select O
A2 —— —
GGPIO145 GPIO I/O
eTPU_B
146 TCRCLKB_IRQ6_
GPIO146 PTCRCLKB eTPU B TCR clock I MH VDDEH6 —/Up —/Up T23
A1 IRQ6 External interrupt request I
A2 —— —
GGPIO146 GPIO I/O
147 ETPUB0_ETPUB16_
GPIO147 PETPUB0 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T24
A1 ETPUB16 eTPU B channel (output only) O
A2 —— —
GGPIO147 GPIO I/O
148 ETPUB1_ETPUB17_
GPIO148 PETPUB1 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T25
A1 ETPUB17 eTPU B channel (output only) O
A2 —— —
GGPIO148 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
18 Freescale Semiconductor
149 ETPUB2_ETPUB18_
GPIO149 PETPUB2 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T26
A1 ETPUB18 eTPU B channel (output only) O
A2 —— —
GGPIO149 GPIO I/O
150 ETPUB3_ETPUB19_
GPIO150 PETPUB3 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R23
A1 ETPUB19 eTPU B channel (output only) O
A2 —— —
GGPIO150 GPIO I/O
151 ETPUB4_ETPUB20_
GPIO151 PETPUB4 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R24
A1 ETPUB20 eTPU B channel (output only) O
A2 —— —
GGPIO151 GPIO I/O
152 ETPUB5_ETPUB21_
GPIO152 PETPUB5 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R25
A1 ETPUB21 eTPU B channel (output only) O
A2 —— —
GGPIO152 GPIO I/O
153 ETPUB6_ETPUB22_
GPIO153 PETPUB6 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R26
A1 ETPUB22 eTPU B channel (output only) O
A2 —— —
GGPIO153 GPIO I/O
154 ETPUB7_ETPUB23_
GPIO154 PETPUB7 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P23
A1 ETPUB23 eTPU B channel (output only) O
A2 —— —
GGPIO154 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 19
155 ETPUB8_ETPUB24_
GPIO155 PETPUB8 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P24
A1 ETPUB24 eTPU B channel (output only) O
A2 —— —
GGPIO155 GPIO I/O
156 ETPUB9_ETPUB25_
GPIO156 PETPUB9 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P25
A1 ETPUB25 eTPU B channel (output only) O
A2 —— —
GGPIO156 GPIO I/O
157 ETPUB10_ETPUB26_
GPIO157 PETPUB10 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P26
A1 ETPUB26 eTPU B channel (output only) O
A2 —— —
GGPIO157 GPIO I/O
158 ETPUB11_ETPUB27_
GPIO158 PETPUB11 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N24
A1 ETPUB27 eTPU B channel (output only) O
A2 —— —
GGPIO158 GPIO I/O
159 ETPUB12_ETPUB28_
GPIO159 PETPUB12 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N25
A1 ETPUB28 eTPU B channel (output only) O
A2 —— —
GGPIO159 GPIO I/O
160 ETPUB13_ETPUB29_
GPIO160 PETPUB13 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N26
A1 ETPUB29 eTPU B channel (output only) O
A2 —— —
GGPIO160 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
20 Freescale Semiconductor
161 ETPUB14_ETPUB30_
GPIO161 PETPUB14 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M25
A1 ETPUB30 eTPU B channel (output only) O
A2 —— —
GGPIO161 GPIO I/O
162 ETPUB15_ETPUB31_
GPIO162 PETPUB15 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M24
A1 ETPUB31 eTPU B channel (output only) O
A2 —— —
GGPIO162 GPIO I/O
163 ETPUB16_PCSA1_
GPIO163 PETPUB16 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U26
A1 PCSA1 DSPI A peripheral chip select O
A2 —— —
GGPIO163 GPIO I/O
164 ETPUB17_PCSA2_
GPIO164 PETPUB17 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U25
A1 PCSA2 DSPI A peripheral chip select O
A2 —— —
GGPIO164 GPIO I/O
165 ETPUB18_PCSA3_
GPIO165 PETPUB18 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U24
A1 PCSA3 DSPI A peripheral chip select O
A2 —— —
GGPIO165 GPIO I/O
166 ETPUB19_PCSA4_
GPIO166 PETPUB19 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U23
A1 PCSA4 DSPI A peripheral chip select O
A2 —— —
GGPIO166 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 21
167 ETPUB20_
GPIO167 PETPUB20 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V26
A1 —— —
A2 —— —
GGPIO167 GPIO I/O
168 ETPUB21_
GPIO168 PETPUB21 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V25
A1 —— —
A2 —— —
GGPIO168 GPIO I/O
169 ETPUB22_
GPIO169 PETPUB22 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V24
A1 —— —
A2 —— —
GGPIO169 GPIO I/O
170 ETPUB23_
GPIO170 PETPUB23 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG W26
A1 —— —
A2 —— —
GGPIO170 GPIO I/O
171 ETPUB24_
GPIO171 PETPUB24 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG W25
A1 —— —
A2 —— —
GGPIO171 GPIO I/O
172 ETPUB25_
GPIO172 PETPUB25 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG W24
A1 —— —
A2 —— —
GGPIO172 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
22 Freescale Semiconductor
173 ETPUB26_
GPIO173 PETPUB26 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V23
A1 —— —
A2 —— —
GGPIO173 GPIO I/O
174 ETPUB27_
GPIO174 PETPUB27 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y25
A1 —— —
A2 —— —
GGPIO174 GPIO I/O
175 ETPUB28_
GPIO175 PETPUB28 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y24
A1 —— —
A2 —— —
GGPIO175 GPIO I/O
176 ETPUB29_
GPIO176 PETPUB29 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y23
A1 —— —
A2 —— —
GGPIO176 GPIO I/O
177 ETPUB30_
GPIO177 PETPUB30 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG AA24
A1 —— —
A2 —— —
GGPIO177 GPIO I/O
178 ETPUB31_
GPIO178 PETPUB31 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG AB24
A1 —— —
A2 —— —
GGPIO178 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 23
GPIO, IRQ, FlexRay
440 TCRCLKC_
GPIO4409P—— —MHV
DDEH7 —/Up —/Up B26
A1 —— —
A2 —— —
GGPIO440 GPIO I/O
441 ETPUC0_
GPIO4419P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG C25
A1 —— —
A2 —— —
GGPIO441 GPIO I/O
442 ETPUC1_
GPIO4429P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG C26
A1 —— —
A2 —— —
GGPIO442 GPIO I/O
443 ETPUC2_
GPIO4439P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG D25
A1 —— —
A2 —— —
GGPIO443 GPIO I/O
444 ETPUC3_
GPIO4449P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG D26
A1 —— —
A2 —— —
GGPIO444 GPIO I/O
445 ETPUC4_
GPIO4459P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG E24
A1 —— —
A2 —— —
GGPIO445 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
24 Freescale Semiconductor
446 ETPUC5_
GPIO4469P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG E25
A1 —— —
A2 —— —
GGPIO446 GPIO I/O
447 ETPUC6_
GPIO4479P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG E26
A1 —— —
A2 —— —
GGPIO447 GPIO I/O
448 ETPUC7_
GPIO4489P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG F23
A1 —— —
A2 —— —
GGPIO448 GPIO I/O
449 ETPUC8_
GPIO4499P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG F24
A1 — — —
A2 —— —
GGPIO449 GPIO I/O
450 ETPUC9_IRQ0_
GPIO4509P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG F25
A1 IRQ0 External interrupt request I
A2 —— —
GGPIO450 GPIO I/O
451 ETPUC10__IRQ1_
GPIO4519P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG F26
A1 IRQ1 External interrupt request I
A2 —— —
GGPIO451 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 25
452 ETPUC11_IRQ2_
GPIO4529P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G23
A1 IRQ2 External interrupt request I
A2 —— —
GGPIO452 GPIO I/O
453 ETPUC12_IRQ3_
GPIO4539P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G24
A1 IRQ3 External interrupt request I
A2 —— —
GGPIO453 GPIO I/O
454 ETPUC13_3_IRQ4_
GPIO4549P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G25
A1 IRQ4 External interrupt request I
A2 —— —
GGPIO454 GPIO I/O
455 ETPUC14_4_IRQ5_
GPIO4559P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G26
A1 IRQ5 External interrupt request I
A2 —— —
GGPIO455 GPIO I/O
456 ETPUC15__
GPIO4569P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H23
A1 —— —
A2 —— —
GGPIO456 GPIO I/O
457 ETPUC16_FR_A_TX_
GPIO4579P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H24
A1 FR_A_TX FlexRay A transfe r O
A2 —— —
GGPIO457 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
26 Freescale Semiconductor
458 ETPUC17_FR_A_RX_
GPIO4589P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H25
A1 FR_A_RX FlexRay A receive I
A2 —— —
GGPIO458 GPIO I/O
459 ETPUC18_
FR_A_TX_EN_
GPIO459
9
P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H26
A1 FR_A_TX_EN FlexRay A transfer enable O
A2 —— —
GGPIO459 GPIO I/O
460 ETPUC19_TXDA_
GPIO4609P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J23
A1 TXDA eSCI A transmit O
A2 —— —
GGPIO460 GPIO I/O
461 ETPUC20_RXDA _
GPIO4619P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J24
A1 RXDA eSCI A receive I
A2 —— —
GGPIO461 GPIO I/O
462 ETPUC21_TXDB_
GPIO4629P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J25
A1 TXDB eSCI B transmit O
A2 —— —
GGPIO462 GPIO I/O
463 ETPUC22_RXDB_
GPIO4639P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J26
A1 RXDB eSCI B receive I
A2 —— —
GGPIO463 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 27
464 ETPUC23_PCSD5_
GPIO4649P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K23
A1 PCSD5 DSPI D peripheral chip select O
A2 MAA0 ADC A Mux Address 0 O
A3 MAB0 ADC B Mux Address 0 O
GGPIO464 GPIO I/O
465 ETPUC24_PCSD4_
GPIO4659P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K24
A1 PCSD4 DSPI D peripheral chip select O
A2 MAA1 ADC A Mux Address 1 O
A4 MAB1 ADC B Mux Address 1 O
GGPIO465 GPIO I/O
466 ETPUC25_PCSD3_
GPIO4669P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K25
A1 PCSD3 DSPI D peripheral chip select O
A2 MAA2 ADC A Mux Address 2 O
A3 MAB2 ADC B Mux Address 2 O
GGPIO466 GPIO I/O
467 ETPUC26_PCSD2_
GPIO4679P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K26
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO467 GPIO I/O
468 ETPUC27_PCSD1_
GPIO4689P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG L23
A1 PCSD1 DSPI D peripheral chip select O
A2 —— —
GGPIO468 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
28 Freescale Semiconductor
469 ETPUC28_PCSD0_
GPIO4699P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG L24
A1 PCSD0 DSPI D peripheral chip select I/O
A2 —— —
GGPIO469 GPIO I/O
470 ETPUC29_SCKD_
GPIO4709P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG L25
A1 SCKD DSPI D clock I/O
A2 —— —
GGPIO470 GPIO I/O
471 ETPUC30_SOUTD_
GPIO4719P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG L26
A1 SOUTD DSPI D data output O
A2 —— —
GGPIO471 GPIO I/O
472 ETPUC31_SIND_
GPIO4729P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG M23
A1 SIND DSPI D data input I
A2 —— —
GGPIO472 GPIO I/O
eMIOS
179 EMIOS0_ETPUA0_
GPIO179 PEMIOS0 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE10
A1 ETPUA0 eTPU A channel O
A2 —— —
GGPIO179 GPIO I/O
180 EMIOS1_ETPUA1_
GPIO180 PEMIOS1 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF10
A1 ETPUA1 eTPU A channel O
A2 —— —
GGPIO180 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 29
181 EMIOS2_ETPUA2_
GPIO181 PEMIOS2 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD11
A1 ETPUA2 eTPU A channel O
A2 —— —
GGPIO181 GPIO I/O
182 EMIOS3_ETPUA3_
GPIO182 PEMIOS3 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE11
A1 ETPUA3 eTPU A channel O
A2 —— —
GGPIO182 GPIO I/O
183 EMIOS4_ETPUA4_
GPIO183 PEMIOS4 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF11
A1 ETPUA4 eTPU A channel O
A2 —— —
GGPIO183 GPIO I/O
184 EMIOS5_ETPUA5_
GPIO184 PEMIOS5 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD12
A1 ETPUA5 eTPU A channel O
A2 —— —
GGPIO184 GPIO I/O
185 EMIOS6_ETPUA6_
GPIO185 PEMIOS6 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE12
A1 ETPUA6 eTPU A channel O
A2 —— —
GGPIO185 GPIO I/O
186 EMIOS7_ETPUA7_
GPIO186 PEMIOS7 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF12
A1 ETPUA7 eTPU A channel O
A2 —— —
GGPIO186 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
30 Freescale Semiconductor
187 EMIOS8_ETPUA8_
GPIO187 PEMIOS8 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC13
A1 ETPUA8 eTPU A channel O
A2 —— —
GGPIO187 GPIO I/O
188 EMIOS9_ETPUA9_
GPIO188 PEMIOS9 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD13
A1 ETPUA9 eTPU A channel O
A2 —— —
GGPIO188 GPIO I/O
189 EMIOS10_SCKD_
GPIO189 PEMIOS10 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE13
A1 SCKD DSPI D clock O
A2 —— —
GGPIO189 GPIO I/O
190 EMIOS11_SIND_
GPIO190 PEMIOS11 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF13
A1 SIND DSPI D data input I
A2 —— —
GGPIO190 GPIO I/O
191 EMIOS12_SOUTC_
GPIO191 PEMIOS12 eMIOS channel O M H VDDEH4 —/WKPCFG —/WKPCFG AF14
A1 SOUTC DSPI C data output O
A2 —— —
GGPIO191 GPIO I/O
192 EMIOS13_SOUTD_
GPIO192 PEMIOS13 eMIOS channel O M H VDDEH4 —/WKPCFG —/WKPCFG AE14
A1 SOUTD DSPI D data output O
A2 —— —
GGPIO192 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 31
193 EMIOS14_IRQ0_
GPIO193 PEMIOS14 eMIOS channel O M H VDDEH4 —/WKPCFG —/WKPCFG AC14
A1 IRQ0 External interrupt request I
A2 CNTXD FlexCAN D transmit O
GGPIO193 GPIO I/O
194 EMIOS15_IRQ1_
GPIO194 PEMIOS15 eMIOS channel O M H VDDEH4 —/WKPCFG —/WKPCFG AD14
A1 IRQ1 External interrupt request I
A2 CNRXD FlexCAN D receive I
GGPIO194 GPIO I/O
195 EMIOS16_ETPUB0_
GPIO195 PEMIOS16 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF15
A1 ETPUB0 eTPU B channel O
A2 FR_DBG[3] FlexRay debug O
GGPIO195 GPIO I/O
196 EMIOS17_ETPUB1_
GPIO196 PEMIOS17 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE15
A1 ETPUB1 eTPU B channel O
A2 FR_DBG[2] FlexRay debug O
GGPIO196 GPIO I/O
197 EMIOS18_ETPUB2_
GPIO197 PEMIOS18 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC15
A1 ETPUB2 eTPU B channel O
A2 FR_DBG[1] FlexRay debug O
GGPIO197 GPIO I/O
198 EMIOS19_ETPUB3_
GPIO198 PEMIOS19 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD15
A1 ETPUB3 eTPU B channel O
A2 FR_DBG[0] FlexRay debug O
GGPIO198 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
32 Freescale Semiconductor
199 EMIOS20_ETPUB4_
GPIO199 PEMIOS20 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF16
A1 ETPUB4 eTPU B channel O
A2 —— —
GGPIO199 GPIO I/O
200 EMIOS21_ETPUB5_
GPIO200 PEMIOS21 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE16
A1 ETPUB5 eTPU B channel O
A2 —— —
GGPIO200 GPIO I/O
201 EMIOS22_ETPUB6_
GPIO201 PEMIOS22 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC16
A1 ETPUB6 eTPU B channel O
A2 —— —
GGPIO201 GPIO I/O
202 EMIOS23_ETPUB7_
GPIO202 PEMIOS23 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD16
A1 ETPUB7 eTPU B channel O
A2 —— —
GGPIO202 GPIO I/O
203 EMIOS24_PCSB0_
GPIO203 PEMIOS24 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF17
A1 PCSB0 DSPI B peripheral chip select I/O
A2 —— —
GGPIO203 GPIO I/O
204 EMIOS25_PCSB1_
GPIO204 PEMIOS25 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE17
A1 PCSB1 DSPI B peripheral chip select O
A2 —— —
GGPIO204 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 33
432 EMIOS26_PCSB2_
GPIO432 PEMIOS26 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD17
A1 PCSB2 DSPI B peripheral chip select O
A2 —— —
GGPIO432 GPIO I/O
433 EMIOS27_PCSB3_
GPIO433 PEMIOS27 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC17
A1 PCSB3 DSPI B peripheral chip select O
A2 —— —
GGPIO433 GPIO I/O
434 EMIOS28_PCSC0_
GPIO434 PEMIOS28 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF18
A1 PCSC0 DSPI C peripheral chip select I/O
A2 —— —
GGPIO434 GPIO I/O
435 EMIOS29_PCSC1_
GPIO435 PEMIOS29 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE18
A1 PCSC1 DSPI C peripheral chip select O
A2 —— —
GGPIO435 GPIO I/O
436 EMIOS30_PCSC2_
GPIO436 PEMIOS30 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD18
A1 PCSC2 DSPI C peripheral chip select O
A2 —— —
GGPIO436 GPIO I/O
437 EMIOS31_PCSC5_
GPIO437 PEMIOS31 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC18
A1 PCSC5 DSPI C peripheral chip select O
A2 —— —
GGPIO437 GPIO I/O
eQADC
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
34 Freescale Semiconductor
—ANA0 PANA010 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA0 ANA0 A4
—ANA1 PANA110 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA1 ANA1 B5
—ANA2 PANA210 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA2 ANA2 C5
—ANA3 PANA310 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA3 ANA3 D6
—ANA4 PANA410 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA4 ANA4 A5
—ANA5 PANA510 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA5 ANA5 B6
—ANA6 PANA610 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA6 ANA6 C6
—ANA7 PANA710 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA7 ANA7 D7
—ANA8 PANA8 eQADC A analog input I AE VDDA_A1 ANA8 ANA8 A6
—ANA9 PANA9 eQADC A analog input I AE VDDA_A1 ANA9 ANA9 C7
—ANA10 PANA10 eQADC A analog input I AE VDDA_A1 ANA10 ANA10 B7
—ANA11 PANA11 eQADC A analog input I AE VDDA_A1 ANA11 ANA11 A7
—ANA12 PANA12 eQADC A analog input I AE VDDA_A1 ANA12 ANA12 D8
—ANA13 PANA13 eQADC A analog input I AE VDDA_A1 ANA13 ANA13 C8
—ANA14 PANA14 eQADC A analog input I AE VDDA_A1 ANA14 ANA14 B8
—ANA15 PANA15 eQADC A analog input I AE VDDA_A1 ANA15 ANA15 A8
—ANA16 PANA16 eQADC A analog input I AE VDDA_A1 ANA16 ANA16 D9
—ANA17 PANA17 eQADC A analog input I AE VDDA_A1 ANA17 ANA17 C9
—ANA18 PANA18 eQADC A analog input I AE VDDA_A1 ANA18 ANA18 D10
—ANA19 PANA19 eQADC A analog input I AE VDDA_A1 ANA19 ANA19 C10
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 35
—ANA20 PANA20 eQADC A analog input I AE VDDA_A1 ANA20 ANA20 D11
—ANA21 PANA21 eQADC A analog input I AE VDDA_A1 ANA21 ANA21 C11
—ANA22 PANA22 eQADC A analog input I AE VDDA_A1 ANA22 ANA22 D12
—ANA23 PANA23 eQADC A analog input I AE VDDA_A1 ANA23 ANA23 C12
—AN24 PAN24 eQADC A and B shared analog input I AE VDDA_A0 AN24 AN24 B12
—AN25 PAN25 eQADC A and B shared analog input I AE VDDA_A0 AN25 AN25 D13
—AN26 PAN26 eQADC A and B shared analog input I AE VDDA_A0 AN26 AN26 C13
—AN27 PAN27 eQADC A and B shared analog input I AE VDDA_A0 AN27 AN27 B13
—AN28 PAN28 eQADC A and B shared analog input I AE VDDA_A0 AN28 AN28 A13
—AN29 PAN29 eQADC A and B shared analog input I AE VDDA_A0 AN29 AN29 B14
—AN30 PAN30 eQADC A and B shared analog input I AE VDDA_B1 AN30 AN30 C14
—AN31 PAN31 eQADC A and B shared analog input I AE VDDA_B1 AN31 AN31 D14
—AN32 PAN32 eQADC A and B shared analog input I AE VDDA_B1 AN32 AN32 A14
—AN33 PAN33 eQADC A and B shared analog input I AE VDDA_B0 AN33 AN33 B15
—AN34 PAN34 eQADC A and B shared analog input I AE VDDA_B0 AN34 AN34 C15
—AN35 PAN35 eQADC A and B shared analog input I AE VDDA_B0 AN35 AN35 D15
—AN36 PAN36 eQADC A and B shared analog input I AE VDDA_B1 AN36 AN36 A15
—AN37 PAN37 eQADC A and B shared analog input I AE VDDA_B0 AN37 AN37 C16
—AN38 PAN38 eQADC A and B shared analog input I AE VDDA_B0 AN38 AN38 C17
—AN39 PAN39 eQADC A and B shared analog input I AE VDDA_B0 AN39 AN39 D16
—ANB0 PANB0 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB0 ANB0 C18
—ANB1 PANB1 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB1 ANB1 D17
—ANB2 PANB2 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB2 ANB2 D18
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
36 Freescale Semiconductor
—ANB3 PANB3 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB3 ANB3 D19
—ANB4 PANB4 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB4 ANB4 C19
—ANB5 PANB5 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB5 ANB5 C20
—ANB6 PANB6 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB6 ANB6 B19
—ANB7 PANB7 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB7 ANB7 A20
—ANB8 PANB8 eQADC B analog input I AE VDDA_B0 ANB8 ANB8 B20
—ANB9 PANB9 eQADC B analog input I AE VDDA_B0 ANB9 ANB9 D20
—ANB10 PANB10 eQADC B analog input I AE VDDA_B0 ANB10 ANB10 B21
—ANB11 PANB11 eQADC B analog input I AE VDDA_B0 ANB11 ANB11 A21
—ANB12 PANB12 eQADC B analog input I AE VDDA_B0 ANB12 ANB12 C21
—ANB13 PANB13 eQADC B analog input I AE VDDA_B0 ANB13 ANB13 D21
—ANB14 PANB14 eQADC B analog input I AE VDDA_B0 ANB14 ANB14 A22
—ANB15 PANB15 eQADC B analog input I AE VDDA_B0 ANB15 ANB15 B22
—ANB16 PANB16 eQADC B analog input I AE VDDA_B0 ANB16 ANB16 C22
—ANB17 PANB17 eQADC B analog input I AE VDDA_B0 ANB17 ANB17 A23
—ANB18 PANB18 eQADC B analog input I AE VDDA_B0 ANB18 ANB18 B23
—ANB19 PANB19 eQADC B analog input I AE VDDA_B0 ANB19 ANB19 C23
—ANB20 PANB20 eQADC B analog input I AE VDDA_B0 ANB20 ANB20 D22
—ANB21 PANB21 eQADC B analog input I AE VDDA_B0 ANB21 ANB21 A24
—ANB22 PANB22 eQADC B analog input I AE VDDA_B0 ANB22 ANB22 B24
—ANB23 PANB23 eQADC B analog input I AE VDDA_B0 ANB23 ANB23 A25
— VRH_A PVRH_A ADC A Voltage reference high I
VDDINT
VRH_A VRH_A VRH_A A12
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 37
— VRL_A PVRL_A ADC A Voltage reference low I
VSSINT
VRL_A VRL_A VRL_A A11
— VRH_B PVRH_B ADC B Voltage reference high I
VDDINT
VRH_B VRH_B VRH_B A19
— VRL_B PVRL_B ADC B Voltage reference low I
VSSINT
VRL_B VRL_B VRL_B A18
— REFBYPCB PREFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B18
— REFBYPCA PREFBYPCA ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA REFBYPCA B11
— VDDA_A0 PVDDA_A Internal logic supply input I VDDE VDDA_A0 VDDA_A0 VDDA_A0 A9
— VDDA_A1 PVDDA_A Internal logic supply input I VDDE VDDA_A1 VDDA_A1 VDDA_A1 B9
— REFBYPCA1 PREFBYPCA1 ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA1 REFBYPCA1 A10
— VSSA_A1 PVSSA_A Ground I VSSE VSSA_A1 VSSA_A1 VSSA_A1 B10
— VDDA_B0 PVDDA_B Internal logic supply input I VDDE VDDA_B0 VDDA_B0 VDDA_B0 A16
— VDDA_B1 PVDDA_B Internal logic supply input I VDDE VDDA_B1 VDDA_B1 VDDA_B1 B16
— VSSA_B0 PVSSA_B Ground I VSSE VSSA_B0 VSSA_B0 VSSA_B0 B17
— REFBYPCB1 PREFBYPCB1 ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB1 REFBYPCB1 A17
FlexRay
248 FR_A_TX_
GPIO248 PFR_A_TX FlexRay A transfer O FS VDDE2 —/Up
(–/– for Rev.1
of the device)
—/Up
(–/– for Rev.1
of the device)
AD4
A1 —— —
A2 —— —
GGPIO248 GPIO I/O
249 FR_A_RX_
GPIO249 PFR_A_RX FlexRay A receive I FS VDDE2 —/Up
(–/– for Rev.1
of the device)
—/Up
(–/– for Rev.1
of the device)
AE3
A1 —— —
A2 —— —
GGPIO249 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
38 Freescale Semiconductor
250 FR_A_TX_EN_
GPIO250 PFR_A_TX_EN FlexRay A transfer enable O FS VDDE2 —/Up
(–/– for Rev.1
of the device)
—/Up
(–/– for Rev.1
of the device)
AF3
A1 —— —
A2 —— —
GGPIO250 GPIO I/O
251 FR_B_TX_
GPIO251 PFR_B_TX FlexRay B transfer O FS VDDE2 —/Up
(–/– for Rev.1
of the device)
—/Up
(–/– for Rev.1
of the device)
AD5
A1 —— —
A2 —— —
GGPIO251 GPIO I/O
252 FR_B_RX_
GPIO252 PFR_B_RX FlexRay B receive I FS VDDE2 —/Up
(–/– for Rev.1
of the device)
—/Up
(–/– for Rev.1
of the device)
AE4
A1 —— —
A2 —— —
GGPIO252 GPIO I/O
253 FR_B_TX_EN_
GPIO253 PFR_B_TX_EN FlexRay B transfer enable O FS VDDE2 —/Up
(–/– for Rev.1
of the device)
—/Up
(–/– for Rev.1
of the device)
AF4
A1 —— —
A2 —— —
GGPIO253 GPIO I/O
FlexCAN
83 CNTXA_TXDA_
GPIO83 PCNTXA FlexCAN A transmit O MH VDDEH4 —/Up —/Up AF19
A1 TXDA eSCI A transmit O
A2 —— —
GGPIO83 GPIO I/O
84 CNRXA_RXDA_
GPIO84 PCNRXA FlexCAN A receive I MH VDDEH4 —/Up —/Up AE19
A1 RXDA eSCI A receive I
A2 —— —
GGPIO84 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 39
85 CNTXB_PCSC3_
GPIO85 PCNTXB FlexCAN B transmit O MH VDDEH4 —/Up —/Up AD19
A1 PCSC3 DSPI C peripheral chip select O
A2 —— —
GGPIO85 GPIO I/O
86 CNRXB_PCSC4_
GPIO86 PCNRXB FlexCAN B receive I MH VDDEH4 —/Up —/Up AC19
A1 PCSC4 DSPI C peripheral chip select O
A2 —— —
GGPIO86 GPIO I/O
87 CNTXC_PCSD3_
GPIO87 PCNTXC FlexCAN C transmit O MH VDDEH4 —/Up —/Up AF20
A1 PCSD3 DSPI D peripheral chip select O
A2 —— —
GGPIO87 GPIO I/O
88 CNRXC_PCSD4_
GPIO88 PCNRXC FlexCAN C receive I MH VDDEH4 —/Up —/Up AE20
A1 PCSD4 DSPI D peripheral chip select O
A2 —— —
GGPIO88 GPIO I/O
246 CNTXD_
GPIO246 PCNTXD FlexCAN D transmit O MH VDDEH4 —/Up —/Up AD20
A1 —— —
A2 —— —
GGPIO246 GPIO I/O
247 CNRXD_
GPIO247 PCNRXD FlexCAN D receive I MH VDDEH4 —/Up —/Up AC20
A1 —— —
A2 —— —
GGPIO247 GPIO I/O
eSCI
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
40 Freescale Semiconductor
89 TXDA_
GPIO89 PTXDA eSCI A transmit O MH VDDEH1 —/Up —/Up M2
A1 —— —
A2 —— —
GGPIO89 GPIO I/O
90 RXDA _
GPIO90 PRXDA eSCI A receive I MH VDDEH1 —/Up —/Up M3
A1 —— —
A2 —— —
GGPIO90 GPIO I
91 TXDB_PCSD1_
GPIO91 PTXDB eSCI B transmit O MH VDDEH1 —/Up —/Up P1
A1 PCSD1 DSPI D peripheral chip select O
A2 —— —
GGPIO91 GPIO I/O
92 RXDB_PCSD5_
GPIO92 PRXDB eSCI B receive I MH VDDEH1 —/Up —/Up N1
A1 PCSD5 DSPI D peripheral chip select O
A2 —— —
GGPIO92 GPIO I/O
244 TXDC_ETRIG0_
GPIO244 PTXDC eSCI C transmit O MH VDDEH4 —/Up —/Up AF23
A1 ETRIG0 eQADC trigger input I
A2 —— —
GGPIO244 GPIO I/O
245 RXDC_
GPIO245 PRXDC eSCI C receive I MH VDDEH5 —/Up —/Up AD22
A1 —— —
A2 —— —
GGPIO245 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 41
DSPI
93 SCKA_PCSC1_
GPIO93 PSCKA DSPI A clock I/O MH VDDEH3 —/Up —/Up AD8
A1 PCSC1 DSPI C peripheral chip select O
A2 —— —
GGPIO93 GPIO I/O
94 SINA_PCSC2_
GPIO94 PSINA DSPI A data input I MH VDDEH3 —/Up —/Up AF7
A1 PCSC2 DSPI C peripheral chip select O
A2 —— —
GGPIO94 GPIO I/O
95 SOUTA_PCSC5_
GPIO95 PSOUTA DSPI A data output O MH VDDEH3 —/Up —/Up AD7
A1 PCSC5 DSPI C peripheral chip select O
A2 —— —
GGPIO95 GPIO I/O
96 PCSA0_PCSD2_
GPIO96 PPCSA0 DSPI A peripheral chip select I/O MH VDDEH3 —/Up —/Up AE6
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO96 GPIO I/O
97 PCSA1_
GPIO97 PPCSA1 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AC6
A1 —— —
A2 —— —
GGPIO97 GPIO I/O
98 PCSA2_
GPIO98 PPCSA2 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AC7
A1 —— —
A2 —— —
GGPIO98 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
42 Freescale Semiconductor
99 PCSA3_
GPIO99 PPCSA3 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AE7
A1 —— —
A2 —— —
GGPIO99 GPIO I/O
100 PCSA4_
GPIO100 PPCSA4 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AE5
A1 —— —
A2 —— —
GGPIO100 GPIO I/O
101 PCSA5_ETRIG1_
GPIO101 PPCSA5 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AD6
A1 ETRIG1 eQADC trigger input I
A2 —— —
GGPIO101 GPIO I/O
102 SCKB_
GPIO102 PSCKB DSPI B clock I/O MH VDDEH3 —/Up —/Up AE8
A1 —— —
A2 —— —
GGPIO102 GPIO I/O
103 SINB_
GPIO103 PSINB DSPI B data input I MH VDDEH3 —/Up —/Up AE9
A1 —— —
A2 —— —
GGPIO103 GPIO I/O
104 SOUTB_
GPIO104 PSOUTB DSPI B data output O MH VDDEH3 —/Up —/Up AF9
A1 —— —
A2 —— —
GGPIO104 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 43
105 PCSB0_PCSD2_
GPIO105 PPCSB0 DSPI B peripheral chip select I/O MH VDDEH3 —/Up —/Up AD9
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO105 GPIO I/O
106 PCSB1_PCSD0_
GPIO106 PPCSB1 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AC9
A1 PCSD0 DSPI D peripheral chip select I/O
A2 —— —
GGPIO106 GPIO I/O
107 PCSB2_SOUTC_
GPIO107 PPCSB2 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AF8
A1 SOUTC DSPI C data output O
A2 —— —
GGPIO107 GPIO I/O
108 PCSB3_SINC_
GPIO108 PPCSB3 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AD10
A1 SINC DSPI C data input I
A2 —— —
GGPIO108 GPIO I/O
109 PCSB4_SCKC_
GPIO109 PPCSB4 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AC8
A1 SCKC DSPI C clock I/O
A2 —— —
GGPIO109 GPIO I/O
110 PCSB5_PCSC0_
GPIO110 PPCSB5 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AF6
A1 PCSC0 DSPI C peripheral chip select I/O
A2 —— —
GGPIO110 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
44 Freescale Semiconductor
235 SCKC_SCK_C_LVDSP_
GPIO235 PSCKC DSPI C clock I/O MH +
LVDS VDDEH4 —/Up —/Up AD21
A1 SCK_C_LVDSP LVDS+ downstream signal positive
output clock O
A2 —— —
GGPIO235 GPIO I/O
236 SINC_SCK_C_LVDSM_
GPIO236 PSINC DSPI C data input I MH+
LVDS VDDEH4 —/Up —/Up AE22
A1 SCK_C_LVDSM LVDS– downstream signal negative
output clock O
A2 —— —
GGPIO236 GPIO I/O
237 SOUTC_SOUT_C_LVDSP_
GPIO237 PSOUTC DSPI C data output O MH+
LVDS VDDEH4 —/Up —/Up AF21
A1 SOUT_C_LVDSP LVDS+ downstream signal positive
output data O
A2 —— —
GGPIO237 GPIO I/O
238 PCSC0_SOUT_C_LVDSM_
GPIO238 PPCSC0 DSPI C peripheral chip select I/O MH+
LVDS VDDEH4 —/Up —/Up AE21
A1 SOUT_C_LVDSM LVDS– downstream signal negative
output data O
A2 —— —
GGPIO238 GPIO I/O
239 PCSC1_
GPIO239 PPCSC1 DSPI C peripheral chip select O MH VDDEH4 —/Up —/Up AC22
A1 —— —
A2 —— —
GGPIO239 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 45
240 PCSC2_GPIO240 PPCSC2 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AE23
A1 —— —
A2 —— —
GGPIO240 GPIO I/O
241 PCSC3_GPIO241 PPCSC3 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AD23
A1 —— —
A2 —— —
GGPIO241 GPIO I/O
242 PCSC4_GPIO242 PPCSC4 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AF24
A1 —— —
A2 —— —
GGPIO242 GPIO I/O
243 PCSC5_GPIO243 PPCSC5 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AE24
A1 —— —
A2 —— —
GGPIO243 GPIO I/O
Reset and Clocks
— RESET PRESET External reset input I MH VDDEH1 RESET/Up RESET/Up R2
230 RSTOUT PRSTOUT External reset output O MH VDDEH1 RSTOUT/Low RSTOUT/
High A3
212 BOOTCFG1_IRQ3_
GPIO212 PBOOTCFG1 Boot configuration I MH VDDEH1 BOOTCFG/
Down Input/Down N2
A1 IRQ3 External interrupt request I
A2 —— —
GGPIO212 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
46 Freescale Semiconductor
213 WKPCFG_NMI_
GPIO213 PWKPCFG Weak pull configuration input I MH VDDEH1 WKPCFG/Up Input/Up N3
A1 NMI Critical interrupt to core11 I
A2 —— —
GGPIO213 GPIO I
208 PLLCFG0_IRQ4_
GPIO208 PPLLCFG0 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up Input/Up R3
A1 IRQ4 External interrupt request I
A2 —— —
GGPIO208 GPIO I/O
209 PLLCFG1_IRQ5_
GPIO209 PPLLCFG1 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up Input/Up
(for Rev2 of
the device:
—/Up)
P2
A1 IRQ5 External interrupt request I
A2 SOUTD DSPI D data output O
GGPIO209 GPIO I/O
— PLLCFG2 PPLLCFG2 FMPLL mode configuration input I MH VDDEH1
PLLCFG/
Down PLLCFG/
Down
P3
—XTAL PXTAL Crystal oscillator output O
AE
VDD33 XTAL XTAL AC26
—EXTAL PEXTAL Crystal oscillator input I
AE
VDD33 EXTAL EXTAL AB26
214 ENGCLK PENGCLK EBI engineering clock output
Note: EXTCLK (External clock input)
selected through SIU register)
OFV
DDE2 ENGCLK/
Enabled ENGCLK/
Enabled AD1
JTAG and Nexus
(see footnote12 about resets)
—EVTI –13 EVTI Nexus event in I F VDDE2 —/Up EVTI/Up T4
227 EVTO
(the BAM uses this pin to
select if auto baud rate is on
or off)
–13 EVTO Nexus event out O F VDDE2 ABS/Up EVTO/HI U1
219 MCKO –13 MCKO Nexus message clock out O F VDDE2 O/Low Disabled14 T2
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 47
220 MDO0_GPIO220
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO015 Nexus message data out O F VDDE2 O/Low MDO0/Low U3
A1 —— —
A2 —— —
GGPIO220 GPIO I/O
221 MDO1_GPIO221
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO115 Nexus message data out O F VDDE2 O/Low —/Down U4
A1 —— —
A2 —— —
GGPIO221 GPIO I/O
222 MDO2_GPIO222
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO215 Nexus message data out O F VDDE2 O/Low —/Down V1
A1 —— —
A2 —— —
GGPIO222 GPIO I/O
223 MDO3_GPIO223
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO315 Nexus message data out O F VDDE2 O/Low —/Down V2
A1 —— —
A2 —— —
GGPIO223 GPIO I/O
75 MDO4_GPIO75
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO415 Nexus message data out O F VDDE2 O/Low —/Down V3
A1 —— —
A2 —— —
GGPIO75 GPIO I/O
76 MDO5_GPIO76
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO515 Nexus message data out O F VDDE2 O/Low —/Down V4
A1 —— —
A2 —— —
GGPIO76 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
48 Freescale Semiconductor
77 MDO6_GPIO77
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO615 Nexus message data out O F VDDE2 O/Low —/Down W1
A1 —— —
A2 —— —
GGPIO77 GPIO I/O
78 MDO7_GPIO78
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO715 Nexus message data out O F VDDE2 O/Low —/Down W2
A1 —— —
A2 —— —
GGPIO78 GPIO I/O
79 MDO8_GPIO79
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO815 Nexus message data out O F VDDE2 O/Low —/Down W3
A1 —— —
A2 —— —
GGPIO79 GPIO I/O
80 MDO9_GPIO80
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO915 Nexus message data out O F VDDE2 O/Low —/Down Y1
A1 —— —
A2 —— —
GGPIO80 GPIO I/O
81 MDO10_GPIO81
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO1015 Nexus message data out O F VDDE2 O/Low —/Down Y2
A1 —— —
A2 —— —
GGPIO81 GPIO I/O
82 MDO11_GPIO82
(GPIO function on this pin is
only available on Re v .2 of the
device)
–13 MDO1115 Nexus message data out O F VDDE2 O/Low —/Down Y3
A1 —— —
A2 —— —
GGPIO82 GPIO I/O
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 49
231 MDO12_GPIO231 –13 MDO1215 Nexus message data out O F VDDE2 O/Low —/Down AA1
A1 —— —
A2 —— —
GGPIO231 GPIO I/O
232 MDO13_GPIO232 –13 MDO1315 Nexus message data out O F VDDE2 O/Low —/Down AA2
A1 —— —
A2 —— —
GGPIO232 GPIO I/O
233 MDO14_GPIO233 –13 MDO1415 Nexus message data out O F VDDE2 O/Low —/Down AA3
A1 —— —
A2 —— —
GGPIO233 GPIO I/O
234 MDO15_GPIO234 –13 MDO1515 Nexus message data out O F VDDE2 O/Low —/Down Y4
A1 —— —
A2 —— —
GGPIO234 GPIO I/O
224 MSEO0 –13 MSEO015 Nexus message start/end out O F VDDE2 O/Low MSEO/HI U2
225 MSEO1 –13 MSEO115 Nexus message start/end out O F VDDE2 O/Low MSEO/HI T3
226 RDY –13 RDY Nexus ready output O F VDDE2 O/Low RDY/HI R4
—TCK –13 TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down AB2
—TDI –13 TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up AC2
228 TDO –13 TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up AB1
—TMS –13 TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up AB3
—JCOMP –13 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down R1
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
50 Freescale Semiconductor
— TEST —TEST Test mode select (not for customer
use) IFV
DDEH1 TEST/Down TEST/Down B4
— VDDSYN —VDDSYN Clock synthesizer power input I VDDE VDDSYN VDDSYN VDDSYN AD26
— VSSSYN —VSSSYN Clock synthesizer ground input I VSSE VDDSYN VSSSYN VSSSYN AA26
—VSTBY —VSTBY SRAM standby power input I VHV VDDEH1 VSTBY VSTBY M4
— REGSEL —REGSEL Selects regulator mode
(Linear/Switch mode) IAEV
DDREG REGSEL REGSEL W23
—REGCTL —REGCTL Regulator controller output to
base/gate of power transistor O
AE
VDDREG REGCTL REGCTL Y26
—VSSFL —VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL AB25
— VDDREG —VDDREG Source voltage for on-chip regulators
and Low voltage detect circuits I
VDDINT
VDDREG VDDREG VDDREG AA25
1The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not
have GPIO functionality, this number is the PCR number.
2The primary signal name is used as the pin label on the BGA map for identification purposes. Howe ver , the primary signal function is not available on all devices
and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.
3P/A/G stands for Primary/Alternate/GPIO. This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.
4Each line in the Function column corresponds to a separate signal function on the pin. F or all device I/O pins, the primary, alternate, or GPIO signal functions
are designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5MH = High voltage, medium speed
F = Fast speed
FS = Fast speed with slew
AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)
VHV = Very high voltage
6VDDE (fast I/O) and VDDEH (slow I/O) pow er supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V
(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.
7The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in
this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS —
Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are
off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates
the pin is enabled.
8The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the
pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
Table 2. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
State
during
RESET7
State
after
RESET8
Package
Location
(416)
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 51
9This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C.
10 During and just after POR negates , internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when
the system clock propagates through the device.
11 NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER re gisters.
12 Ne xus reset is different than system reset; MDO 1-11 are enab led when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO
and MCKO are also dependent on trace (RPM or FPM) being enabled.
13 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC.
SIU values have no effect on the function of these pins once enabled.
14 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).
15 Do not connect pin directly to a power supply or ground.
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor52
5 Electrical characteristics
This section contains detailed inform at ion on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the PXR40.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these
specifications will be met. Finalized specifications will be published after complete characterization and device qualifications
have been completed.
5.1 Maximum ratings
Table 3. Absolute maximum ratings1
Spec Characteristic Symbol Min Max Unit
1 1.2 V Core Supply Voltage VDD –0.3 2.0
2V
2 SRAM Standby Voltage VSTBY –0.3 6.4
3,4 V
3 Clock Synthesizer Voltage VDDSYN –0.3 5.3
4,5 V
4 I/O Supply Voltage (I/O buffers and predrivers) VDD33 –0.3 5.3
4,5 V
5 Analog Supply Voltage (reference to VSSA6)V
DDA7–0.3 6.4 3,4 V
6 I/O Supply Voltage (fast I/O pads) VDDE –0.3 5.3
4,5 V
7 I/O Supply Voltage (medium I/O pads) VDDEH –0.3 6.4
3,4 V
8 Voltage Regulator Input Supply Voltage VDDREG –0.3 6.4
3,4 V
9 Analog Reference High Voltage (reference to VRL8)V
RH9–0.3 6.4 3,4 V
10 VSS to VSSA8 Differential Voltage VSS –V
SSA –0.1 0.1 V
11 VREF Differential Voltage VRH –V
RL –0.3 6.4
3,4 V
12 VRL to VSSA Differential Voltage VRL –V
SSA –0.3 0.3 V
13 VDD33 to VDDSYN Differential Voltage VDD33 –V
DDSYN –0.1 0.1 V
14 VSSSYN to VSS Differential Voltage VSSSYN –V
SS –0.1 0.1 V
15 Maximum Digital Input Current 10 (per pin, applies to all
digital pins) IMAXD –3 11 3 11 mA
16 Maximum Analog Input Current 12 (per pin, applies to all
analog pins) IMAXA – 3 7 3
7,11 mA
17 Maximum Operating Temperature Range 13 – Die Junct ion
Temperature TJ–40.0 150.0 oC
18 Storage Temperature Range Tstg –55.0 150.0 oC
19 Maximum Solder Temperature 14
Pb-free package
SnPb package
Tsdr —
—260.0
245.0
oC
20 Moisture Sensitivity Level 15 MSL — 3 —
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 53
5.2 Thermal characteristics
1Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause perm anent damage to the device.
22.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining.
36.4 V for 10 hours cumulative time, 5.25 V +10% for time remaining.
4Voltage overshoots dur ing a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
55.3 V for 10 hours cumulative time, 3.60 V +10% for time remaining.
6PXR40 has two analog power supply pins on the pinout: VDDA_A and VDDA_B.
7PXR40 has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.
8PXR40 has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.
9PXR40 has two analog high reference voltage pins on the pinout: VRH_A an d VRH_B.
10 Total injection current for all pins must not exceed 25 mA at maximum operating voltage.
11 Injection current of ±5 mA allow ed for limited duration f or analog (ADC) pads and digital 5 V pads. The maximum accumulated
time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under
this stress condition.
12 Total injection current for all analog input pins must not exceed 15 mA.
13 Lifetime operation at these specification limits is not guaranteed.
14 Solder profile per CDF-AEC-Q100.
15 Moisture sensitivity per JEDEC test method A112.
Table 4. Thermal characteristics, 416-pin TEPBGA package1
1Thermal characteristics are targets based on simulation that are subject to change per device
characterization. This data is PRELIMINARY based on similar package used on other devices.
Characteristic Symbol Value Unit
Junction to Ambient 2,3 Natural Convection (Single layer board)
2Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specifi ca tion.
RJA 24 °C/W
Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p)
4Per JEDEC JESD51-6 with the board horizontal.
RJA 18 °C/W
Junction to Ambient (@200 ft./min., Single layer board) RJMA 19 °C/W
Junction to Ambient (@200 ft./min., Four layer board 2s2p) RJMA 14 °C/W
Junction to Board 5
5Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
RJB 9°C/W
Junction to Case 6
6Indicates the aver age thermal resistance between the die and the case top surf ace as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
RJC 6°C/W
Junction to Package Top 7 Natural Convection
7Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
JT 2°C/W
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor54
5.2.1 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ=T
A + (RJA * PD)Eqn. 1
where:
TA= ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the TEPBGA, these values can be dif ferent by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer boar d i s appr opr iate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to
ambient thermal resistance:
RJA =R
JC + RCA Eqn. 2
where:
RJA = junction to ambient thermal resistance (oC/W)
RJC = junction to case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounti ng arrangem e nt on prin ted circuit bo ard, or chan ge the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperatu re of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ=T
T + (JT x PD)Eqn. 3
where:
TT= thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured per J ESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling ef fects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 55
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
• C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
• G. Krom ann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53-58, March 1998.
• B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of Sem iTherm , San Diego, 1999, pp. 212 -220.
5.3 EMI (Electromagnetic Interference) characteristics
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go
to www.freescale.com and perform a keyword search for “radiated emissions.” The following tables list the values of the
device's radiated emissions operating behaviors.
Table 5. EMC radiat ed emissions operating behaviors: 416 BGA
Symbol Description Conditions fOSC
fSYS
Frequency
band (MHz) Level
(max.) Unit Notes
VRE_TEM Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
416 BGA
EBI off
CLK on
FM off
40 MHz crystal
264 MHz
(fEBI_CAL =66
MHz)
0.15–50 26 dBV1
1Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell
Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM
(GTEM) Cel l Method.
50–150 30
150–500 34
500–1000 30
IEC and SAE level I2
2I = 36 dBV
—1, 3
3Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
VRE_TEM Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
416 BGA
EBI off
CLK off
FM on4
4“FM on” = FM depth of ±2%
40 MHz crystal
264 MHz
(fEBI_CAL =66
MHz)
0.15–50 24 dBV1
50–150 25
150–500 25
500–1000 21
IEC and SAE level K5
5K = 30 dBV
—1,3
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor56
5.4 ESD characteristics
5.5 PMC/POR/LVI electrical specifications
Note: For ADC internal resource measurements, see Table 18 in Section 5.9.1 ADC internal resource measurements.
NOTE
In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”.
Table 6. ESD ratings1,2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits .
2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature follow ed by hot temperature, unless specified otherwise in the
device specification.
Spec Characteristic Symbol Value Unit
1 ESD for Human Body Model (HBM) VHBM 2000 V
2 ESD for Charged Device Model (CDM) VCDM 750 (corners)
500 (other) V
Table 7. PMC operating conditions
Name Parameter Condition Min Typ Max Unit Note
VDDREG Supply voltage VDDREG
5V nominal LDO5V / SMPS5V mode 4.5 5 5.5 V 1
1Voltage should be higher than maximum VLVDREG to avoid LVD event
VDDREG Supply voltage VDDREG
3V nominal LDO3V mode 3.0 3.3 3.6 V 1
VDD33 Supply voltage VDDSYN /
VDD33 3.3V nominal LDO3V mode 3.0 3.3 3.6 V 2
2Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. V oltage should be higher than maximum VLVD33 to avoid
LVD event
VDD Supply voltage VDD
1.2V nominal — 1.14 1.2 1.32 V 3
3Voltage should be higher than maximum VLVD12 to avoid LVD event
Table 8. PMC electrical specifications
ID Name Parameter Min Typ Max Unit
1V
BG Nominal bandgap reference voltage 0.608 0.620 0.632 V
1a — Untrimmed bandgap reference voltage VBG – 5% VBG VBG + 5% V
2V
DD12OUT Nominal VRC regulated 1.2V output VDD — 1.2 — V
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 57
2a — Untrimmed VRC 1.2V output variation before
band gap trim (unloaded)
Note: Voltage should be higher than maximum
VLVD12 to avoid LVD event
VDD12OUT – 8% VDD12OUT VDD12OUT + 17% V
2b — Trimmed VRC 1.2V output vari ation after band
gap tri m (REGC TL load max. 20mA, VDD load
max. 1A)1
VDD12OUT – 5% VDD12OUT VDD12OUT + 10% V
2c VSTEPV12 Trimming step VDD12OUT —10—mV
3V
PORC POR rising VDD 1.2V — 0.7 — V
3a — POR VDD 1.2V variation VPORC – 30% VPORC VPORC + 30%
3b — POR 1.2V hysteresis — 75 — mV
4V
LVD12 Nominal rising LVD 1.2V
Note: ~VDD12OUT × 0.87 — 1.100 — V
4a — Untrimmed LVD 1.2V variation before band gap
trim
Note: Rising VDD
VLVD12 – 6% VLVD12 VLVD12 + 6% V
4b — Trimmed LVD 1.2V variation after band gap trim
Rising VDD VLVD12 – 3% VLVD12 VLVD12 + 3% V
4c — LVD 1.2V Hysteresis 15 20 25 mV
4d VLVDSTEP12 Trimming step LVD 1.2V — 10 — mV
5I
REGCTL VRC DC current output on REGCTL — — 20 mA
6 — Voltage regulator 1.2V curren t consu mp tion
VDDREG —3—mA
7V
DD33OUT Nominal VREG 3.3V output — 3.3 — V
7a — Untrimmed VREG 3.3V output variation before
band gap trim (unloaded)
Note: Rising VDDSYN
VDD33OUT – 6% VDD33OUT VDD33OUT + 10% V
7b — Trimmed VREG 3.3V output variation after band
gap tri m (max. load 80mA) VDD33OUT – 5% VDD33OUT VDD33OUT + 10% V
7c VSTEPV33 Trimming step VDDSYN — 30 — mV
8V
LVD33 Nominal rising LVD 3.3V
Note: ~VDD33OUT × 0.872 — 2.950 — V
8a — Untrimmed LVD 3.3V variation before band gap
trim
Note: Rising VDDSYN
VLVD33 – 5% VLVD33 VLVD33 + 5% V
8b — Trimmed LVD 3.3V variation after bad gap trim
Note: Rising VDDSYN VLVD33 – 3% VLVD33 VLVD33 + 3% V
8c — LVD 3.3V Hysteresis — 30 — mV
8d VLVDSTEP33 Trimming step LVD 3.3V — 30 — mV
Table 8. PMC electrical specifications (continued)
ID Name Parameter Min Typ Max Unit
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor58
9I
DD33 VREG = 4.5 V, max DC output current
VREG = 4.25 V, max DC output current, crank
condition
Note: Max current supplied by VDDSYN that
does not cause it to drop below VLVD33
—
——
—80
40 mA
mA
10 — Voltage regul ator 3.3 V current consumption
VDDREG
Note: Except IDD33
—2—mA
11 VPORREG POR rising on VDDREG — 2.00 — V
11a — POR VDDREG variation VPORREG – 30% VPORREG VPORREG + 30% V
11b — POR VDDREG h y steresis — 250 — mV
12 VLVDREG Nominal rising LVD VDDREG
(LDO3V / LDO5V mode) — 2.950 — V
12a — Untrimmed LVD VDDREG variation before band
gap trim
Note: Rising VDDREG
VLVDREG – 5% VLVDREG VLVDREG + 5% V
12b — Trimmed LVD VDDREG variation after band gap
trim
Note: Rising VDDREG
VLVDREG – 3% VLVDREG VLVDREG + 3% V
12c — LVD VD DREG Hysteresis
(LDO3V / LDO5V mode) —30—mV
12d VLVDSTEPREG Trimming step LVD VDDREG
(LDO3V / LDO5V mode) —30—mV
13 VLVDREG Nominal rising LVD VDDREG
(SMPS5V mode) — 4.360 — V
13a — Untrimmed LVD VDDREG variation before band
gap trim
Note: Rising VDDREG
VLVDREG – 5% VLVDREG VLVDREG + 5% V
13b — Trimmed LVD VDDREG variation after band gap
trim
Note: Rising VDDREG
VLVDREG – 3% VLVDREG VLVDREG + 3% V
13c — LVD VD DREG Hysteresis
(SMPS5V mode) —50—mV
13d VLVDSTEPREG Trimming step LVD VDDREG
(SMPS5V mode) —50—mV
14 VLVDA Nominal rising LVD VDDA — 4.60 — V
14a — Untrimmed LVD VDDA variation before band
gap trim VLVDA – 5% VLVDA VLVDA + 5% V
14b — Trimmed LVD VDDA variation after band gap
trim VLVDA – 3% VLVDA VLVDA + 3% V
14c — LVD VD DA Hysteresis — 150 — mV
Table 8. PMC electrical specifications (continued)
ID Name Parameter Min Typ Max Unit
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 59
5.6 Power up/down sequencing
There is no power sequencing required among pow er sources during power up and power down in order to operate within
specification as long as the following two rules are me t:
• When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
• When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up
each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V fi rst, and then drop all VDDE/VDDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 9 and Table 10.
14d VLVDASTEP Trimming step LVD VDDA — 20 — mV
15 — SMPS regulator output resistance
Note: Pullup to VDDREG when high, pulldown
to VSSREG when low.
—1525Ohm
16 — SMPS regulator clock frequency (after reset) 1.0 1.5 2.4 MHz
17 — SMPS regulator overshoot at start-up2—1.321.4V
18 — SMPS maximum output current — 1.0 — A
19 — Voltage variation on current step2 (20% to 80%
of maximum current with 4 µsec constant time) ——0.1V
1VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 µA. Whe n using the
recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core
voltage is up to 1A.
2Parameter cannot be tested; this value is based on simulation and characterization.
Table 9. Power sequence pin states for MH and AE pads
VDD VDD33 VDDE MH Pad MH+LVDS Pads1
1MH+LVDS pads are output-only.
AE/up-down Pads
High High High Normal operation Normal operation Normal operation
— Low High Pin is tri-stated (output buffer ,
input buffer, and weak pulls
disabled)
Outputs driven high Pull-ups enabled,
pull-downs disabled
Low High Low Output low,
pin unpowered Outputs disabled Output low,
pin unpowered
Low High High Pin is tri-stated (output buffer ,
input buffer, and weak pulls
disabled)
Outputs disabled Pull-ups enabled,
pull-downs disabled
Table 8. PMC electrical specifications (continued)
ID Name Parameter Min Typ Max Unit
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor60
5.6.1 Power-up
If VDDE/VDDEH is powered up first, then a threshold detector tristates all dr ivers con nected to VDDE/VDDEH. There is no limit
to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can
be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit
the characteristics described in the next paragraph.
If VDD is powered up first, then all pads are loaded through the drain diodes to V DDE/VDDEH. This presents a heavy load that
pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current
injection specification. There is no li mi t to how long after VDD powers up befo re VDDE/VDDEH must power up .
The rise times on the power supplies are to be no faster than 25 V/milli second.
5.6.2 Power-down
If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD pow ers down before
VDDE/VDDEH must power down.
If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy
load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the
current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must po wer down.
There are no limits on the fall times for the power supplies.
5.6.3 Power sequencing and POR dependent on VDDA
During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any
forward-bi asing o f de vice di odes that caus es leakage current and/or POR. If the voltage dif ference between VDDA and VDDEH
is more than 1 V, the following will result:
• T riggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created,
when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect
level.
•If V
DDA is between 0–2 V, powering all the other segments (especially VDDEH1) will not be su fficient to get the part
out of reset.
• Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH –V
DDA – 1 V(diode drop)/200 KOhms)
up to (VDDEH/2 = VDDA +1V).
Table 10. Power sequence pin states for F and FS pads
VDD VDD33 VDDE F and FS pads
low low high Outputs drive high
low high — Outputs Disabled
high low lo w Outputs Disabled
high low high Outputs drive high
high h igh low Normal operation - except no drive current
and input buffer output is unknown.1
1The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pm os can be enabled.
high high high Nor mal Operation
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 61
• Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor
since VDD = 1.32 V max.
5.7 DC electrical specifications
Table 11. DC electrical specifications
Spec Characteristic Symbol Min Max Unit
1 Core Supply Voltage (External Regulation) VDD 1.14 1.321,2 V
1a Core Supply Voltage (Internal Regulation)3VDD 1.08 1.32 V
2 I/O Supply Voltage (fast I/O pads) VDDE 3.0 3.61,4 V
3 I/O Supply Voltage (medium I/O pads) VDDEH 3.0 5.251,5 V
4 3 .3 V I/O Buffer Voltage VDD33 3.0 3.61,4 V
5 Analog Supply Voltage VDD A 4.75 5.251,5 V
6a SRAM Standby Voltage
Keep-out Range: 1.2V–2V VSTBY_LOW 0.9561.2 V
6b SRAM Standby Voltage
Keep-out Range: 1.2V–2V VSTBY_HIGH 26V
7 Voltage Regulator Control Input Voltage7VDDREG 2.785.51,5 V
8 Clock Synthesizer Operating Voltage9VDDSYN 3.0 3.61,4 V
9 Fast I/O Input High Voltage
Hysteresis enabled
Hysteresis disabled
VIH_F 0.65 × VDDE
0.55 × VDDE
VDDE +0.3 V
10 Fast I/O Input Low Voltage
Hysteresis enabled
Hysteresis disabled
VIL_F V
SS –0.3 0.35 × VDDE
0.40 × VDDE
V
11 Medium I/O Input High Voltage
Hysteresis enabled
Hysteresis disabled
VIH_S 0.65 × VDDEH
0.55 × V
DDEH
VDDEH +0.3 V
12 Medium I/O Input Low Voltage
Hysteresis enabled
Hysteresis disabled
VIL_S V
SS –0.3 0.35 × VDDEH
0.40 × VDDEH
V
13 Fast I/O Input Hysteresis VHYS_F 0.1 × VDDE —V
14 Medium I/O Input Hysteresis VHYS_S 0.1 × VDDEH —V
15 Analog Input Voltage VINDC VSSA –0.1 V
DDA +0.1 V
16 Fast I/O Output High Voltage10 V
OH_F 0.8 × VDDE —V
17 Medium I/O Output High Voltage11 VOH_S 0.8 × VDDEH —V
18 Fast I/O Output Low Voltage10 VOL_F —0.2×V
DDE V
19 Medium I/O Output Low Voltage11 VOL_S —0.2×V
DDEH V
20 Load Capacitance (Fast I/O)12
DSC(PCR[8:9]) = 0b00
DSC(PCR[8:9]) = 0b01
DSC(PCR[8:9]) = 0b10
DSC(PCR[8:9]) = 0b11
CL—
—
—
—
10
20
30
50
pF
pF
pF
pF
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor62
21 Input Capacitance (Digital Pins) CIN —7pF
22 Input Capacitance (Analog Pins) CIN_A —10pF
24 Operating Current 1.2 V Supplies @ fsys = 264 MHz
VDD @1.32 V
VSTBY13 @1.2 V and 85oC
VSTBY @6.0 V and 85oC
IDD
IDDSTBY
IDDSTBY6
—
—
—
1.014
0.10
0.15
A
mA
mA
25 Operating Current 3.3 V Supplies @ fsys = 264 MHz
VDD3315
VDDSYN IDD33
IDDSYN
—
— note15
716 mA
mA
26 Operating Current 5.0 V Supplies @ fsys = 264 MHz
VDDA
Analog Reference Supply Current (Transient)
VDDREG
IDDA
IREF
IREG
—
—
—
5017
1.0
22
mA
mA
mA
27 Operating Current VDDE/VDDEH18 Supplies
VDDE2
VDDEH1
VDDEH3
VDDEH4
VDDEH5
VDDEH6
VDDEH7
IDD2
IDD1
IDD3
IDD4
IDD5
IDD6
IDD7
—
—
—
—
—
—
—
note18
mA
mA
mA
mA
mA
mA
mA
28 Fast I/O Weak Pull Up/Down Current19
3.0 V–3.6 V IACT_F 42 158 A
29 Medium I/O Weak Pull Up/Down Current20
3.0 V–3.6 V
4.5 V–5.5 V
IACT_S 15
35 95
200 A
A
30 I/O Input Leakage Cu rrent21 IINACT_D –2.5 2.5 A
31 DC Injection Current (per pin) IIC –1.0 1.0 mA
32 Analog Input Current, Channel Off22, AN[0:7], AN38,
AN39
Analog Input Current, Channel Off, all other analog
inputs AN[x]
IINACT_A –250
–150
250
150
nA
nA
33 VSS Differential Voltage VSS –V
SSA –100 100 mV
34 Analog Reference Low Voltage VRL V
SSA V
SSA +100 mV
35 VRL Differential Voltage VRL –V
SSA –100 100 mV
36 Analog Reference High Voltage VRH V
DDA –100 V
DDA mV
37 VREF Differential Voltage VRH –V
RL 4.75 5.25 V
38 VSSSYN to VSS Differential Voltage VSSSYN –V
SS –100 100 mV
39
Operating Temperature Range—Ambient (Packaged)
TA (TL to TH) –40.0 125.0 C
40 Slew rate on power supply pins — — 25 V/ms
Table 11. DC electrical specifications (continued)
Spec Characteristic Symbol Min Max Unit
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 63
41 Weak Pull-Up/Down Resistance23, 200 K Option RPUPD200K 130 280 k
42 Weak Pull-Up/Down Resistance23, 100 K Option RPUPD100K 65 140 k
43 Weak Pull-Up/Down Resistance23, 5 K Option RPUPD5K 1.4 7.5 k
44 Pull-Up/Down Resistance Matching Ratios24
(100K/200K) RPUPDMTCH –2.5 +2.5 %
1Voltage overshoots during a high-to -l ow or low-to-high transition must not exceed 10 seconds per instance.
22.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
3Assumed with DC load.
45.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
56.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
6VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode.
7Regulator is functional with derated performance, with supply v o ltage down to 4.0 V for system with VDDREG = 4.5 V (min).
82.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage
should be either VDDREG = 3.0 V (mi n) or 4.5 V (mi n) depending on the user regulation voltage system selected.
9Required to be supplied when 3.3 V regulator is disa bled. See Section 5.5 PMC/POR/LVI electrical specifications.
10 IOH_F = {16,32,47,77} mA and IOL_F = {24,48,71,115} m A for {00,01,10,11} drive mode with VDDE = 3.0 V. This spec is for
characterization only.
11 IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDE =4.5V;
IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDE = 3.0 V. These specs are for characterization only.
12 Applies to D_CLKOUT, external bus pins, and Nexus pins.
13 VSTBY current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction temperature
of 150 oC.
14 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization.
900 mA based on transistor count estimate at Worst Case (wcs) process and temperature condition.
15 Power requirements for the VDD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on
the I/O segments. See Section 5.7.2 I/O pad VDD33 current specifications, for information on both fast (F, FS) and medium (MH)
pads. Also refer to Table 13 for values to calculate power dissipation for specific operation.
16 This value is a target that is subject to change.
17 This value allows a 5 V reference to supply ADC + REF.
18 Power requirements for each I/O segment depend on the freq uency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. See Section 5.7.1 I/O pad current specifications, for information on I/O pad
power. Also refe r to Table 12 for values to calculate power dissipation for specific operation. The total power consumption of
an I/O segment is the sum of the individual power consumptions for each pin on the segment.
19 Absolute value of current, measured at VIL and VIH.
20 Absolute value of current, measured at VIL and VIH.
21 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH.
22 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half f or each
8to12oC, in the ambient temperature range of 50 to 125 oC . Applies to pad types AE and AE/up-down. See Section 4 Signal
properties and muxing.
23 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics
24 Pull-up and pull-down resistances are both enabled and settings are equal.
Table 11. DC electrical specifications (continued)
Spec Characteristic Symbol Min Max Unit
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor64
5.7.1 I /O pad current specifications
The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power
consumption is the sum of all outpu t pin curren ts for a particular segmen t. The output pin current can be calculated from
Table 12 based on the voltage, frequency , and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency ,
and load parameters that fall outside the values given in Table 12.
The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications.
5.7.2 I /O pad VDD33 current specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be
calculated from Table 13 dependent on the voltage, frequency , and load on all F type pins. The VDD33 current draw on medium
pads can be calculated from Table 13 dependent on voltage and independent on the frequency and load on all MH type pins.
Use linear scaling to calculate pin currents for volt a ge, frequency, and load parameters that fall outside the values given in
Table 13.
The AC timing of these pads are described in the Section 5.11.2 Pad AC specifications.
Table 12. VDDE/VDDEH I/O Pad Average DC Current1
1These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.
Spec Pad Type Symbol Frequency
(MHz) Load2
(pF)
2All loads are lumped.
Voltage
(V) Drive/Slew
Rate Select Current (mA)
1Medium I
DRV_MH 50 50 5.25 11 16.0
2 20 505.2501 6.3
3 3.0 50 5.25 00 1.1
4 2.0 200 5.25 00 2.4
5Fast I
DRV_FC 66 10 3.6 00 6.5
666203.6019.4
766303.61010.8
866503.61133.3
9 Fast w/ Slew
Control IDRV_FSR 66 50 3.6 11 12.0
10 50 50 3.6 10 6.2
11 33.33 50 3.6 01 4.0
12 20 50 3.6 00 2.4
13 20 200 3.6 00 8.9
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 65
5.7.3 LVDS pad specifications
LVDS pads are implement ed to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI
module.
Table 13. VDD33 Pad Average DC Current1
1These are av erage IDDE f or worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input
pins only for the medium pads.
Spec Pad Type Symbol Frequency
(MHz) Load2
(pF)
2All loads are lumped.
VDD33
(V) VDDE
(V) Drive/Slew
Rate Select Current (mA)
1MediumI
33_MH — — 3.6 5.5 — 0.0007
2FastI
33_FC 66 10 3.6 3.6 00 0.92
366203.63.6011.14
466303.63.6101.50
566503.63.6112.19
6Fast w/ Slew
Control I33_FSR 66 50 3.6 3.6 11 0.74
750503.63.6100.52
8 33.33 50 3.6 3.6 00 0.19
920503.63.6000.19
10 20 200 3.6 3.6 00 0.19
Table 14. DSPI LVDS pad specification
# Characteristic Symbol Condition Min.
Value Typ.
Value Max.
Value Unit
Data Rate
1 Data Frequency fLVDSCLK ——50—MHz
Driver Specs
2 Differential outpu t voltage VOD SRC=0b00 or 0b11 1 50 — 400 mV
SRC=0b01 90 — 320
SRC=0b10 160 — 480
3 Common mode voltage (LVDS),
VOS VOS — 1.06 1.2 1.39 V
4 Rise/Fall time TR/TF——2—ns
5 Propagation delay (Low to High) TPLH ——4—ns
6 Propagation delay (High to Low) TPHL ——4—ns
7 Delay (H/L), sync Mode tPDSYNC ——4—ns
8 Dela y, Z to Normal (High/Low) TDZ ——500—ns
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor66
5.8 Oscillator and FMPLL electrical characteristics
9 Diff Skew Itphla-tplhbI or
Itplhb-tphlaI TSKEW ———0.5ns
Termination
10 Trans. Line (differential Zo) — — 95 100 105 ohms
11 Temperature — — –40 — 150 C
Table 15. FMPLL Electrical Specifications 1
(VDDSYN = 3.0 V to 3.6 V, VSS =V
SSSYN =0V, T
A=T
L to TH)
1All values given are initial design targets and subject to change.
Spec Characteristic Symbol Min Max Unit
1 PLL Reference Frequency Range2 (Normal Mode)
Crystal Reference (PLLCFG2 = 0b0)
Crystal Reference (PLLCFG2 = 0b1)
Exter nal Reference (PLLCFG2 = 0b0)
Exter nal Reference (PLLCFG2 = 0b1)
2Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.
fref_crystal
fref_crystal
fref_ext
fref_ext
8
16
8
16
20
403
20
40
3Upper tolerance of less than 1% is allowed on 40MHz crystal.
MHz
2 Loss of Reference Freque ncy4
4“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clock ed mode.
fLOR 100 1000 kHz
3 Self Clocked Mode Frequency5
5Self clocked mode frequency is the frequency that the PLL operates at when the re ference frequency falls below fLOR. This
frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and
RFD values have no effect
fSCM 416MHz
4 PLL Lock Time6tLPLL — < 400 s
5 Duty Cycle of Reference 7 tDC 40 60 %
6 Frequency un-LOCK Range fUL –4.0 4.0 % fsys
7 Frequency LOCK Range fLCK –2.0 2.0 % fsys
8 D_CLKOUT Period Jitter8, 9 Measured at fSYS Ma x
Cycle-to-cycle Jitter CJitter –5 5 %fclkout
9
Peak-to-Peak Frequency Modulation Range Limit
10,11
(fsys Max must not be e xceeded) Cmod 04%f
sys
10 FM Depth Tolerance12 Cmod_err –0.25 0.25 %fsys
11 VCO Frequency fVCO 192 600 MHz
12 Modulation Rate Limits13 fmod 0.400 1 MHz
13 Predivider output frequency range14 fprediv 410MHz
Table 14. DSPI LVDS pad specification (continued)
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 67
6This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
7 For Flexray operation, duty cycle requirements are higher.
8Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable exter nal clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
9Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter +C
mod.
10 Modulation depth selected must not result in fpll value greater than the fpll maximum specified value.
11 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings availab le in
control register are: 2%, 3%, and 4% peak-to-peak.
12 Depth tolerance is the programmed modulation depth ±0.25% of Fsys. Violatin g th e VC O mi n/ ma x range ma y pr event the
system from e xiting reset.
13 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz
will result in reduced calibration accuracy.
14 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.
Table 16. Oscillator electrical specifications1
(VDDSYN = 3.0 V to 3.6 V, VSS =V
SSSYN =0V, T
A=T
L to TH)
1All values given are initial design ta rgets and subject to change.
Spec Characteristic Symbol Min Max Unit
1 Crystal Mode Differential Amplitude2
(Min differential voltage between EXTAL and XTAL )
2This parameter is meant f or those who do not use quartz crystals or resonators , but instead use CAN oscillators in crystal mode.
In that case, Vextal –V
xtal 400 mV criterion has to be met for oscillator’s comparator to produce output clock.
Vcrystal_diff_amp
| Vextal – Vxtal | > 0.4 V —V
2 Crystal Mode: Internal Differential Amplifier Noise
Rejection Vcrystal_diff_amp_nr —| Vextal – Vxtal | < 0.2 V V
3 EXTAL Input High Voltage
Bypass mode, External Reference VIHEXT
((V
DD33
/2) + 0.4 V)
—V
4 EXTAL Input Low Voltage
Bypass mode, External Reference VILEXT —
(V
DD33
/2) – 0.4 V
V
5 XTAL Curr en t3
3Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
IXTAL 13mA
6 Total On-chip stray capacitance on XTAL CS_XTAL —1.5 pF
7 Total On-chip stray capacitance on EXTAL CS_EXTAL —1.5 pF
8 Crystal manufacturer’s recommended capacitive load CL See crystal spec See crystal spec pF
9 Discrete load capacitance to be connected to EXTAL CL_EXTAL —
(2 × C
L
–C
S_EXTAL
–C
PCB_EXTAL4)
4CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
pF
10 Discrete load capacitance to be connected to XTAL CL_XTAL —
(2 × C
L
–C
S_XTAL
–C
PCB_XTAL4)
pF
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor68
5.9 eQADC electrical characteristics
Table 17. eQADC Conversion Specifications (Operating)
Spec Characteristic Symbol Min Max Unit
1 ADC Clock (ADCLK) Frequency fADCLK 216MHz
2 Conversion Cycles
Single Ended Conversion Cycles 12 bit resolution
Single Ended Conversion Cycles 10 bit resolution
Single Ended Conversion Cycles 8 bit resolution
Note: Differential conversion (min) is one clock
cycle less than the single-ended
conversion values listed here.
CC 2+14
2+12
2+10
128 + 14
128 + 12
128 + 10
ADCLK cycles
3 S top Mode Recovery Time1
1Stop mode recovery time is the time from the setting of ei th er of the enable bits in the AD C Control Register to th e ti me that
the ADC is ready to perform conversions. Delay from power up to full accur acy = 8 ms.
TSR 10 — s
4 Resolution2
2At VRH –V
RL = 5.12 V, one count = 1.25 mV without using pregain.
—1.25 — mV
5 INL: 8 MHz ADC Clock3
3INL and DNL are tested from VRL + 50 LSB to VRH – 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy
(12 bit resolution selected).
INL8 –44
4New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully
included.
44LSB5
5At VRH –V
RL = 5.12 V, one LSB = 1.25 mV.
6 INL: 16 MHz ADC Clock3INL16 –8484LSB
7 DNL: 8 MHz ADC Clock3DNL8 –3434LSB
8 DNL: 16 MHz ADC Clock3DNL16 –3434LSB
9 Offse t Error without Cali bration OFFNC 041004LSB
10 Offset Error with Calibration OFFWC –4444LSB
11 Full Scale Gain Error without Calibration GAINNC –120404LSB
12 Full Scale Gain Error with Calibration GAINWC –44,6
6The value is valid at 8 M Hz, it is ±8 counts at 16 Mhz.
44,6 LSB
13 Non-Disruptive Input Injection Current 7, 8, 9, 10
7Below disruptive current conditions, the channel being stressed has conv ersion v alues of $3FF for analog inputs greater than
VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions.
IINJ –3 3 m
14 Incremental Error due to injection current11, 12 EINJ –4444Counts
15 TUE value at 8 MHz 13 , 14 (with calibration) TUE8 –44,6 44,6 Counts
16 TUE value at 16 MHz 13, 14 (with calibration) TUE16 –8 8 Counts
17 Maximum differential voltage15
(DANx+ - DANx-) or (DANx- - DANx+)
PREGAIN set to 1X setting
PREGAIN set to 2X setting
PREGAIN set to 4X setting
DIFFmax
DIFFmax2
DIFFmax4
—
—
—
(VRH –V
RL)/2
(VRH –V
RL)/4
(VRH -V
RL)/8
V
V
V
18 Differential input Common mode voltage15
(DANx- + DANx+)/2 DIFFcmv (VRH –V
RL)/2
–5% (VRH –V
RL)/2
+5% V
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 69
5.9.1 AD C intern al resource measurements
8Exceeding limit ma y cause conv ersion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.
9Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP =V
DDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values.
10 Condition applies to two adjacent pins at injection limits.
11 Performance expected with production silicon.
12 All channels have same 10 k<Rs<100kChannel under test has Rs = 10 k, IINJ=IINJMAX,IINJMIN.
13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.
14 TUE does not apply to differential conversions.
15 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the
differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode
voltage of the differential signal violates the Differential Input common mode voltage specification.
Table 18. Power Management Control (PMC) specification
Spec Characteristic Symbol Min Typical Max Unit
PMC Normal Mode
1Bandgap 0.62 V
ADC0 channel 145 VADC145 — 0.62 — V
2Bandgap 1.2 V
ADC0 channel 146 VADC146 — 1.22 — V
3Vreg1p2 Feedback
ADC0 channel 147 VADC147 — VDD /2.045 — V
4LVD 1.2V
ADC0 channel 180 VADC180 — V
DD /1.774 — V
5 Vreg3p3 Feedback
ADC0 channel 181 VADC181 — Vreg3p3 / 5.460 — V
6LVD 3.3V
ADC0 channel 182 VADC182 — Vreg3p3 / 4.758 —V
7LVD 5.0V
ADC0 channel 183
— LDO mode
— SMPS mode
VADC183 —
VDDREG / 4.758
VDDREG/7.032
— V
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor70
Table 19. Standby RAM regulator electrical specifications
Spec Characteristic Symbol Min Typ Max Unit
Normal Mode
1 Standby Regulator Output
ADC1 channel 194 VADC194 —1.2 —V
2 Standby Source Bias
150 mV to 360 mV (30mV Increment @
vref_sel)
ADC1 channel 195
Default Value 150 mV (@vref_sel = 1 1 1)
VADC195 150 —360 mV
3 Standby Brownout Reference
ADC1 channel 195 VADC195 500 —850 mV
Table 20. ADC band gap reference / LVI electrical specifications
Spec Characteristic Symbol Min Typ Max Unit
1 4.75 LVD (from VDDA)
ADC1 channel 196 VADC196 —4.75 —V
2 ADC Bandgap
ADC0 channel 45
ADC1 channel 45
VADC45 1.171 1.220 1.269 V
Table 21. Temperature sensor electrical specifications
Spec Characteristic Symbol Min Typ Max Unit
1Slope
–40 C to 100 C ±1.0 C
100 C to 150 C ±1.6 C
ADC0 channel 128
ADC1 channel 128
V
SADC1281
1Slope is the measured voltage change per °C.
—5.8 —mV/ C
2 Accuracy
–40 C to 150 C
ADC0 channel 128
ADC1 channel 128
——
±10.0 —C
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 71
5.10 C90 flash memory electrical characteristics
Table 24 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the
device reference manual for definitions of these bit fields.
Table 22. Flash program and erase specifications
Spec Characteristic Symbol Min Typ1
1Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial
Max2
2Initial f actory condition: 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency.
Max3
3The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
Unit
1 Double Word (64 bits) Program Time4
4Program times are actual hardware programmin g times and do not include software overhead.
tdwprogram — 38 — 500 s
2 Page Program Time4,5
5Page size is 128 bits (4 words).
tpprogram — 45 160 500 s
3 16 KB Block Pre-program and Erase Time t16kpperase — 270 1000 5000 ms
4 64 KB Block Pre-program and Erase Time t64kpperase — 800 1800 5000 ms
5 128 KB Block Pre-program and Erase Time t128kpperase — 1500 2600 7500 ms
6 256 KB Block Pre-program and Erase Time t256kpperase — 3000 5200 15000 ms
Table 23. Flas h EEPROM module life
Spec Characteristic Symbol Min Typical1
1Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refe r to Engineering Bulletin EB619, Typical Endurance
for Nonvolatile Memory.
Unit
1 Number of program/erase cycles per block for 16 KB and 64
KB blocks over the operating temperature range (TJ)P/E 100,000 — cycles
2 Number of progr am/erase cycles per bloc k for 128 KB and 256
KB blocks over the operating temperature range (TJ)P/E 1,000 100,000 cycles
3 Mini mum Data Retention at 85 °C ambient temperature2
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
2Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
Retention 20
10
5
—
—
—
years
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor72
Table 24. PFCPR1 settings vs. frequency of operation1
1Illegal combinations exist. Use entries from the same row in this table.
Spec Clock
Mode
Maximum Frequency2
(MHz)
2This is the nominal maximum frequency of operation: platform runs at fsys/2 in Enhanced Mode .
APC =
RWSC WWSC DPFEN3
3For maximum flash performance, set to 0b1.
IPFEN3PFLIM4
4For maximum flash performance, set to 0b10.
BFEN5
5For maximum flash performance, set to 0b1.
Core
fsys
Platform
fplatf
1 Enhanced 264 MHz6
6This is the nominal maximum frequency of operation in Enhanced Mode. Max speed is the maximum speed
allowed including frequency modu lation (FM). 270 MHz parts allow f or 264 MHz system core clock(fsys)+2% FM
and 132 Mhz platform clock (fplatf)+ 2% FM.
132 MHz60b011 0b01 0b0
0b1 0b0
0b1 0b00
0b01
0b1x
0b0
0b1
2 Enhanced/
Full 200 MHz 100 MHz 0b010 0b01 0b0
0b1 0b0
0b1 0b00
0b01
0b1x
0b0
0b1
3 Legacy 132 MHz 132 MHz 0b100 0b01 0b0
0b1 0b0
0b1 0b00
0b01
0b1x
0b0
0b1
Default setting after reset: 0b111 0b11 0b00 0b00 0b00 0b0
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 73
5.11 AC specifications
5.11.1 Clocking
Figure 8 shows the operating frequency domains of various blocks on PXR40.
Figure 8. PXR40 bl ock operating frequency domain diagram
Table 25 shows the operating frequencies of various blocks depending on the device’ s clocking mode configuration settings (see
Table 26 and Table 27 for descriptions of bit settin gs).
Table 25. PXR40 operating frequencies1, 2
1The values in the table are specified at:
VDD = 1.02 V to 1.32 V
VDDE = 3.0 V to 3.6 V
VDDEH = 4.5 V to 5.5 V
VDD33 and VDDSYN = 3.0 V to 3.6 V
TA=T
L to TH.
Mode SIU_ECCR
[EBDF[0:1]]3fsys
(core)
fplatf
(platform and all blocks
except eTPU)
fetpu
(eTPU , eTPU RAM,
and NDEDI) febi_cal4,5 Unit
Enhanced 01
11 264
264 132
132 132
132 66
33 MHz
Full 01
11 200
200 100
100 200
200 50
25 MHz
Legacy 01
11 132
132 132
132 132
132 66
33 MHz
PLL
CORE
PLATFORM /
eTPU /
EBI
CAL BU S
EXTAL
D_CLKOUT
fplatf
Note: tcycsys = 1 / fsys
tcyc =1 / f
platf
2 = divide-by-2
X = divide-by-X, depending on SIU_SYSDIV[BYPASS]
and SIU_SYSDIV[SYSCLKDIV].
BLOCKS /
(D_CLKOUT is not available
on all packages and cannot
be programmed for faster
than fsys/2.)
2
PLLCFG[0:1]
SIU_SYSDIV[SYSCLKDIV[0:1]]
IPG DIV SEL
ETPU DIV SEL
SIU_SYSDIV[IPCLKDIV[0:1]]
fetpu
SYSDIV
X
FLASH
NDEDI
DIV febi_cal
SIU_SYSDIV[BYPASS]
X = 2, 4, 8, or 16
X=1
fsys
SIU_ECCR[EBDF[0:1]]
fperiph
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor74
5.11.2 Pad AC specifications
2Up to the maximum frequency rating of the device (refer to Table 39). The fsys speed is the nominal maximum frequency.
270 Mhz parts allow for 264 Mhz system clock + 2% FM.
3See the PXR40 Reference Manual for full description as not all bit combinations are valid.
4EBI/Calibration bus is not available in all packages.
5The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block’s max allowed
frequency of operation. Normally febi_cal =f
platf /2, but can be limited to < fplatf /2 in Full Mode.
Table 26. IPCLKDIV settings
SIU_SYSDIV
[IPCLKDIV[0:1]] Mode Description
00 Enhanced CPU frequency is doubled (Max 264Mhz). Platform,
peripheral, an d eTPU clocks are 1/2 of CPU frequency
01 Full CPU and eTPU frequency is doubled (Max 200Mhz).
Platform and peripheral clocks are 1/2 of CPU frequency.
10 — Reserved
11 Legacy CPU, eTPU, platform, and per ipheral’s clocks all run at
same speed (Max 132Mhz).
Table 27. SYSCLKDIV settings
SIU_SYSDIV
[SYSCLKDIV[0:1]] Description
00 Divide by 2.
01 Divide by 4.
10 Divide by 8.
11 Divide by 16.
Table 28. Pad AC specifications (vddeh = 5.0 V, VDDE =3.3V)
1
Spec Pad SRC/DSC Out Delay2,4
L
H/H
L (ns)
Rise/Fall3,4
(ns) Load Drive
(pF)
1Medium
500 152/165 70/74 50
2 205/220 96/96 200
3 01 28/34 12/15 50
4 52/59 28/31 200
5 11 12/12 5.3/5.9 50
6 32/32 22/22 200
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 75
7Fast
600
2.5 1.2
10
801 20
910 30
10 11 50
11 Fast with Slew Rate 00 40/40 16/16 50
12 50/50 21/21 200
13 01 13/13 5/5 50
14 19/19 8/8 200
15 10 8/8 2.4/2.4 50
16 12/12 5/5 200
17 11 5/5 1.1/1/1 50
18 8/8 2.6 2.6
19 Pull Up/Down (3.6 V max) — — 7500 50
20 Pull Up/Down (5.25 V max) — 6000 5000/5000 50
1These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH.
2This parameter is supplied for reference and is not guaranteed by design and not tested.
3This parameter is guaranteed by characterization before qualification rather than 100% tested.
4Delay and rise/fall are measured to 20% or 80% of the respe ctive signal.
5Out dela y is shown in Figure 9. Add a maximum of one system cloc k to the output dela y f or dela y with respect to system clock.
6Out dela y is shown in Figure 9. Add a maximum of one system cloc k to the output dela y f or dela y with respect to system clock.
Table 29. Derated pad AC specifications (VDDEH =3.3V)
1
1These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH.
Spec Pad SRC/DSC Out Delay2,3
L
H/H
L (ns)
2This parameter is supplied for reference and is not guaranteed by design and not tested.
3Delay and rise/fall are measured to 20% or 80% of the respective signal.
Rise/Fall4,3
(ns)
4This parameter is guaranteed by characterization before qualification rather than 100% tested.
Load Drive
(pF)
1 Medium5
5Out delay is sho wn in Figure 9. Add a maximum of one system cloc k to the output delay f or dela y with respect to system clock.
00 200/210 86/86 50
2 270/285 120/120 200
3 01 37/45 15.5/19 50
4 69/82 38/43 200
5 11 18/17 7.6/8.5 50
6 46/49 30/34 200
Table 28. Pad AC specifications (vddeh =5.0V, V
DDE =3.3V)
1 (continued)
Spec Pad SRC/DSC Out Delay2,4
L
H/H
L (ns)
Rise/Fall3,4
(ns) Load Drive
(pF)
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor76
Figure 9. Pad output delay
VDDEn / 2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
VDDEHn / 2
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 77
5.12 AC timing
5.12.1 Generic timing diagrams
The generic timing diagrams in Figure 10 and Figure 11 apply to all I/O pins with pad types F and MH. See 4, Signal properties
and muxing, for the pad type for each pin.
Figure 10. Generic output delay/hold timing
Figure 11. Generic input setup/hold timing
VDDE / 2
D_CLKOUT
A – Maximum Output Delay Time B – Minimum Output Hold Time
VDDEn / 2
A
B
I/O Outputs VDDEHn / 2
VDDE / 2
A
B
D_CLKOUT
VDDEn / 2
I/O Inputs
A – Minimum Input Setup Time B – Minimum Input Hold Time
VDDEHn / 2
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor78
5.12.2 Reset and configuration pin timing
Figure 12. Reset and configuration pin timing
5.12.3 IEEE 1149.1 interface timing
Table 30. Reset and configuration pin timing1
1Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA=T
L to TH.
Spec Characteristic Symbol Min Max Unit
1 RESET Pulse Width tRPW 10 — tcyc2
2See Notes on tcyc on Figure 8 and Table 25 in Section5.11.1Clocking.
2 RESET Glitch Detect Pulse Width t GPW 2—t
cyc2
3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc2
4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0—t
cyc2
Table 31. JTAG pin AC electrical characteristics1
Spec Characteristic Symbol Min Max Unit
1 TCK Cycle Time tJCYC 100 — ns
2 TCK Clock Pulse Width (Measured at VDDE / 2) tJDC 40 60 ns
3 TCK Rise and Fall Time s (40%–70%) tTCKRISE —3ns
4 TMS, TDI Data Setup Time tTMSS, tTDIS 5—ns
5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid tTDOV —10ns
1
2
RESET
RSTOUT
WKPCFG
PLLCFG
3
4
BOOTCFG
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 79
Figure 13. JTAG test clock input timing
7 TCK Low to TDO Data Invalid tTDOI 0—ns
8 TCK Low to TDO High Impedance tTDOHZ —20ns
9 JCOMP Assertion Time tJCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low tJCMPS 40 — ns
11 TCK Falling Edge to Output Valid tBSDV —50ns
12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ —50ns
13 TCK Falling Edge to Output High Impedance tBSDHZ —50ns
14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 — ns
1JTA G timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH, and
CL= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only . See Table 32 for functional
specifications.
Table 31. JTAG pin AC electrical characteristics1 (continued)
Spec Characteristic Symbol Min Max Unit
TCK
1
2
3
3
2
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor80
Figure 14. JTAG Test Access Port (TAP) timing
Figure 15. JTAG JCOMP timing
TCK
4
5
6
78
TMS, TDI
TDO
TCK
JCOMP
9
10
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 81
Figure 16. JTAG boundary scan timing
5.12.4 Nexus timing
Table 32. Nexus debug port timing1
Spec Characteristic Symbol Min Max Unit
1 MCKO Cycle Time tMCYC 228t
CYC3
2 MCKO Duty Cycle tMDC 40 60 %
3 MCKO Low to MDO Data Valid4tMDOV –0.1 0.2 tMCYC
4 MCKO Low to MSEO Data Valid4tMSEOV –0.1 0.2 tMCYC
5 MCKO Low to EVTO Data Va lid4tEVTOV –0.1 0.2 tMCYC
6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC3
7 EVTO Pulse Width tEVTOPW 1—t
MCYC
8 TCK Cycle Time tTCYC 45—t
CYC3
9 TCK Duty Cycle tTDC 40 60 %
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor82
Figure 17. Nexus timings
10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8— ns
11 TDI, TMS Data Hold Time TNTDIH, tNTMSH 5— ns
12 TCK Low to TDO Data Valid tNTDOV 010 ns
13 RDY Valid to MCKO6————
1All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified
at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH, and CL= 30 pF with
DSC = 0b10.
2The Nexus A UX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending
on the system frequency, not to exceed maximum Nexus AUX port frequency.
3See Notes on tcyc on Figure 13 and Table 25 in Section Section 5.11.1 Clocking.
4MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
5Lower frequency is required to be fully compliant to standard.
6The RDY pi n timing is asynchronous to MCKO. The timing is guaranteed by design to function correctl y.
Table 32. Nexus debug port timing1 (continued )
Spec Characteristic Symbol Min Max Unit
4
1
2
3
5
MCKO
MDO
MSEO
EVTO Output Data Valid
7
EVTI 6
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 83
Figure 18. Nexus TCK, TDI, TMS, TDO timing
TDO
10
11
TMS, TDI
12
TCK
8
9
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor84
5.12.5 External Bus Interface (EBI) timing
Table 33. Bus operation timing 1
Spec Characteristic Symbol 66 MHz (Ext. Bus Freq)2 3
Unit Notes
Min Max
1 D_CLKOUT Period tC15.2 — ns Signals are measured at 50% VDDE.
2 D_CLKOUT Duty Cycle tCDC 45% 55% tC
3 D_CLKOUT Rise Time tCRT ——
4ns
4D_CLKOUT Fall Time t
CFT ——
4ns
5 D_CLKOUT Posedge to Output
Signal Inv alid or High Z (Hold Time)
D_ADD[9:30]
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
tCOH 1.0/1.5 — ns Hold time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0: 1.0 ns
EBTS = 1: 1.5 ns
6 D_CLKOUT Posedge to Output
Signal Valid (Output Delay)
D_ADD[9:30]
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
tCOV — 7.0/7.5 ns Output valid time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0: 7.0 ns
EBTS = 1: 7.5 ns
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 85
Figure 19. D_CLKOUT timing
7 Input Signal Valid to D_CLKOUT
Posedge (Setup Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
tCIS 5.0/4.5 — ns Input setup time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0; 5.0ns
EBTS = 1; 4.5ns
8 D_CLKOUT Posedge to Input
Signal Invalid (Hold Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
tCIH 1.0 — ns
9 D_ALE Pulse Width tAPW 6.5 — ns The timing is f or Asynchronous
external mem ory system .
10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5— ns The timing is for Asynchronous
external mem ory system .
ALE is measured at 50% of VDDE.
1EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH, and
CL= 30 pF with DSC = 0b10.
2Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
3Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum e xternal b us frequency.
The maximum external bus frequency is 66 MHz.
4Refer to Fast pad timing in Table 28 and Table 29.
5ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0 C. 2.0 ns spec applies to
temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.
Table 33. Bus operation timing 1 (continued)
Spec Characteristic Symbol 66 MHz (Ext. Bus Freq)2 3
Unit Notes
Min Max
1
2
2
3
4
D_CLKOUT
VDDE / 2
VOL_F
VOH_F
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor86
Figure 20. Synchronous output timing
65
5
D_CLKOUT
Bus
5
Output
Signal
Output
VDDE / 2
VDDE / 2
VDDE / 2
6
5
Output
Signal VDDE / 2
6
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 87
Figure 21. Synchronous input timing
Figure 22. ALE signal timing
7
8
D_CLKOUT
Input
Bus
7
8
Input
Signal
VDDE / 2
VDDE / 2
VDDE / 2
ipg_clk
D_CLKOUT
D_ALE
D_TS
ADDR DATA
D_ADD/D_DAT
9
10
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor88
5.12.6 External interrupt timing (IRQ pin)
Figure 23. External interrupt timing
5.12.7 eTPU timing
Table 34. External inte rru pt timi n g1
1IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L
to TH.
Spec Characteristic Symbol Min Max Unit
1 IRQ Pulse Width Low tIPWL 3—t
cyc2
2See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking.
2 IRQ Pulse Width High tIPWH 3—t
cyc2
3 IRQ Edge to Edge Time3
3Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
tICYC 6—t
cyc2
Table 35. eTPU timing1
1eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and V DDSYN = 3.0 V to 3.6 V, TA=T
L to TH,
and CL= 200 pF with SRC = 0b00.
Spec Characteristic Symbol Min Max Unit
1 eTPU Input Channel Pulse Width tICPW 4—t
cyc2
2See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking.
2 eTPU Output Channel Pulse Width tOCPW 13
3This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
—t
cyc2
IRQ
12
3
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 89
Figure 24. eTPU timing
5.12.8 eMIOS timing
Table 36. eMIOS timing1
1eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH,
and CL= 50 pF with SRC = 0b00.
Spec Characteristic Symbol Min Max Unit
1 eMIOS Input Pulse Width tMIPW 4—t
cyc2
2See Notes on tcyc on Figure 8 and Table 25 in Section 5.11.1 Clocking.
2 eMIOS Output Pulse Width tMOPW 13
3This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
—t
cyc2
1
2
eTPU
Output
eTPU Input
and TCRCLK
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor90
Figure 25. eMIOS timing
5.12.9 DSPI timing
Table 37. DSPI timing1 2
Spec Characteristic Symbol Peripheral Bus Freq: 132 MHz Unit
Min Max
1 DSPI Cycle Time3, 4
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK tSYS * 2 tSYS*32768*7 ns
2 PCS to SCK Delay5tCSC 12 — ns
3 After SCK Delay6
Master mode
Slave mode
tASC tSYS * 2
tSYS *3 –
constraints 7
—ns
4 SCK Duty Cycle tSDC 0.33 * tSCK 0.66 * tSCK ns
5 Slave Access Time
(SS active to SOUT valid) tA—25 ns
6 Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid) tDIS —25 ns
7PCSx to PCSS time tPCSC tSYS * 2 tSYS * 7 ns
8PCSS
to PCSx time tPASC tSYS * 2 tSYS * 7 ns
1
2
eMIOS
Output
eMIOS Input
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 91
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.
9 Data Setup Time f or Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1 , CPHA = 0)8
Master (MTFE = 1 , CPHA = 1)
tSUI 20
4
6
20
—
—
—
—
ns
ns
ns
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1 , CPHA = 0)8
Master (MTFE = 1 , CPHA = 1)
tHI –3
7
12
–3
—
—
—
—
ns
ns
ns
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1 , CPHA = 0)
Master (MTFE = 1 , CPHA = 1)
tSUO —
—
—
—
5
25
13
5
ns
ns
ns
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1 , CPHA = 0)
Master (MTFE = 1 , CPHA = 1)
tHO –5
2.5
3
–5
—
—
—
—
ns
ns
ns
ns
1DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA=T
L to TH
2Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed all owed including
frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM.
3The minimum DSPI Cycle Time restricts th e baud rate selection f or given system clock rate . These numbers are calculated
based on two devices communicating over a DSPI link.
4The actual minimum SCK cycle time is limited by pad performance.
5The maximum v alue is programmabl e in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
6The maximum v alue is programmabl e in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
7For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS
8This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
Table 38. DSPI LVDS timing1, 2
1These are typical values that are estimated from simulation.
2See DSPI LVDS Pad related data in Table 14.
Characteristic Symbol Min Max Unit
LVDS Clock to Data/Chip Select Outputs tLVDSDATA –0.25 ×
tSCYC
+0.25 ×
tSCYC
ns
Table 37. DSPI timing1 2 (continued)
Spec Characteristic Symbol Peripheral Bus Freq: 132 MHz Unit
Min Max
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor92
Figure 26. DSPI classic SPI timing — Master, CPHA = 0
Figure 27. DSPI classic SPI timing — Master, CPHA = 1
Data Last Data
First Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output 4
9
12
1
11
10
4
SCK Output
(CPOL = 0)
(CPOL = 1)
3
2
Data Last Data
First Data
SIN
SOUT
12 11
10
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
9
(CPOL=0)
(CPOL=1)
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 93
Figure 28. DSPI classic SPI timing — Slave, CPHA = 0
Figure 29. DSPI classic SPI timing — Slave, CPHA = 1
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
PXR40 Microcontroller Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor94
Figure 30. DSPI modified transfer format timing — Master, CPHA = 0
Figure 31. DSPI modified transfer format timing — Master, CPHA = 1
PCSx3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL = 0)
(CPOL = 1)
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL = 0)
(CPOL = 1)
Electrical characteristics
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 95
Figure 32. DSPI modified transfer format timing — Slave, CPHA = 0
Figure 33. DSPI modified transfer format timing — Slave, CPHA = 1
Figure 34. DSPI PCS strobe (PCSS) timing
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
12
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
PCSx
78
PCSS
PXR40 Microcontroller Data Sheet, Rev. 1
Ordering information
Freescale Semiconductor96
6 Ordering information
6.1 Orderable parts
Figure 35 and Table 39 describe and list the orderable part numbers for the PXR40.
Figure 35. PXR40 orderable part number description
Table 39. PXR40 orderable part number summary
P art number Flash/SRAM P ackage Speed
(MHz)
MPXR4030VVU264 3 MB / 192 KB 416 PBGA (27 mm x 27 mm) 264
MPXR4040VVU264 4 MB / 256 KB 416 PBGA (27 mm x 27 mm) 264
MPX
40
Note: Not all options are available on all devices. See Table 39 for more information.
R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
V = –40 °C to 105 °C
Operating frequency
1 = 150 MHz
Tape and reel status
R = Tape and reel
(blank) = Trays
Qualification status
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
30
V
Temperature range
VU
Package identifier
264 R
Operating frequency
Tape and reel indicator
P ackage identifier
VU = 416 PBGA 2 = 180 MHz
(ambient)
Family
D = Display Graphics
N = Connectivity/Network
R = Performance/Real Time Control
S=Safety
Flash Memory Size
30 = 3 MB
40 = 4 MB
PXR40 Microcontroller Data Sheet, Rev. 1
Package information
Freescale Semiconductor98
Figure 37. 416 TEPBGA package (2 of 2)
Product documentation
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor 99
8 Product documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.freescale.com.
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
•PXR40 Microprocessor Reference Manual (document number PXR40RM).
9 Re vision history
Table 40 describes the changes made to this docum ent between revisions.
Table 40. Revision history
Revision Date Description of Changes
1 September 2011 Initial release: Technical Data
Document N umber : PXR40
Rev. 1
09/2011
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