1K/4K x36 x2 Bidirectional Synchronous
FIFO with Bus Matching
CY7C43644
CY7C43664
CY7C43684
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06022 Rev. *B Revised December 26, 2002
Features
• High-speed, low-power, bidirectional, First-In, First-Out
(FIFO) memories with bus matching capabilities
• 1K x36 x2 (CY7C43644)
• 4K x36 x2 (CY7C43664)
• 16K x36 x2 (CY7C43 684 )
• 0.35-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5 ns read/write
cycle times)
• Low power
—ICC = 100 mA
—ISB = 10 mA
• Fully asynchronous and simultaneous read and write
operation pe rmi tted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost-Full and
Almost-Empty flags
• Retransmit function
• Standard or FWFT mode user selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic Port B
Control
Logic
Mail 1
Register
Input
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable
Flag Offset Timing
Mode
Status
Flag Logic
Write
Pointer Read
Pointer
1K/4K/16K
Dual Ported
Memory
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail 2
Register
Output
Register
Input
Register
FIFO1,
Mail 1
Reset
Logic
FIFO1,
Mail 1
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0–35
EFA/ORA
AEA
MBF2
MRS2
PRS2
FFB/IRB
AFB
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
RTI
BE
BM
SIZE
EFB/ORB
AEB
MBF1
Output
Register
Bus Matching
36
36 Registers
x36
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 2 of 39
Selection Guide
CY7C43644/64/84
–7CY7C43644/64/84
–10 CY7C43644/64/84
–15 Unit
Maximum Frequency 133 100 66.7 MHz
Maximum Access Time 6 8 10 ns
Minimum Cycle Time 7.5 10 15 ns
Minimum Data or Enable Set-up 345ns
Minimum Data or Enable Hold 000ns
Maximum Flag Delay 688ns
Active Power Supply
Current (ICC1)Commercial 100 100 100 mA
Industrial 100
CY7C43644 CY7C43664 CY7C43684
Density 1K x 36 x2 4K x 36 x2 16K x 36 x2
Package 128 TQFP 128 TQFP 128 TQFP
CY7C43644
CY7C43664
CY7C43684
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
GND
MRS1
MBA
MBF2
AEA
AFA
VCC
PRS1
EFA/ORA
FFA/IRA
CSA
ENB
W/RB
CSB
GND
FFB/IRB
EFB/ORB
AFB
AEB
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
GND
GND
B32
B33
B34
B35
VCC
PRS2
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
BE/FWFT
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
RT2
A10
A11
GND
A13
A14
A15
A16
A17
Pin Configuration
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 3 of 39
Functional Description
The CY7C436X4 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
whic h supports clock frequ encies up to 133 MHz an d has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or
Little Endian configurations.
The CY7C436X4 is a synchronous (clocked) FIFO, meaning
each po rt em plo ys a sy nc hro nou s i nterface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coinc ide nt. T he e nab les for e ac h po rt are a rran ged to pro vi de
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Comm unicati on between ea ch port may bypas s the FIFO s via
two mailbox registers. The mailbox registers’ width matches
the sele cted Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X4: Master
Reset an d Partia l Rese t. Mas ter Rese t init ializes the rea d and
write pointers to the first location of the memory array,
config ures the FIFO for Big or Lit tle End ian byte arrang em ent
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
parti al flag default o ffsets) are retained. Partial Reset is u sef ul
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own,
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X4 have two modes of operation. In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first lon g-word (36-b it wide) writt en to an em pty FIFO ap pears
automatically on the outputs, no read operation required
(neverth eless , acc essin g subs equen t words d oes ne cess ita te
a form al rea d reque st). The state of the B E/FW FT pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard mode. EF indicates whether the
memory is full o r no t. The IR a nd OR fu nctio ns are s elec ted in
the First- Word Fall-Through mode. IR indicates whether or not
the FIFO has available m em ory l oc atio ns . O R shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.[1]
Each FIF O has a pro gra mm ab le Alm ost Em pty fl ag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state. ”[2]
IRA, IRB, AF A, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFB can be
loaded in parallel using Port A or in serial via the SD input.
Three default offset settings are also provided. The AEA and
AEB threshold can be set at 8, 16, or 64 locations from the
empty bou nd a ry an d A FA and AFB threshold can be set at 8,
16, or 64 locations from the full boundary . All these choices are
made using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
Retran sm it feat ure is av ail able on these devi ce s.
The CY7C436X4 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost
Empty Flag OProgrammable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register ,
X2. [2]
AEB Port B Almost
Empty Flag OProgrammable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register ,
X1. [2]
AFA Port A Almost
Full Flag OProgrammable Almost Full flag synchronized to CLKA. It is LOW when the nu mbe r
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.[2]
AFB Port B Almost
Full Flag OProgrammable Almost Full flag synchronized to CLKB. It is LOW when the nu mbe r
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the
boundary fl ag (e. g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deasse rtion. Refer
to “Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 4 of 39
B0–35 Port B Data I/O 36-bit bidirectional data port for side B.
BE/FWFT Big
Endian/First-
Word Fa ll-
Through
Select
IThis is a dual- purpose pin. Duri ng Mast er Rese t, a HIGH on BE will se lect Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first for A-to-B data flow. For data flowing from Port B to
Port A the first word/b yte written to Port B will come ou t as the most significan t word/byte
on Port A. A LOW on BE will select Little Endian operation. In this case, the least signif-
icant byte or word on Port A is transferred to Port B first for A-to-B data flow. Similarly,
the fist word/byte written into Port B will come out as the least significant word/byte on
Port A for B-to-A d ata flow. After Master Reset, this pi n selec ts the t iming m ode. A HIGH
on FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode.
Once th e timi ng mod e has b een sel ected , the lev el on t his pin must be s tat ic throu ghout
device operation.
BM Bus Match
Select (Port
A)
I A HIGH on this pin enables either byte or word bus width on Port B, depending on
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA Port A Clock ICLKA is a continuous clock that synchronizes all dat a transfers through Port A and
can be as yn chronous or coin ci dent to CLKB. FFA/IRA, EF A/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock ICLKB is a continuous clock that synchronizes all dat a transfers through Port B and
can be asyn chronous or coincident to CLKA. FF B/IRB, EFB/ORB, AF B, and A EB are al l
synchronized to the LOW-to-HIGH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/
Output Ready
Flag
OThis is a du al-function pin. In the CY St an dard mode, the E F A func tion is selec ted.
EFA indicates w he ther or not the FIFO2 mem ory is em pty. In the F WFT mode, the OR A
function is selected. ORA indicates the presence of valid data on A0–35 outputs, available
for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.[1]
EFB/ORB Port B Empty/
Output Ready
Flag
OThis is a dual-function pin. In the CY St andard mo de, the EFB function is selected.
EFB indica tes whethe r or not the FIFO1 memory is empt y. In the FWFT mode, t he ORB
function is selected. ORB indicates the presence of valid data on B0–35 outputs, available
for reading. EFB/ORB is synchronized to the LOW-to-HIGH tran sition of CLKB.[1]
ENA Port A Enable IENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB Port B Enable IENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
FFA/IRA Port A
Full/Input
Ready Flag
OThis is a dual-function pin. In the CY S tandard mode, the FF A function is selected. FF A
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is sel ected. IRA i ndicates whether or not there i s spa ce availab le for wr iting to th e FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB Port B
Full/Input
Ready Flag
OThis is a dual-function pin. I n the CY S tandard mode, th e FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function
is sel ected. IRB i ndicates whether or not there i s spa ce availab le for wr iting to th e FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 5 of 39
FS1/SEN Flag Offset
Select
1/Serial
Enable
IFS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, toge ther wi th SPM , select
the flag offset programming method. Three offset register programming methods are
availa ble : automatically load o ne of three preset value s (8 , 16 , or 6 4), parallel load fro m
Port A, or serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When F S1/SEN is LOW , a ri sing edge on C LKA loads the bit presen t on FS0/SD into the
X and Y re giste rs. The numb er of b it wri tes re quired to program the o ffs et reg isters is 40
for the CY7C43644, 48 for the CY7C43664, and 56 for the CY7C43684. The first bit write
stores the Y-register MSB and the last bit write stores the X-register LSB.
FS0/SD Flag Offset
Select
0/Serial Data
I
MBA Port A
Mailbox
Select
IA HIGH level on MBA chooses a mailbox register for a Port A read or write
operation. When a rea d operation is perform ed on Port A, a HIG H level on MBA select s
data from the Mail2 register for output and a LOW level selects FIFO2 output register data
for output. When a write operation is performed on Port A, a HIGH level on MBA will write
the data into Mail 1 register. While a LOW level will write the data into FIFO1.
MBB Port B
Mailbox
Select
IA HIGH level on MBB chooses a mailbox register for a Port B read or write
operation. When a rea d operation is perform ed on Port B, a HIG H level on MBB select s
data from the Mail1 register for output and a LOW level selects FIFO1 output register data
for output. When a write operation is performed on Port B, a HIGH level on MBB will write
the data into Mail 2 register, while a LOW level will write the data into FIFO2.
MBF1 Mail1
Register Flag OMBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Wr ites to the Mail1 re gister are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LO W-to-HIG H transitio n of CLKB when a Po rt B read is sel ected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 Mail2
Register Flag OMBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Wr ites to the Mail2 re gister are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LO W-to-HIG H transitio n of CLKA when a Po rt A read is sel ected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 FIFO1 Master
Reset IA LOW on this pin initial izes the F IFO1 read and wri te pointers t o the f irst locatio n of
memory and sets the Port B output regis ter to all zero es. A LOW pulse on MRS1 selects
the program ming me thod (seri al or pa rallel) an d one of three prog rammable flag defaul t
offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur
while MRS1 is LOW.
MRS2 FIFO2 Master
Reset IA LOW on this pin initial izes the F IFO2 read and wri te pointers t o the f irst locatio n of
memory and sets the Port A output regis ter to all zero es. A LOW pulse on MRS2 selects
one of three programmable flag de fault offs ets for FIFO2 . Four LOW -to-HIGH tra nsitions
of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
PRS1 FIFO1 Partial
Reset IA LOW on this pin initial izes the F IFO1 read and wri te pointers t o the f irst locatio n of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or parallel),
and programmab le fl ag set tings are all retained.
PRS2 FIFO2 Partial
Reset IA LOW on this pin initializes the FIFO 2 read and write pointers to the first location
of memory and sets the Port A output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RT1 Retransmit
FIFO1 IA LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by
bringing the read pointer back to location zero. The user will still need to perform read
operatio ns to retransmi t the data. Re transmit functi on applies to C Y standard mode only.
RT2 Retransmit
FIFO2 IA LOW strobe on this pin will retrans mit data on FIFO2. This is a chiev ed by brin ging
the read poin ter back to loc ation zero. The u ser will still need to p erfo rm rea d ope rations
to retransmit the data. Retransmit function applies to CY standard mode only.
SIZE Bus Size
Select IA HIGH on th is pin wh en BM is HIGH s elect s byte bu s (9-bit) size o n Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE
to select the bus size and endian arrangement for Port B. The level of SIZE must be static
throughout device operation.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 6 of 39
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X4 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW ,
the Empty/Output Ready flag (EF A/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
Reset must be performed on the FIFO after power up, before
data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latche s th e va lue of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X4 undergoes
a limited reset by taking its associated Partial Reset (PRS1,
PRS2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Partial
Reset inputs can switch asynchronously to the clocks. A
Partial Reset initializes the internal read and write pointers and
forces the Ful l/Input Rea dy flag (FF A/IRA, FFB/I RB) LOW, the
Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Partial Res et also force s the Ma ilbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currentl y selecte d at the time a Partial Res et is initiate d, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of big or little
endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B. (Note that when Port B is
configured for a long-word size, the Big Endian function has
no application and the BE input is a “Don’t Care”.)
A HIGH on th e BE/FWFT input when the Maste r Reset (MR S1
and MRS2) inputs go from LOW to HIGH will select a Big
Endian arrangement. When data is moving in the direction
from Port A to Port B, the most significant byte (word) of the
long word written to Port A will be transferred to Port B first;
the least significant byte (word) o f the long-word written to Port
A will b e tran sferred to Po rt B la st. Wh en da ta is m oving i n the
direction from Port B to Port A, the byte (word) written to Port
B first will be tra ns ferre d t o Po rt A as th e m os t s ignificant byte
(word) of the long-word; the byte (word) written to Port B last
will b e transferred to Port A as the leas t signifi cant byte (wor d)
of the long word.
A LOW on the BE/FWFT input when the Master Reset (RST1
and RST2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
the most significant byte (word) of the long-word written to Port
A will b e tran sferred to Po rt B la st. Wh en da ta is m oving i n the
direction from Port B to Port A, the byte (word) written to Port
B first wil l be tran sfe rred to Po rt A as th e le as t si gni fic an t by te
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the most significant byte (word)
of the long-word.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) mode.
Once the Master Reset (RST1, RST2) input is HIGH, a HIGH
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY
Standard mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal read operation.
Once the Master Reset (MRS1,MRS2) input is HIGH, a LOW
on the BE/FWFT input during the second LOW-to-HIGH
SPM Serial
Programming IA LOW on this pin selec ts serial p rogramming of p artial flag offs ets. A HIGH on this
pin selects parallel programming or default offsets (8, 16, or 64).
W/RA Port A
Write/Read
Select
IA HIGH se lect s a wri te operati on an d a LOW se lects a read ope ration on Po rt A for
a LOW- to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance state
when W/RA is HIGH.
W/RB Port B
Write/Read
Select
IA LOW sel ect s a w rite ope ration and a HIGH se lects a read opera tion on Po rt B for
a LOW- to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance state
when W/RB is LOW.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 7 of 39
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the da ta output s (A0–35 or B0–35). It also uses the Input Ready
function (IRA, IRB) to indicate whether or not the FIFO
memory has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must
be ac cessed by performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
through out the FIFO opera tio n.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X4 are used to hold the offset
values for th e Almo st Emp ty and Almost F ull fl ags. Th e Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset reg is ter is la bel ed
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see Table 1).
To l oad a FIFO’s Almost Emp ty flag and Al most Full fl ag offs et
registers with one of the three preset values listed in Table 1.
The Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1 and MRS2). For
example, to load the preset value of 64 into X1 and Y1, SPM,
FS0 and FS1 must be HIGH when FIFO1 reset (MRS1) returns
HIGH. Flag-offse t regi st ers ass oc ia ted w i th FIF O2 are l oad ed
with one of the preset values in the same way with Master
Reset (MRS2). When using one of the preset values for the
flag offsets, the FIFOs can be reset simultaneously or at
different times.
To program the X1, X2, Y1, and Y2 registers from Port A,
perform a Master Reset on both FIFOs simultaneously with
SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH
trans ition o f MRS1 a nd MR S2. After this reset is com plete, the
first fo ur writes to FIFO1 do no t store da ta in RA M but load the
offs et registers in the order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A0–9), (A0–11), or
(A0–13), for the CY7C436X4, respectively. The highest
numbered input is used as the most significant bit of the binary
number in each case. Valid programming values for the
registers range from 0 to 1023 for the CY7C43644; 0 to 4095
for the CY7C43664; 0 to 16383 fo r the CY7C43684. After all
the offset registers are programmed from Port A, the Port B
Full/In put Ready (FFB/IRB) is set HIG H and both F IFOs beg in
normal operation.
To pro gram the X1, X2, Y1, and Y2 registers seria lly, initiate a
Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN
HIGH during the LOW-to-HIGH transition of MRS1 and MRS2.
After this reset is complete, the X and Y register values are
loaded bit-wise through the FS0/SD input on each
LOW-to-HIGH transition of CLKA that the FS1/SEN input is
LOW. Forty, forty-eight, or fifty-six bit writes are needed to
comple te th e pr ogra mmin g for t he CY7 C436 X4, resp ect ively.
The four registers are written in the order Y1, X1, Y2, and,
finally, X2. The first-bit write stores the most significant bit of
the Y1 regis ter and the last-b it write stores the le ast significant
bit of the X2 reg ister. Each register valu e can be pro grammed
from 0 to 1023 for the CY7C43644; 0 to 4095 for the
CY7C43664; 0 to 16383 for the CY7C43684.
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FFA/IRA) flag remains
LOW until all regi ster bits are written. F FA/IRA is set HIGH by
the LOW -to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO1 operation. The Port B Full/Input ready
(FFB/IRB) flag also remains LOW throughout the serial
programming process, until all register bits are written.
FFB/IRB is set HIGH by the LO W-to-HIGH transitio n of C LKB
after the last bit is loaded to allow normal FIFO2 operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standa rd and FWFT mode s.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LOW-to -HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW , and FF A/IRA is HIGH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
tran si t io n of CL K A w h en C SA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2).
FIFO reads and writes on Port A are independent of any
concurrent Port B operation.
The Port B c ont rol s ig nal s a r e i den tic al to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Po rt B Write/ Read select (W/RB). The B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs whe n CSB
is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0–35 inputs on a
LOW-to -HIGH transition of CLKB when CSB is LOW, W/RB is
LOW , ENB is HIGH, MBB is LOW , and FFB/IRB is HIGH. Data
is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH
transiti on of CL KB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3).
FIFO reads and writes on Port B are independent of any
concurrent Port A operation.
The set-u p and hold tim e con st r ain t s to the po rt clocks for the
port Ch ip Select s and Wr ite/Read se lects are only for enab ling
write and read operations and are not related to
high-im pe dance control of t he d at a outputs. If a p ort e nab le i s
LOW during a clock cycle, the port’s Chip Select and
Write/Read select may change states during the set-up and
hold time window of the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the next word w ritten is a utoma ticall y se nt
to the FIFO’s output regist er by the LOW -to-HIGH trans ition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip
Select, Write/Read select, Enable, and Mailbox select.
When op erating the FIFO in CY S ta ndard mod e, regardle ss of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 8 of 39
when a read is selected using the port’s Chip Select,
Write/Read select, Enable, and Mailbox select.
Synch roniz ed FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is don e to improve f lag-signal reliability by
reducing the probability of the metastable ev ents when CLKA
and CLKB ope rate async hronousl y to one anothe r . EFA/ORA,
AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to
CLKB. Table 4 and Table 5 show the relati ons hi p of ea ch port
flag to FIFO1 and FIFO2.
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These a r e du al-p urp ose fla gs . In the FWFT Mode, the O ut put
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
register. When the Output ready flag is LOW , the previous data
word is present in the FIFO output register and attempted
FIFO reads are ignored. (See footnote #1)
In the CY S tandard mode, the Empty Flag (EF A, EFB) fun ction
is selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word is present
in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY S tandard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write poi nte r a nd read po in ter c om p a rator that indicates when
the FIFO SRAM status is empty, or empty+1.
In FWFT mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycle s hav e not elapse d si nce t he tim e th e wor d was wr it ten .
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data
availa bl e for rea di ng in a minim um of two c yc les of th e Empty
flag sy nchro nizin g cloc k. The refor e, an Em pty flag is LOW i f a
word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synch ron iz ing c loc k be gins the fi rst s ync hro ni zat ion cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard mode, the
Ful l Fl ag (F FA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Read y flag of a FIF O is sync hronized to the p ort
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
minimum of two cycles of the Full/Input Ready flag synchro-
nizing clock. Therefore, a Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock ha ve el apsed sinc e the ne xt me mory w rite locati on h as
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW -to-HIGH trans ition on a Fu ll/Input Rea dy flag synch ro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchroni zati on cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
sta tus is almo st empty, or almost em pty+1. The Alm ost Empty
state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag of fset program ming above). An Alm ost Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its
FIFO contains (X+1) or more words. [2]
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty fl ag to reflect th e new le vel of fill . Therefore, t he
Almost Empty flag of a FIFO containing (X+1) or more words
rema ins LOW if two cycl es of it s sy nchron izing clock hav e not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is sy nchronized to the port cl ock
that write s data to it s array . The st ate machine that controls an
Almost Full flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is
almos t full, or al most full–1 . The Alm ost Full st ate is def ined by
the contents of register Y1 for AFA and register Y2 for AFB.
These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 9 of 39
Almost Empty flag and Almost Full flag offset programming
above) . An Almost Full fla g is LOW when the nu mber of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X4 respectively. An Almost Full
flag is HIGH when th e numbe r of word s in it s FIFO is le ss than
or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for
the CY7C 43 6X4 respectively.[2]
Two LO W-to-HIGH tran si tio ns o f the Almost F ull f lag sy nc hro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words i n mem ory to [102 4/4096/16 384–(Y+1)]. An Al most Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1 024/4096/1638 4–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO h as a 36 -bit byp ass re gister to p ass comm and and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matc hes the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0–35 data to the
Mail1 Register when a Port A write is sel ected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
emplo ys data lines A0–35. If th e s ele cte d Po rt A bus size is 18
bits , then the usable w idth of the Ma il1 R eg is ter em plo ys da ta
lines A0–17. (In this case, A18–35 are “Don’t Care” input s.) If the
selec ted Port A bus si ze is 9 bits, then the usabl e width of the
Mail1 Register employs data lines A0–8. (In this case, A9–35 are
“Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0–35 data to the
Mail2 Register when a Port B write is sel ected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
emplo ys data lines B0–35. If th e s ele cte d Po rt B bus size is 18
bits , then the usable w idth of the Ma il2 R eg is ter em plo ys da ta
lines B0–17. (In t his ca se, B18–35 are “don’t ca re” inputs.) If the
selec ted Port B bus si ze is 9 bits, then the usabl e width of the
Mail2 Register employs data lines B0–8. (In this case, B9–35 are
“don’t care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW . Attemp ted writes to a ma il register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mai lb ox S ele ct input is HI GH.
The Mail1 Register Flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In th is c ase, B 18–35 are indetermi nate.) For a 9-b it bus
size, 9 bits of mailbox data are placed on B0–8. (In this ca se,
B9–35 are indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selec ted by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mailbox data are plac ed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be config ured in a 36- bit long -word, 18-b it
word, or 9-bit byte format for data read from FIFO1 or written
to FIFO2. The levels applied to the Port B Bus Size Select
(SIZE) and the Bus Match Select (BM) determine the Port B
bus size. These levels should be static throughout FIFO
operation. Both bus size selections are implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either
byte-or word-size. They are referred to as Big Endian (most
significant byte first) and Little Endian (least significant byte
first). The level applied to the Big Endian Select (BE) input
during the LOW-to-HIGH transition of MRS1 and MRS2
selects the endian method that will be active during FIFO
oper ation. BE is a d on’t ca re inpu t when the b us siz e sel ected
for Port B is lon g w ord . The e ndi an m eth od is imple me nte d at
the completion of Master Reset, by the time the Full/Input
ready flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7 C436X4. Bus-matching operat ions
are done after data is read from the FIFO1 RAM and before
data is written to th e FIFO2 RAM. Thes e bus-matc hing opera-
tions are not available when transferring data via mailbox
registers. Furthermore, both the word- and byte-size bus
selections limit the width of the data bus that can be used for
mail register operations. In this case, only those byte lanes
belonging to the selected word- or byte-size bus can carry
mailbox data. The remaining data outputs will be indeter-
minat e. The remain ing data inputs wi ll be “don’t care” inputs.
For example, when a word-size bus is selected, then mailbox
dat a ca n b e t r ans m itte d o nly be tween A0–17 and B0–17. When
a byte-size bus is selected, then mailbox data can be trans-
mitted only betwe en A0–8 and B0–8.
Bus-Matching FIFO1 Reads
Data is read from the FIFO1 RAM in 36-bit long-word incre-
ments. If a long-word bus size is implemented, the entire
long-word immediately shifts to the FIFO1 output register. If
byte or w or d s iz e i s im pl e me nt e d o n Po r t B, on ly th e fir st on e
or two bytes appear on the selected portion of the FIFO1
output register , with the rest of the long-word stored in auxiliary
registers. In this case, subsequent FIFO1 reads output the rest
of the long-word to the FIFO1 ou tput register.
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 10 of 39
When read ing data fro m FIFO1 in the byte or word fo rmat, the
unus ed B0–35 outputs are ind eter mi nate .
Bus-Match ing FIFO2 W r ite s
Data is written to the FIFO2 RAM in 36-bit long-word incre-
ments. Data written to FIFO2 with a byte or word bus size
stores the initial bytes or words in auxiliary registers. The
CLKB rising edge that writes the fourth byte or the second
word of the long-word to FIFO2 also stores the entire
long-word in FIFO2 RAM.
When reading data from FIFO2 in byte or word format, the
unus ed B0–35 outputs are LOW.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth min us 2/4/8 word s betwe en the rese t of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT1, (RT2) resets the int ernal read pointer to the first
physical location of the FIFO. CLKA and CLKB may be free
running but ENB, (ENA) must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer . Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT1, (RT2) are trans-
mitted also. The full depth of the FIFO can be repeatedly
retransmitted.
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 11 of 39
.
B27–35 B18–26 B9–17 B0–8
A
A27–35
B
A18–26
C
A9–17
D
A0–8
A
B27–35
B
B18–26
C
B9–17
D
B0–8
AB
CD
CD
A B
A
B
C
D
(a) LONG WORD SIZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD SIZE – LITTLE ENDIAN
(d) BYTE SIZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Write to FIFO
Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
BYTE ORDER ON
PORT A:
D
C
B
A
(e) BYTE SIZE – LITTLE ENDIAN
BE BM SIZE
LHH
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
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Table 1. Flag Program ming
SPM FS1/SEN FS0/SD MRS1 MRS2 X1 and Y1 Registers[3] X2 and Y2 Registers[4]
HHH↑X64 X
H0 H H X ↑X64
HHL↑X16 X
HHLX↑X16
HLH↑X8 X
HLHX↑X8
HLL↑↑Parallel programming via Port A Parallel programming via Port A
LHL↑↑Serial programming via SD Serial programming via SD
LHH↑↑ Reserved Reserved
LLH↑↑ Reserved Reserved
LLL↑↑ Reserved Reserved
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function
H X X X X In high-impe dance state None
L H L X X In high-impe dan ce state None
L H H L ↑In high-impedan ce st ate FIFO 1 write
L H H H ↑In hig h-im pe dan ce state Mail1 write
L L L L X Active, FIFO2 output register None
L L H L ↑Active, FIFO2 output register FIFO2 read
L L L H X Active, Ma il2 regis ter None
L L H H ↑Ac tiv e, Ma il2 regis ter Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L ↑In high-impedance state FIFO2 write
L L H H ↑In high-impedance state Mail2 write
L H L L X Active, FIFO1 output register None
L H H L ↑Active, FIFO1 output register FIFO1 read
L H L H X Active, Mail1 regi ster None
L H H H ↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes) [2]
Number of Words in FIFO Memory[5, 6, 7, 8] Synchronized to CLKB Synchronized to CLKA
CY7C43644 CY7C43664 CY7C43684 EFB/ORB AEB AFA FFA/IRA
0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 H L H H
Notes:
3. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
4. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
5. X 1 is the A lm os t Emp t y offset f or F IFO 1 u s ed by AE B. Y1 is the Almost Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
6. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
7. Data in the output register does not count as a “word i n FI FO m em o ry”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
8. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.
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Document #: 38-06022 Rev. *B Page 13 of 39
(X1+1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to 1638 3 H H L H
1024 4096 16384 H H L L
Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes) (continued)[2]
Table 5. FIFO2 Flag Operation (CY Standard and FWFT Modes)[2]
Number of Words in FIFO Memory[6, 7, 9, 10] Synchronized to CLKA Synchronized to CLKB
CY7C43644 CY7C43664 CY7C43684 EFA/ORA AEA AFB FFB/IRB
0 0 0 L L H H
1 TO X2 1 TO X2 1 TO X2 H L H H
(X2+1) to
[1024–(Y2+1)] (X2+1) to
[4096–(Y2+1)] (X2+1) to
[16384–(Y2+1)] HHHH
(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to 16383 H H L H
1024 4096 16384 H H L L
Table 6. Data Size for Long-Word Writes to FIFO2
Size Mode[11] Data Written to FIFO2 Data Read From FIFO2
BM SIZE BE B27–35 B18–26 B9–17 B0–8A27–35 A18–26 A9–17 A0–8
LXXABCDABCD
Table 7. Data Size for Word Writes to FIFO2
Size Mode[11] Write No. Data Written to FIFO2 Data Read From FIFO2
BM SIZE BE B9–17 B0–8A27–35 A18–26 A9–17 A0–8
H L H 1 A B A B C D
2 C D
H L L 1 C D A B C D
2 A B
Table 8. Data Size for Byte Writes to FIFO2
Size Mode[11] Write No. Data Written to
FIFO2 Data Read From FIFO2
BM SIZE BE B0–8A27–35 A18–26 A9–17 A0–8
H H H 1 A A B C D
2 B
3 C
4 D
H H L 1 D A B C D
2 C
3 B
4 A
Notes:
9. X2 is the Almost Empty offset for FIFO2 used by AEA. Y2 is the Almost Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
10. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.
11. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
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Table 9. Data Size for FIFO Long-Word Reads from FIFO1
Size Mode[11] Data Written to FIFO1 Data Read From FIFO1
BM SIZE BE A27–35 A18–26 A9–17 A0–8B27–35 B18–26 B9–17 B0–8
L X X A B C D A B C D
Table 10. Data Size for Word Reads form FIFO1
Size Mode[11] Data Written to FIFO1 Read No. Data Read From FIFO1
BM SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8
H L H A B C D 1 A B
2 C D
H L L A B C D 1 C D
2 A B
Table 11. Data Size for Byte Reads from FIFO1
Size Mode[11] Data Written to FIFO1 Read No. Data Read From
FIFO1
BM SIZE BE A27–35 A18–26 A9–17 A0–8B0–8
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
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Maximum Ratings[12,13]
(Abov e wh ic h th e us eful life may be i mpaired. For user gui de-
lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[14] ....................................–0.5V to VCC+0.5V
DC Input Voltage[14].................................–0.5V to VCC+0.5V
Output Current into Outpu t s (LO W)..................... ..... ...20 mA
Static Discharge Voltage..............................................>001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
AC Test Loads and Waveforms (–10 and –15)
Notes:
12. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to abso-
lute-maximum-rated conditions for extended periods may affect device reliability.
13. The Voltage on any input or I/O pin cannot exceed the power pin during power-up
14. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
15. Operating VCC Range for -7 speed is 5.0V ±0.25V.
16. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unlo ade d.
17. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
18. Tested initially and after any design or process changes that may affect these parameters.
Operating Range
Range Ambient
Temperature VCC[15]
Commercial 0°C to +70°C 5.0V ± 0.5V
Industrial –40°C to +85°C 5.0V ± 0.5V
Electri cal Characteristics Over the Operat ing Range
Parameter Description Test Conditions CY7C43644/64/84 UnitMin. Max.
VOH Output HIGH Voltage VCC = 4.5V ,
IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = 4.5V ,
IOL = 8.0 mA 0.5 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Volta ge –0.5 0.8 V
IIX Input Leaka ge Cu rren t VCC = Max. –10 +10 µA
IOZL
IOZH Output OFF, High-Z
Current VSS < VO< VCC –10 +10 µA
ICC1[16] Active Power Supply Current Com’l100 mA
Ind 100 mA
ISB[17] Avera ge Standby Current Com’l10 mA
Ind 10 mA
Capacitance[18]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 5.0V 4pF
COUT Output Capacitance 8pF
3.0V
5V
OUTPUT
R2 = 680Ω
CL = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1 = 1.1KΩ
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AC Test Loads and Waveforms (–7)
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
V
CC
/2
Z0=50Ω
Switching Characteristics Over the Operating Range
Parameter Description
CY7C43644/
64/84
–7
CY7C43644/
64/84
–10
CY7C43644/
64/84
–15 UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 133 100 67 MHz
tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
tDS Set-up Time, A0–35 before CLKA↑ and B0–35 before CLKB↑3 4 5 ns
tENS Set-up Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB,
W/RB, ENB, and MBB before CLKB↑3 4 5 ns
tRSTS Set-up Time, MRS1, MR S2, PRS1, PRS2, RT1 or RT2 LOW
before CLKA↑ or CLKB↑[19] 2.5 4 5 ns
tFSS Set-up Time, FS0 and FS1 before MRS1 and MRS2 HIGH 6 7 7.5 ns
tBES Set-up Time, BE/FWFT before MRS1 and MRS2 HIGH 5 7 7.5 ns
tSPMS Set-up Time, SPM before MRS1 and MRS2 HIGH 5 7 7.5 ns
tSDS Set-up Time, FS0/SD before CLKA↑3 4 5 ns
tSENS Set-up Time, FS1/SEN before CLKA↑3 4 5 ns
tFWS Set-up Time, BE/FWFT before CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after CLKB↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB,
W/RB, ENB, and MBB after CLKB↑0 0 0 ns
tRSTH Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW after
CLKA↑ or CLKB↑[19] 1 2 4 ns
tFSH Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH 1 1 2 ns
tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 1 1 2 ns
tSPMH Hold Time, SPM after MRS1 and MRS2 HIGH 1 1 2 ns
tSDH Hold Time, FS0/SD after CLKA↑0 0 0 ns
tSENH Hold Time, FS1/SEN after CLKA↑0 0 0 ns
tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS 2 HIGH 0 1 2 ns
tSKEW1[20] Skew Time between CLKA↑ and CLKB↑ for EFA/ORA,
EFB/ORB, FFA/IRA, and FFB/IRB 5 5 7.5 ns
tSKEW2[20] Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA,
AFB 7 8 12 ns
tAAccess Time, CLKA↑ to A0–35 and CLKB↑ to
B0–35 1 6 1 8 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to
FFB/IRB 1 6 1 8 2 8 ns
Notes:
19. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
20. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
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tREF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to
EFB/ORB 1 6 1 8 1 8 ns
tPAE Propagati on Delay Time, C LKA↑ to AEA and CLKB↑ to AEB 1 6 1 8 1 8 ns
tPAF Propagati on Delay Time, C LKA↑ to AFA and CLKB↑ to AFB 1 6 1 8 1 8 ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH
and CLKB↑ to MBF2 LOW or MBF1 HIGH 0 6 0 8 0 12 ns
tPMR Propagation Delay Time, CLKA↑ to B0–35[21] and CLKB↑ to
A0–35[22] 1 7 2 11 312 ns
tMDV Propagation Delay Time, MBA to A0–35 V alid and MBB to B0–35
Valid 1 6 2 9 3 11 ns
tRSF Propa gation Delay Time, MRS1 or PRS1 LOW to AEB LOW,
AFA HIGH, FFA/IRA LOW, EFB/ORB LOW and MBF1 HIGH
and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, FFB/IRB
LOW, EFA /ORA LOW and MBF2 HIGH
1 6 1 10 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active and CSB
LOW and W/RB HIGH to B0–35 Active 1 5 2 8 2 10 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High Impedance
and CSB HIGH or W/RB LOW to B0–35 at High Impedance 1 5 1 6 1 8 ns
tRTR Retransmit recovery Time 90 90 90 ns
Notes:
21. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
22. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
CY7C43644/
64/84
–7
CY7C43644/
64/84
–10
CY7C43644/
64/84
–15 UnitMin. Max. Min. Max. Min. Max.
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Document #: 38-06022 Rev. *B Page 18 of 39
Switching Waveforms
Notes:
23. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
24. PRS1 must be HIGH during Ma ster Rese t.
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKB
MRS1
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[23, 24]
tRSF
tRSF
FWFT
BE
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Notes:
25. Partial Reset is performed in the same manner for FIFO2.
26. MRS1 must be HIGH during Partial Reset.
27. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
28. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.
Switching Waveforms (continued)
FIFO1 Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS1
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[25, 26]
tWFF
tRSF
tRSF
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[28]
AFA Offs et (Y1) AFB Offset (Y2) First Word to FIFO1
CLKA
MRS1, MRS2
SPM
FS1/SEN,
FS0/SD
FFA/IRA
ENA
A0 − 35
CLKB
FFB/IRB
[27]
AEB Offset (X1 ) AEA Off set (X2)
tWFF
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Document #: 38-06022 Rev. *B Page 20 of 39
Notes:
29. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
30. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
31. If W/RA switches from read to write before the assertion of CSA, tENS = tDIS+tENS.
32. Written to FIFO1.
Switching Waveforms (continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tSKEW1[28
tWFF
AFA Offset (Y1) MSB
tFSS tFSH
tWFF
CLKA
MRS1,
MRS2
SPM
FFA/IRA
FS1/SEN
CLKB
FFB/IRB
[29]
FS0/SD [30]
AEA Of fset (X2) L SB
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[32] W2[32]
tCLK
CLKA
FFA/IRA
CSA
W/RA[31]
MBA
ENA
A0–35
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
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Document #: 38-06022 Rev. *B Page 21 of 39
Note:
33. If W/RB switches from read to write before the assertion of CSB, tENS = tDIS+tENS.
34. Written to FIFO2.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[34] W2[34]
tCLK
Port B Long-Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB
FFB/IRB
CSB
W/RB[33]
MBB
ENB
B0−35
tENS
tENS
tENS
tENS tENH
tENS tENH
tDS tDH
tENH
HIGH
tENH
CLKB
FFB/IRB
CSB
W/RB[33]
MBB
ENB
B0–17
Port B Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
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Document #: 38-06022 Rev. *B Page 22 of 39
Note:
35. Read fro m FIFO 1.
Switching Waveforms (continued)
Port B Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tENS
tENS
tENS tENH
tENS tENH
tDS tDH
tENS
tENH
HIGH
tENH
tENH
CLKB
FFB/IRB
CSB
W/RB[33]
MBB
ENB
B0–8
OR
tCLKH tCLKL
tENS
tDIS
tENS tENH
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[35] W2[35]
W1[35] W2[35]
W3[35]
Previous Data
No Operation
CLKB
EFB/ORB
CSB
W/RB[33]
MBB
ENB
B0–35
(Standard Mode)
B0–35
(FWFT Mode)
Port B Long-Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[1]
HIGH
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Document #: 38-06022 Rev. *B Page 23 of 39
Notes:
36. Unused word B18–35 contains all zeroe s for word-size reads.
37. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Switching Waveforms (continued)
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EFB/ORB
CSB
W/RB[33]
MBB
ENB
B0–17
(Standard Mode)
B0–17
(FWFT Mode)
Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[1, 37]
OR
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EFB/ORB
CSB
W/RB[33]
MBB
ENB
B0–8
(Standard Mode)
B0–8
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[1, 36]
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Document #: 38-06022 Rev. *B Page 24 of 39
Note:
38. Read fro m FIFO 2.
Switching Waveforms (continued)
OR
tCLKH tCLKL
tENS
tDIS
tENS tENH
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[38] W2[38]
W1[38] W2[38]
W3[38]
Previous Data
No Operation
CLKA
EFA/ORA
CSA
W/RA[31]
MBA
ENA
A0−35
(Standard Mode)
A0−35
(FWFT Mode)
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)[1]
HIGH
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Document #: 38-06022 Rev. *B Page 25 of 39
Notes:
39. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
40. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 outp ut
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Em pty
LOW
HIGH
LOW
Old Data in FIFO1 Output Register W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW[40]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A0–35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B0–35
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode) [1, 39]
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Document #: 38-06022 Rev. *B Page 26 of 39
Note:
41. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[41]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A0–35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B0–35
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY standard Mode) [39]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 27 of 39
Notes:
42. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively.
43. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 outp ut
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
W1
LOW
tDH
LOW
HIGH
FIFO2 Em pty
LOW
LOW
LOW
Old Data in FIFO2 Outpu t Register W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[43]
tCLK
tDS
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B0–35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0–35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode) [1, 42]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 28 of 39
Note:
44. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[44]
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B0–35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0–35
[42]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 29 of 39
Note:
45. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[45]
tDH
tDS
tENH
tENS
Previous Word in FIFO1 Next W ord From FIFO1
To FIFO1
CLKB
CSB
W/RB
MBB
ENB
EFB/ORB
B0–35
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0–35
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)[42]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 30 of 39
Note:
46. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[46]
tDH
tDS
tENH
tENS
Previous Word in FIFO1 Next W ord Fr om FIFO1
CLKB
CSB
W/RB
MBB
ENB
EFB/ORB
B0–35
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0−35
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)[42]
LOW
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 31 of 39
Notes:
47. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long-word, respectively.
48. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[48]
tDH
tDS
tENH
tENS
Previous Word in FIFO2 Next Word Fro m FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A0–35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B0–35
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)[47]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 32 of 39
Notes:
49. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long-word, respectively.
50. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[50
tDH
tDS
tENH
tENS
Previous Word in FIFO2 Out- Next W ord Fr om FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A0–35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B0–35
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)[49]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 33 of 39
Notes:
51. FIFO1 Write (CSA = LOW , W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has
been read from the FIFO.
52. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively .
53. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
54. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has
been read from the FIFO.
55. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
56. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Switching Waveforms (continued)
CLKA
ENA
CLKB
AEB
ENB
Timing for AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes)[51, 52, 2]
tPAE
tPAE
tENH
tENS
tSKEW2[53]
tENS tENH
X1 Wor d in FIFO1 (X1+1)Words in FIFO2
(X1+1) Words in FIFO1
CLKB
ENB
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[54, 56, 2]
tPAE
tPAE
tENH
tENS
tSKEW2[55]
tENS tENH
X2 Wor d in FIFO2 (X2+1) Words in FIFO2
(X2+1) Word in FIFO2
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 34 of 39
Notes:
57. D = Maximum FIFO Depth = 1K for the CY7C43644, 4K for the CY7C43664, and 16K for the CY7C43684.
58. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
59. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
60. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
CLKA
ENA
AFA
CLKB
ENB
[51, 56, 2, 57]
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO1 (D–Y1)Words in FIFO1
tSKEW2[58]
CLKB
ENB
AFB
CLKA
ENA
Tim ing f or AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)[54, 2, 57, 59]
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y2+1)] Words in FIFO2 (D–Y2)Words in FIFO2
tSKEW2[60]
[2]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 35 of 39
Note:
61. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have
valid data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 ar e “don’t care”
inputs). In this second case, B0–8 will have valid data (B9–35 will be indeterminate).
62. Simultaneous writing to and reading from the mailbox register is not allowed.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO1 Output Register W1 (Remains valid in Mail1 Register after
CLKA
CSA
W/RA[31]
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB[33]
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) [61,62]
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 36 of 39
Notes:
63. If Port B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 are “don’t care” inputs). In this first case A0–17 will have
valid data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 ar e “don’t care”
inputs). In this second case, A0–8 will have valid data (A9–35 will be indeterminate).
64. Retransmit is performed in the same manner for FIFO2.
65. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e. when RT1 is LOW and tRTR after the RT1 rising edge.
66. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
67. For the AEA, AEB, AFA, and AFB flags, two clock cycle are neces sa ry after tRTR to update these flags .
68. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial)
and the Retr ans mit s etup .
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid i n Mail2 Register after
CLKB
CSB
W/RB[33]
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA[31]
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Fl ag (CY Standard and FWFT Modes ) [63,62]
FIFO1 Retransmit Timing
ENB
RT1
tRTR
EFB/FFA
[64, 65, 66, 67, 68]
tRSTS tRSTH
CLKA
CLKB
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 37 of 39
Ordering Information
1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43644–7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43644–10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43644–15AC A128 128-Lead Thin Quad Flat Package Commercial
4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43664–7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43664–10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43664–15AC A128 128-Lead Thin Quad Flat Package Commercial
16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43684–7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43684–10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43684–15AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43684–15AI A128 128-Lead Thin Quad Flat Package Industrial
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 38 of 39
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagram
128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-*B
CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B Page 39 of 39
Document Title: CY7C43644/CY7C43664/CY7C43684 1K/4 K x36 x2 Bidirectional Synchronous FIFO with Bus Matching
Document Number: 38-06022
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 106564 05/14/01 SZV Change from Spec #: 38-00777 to 38-06022
*A 117173 08/27/02 OOR Added footnote to retransmit timing
Added note to retransmit section
*B 122274 12/26/02 RBI Power up requirements added to Maximum Ratings Information
