General-Purpose, Low Cost,
DC-Coupled VGA
AD8337
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Low noise
Voltage noise = 2.2 nV/√Hz
Current noise = 4.8 pA/√Hz (positive input)
Wide bandwidth (−3 dB) = 280 MHz
Nominal gain range: 0 dB to 24 dB (preamp gain = 6 dB)
Gain scaling: 19.7 dB/V
DC-coupled
Single-ended input and output
High speed uncommitted op amp input
Supplies: +5 V, ±2.5 V, or ±5 V
Low power: 78 mW with ±2.5 V supplies
APPLICATIONS
Gain trim
PET scanners
High performance AGC systems
I/Q signal processing
Video
Industrial and medical ultrasound
Radar receivers
FUNCTIONAL BLOCK DIAGRAM
V
OUTGAIN
INPP
2
3
5
PRAO
1
INPN
VCOM
+
–
7
AD8337
EIGHT SECTIONS
6
VNEG
V
POS
8
GAIN CONTROL
INTERFACE
8
18dB
PREAMP
(PrA)
4
05575-001
Figure 1.
GENERAL DESCRIPTION
The AD8337 is a low noise, single-ended, linear-in-dB, general-
purpose variable gain amplifier (VGA) usable at frequencies
from dc to 100 MHz; the −3 dB bandwidth is 280 MHz.
Excellent bandwidth uniformity across the entire gain range
and low output-referred noise makes the AD8337 ideal for
gain trim applications and for driving high speed analog-to-
digital converters (ADCs).
Excellent dc characteristics combined with high speed make the
AD8337 particularly suited for industrial ultrasound, PET
scanners, and video applications. Dual-supply operation enables
gain control of negative-going pulses, such as those generated
by photodiodes or photomultiplier tubes.
The AD8337 uses the popular and versatile X-AMP® architecture,
exclusively from Analog Devices, Inc., with a gain range of 24 dB.
The gain control interface provides precise linear-in-dB scaling
of 19.7 dB/V, referenced to VCOM.
The AD8337 includes an uncommitted operational current-
feedback preamplifier (PrA) that operates in inverting or
noninverting configurations. Using external resistors, the device
can be configured for gains of 6 dB or greater. The AD8337 is
characterized by a noninverting PrA gain of 2× using two external
100 Ω resistors. The attenuator has a range of 24 dB, and the
output amplifier has a fixed gain of 8× (18.06 dB). The lowest
nominal gain range is 0 dB to 24 dB and can be shifted up or down
by adjusting the preamp gain. Multiple AD8337 devices can be
connected in series for larger gain ranges, interstage filtering to
suppress noise and distortion, and nulling offset voltages.
The operating temperature range of the AD8337 is −40°C to
+85°C, and is available in an 8-lead, 3 mm × 3 mm LFCSP.
AD8337
Rev. C | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 14
Theory of Operation ...................................................................... 18
Overvie w ...................................................................................... 18
Preamplifier ................................................................................. 18
VGA .............................................................................................. 18
Gain Control ............................................................................... 18
Output Stage ................................................................................ 19
Attenuator .................................................................................... 19
Single-Supply Operation and AC Coupling ........................... 19
Noise ............................................................................................ 19
Applications Information .............................................................. 20
Preamplifier Connections ......................................................... 20
Driving Capacitive Loads .......................................................... 20
Gain Control Considerations ................................................... 21
Thermal Considerations ............................................................ 22
PSI (Ψ) ......................................................................................... 22
Board Layout ............................................................................... 22
Evaluation Boards ........................................................................... 23
Circuit Options ........................................................................... 24
Output Protection ...................................................................... 24
Measurement Setup.................................................................... 25
Board Layout Considerations ................................................... 25
Bill of Materials ........................................................................... 27
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
9/08—Rev. B to Rev. C
Changes to Table 1 ............................................................................ 3
Added Exposed Pad Note to Figure 2 and Table 3 ....................... 6
Changes to Figure 49 ...................................................................... 14
Changes to Evaluation Boards Section ........................................ 23
Changes to Circuit Options Section ............................................. 24
Changes to Output Protection Section ........................................ 24
Changes to Measurement Setup Section ..................................... 25
Changes to Board Layout Considerations Section ..................... 25
Changes to Bill of Materials Section ............................................ 27
Updated Outline Dimensions, Changes to Ordering Guide .... 29
2/07—Rev. A to Rev. B
Changes to Figure 30, Figure 31, and Figure 32 ......................... 11
Changes to Single-Supply Operation and
AC Coupling Section ..................................................................... 19
Moved Noise Section to Page ........................................................ 19
Changes to Ordering Guide .......................................................... 24
6/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Table 3 ............................................................................. 6
Changes to Figure 22, Figure 25, and Figure 26 ......................... 10
Changes to Figure 39 and Figure 40............................................. 13
Changes to Figure 74 and Figure 75............................................. 23
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
9/05—Revision 0: Initial Version
AD8337
Rev. C | Page 3 of 32
SPECIFICATIONS
VS = ±2.5 V, TA = 25°C, PrA gain = +2, VCOM = GND, f = 10 MHz, CL = 5 pF, RL = 500 Ω, including a 20 Ω snubbing resistor, unless
otherwise specified.
Table 1.
Parameter Conditions Min Typ Max Unit
GENERAL PARAMETERS
−3 dB Small Signal Bandwidth VOUT = 10 mV p-p 280 MHz
−3 dB Large Signal Bandwidth VOUT = 1 V p-p 100 MHz
Slew Rate VOUT = 2 V p-p 625 V/μs
V
OUT = 1 V p-p 490 V/μs
Input Voltage Noise f = 10 MHz 2.15 nV/√Hz
Input Current Noise f = 10 MHz 4.8 pA/√Hz
Noise Figure VGAIN = 0.7 V, RS = 50 Ω, unterminated 8.5 dB
V
GAIN = 0.7 V, RS = 50 Ω, shunt terminated with 50 Ω 14 dB
Output-Referred Noise VGAIN = 0.7 V (gain = 24 dB) 34 nV/√Hz
V
GAIN = −0.7 V (gain = 0 dB) 21 nV/√Hz
Output Impedance DC to 10 MHz 1 Ω
Output Signal Range RL ≥ 500 Ω, VS = ±2.5 V, +5 V VCOM ± 1.3 V
RL ≥ 500 Ω, VS = ±5 V VCOM ± 2.4 V
Output Offset Voltage VGAIN = 0.7 V (gain = 24 dB) −25 ±5 +25 mV
DYNAMIC PERFORMANCE
Harmonic Distortion VGAIN = 0 V, VOUT = 1 V p-p
HD2 f = 1 MHz −72 dBc
HD3 −66 dBc
HD2 f = 10 MHz −62 dBc
HD3 −63 dBc
HD2 f = 45 MHz −58 dBc
HD3 −56 dBc
Input 1 dB Compression Point VGAIN = −0.7 V, f = 10 MHz (preamp limited) 8.2 dBm
V
GAIN = +0.7 V, f = 10 MHz (VGA limited) −9.4 dBm
Two-Tone Intermodulation Distortion (IMD3) VGAIN = 0 V, VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz −71 dBc
V
GAIN = 0 V, VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −57 dBc
V
GAIN = 0 V, VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −58 dBc
V
GAIN = 0 V, VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz −45 dBc
Output Third-Order Intercept VGAIN = 0 V, VOUT = 1 V p-p, f = 10 MHz 34 dBm
V
GAIN = 0 V, VOUT = 1 V p-p, f = 45 MHz 28 dBm
V
GAIN = 0 V, VOUT = 2 V p-p, f = 10 MHz 35 dBm
V
GAIN = 0 V, VOUT = 2 V p-p, f = 45 MHz 26 dBm
Overload Recovery VGAIN = 0.75 V, VIN = 50 mV p-p to 500 mV p-p 50 ns
Group Delay Variation 1 MHz < f < 100 MHz, full gain range ±1 ns
AD8337
Rev. C | Page 4 of 32
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE VS = ±5 V
Harmonic Distortion VGAIN = 0 V, VOUT = 1 V p-p
HD2 f = 1 MHz −85 dBc
HD3 −75 dBc
HD2 f = 10 MHz −90 dBc
HD3 −80 dBc
HD2 f = 35 MHz −75 dBc
HD3 −76 dBc
Input 1 dB Compression Point VGAIN = −0.7 V, f = 10 MHz 14.5 dBm
V
GAIN = +0.7 V, f = 10 MHz −1.7 dBm
Two-Tone Intermodulation Distortion (IMD3) VGAIN = 0 V, VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz −74 dBc
V
GAIN = 0 V, VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −60 dBc
V
GAIN = 0 V, VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −64 dBc
V
GAIN = 0 V, VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz −49 dBc
Output Third-Order Intercept VGAIN = 0 V, VOUT = 1 V p-p, f = 10 MHz 35 dBm
V
GAIN = 0 V, VOUT = 1 V p-p, f = 45 MHz 28 dBm
V
GAIN = 0 V, VOUT = 2 V p-p, f = 10 MHz 36 dBm
V
GAIN = 0 V, VOUT = 2 V p-p, f = 45 MHz 28 dBm
Overload Recovery VGAIN = 0.7 V, VIN = 0.1 V p-p to 1 V p-p 50 ns
ACCURACY
Absolute Gain Error −0.7 V < VGAIN < −0.6 V 0.7 to 3.5 dB
−0.6 V < VGAIN < −0.5 V −1.25 ±0.35 +1.25 dB
−0.5 V < VGAIN < +0.5 V −1.0 ±0.25 +1.0 dB
0.5 V < VGAIN < 0.6 V −1.25 ±0.35 +1.25 dB
0.6 V < VGAIN < 0.7 V −0.7 to −3.5 dB
GAIN CONTROL INTERFACE
Gain Scaling Factor −0.6 V < VGAIN < +0.6 V 19.7 dB/V
Gain Range 24 dB
Intercept VGAIN = 0 V 12.65 dB
Input Voltage (VGAIN) Range No foldover −VS +VS V
Input Impedance 70 MΩ
Bias Current −0.7 V < VGAIN < +0.7 V 0.3 μA
Response Time 24 dB gain change 200 ns
POWER SUPPLY
Supply Voltage VPOS to VNEG (dual- or single-supply operation) 4.5 5 10 V
VS = ±2.5 V
Quiescent Current Each supply (VPOS and VNEG) 10.5 15.5 23.5 mA
Power Dissipation No signal, VPOS to VNEG = 5 V 78 mW
PSRR VGAIN = 0.7 V, f = 1 MHz −40 dB
VS = ±5 V
Quiescent Current Each supply (VPOS and VNEG) 13.5 18.5 25.5 mA
Power Dissipation No signal, VPOS to VNEG = 10 V 185 mW
PSRR VGAIN = 0.7 V, f = 1 MHz −40 dB
AD8337
Rev. C | Page 5 of 32
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage
Supply Voltage (VPOS, VNEG) ±6 V
Input Voltage (INPx) VPOS, VNEG
GAIN Voltage VPOS, VNEG
Power Dissipation
(Exposed Pad Soldered to PCB)
866 mW
Temperature
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Thermal Data, 4-Layer JEDEC Board
No Air Flow Exposed Pad Soldered to PCB
θJA 75.4°C/W
θJB 47.5°C/W
θJC 17.9°C/W
ΨJT 2.2°C/W
ΨJB 46.2°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8337
Rev. C | Page 6 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
4
3
2
INPN
VOUT
VCOM
INPP
PIN 1
AD8337
VPOS
PRAO
VNEG
GAIN
8
7
6
5
TOP VIEW
(Not to Scale)
05575-002
NOTES
1. FOR BEST THERMAL PERFORMANCE, EXPOSED PAD
MUST BE SOLDERED TO PCB.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT VGA Output.
2 VCOM Common Ground When Using Plus and Minus Supply Voltages. For single-supply operation, provide half the
positive supply voltage at the VPOS pin to VCOM pin.
3 INPP Positive Input to Preamplifier.
4 INPN Negative Input to Preamplifier.
5 PRAO Preamplifier Output.
6 VNEG Negative Supply (−VPOS for Dual-Supply; GND for Single-Supply).
7 GAIN Gain Control Input Centered at VCOM.
8 VPOS Positive Supply.
EP Exposed Pad For best thermal performance, exposed pad must be soldered to PCB.
AD8337
Rev. C | Page 7 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±2.5 V, TA = 25°C, RL = 500 Ω, including a 20 Ω snubbing resistor, f = 10 MHz, CL = 2 pF, VIN = 10 mV p-p, noninverting
configuration, unless otherwise noted.
GAIN (dB)
–5
25
10
0
20
30
–800
5
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
15
+85°C
+25°C
–40°C
05575-003
Figure 3. Gain vs. VGAIN at Three Temperatures
(See Figure 44)
1.5
0
2.0
–800
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
–2.0
–0.5
0.5
GAIN ERROR (dB)
–1.0
1.0
–1.5
+85°C
+25°C
–40°C
05575-004
Figure 4. Gain Error vs. VGAIN at Three Temperatures
(See Figure 44)
GAIN ERROR (dB)
0–800
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
–0.5
0.5
RELATIVE TO BEST FIT
LINE FOR 10MHz
–2.0
2.0
–1.5
1.5
–1.0
1.0
f = 1MHz
f = 10MHz
f = 70MHz
f = 100MHz
f = 150MHz
05575-005
Figure 5. Gain Error vs. VGAIN at Five Frequencies
(See Figure 44)
GAIN ERROR (dB)
0
30
50
20
40
10
0
60
0.4
0.3
0.1
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
% OF UNITS
500 UNITS
V
GAIN
= –0.4V
V
GAIN
=0V
V
GAIN
= +0.4V
05575-006
Figure 6. Gain Error Histogram for Three Values of VGAIN
GAIN SCALING (dB/V)
0
30
50
20
40
10
19.7 20.120.019.919.819.619.3 19.4 19.5
% OF UNITS
500 UNITS
–0.4V ≤ V
GAIN
≤ +0.4V
05575-007
Figure 7. Gain Scaling Histogram
INTERCEPT (dB)
0
30
50
20
40
10
12.6 13.012.912.812.712.512.2 12.3 12.4
% OF UNITS
500 UNITS
05575-008
Figure 8. Intercept Histogram
AD8337
Rev. C | Page 8 of 32
30
–5
100k 500M
05575-009
FREQUENCY (Hz)
GAIN (dB)
1M 10M 100M
25
20
15
10
5
0
V
GAIN
= –0.7
V
GAIN
= –0.5
V
GAIN
= –0.2
V
GAIN
= 0
V
GAIN
= +0.2
V
GAIN
= +0.5
V
GAIN
= +0.7
e
IN
= 10mV p-p
Figure 9. Frequency Response for Various Values of VGAIN
(See Figure 45)
20
–15
100k 500M
05575-010
FREQUENCY (Hz)
GAIN (dB)
1M 10M 100M
15
10
5
0
–5
–10
V
GAIN
= –0.7
V
GAIN
= –0.5
V
GAIN
= –0.2
V
GAIN
= 0
V
GAIN
= +0.2
V
GAIN
= +0.5
V
GAIN
= +0.7
e
IN
= 10mV p-p
Figure 10. Frequency Response for Various Values of VGAIN—Inverting Input
(See Figure 58)
30
–5
100k 500M
05575-011
FREQUENCY (Hz)
GAIN (dB)
1M 10M 100M
25
20
15
10
5
0
C
L
= 47pF
C
L
= 22pF
C
L
= 10pF
C
L
= 0pF
V
GAIN
= 0V
e
IN
= 10mV p-p
Figure 11. Frequency Response for Three Values of CL
(See Figure 45)
30
–5
100k 500M
05575-012
FREQUENCY (Hz)
GAIN (dB)
1M 10M 100M
25
20
15
10
5
0
V
GAIN
= 0V
C
L
= 47pF
C
L
= 22pF
C
L
= 10pF
C
L
= 0pF
Figure 12. Frequency Response for Three Values of CL
with a 20 Ω Snubbing Resistor (See Figure 45)
10
0
100k 500M
05575-013
FREQUENCY (Hz)
GAIN (dB)
1M 10M 100M
8
6
4
2
V
S
= ±2.5V
V
S
= ±5V
Figure 13. Frequency Response—Preamp
(See Figure 46)
25
–10
1M 100M
05575-014
FREQUENCY (Hz)
GROUP DELAY (ns)
10M
–5
0
5
10
15
20
Figure 14. Group Delay vs. Frequency
(See Figure 47)
AD8337
Rev. C | Page 9 of 32
10
–10
–800 800
05575-015
V
GAIN
(mV)
OFFSET VOLTAGE (mV)
V
S
= ±5V
V
S
= ±2.5V
+85°C
+25°C
–40°C
–8
–6
–4
–2
0
2
4
6
8
–600 –400 –200 0 200 400 600
Figure 15. Offset Voltage vs. VGAIN at Three Temperatures
(See Figure 48)
OUTPUT OFFSET VOLTAGE (mV)
0
80
40
20
30
10
70
50
60
500 UNITS
V
GAIN
= –0.4V
V
GAIN
=0V
V
GAIN
= +0.4V
% OF UNITS
–15 –10 –5 0 5 10 15 20 25
05575-016
Figure 16. Output Offset Voltage Histogram for Three Values of VGAIN
1k
0.1
1M 500M
05575-017
FREQUENCY (Hz)
IMPEDANCE (Ω)
1
100
10
100M10M
V
S
= ±2.5V
V
S
= ±5V
Figure 17. VGA Output Impedance vs. Frequency
(See Figure 49)
40
15
–800 800
05575-018
V
GAIN
(mV)
NOISE (nV/√Hz)
25
0
20
30
–600 –200–400 400 600200
35
+85°C
+25°C
–40°C
Figure 18. Output-Referred Noise vs. VGAIN at Three Temperatures
(See Figure 50)
25
0
–800 800
05575-019
V
GAIN
(mV)
NOISE (nV/√Hz)
10
0
5
15
–600 –200–400 400 600200
20
+85°C
+25°C
–40°C
Figure 19. Short-Circuit, Input-Referred Noise at Three Temperatures
(See Figure 50)
7
0
100k 100M
05575-020
FREQUENCY (Hz)
NOISE (nV/√Hz)
2
3
5
6
4
1M 10M
1
PREAMP GAIN = +2
PREAMP GAIN = –1
V
GAIN
= 0.7V
R
FB1
= R
FB2
= 100Ω
Figure 20. Short-Circuit, Input-Referred Noise vs. Frequency at Maximum
Gain—Inverting and Noninverting Preamp Gain = −1 and +2
(See Figure 50)
AD8337
Rev. C | Page 10 of 32
10
0.1
11
05575-021
SOURCE RESISTANCE (Ω)
INPUT-REFERRED NOISE (nV/√Hz)
1
10 100 k
R
S
THERMAL NOISE ALONE
INPUT-REFERRED NOISE
f = 10MHz,
V
GAIN
= 0.7V
Figure 21. Input-Referred Noise vs. RS
(See Figure 61)
25
0
20
30
–800
VGAIN (mV)
–600 –200–400 400 600200 800
15
50Ω SOURCE
5
10
35
WITH 50Ω SHUNT
TERMINATION AT INPUT
NOISE FIGURE (dB)
05575-022
UNTERMINATED
Figure 22. Noise Figure vs. VGAIN
(See Figure 51)
05575-023
–40
–50
0
LOAD RESISTANCE (
Ω
)
200 400 600 800
–60
–80
–70
2.0k1.0k 1.2k 1.4k 1.6k 1.8k
V
OUT = 1V p-p
V
GAIN
= 0V
HARMONIC DISTORTION (
dBc)
HD3 VS = ±2.5V
HD3 VS = ±5V
HD2 VS = ±2.5V
HD2 VS = ±5V
Figure 23. Harmonic Distortion vs. RL and Supply Voltage
(See Figure 52)
–40
25
–50
05 4010 3515 3020
–60
–80
–70
45 50
05575-024
LOAD CAPACITANCE (pF)
HARMONIC DISTORTION (dBc)
HD3
HD2
Figure 24. Harmonic Distortion vs. Load Capacitance
(See Figure 52)
–30
200
–50
–800
V
GAIN
(mV)
–600 800–400 600–200 4000
–60
–80
–70
–40
SECOND-ORDER HARMONIC DISTORTION (dBc)
1MHz
10MHz
35MHz
100MHz
05575-025
Figure 25. HD2 vs. VGAIN at Four Frequencies
(See Figure 52)
–30
200
–50
–800
V
GAIN
(mV)
–600 800–400 600–200 4000
–60
–80
–70
–40
THIRD-ORDER HARMONICDISTORTION (dBc)
05575-026
1MHz
10MHz
35MHz
100MHz
Figure 26. HD3 vs. VGAIN at Four Frequencies
(See Figure 52)
AD8337
Rev. C | Page 11 of 32
–30
200
–50
–800
V
GAIN
(mV)
–600 800–400 600–200 4000
–60
–80
–70
–40
–90
LIMITED BY
MAXIMUM PREAMP
OUTPUT SWING
SECOND-ORDER HARMONIC DISTORTION (dBc)
V
OUT
= 2V p-p
V
OUT
= 1V p-p
V
OUT
= 0.5V p-p
05575-027
Figure 27. HD2 vs. VGAIN for Three Levels of Output Voltage
(See Figure 52)
–30
200
–50
–800
V
GAIN
(mV)
–600 800–400 600–200 4000
–60
–80
–70
–40
–90
THIRD-ORDER HARMONIC DISTORTION (dBc)
V
OUT
= 2V p-p
V
OUT
= 1V p-p
V
OUT
= 0.5V p-p
05575-028
LIMITED BY
MAXIMUM PREAMP
OUTPUT SWING
Figure 28. HD3 vs. VGAIN for Three Levels of Output Voltage
(See Figure 52)
–20
10M
–30
1M
–60
–80
–70
100M
05575-029
FREQUENCY (Hz)
IMD3 (dBc)
V
S
= ±2.5V
V
S
= ±5V
V
OUT
= 1V p-p
V
GAIN
= 0V
TONES SEPARATED BY 100kHz
–40
–50
Figure 29. IMD3 vs. Frequency
(See Figure 64)
50
200
40
–800 –600 800–400 600–200 4000
30
10
20
0
OUTPUT-REFERRED IP3 (dBm)
05575-030
1MHz
10MHz
45MHz
70MHz
100MHz
V
GAIN
(mV)
V
OUT
= 1V p-p
TONES SEPARATED BY 100kHz
Figure 30. Output-Referred IP3 (OIP3) vs. VGAIN
at Five Frequencies (See Figure 64)
50
200
40
–800 –600 800–400 600–200 4000
30
10
20
0
OUTPUT-REFERRED IP3 (dBm)
05575-031
1MHz
10MHz
45MHz
70MHz
100MHz
V
GAIN
(mV)
V
S
= ±5V
V
OUT
= 1V p-p
TONES SEPARATED BY 100kHz
Figure 31. Output-Referred IP3 (OIP3) vs. VGAIN, VS = ±5 V
at Five Frequencies (See Figure 64)
20
200
15
–800 –600 800–400 600–200 4000
10
–10
5
–15
INPUT-REFERRED P1dB (dBm)
05575-032
0
–5
PREAMP LIMITED
V
GAIN
(mV)
V
S
= ±2.5V
V
S
= ±5V
Figure 32. Input-Referred P1dB (IP1dB) vs. VGAIN
(See Figure 63)
AD8337
Rev. C | Page 12 of 32
70
TIME (ns)
–60
–20
20
0
80
40
–20
–40
–10 302010 50 6040
V
IN
(mV)
–6
0
–2
2
6
4
–4
0
INPUT
–8
8
60
–80
V
GAIN
= 0.7V
V
OUT
(mV)
05575-033
OUTPUT
Figure 33. Small Signal Pulse Response
(See Figure 53)
70
TIME (ns)
0–20 –10 302010 50 6040
–60
–20
20
80
40
–40
V
IN
(mV)
–6
0
–2
2
6
4
–4
0
INPUT
OUTPUT
–8
8
60
–80
V
GAIN
= 0.7V
V
OUT
(mV)
05575-034
Figure 34. Small Signal Pulse Response—Inverting Feedback
(See Figure 59)
–600
–200
200
0
800
400
–20
–400
TIME (ns)
–10 302010 50 6040 70
V
IN
(mV)
–60
0
–20
20
60
40
–40
0
–80
80
600
–800
V
OUT
(mV)
05575-035
V
GAIN
= 0.7V
INPUT
OUTPUT
Figure 35. Large Signal Pulse Response
(See Figure 53)
–600
–200
200
0
800
400
–20
–400
TIME (ns)
–10 302010 50 6040 70
V
IN
(mV)
–60
0
–20
20
60
40
–40
0
–80
80
600
–800
V
OUT
(mV)
05575-036
V
S
= ±2.5V
V
GAIN
= 0.7V
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
INPUT
OUTPUT
Figure 36. Large Signal Pulse Response for Three Capacitive Loads
(See Figure 53)
–600
–200
200
0
800
400
–20
–400
TIME (ns)
–10 302010 50 6040
V
IN
(mV)
–60
0
–20
20
60
40
–40
0
–80
80
600
–800
V
OUT
(mV)
05575-037
70
V
S
= ±5V
V
GAIN
= 0.7V
OUTPUT
INPUT
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
Figure 37. Large Signal Pulse Response for Three Capacitive Loads, VS = ±5 V
(See Figure 53)
0.8
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
–0.5 0 0.5 1.0 1.5 2.0
05575-038
TIME (µs)
(V)
V
OUT
V
GAIN
Figure 38. Gain Response
(See Figure 54)
AD8337
Rev. C | Page 13 of 32
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
–0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7
05575-039
TIME (µs)
(V)
V
OUT
(V)
V
IN
(V)
V
GAIN
= 0.7V
Figure 39. Preamp Overdrive Recovery
(See Figure 55)
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
–0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7
05575-040
TIME (µs)
(V)
V
GAIN
= 0.7V
V
OUT
(V)
V
IN
(V)
Figure 40. VGA Overdrive Recovery
(See Figure 56)
PSRR (dB)
FREQUENCY (Hz)
–60
–50
–30
–20
100k
–40
1M 100M10M
–10
–80
–70
0
10 V
GAIN
= +0.7V, V
S
= ±2.5V
V
GAIN
= +0.7V, V
S
= ±5V
V
GAIN
= 0V, V
S
= ±2.5V
V
GAIN
= 0V, V
S
= ±5V
V
GAIN
= –0.7V, V
S
= ±2.5V
V
GAIN
= –0.7V, V
S
= ±5V
05575-041
Figure 41. PSRR vs. Frequency of Positive Supply
(See Figure 60)
PSRR (dB)
FREQUENCY (Hz)
–60
–50
–30
–20
100k
–40
1M 100M10M
–10
–80
–70
0
10 V
GAIN
= +0.7V, V
S
= ±2.5V
V
GAIN
= +0.7V, V
S
= ±5V
V
GAIN
= 0V, V
S
= ±2.5V
V
GAIN
= 0V, V
S
= ±5V
V
GAIN
= –0.7V, V
S
= ±2.5V
V
GAIN
= –0.7V, V
S
= ±5V
05575-042
Figure 42. PSRR vs. Frequency of Negative Supply
(See Figure 60)
05575-043
12
16
18
–10
24
22
–50
14
TEMPERATURE (°C)
–30 3010 50 70
20
90
QUIESCENT SUPPLY CURRENT (mA)
V
S
= ±5V
V
S
= ±2.5V
Figure 43. Quiescent Supply Current vs. Temperature
(See Figure 57)
AD8337
Rev. C | Page 14 of 32
TEST CIRCUITS
NETWORK ANALYZER
50Ω
INOUT
20Ω453Ω
AD8337
100Ω
3
4
PrA
+
–
1
100Ω
56.2Ω
49.9Ω
5 7
50Ω
05575-044
V
GAIN
Figure 44. Gain and Gain Error vs. VGAIN
3
4
1
57
50Ω50Ω
IN
NETWORK ANALYZER
OUT
20Ω
VGAIN
PrA49.9Ω
AD8337
100Ω
+
–
100Ω
453Ω
OPTIONAL
POSITIONS FOR
CL
05575-045
Figure 45. Frequency Response
50Ω50Ω
IN
NETWORK ANALYZER
OUT
PrA
3
4
1
5
AD8337
100Ω
100Ω
+
–
7
49.9Ω
20Ω453Ω
NC
NC 453Ω
05575-046
Figure 46. Frequency Response—Preamp
50Ω50Ω
IN
NETWORK ANALYZER
OUT
PrA
3
4
1
57
AD8337
100Ω
100Ω
+
–
49.9Ω
56.2Ω
453Ω
20Ω
0
5575-047
Figure 47. Group Delay
DIFFERENTIAL
FET PROBE
PrA
3
4
7
1
5
100Ω
100Ω
50Ω
50Ω
OUT CH1 CH2
OSCILLOSCOPE
50Ω
453Ω
AD8337
+
–
50Ω
FUNCTION
GENERATOR
V
GAIN
0
5575-048
Figure 48. Offset Voltage
NC
NC
AD8337
50Ω
IN
NETWORK ANALYZER
CONFIGURE TO
MEASURE Z
CONVERTED S11
+
–
PrA
100Ω
3
4
1
5
0Ω
0Ω
100Ω
7
49.9Ω
05575-049
Figure 49. Output Impedance vs. Frequency
AD8337
Rev. C | Page 15 of 32
50Ω
IN
SPECTRUM ANALYZER
PrA
3
4
1
5
100Ω
49.9Ω
100Ω
7
AD8337
+
–
0Ω
0Ω
V
GAIN
05575-050
Figure 50. Input-Referred and Output-Referred Noise
NOISE FIGURE METER
AD8337
100Ω
5
3
4
PrA
+
–
1
100Ω
7
49.9Ω
(OR ∞)
INPUT
0Ω
0Ω
NOISE
SOURCE
DRIVE
NOISE
SOURCE
V
GAIN
05575-051
Figure 51. Noise Figure vs. VGAIN
SPECTRUM ANALYZER
AD8337
100Ω
5
3
4
PrA
+
–
1
100Ω
7
49.9Ω
INPUT
20Ω
LOW-
PASS
FILTER
SIGNAL
GENERATOR
CL
50Ω
RL
VGAIN
05575-052
Figure 52. Harmonic Distortion
OSCILLOSCOPE
CH2
50Ω
OUT
50Ω
CH1
PULSE
GENERATOR
20Ω453Ω
56.2Ω
0.7V
POWER
SPLITTER
100Ω
05575-053
AD8337
5
3
4
PrA
+
–
1
100Ω
7
49.9Ω
Figure 53. Pulse Response
OSCILLOSCOPE
AD8337
100Ω
5
3
4
PrA
+
–
1
100Ω
7
CH2
50Ω
DIFFERENTIAL
FET PROBE
50Ω
CH1
DUAL
FUNCTION
GENERATOR
V
GAIN
05575-054
20Ω453Ω
NC
POWER
SPLITTER
SQUARE
WAVE
49.9Ω
SINE
WAVE
Figure 54. Gain Response
OSCILLOSCOPE
AD8337
100Ω
5
3
4
PrA
+
–
1
100Ω
7
CH2
50Ω
CH1
FUNCTION
GENERATOR
05575-055
NC
OUTPUT
49.9Ω
100Ω
NC
Figure 55. Preamp Overdrive Recovery
AD8337
Rev. C | Page 16 of 32
OSCILLOSCOPE
AD8337
100Ω
5
3
4
PrA
+
–
1
100Ω
CH2
50Ω50Ω
CH1
05575-056
20Ω453Ω
NC
POWER
SPLITTER
OUTPUT
49.9Ω
FUNCTION
GENERATOR
Figure 56. VGA Overdrive Recovery
AD8337
100Ω
5
3
4
PrA
1
100Ω
7
DMM
(+I)
8
6
DMM
(–I)
DMM
(V)
+
–
05575-057
Figure 57. Supply Current
NETWORK ANALYZER
100Ω
5
3
4
PrA
1
100Ω
7
100Ω
50Ω
INOUT
20Ω
453Ω
50Ω
V
GAIN
AD8337
+
–
05575-058
Figure 58. Frequency Response—Inverting Feedback
OSCILLOSCOPE
100Ω
5
3
4
PrA 1
100Ω
7
CH2
50Ω
OUT
50Ω
CH1
PULSE
GENERATOR
100Ω
20Ω453Ω
56.2Ω
0.7V
POWER
SPLITTER
AD8337
+
–
05575-059
Figure 59. Pulse Response—Inverting Feedback
NETWORK ANALYZER
100Ω
5
3
4
PrA
1
100Ω
7
49.9Ω
50Ω
INOUT
BYPASS
CAPACITORS
REMOVED FOR
MEASUREMENT
50Ω
DIFFERENTIAL
FET PROBE
BENCH
POWER SUPPLY
VPOS
+SUPPLY TO NETWORK
ANALYZER BIAS PORT
AD8337
+
–
05575-060
V
GAIN
Figure 60. PSRR
SPECTRUM ANALYZER
AD8337
100Ω
5
3
4
PrA
1
100Ω
7
IN
50Ω
+
–
05575-061
V
GAIN
Figure 61. Input-Referred Noise vs. RS
AD8337
Rev. C | Page 17 of 32
SPECTRUM ANALYZER
AD8337
100Ω
5
3
4
PrA 1
100Ω
7
0.7V
IN
50Ω
+
–
05575-062
Figure 62. Short-Circuit Input Noise vs. Frequency
NETWORK ANALYZER
POWER SWEEP
AD8337
5
3
4
PrA
1
7
50Ω
INOUT
453Ω
50Ω
22dB
V
GAIN
+
–
100Ω
05575-063
20Ω
49.9Ω
100Ω
Figure 63. IP1dB vs. VGAIN
SPECTRUM ANALYZER
AD8337
100Ω
5
3
4
PrA
+
–
1
100Ω
7
49.9Ω
INPUT
20Ω
453Ω
50Ω
SIGNAL
GENERATOR
SIGNAL
GENERATOR
COMBINER
–6dB
V
GAIN
05575-064
+22dB –6dB
+22dB –6dB
–6dB
Figure 64. IMD and OIP3
AD8337
Rev. C | Page 18 of 32
THEORY OF OPERATION
VOUT
GAIN
RG
18dB
(8x)
2
1
6
PRAO
VNEG
VCOM
+
–
7
749Ω
107Ω
PrA
6dB
GAIN
INTERFACE
BIAS
+
–
8
VPOS
INPP
INPN
5
3
4
INTERPOLATOR
ATTENUATOR
–24dB TO 0dB
+
–
RFB1 = RFB2 = 100Ω
05575-065
RFB2
RFB1
Figure 65. Circuit Block Diagram
OVERVIEW
The AD8337 is a low noise, single-ended, linear-in-dB, general-
purpose variable gain amplifier (VGA) usable at frequencies up
to 100 MHz. It is fabricated using a proprietary Analog Devices
dielectrically isolated, complementary bipolar process. The
bandwidth is dc to 280 MHz and features low dc offset voltage
and an ideal nominal gain range of 0 dB to 24 dB. Requiring
about 15.5 mA, the power consumption is only 78 mW from
either a single +5 V or a dual ±2.5 V supply. Figure 65 is the
circuit block diagram of the AD8337.
PREAMPLIFIER
An uncommitted current-feedback op amp included in the
AD8337 can be used as a preamplifier to buffer the ladder
network attenuator of the X-AMP. As with any op amp, the gain
is established using external resistors, and the preamplifier is
specified with a noninverting gain of 6 dB (2×) and gain resistor
values of 100 Ω. The preamplifier gain can be increased using
larger values of RFB2, trading off bandwidth and offset voltage.
The value of RFB2 is to be ≥100 Ω because the value and an
internal compensation capacitor determine the 3 dB bandwidth,
and smaller values can compromise preamplifier stability.
Because the AD8337 is dc-coupled, larger preamp gains increase
the offset voltage. The offset voltage can be compensated by
connecting a resistor between the INPN input and the supply
voltage. If the offset is negative, the resistor value connects to
the negative supply. For ease of adjustment, a trimmer network
can be used.
For larger gains, the overall noise is reduced if a low value of
RFB1 is selected. For values of RFB1 = 20 Ω and RFB2 = 301 Ω, the
preamp gain is 16× (24.1 dB), and the input-referred noise is
approximately 1.5 nV/√Hz. For this value of gain, the overall
gain range increases by 18 dB; therefore, the gain range is 18 dB
to 42 dB.
VGA
This X-AMP, with its linear-in-dB gain characteristic
architecture, yields the optimum dynamic range for receiver
applications. Referring to Figure 65, the signal path consists of
a −24 dB variable attenuator followed by a fixed gain amplifier of
18 dB, for a total VGA gain range of −6 dB to +18 dB. With the
preamplifier configured for a gain of 6 dB, the composite gain
range is 0 dB to 24 dB.
The VGA plus preamp, with 6 dB of gain, implements the
following exact gain law:
(dB)
V
dB
19.7(dB) ICPT
GAIN
VGain +
⎥
⎦
⎤
⎢
⎣
⎡×=
where the nominal intercept (ICPT) = 12.65 dB.
The ICPT increases as the gain of the preamp is increased. For
example, if the gain of the preamp is increased by 6 dB, ICPT
increases to 18.65 dB. Although the previous equation shows
the exact gain law as based on statistical data, a quick estimation
of signal levels can be made using the default slope of 20 dB/V
for a particular gain setting. For example, the change in gain for
a VGAIN change of 0.3 V is 6 dB using a slope of 20 dB/V and
5.91 dB using the exact slope of 19.6 dB/V. This is a difference
of only 0.09 dB.
GAIN CONTROL
The gain control interface provides a high impedance input and
is referenced to the VCOM pin (in a single-supply application to
midsupply at [VPOS + VNEG]/2 for optimum swing). When
dual supplies are used, VCOM is connected to ground. The voltage
on the VCOM pin determines the midpoint of the gain range. For
a ground referenced design, the VGAIN range is from −0.7 V to
+0.7 V with the most linear-in-dB section of the gain control
between −0.6 V and +0.6 V. In the center 80% of the VGAIN
range, the gain error is typically less than ±0.2 dB. The gain
control voltage can be increased or decreased to the positive or
negative rails without gain foldover.
AD8337
Rev. C | Page 19 of 32
The gain scaling factor (gain slope) is designed for 20 dB/V. This
relatively low slope ensures that noise on the GAIN input is not
unduly amplified. Because a VGA functions as a multiplier, it is
important that the GAIN input does not inadvertently modulate
the output signal with unwanted noise. Because of its high input
impedance, a simple low-pass filter can be added to the GAIN
input to filter unwanted noise.
OUTPUT STAGE
The output stage is a Class AB, voltage-feedback, complementary
emitter-follower with a fixed gain of 18 dB, similar to the pream-
plifier in speed and bandwidth. Because of the ac-beta roll-off
of the output devices and the inherent reduction in feedback
beyond the −3 dB bandwidth, the impedance looking into the
output pin of the preamp and output stages appears to be inductive
(increasing impedance with increasing frequency). The high
speed output amplifier used in the AD8337 can drive large
currents, but its stability is susceptible to capacitive loading.
A small series resistor mitigates the effects of capacitive loading
(see the Applications Information section).
ATTENUATOR
The input resistance of the VGA attenuator is nominally 265 Ω.
For example, if the default preamplifier feedback network RFB1 +
RFB2 is 200 Ω, the effective preamplifier load is approximately
114 Ω. The attenuator is composed of eight 3.01 dB sections for
a total attenuation range of −24.08 dB. Following the attenuator
is a fixed gain amplifier with 8× (18.06 dB) gain. Because of this
relatively low gain, the output offset is kept well below 20 mV
over temperature; the offset is largest at maximum gain when
the preamplifier offset is amplified. The VCOM pin defines the
common-mode reference for the output, as shown in Figure 65.
SINGLE-SUPPLY OPERATION AND AC COUPLING
If the AD8337 is to be operated from a single 5 V supply, the
bias supply for VCOM must be a very low impedance 2.5 V
reference, especially if dc coupling is used. If the device is dc-
coupled, the VCOM source must be able to handle the preamplifier
and VGA dynamic load currents in addition to the bias currents.
When ac coupling the preamplifier input, a bias network and
bypass capacitor must be connected to the opposite polarity
input pin. The bias generator for the VCOM pin must provide
the dynamic current to the preamplifier feedback network and
the VGA attenuator. For many single 5 V applications, a refer-
ence, such as the ADR391, and a good op amp provide an
adequate VCOM source if a 2.5 V supply is unavailable.
NOISE
The total input-referred voltage and current noise of the positive
input of the preamplifier are about 2.2 nV/√Hz and 4.8 pA/√Hz.
The VGA output-referred noise is about 21 nV/√Hz at low gains.
This result is divided by the VGA fixed gain amplifier gain of 8×
and results in a voltage noise density of 2.6 nV/√Hz referred to
the VGA input. This value includes the noise of the VGA gain
setting resistors as well. If this voltage is again divided by the
preamp gain of 2, the VGA noise referred all the way to the
preamp input is about 1.3 nV/√Hz. From this, it is determined
that the preamplifier, including the 100 Ω gain setting resistors,
contributes about 1.8 nV/√Hz. The two 100 Ω resistors contribute
1.29 nV/√Hz each at the output of the preamp. With the gain
resistor noise subtracted, the preamplifier noise is approximately
1.55 nV/√Hz.
Equation 2 shows the calculation that determines the output-
referred noise at maximum gain (24 dB or 16×).
where:
At is the total gain from preamp input to VGA output.
RS is the source resistance.
en − PrA is the input-referred voltage noise of the preamp.
in − PrA is the current noise of the preamp at the INPP pin.
en − is the voltage noise of RFB1.
en − is the voltage noise of RFB2.
en − VGA is the input-referred voltage noise of the VGA (low gain,
output-referred noise divided by a fixed gain of 8×).
1FB
R
2FB
R
Assuming RS = 0 Ω, RFB1 = RFB2 = 100 Ω, At = 16×, and AVGA =
8×, the noise simplifies to
en − out = HznV 35 8) (1.9 8) 2(1.29 16) (1.75 222 =×+×+× (1)
Dividing the result by 16 gives the total input-referred noise with
a short-circuited input as 2.2 nV/√Hz. When the preamplifier is
used in the inverting configuration with the same RFB1 and RFB2 =
100 Ω as previously noted, en − out does not change. However,
because the gain dropped by 6 dB, the input-referred noise
increases by a factor of 2 to about 4.4 nV/√Hz. The reason for this
increase is that the noise gain to the output of the noise generators
stays the same, yet the preamp in the inverting configuration has a
gain of −1 compared to the +2 in the noninverting configuration;
this increases the input-referred noise by 2.
2
)
VGA
A
n
(e
2
)
VGA
A
n
(e
2
)
VGA
A
FB1
R
FB2
R
n
(e
2
)
S
R
n
(i
2
)
t
A
n
(e
2
t
A
S
R
n
e
n
eVGARRPrAPrAout FB2FB1
×
−
+×
−
+××
−
+×
−
+×
−
+×=
−)( (2)
AD8337
Rev. C | Page 20 of 32
APPLICATIONS INFORMATION
PREAMPLIFIER CONNECTIONS
Noninverting Gain Configuration
The AD8337 preamplifier is an uncommitted current-feedback
op amp that is stable for values of RFB2 ≥ 100 Ω. See Figure 66
for the noninverting feedback connections.
R
G
PRAO
PREAMPLIFIER
+
–
INPP
INPN
5
3
4
05575-066
R
FB2
R
FB1
Figure 66. AD8337 Preamplifier Configured for Noninverting Gain
Two surface-mount resistors establish the preamplifier gain.
Equal values of 100 Ω configure the preamplifier for a 6 dB gain
and the device for a default gain range of 0 dB to 24 dB.
For preamplifier gains ≥2, select a value of RFB2 ≥ 100 Ω and
RFB1 ≤ 100 Ω. Higher values of RFB2 reduce the bandwidth and
increase the offset voltage, but smaller values compromise
stability. If RFB1 ≤ 100 Ω, the gain increases and the input-
referred noise decreases.
Inverting Gain Configuration
For applications requiring polarity inversion of negative pulses, or
for waveforms that require current sinking, the preamplifier can
be configured as an inverting gain amplifier. When configured
with bipolar supplies, the preamplifier amplifies positive or
negative input voltages with no level shifting of the common-
mode input voltage required. Figure 67 shows the AD8337
configured for inverting gain operation.
Because the AD8337 is a very high frequency device, stability
issues can occur unless the circuit board on which it is used is
carefully laid out. The stability of the preamp is affected by
parasitic capacitance around the INPN pin. To minimize stray
capacitance position the preamp gain resistors, RFB1 and RFB2, as
close as possible to the INPN pin.
PRAO
PREAMPLIFIER
+
–
INPP
INPN
5
3
4
05575-067
RFB2
RFB1
Figure 67. The AD8337 Preamplifier Configured for Inverting Gain
DRIVING CAPACITIVE LOADS
Because of the large bandwidth of the AD8337, stray capacitance at
the output pin can induce peaking in the frequency response as the
gain of the amplifier begins to roll off. Figure 68 shows peaking
with two values of load capacitance using ±2.5 V supplies and
VGAIN = 0 V.
GAIN (dB)
–5
0
10
20
15
25
100k
5
FREQUENCY (Hz)
1M 500M100M10M
05575-068
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
V
GAIN
= 0V
NO SNUBBING RESISTOR
Figure 68. Peaking in the Frequency Response for Two Values of Output
Capacitance with ±2.5 V Supplies and No Snubbing Resistor
GAIN (dB)
–5
0
10
20
15
25
100k
5
FREQUENCY (Hz)
1M 500M100M10M
05575-069
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
V
GAIN
= 0V
WITH 20Ω SNUBBING RESISTOR
Figure 69. Frequency Response for Two Values of Output Capacitance
with a 20 Ω Snubbing Resistor
In the time domain, stray capacitance at the output pin can
induce overshoot on the edges of transient signals, as shown in
Figure 70 and Figure 72. The amplitude of the overshoot is also a
function of the slewing of the transient (not shown in Figure 70
and Figure 72). The transition time of the input pulses used for
Figure 70 and Figure 72 is deliberately set high at 300 ps to demon-
strate the fast response time of the amplifier. Signals with longer
transition times generate less overshoot.
AD8337
Rev. C | Page 21 of 32
–600
–200
0
0
600
400
–20
–400
TIME (ns)
–10 302010 50 6040 80
V
IN
(mV)
–60
0
–20
20
60
40
–40
200
OUTPUT
800
–800
70
80
–80
05575-070
V
OUT
(mV)
INPUT
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
NO SNUBBING RESISTOR
Figure 70. Pulse Response for Two Values of Output Capacitance
with ±2.5 V Supplies and No Snubbing Resistor
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
WITH 20Ω SNUBBING RESISTOR
V
OUT
(mV)
–600
–200
0
0
600
400
–20
–400
TIME (ns)
–10 302010 50 6040 80
V
IN
(mV)
–60
0
–20
20
60
40
–40
200
INPUT
OUTPUT
800
–800
70
80
–80
05575-071
Figure 71. Pulse Response for Two Values of Output Capacitance
with ±2.5 V Supplies and a 20 Ω Snubbing Resistor
CL = 0pF
CL= 10pF
CL = 22pF
WITH NO SNUBBING RESISTOR
VOUT (mV)
–600
–200
0
0
600
400
–20
–400
TIME (ns)
–10 302010 50 6040 80
–60
0
–20
20
60
40
–40
200
INPUT
OUTPUT
800
–800
70
–80
80
VS = ±5V
VIN (mV)
05575-072
Figure 72. Large Signal Pulse Response for Two Values of Output
Capacitance with ±5 V Supplies and No Snubbing Resistor
CL = 0pF
CL = 10pF
CL = 22pF
WITH 20Ω SNUBBING RESISTOR
VOUT (mV)
–600
–200
0
0
600
400
–20
–400
TIME (ns)
–10 302010 50 6040 80
–60
0
–20
20
60
40
–40
200
INPUT
OUTPUT
800
–800
70
–80
80
VIN (mV)
VS = ±5V
05575-073
Figure 73. Pulse Response for Two Values of Output Capacitance
with ±5 V Supplies and a 20 Ω Snubbing Resistor
The effects of stray output capacitance are mitigated with a
small value snubbing resistor, RSNUB, placed in series with, and
as near as possible to, the VOUT pin. Figure 69, Figure 71, and
Figure 73 show the improvement in dynamic performance with
a 20  snubbing resistor. RSNUB reduces the gain slightly by the
ratio of RL/(RSNUB + RL), a very small loss when used with high
impedance loads, such as ADCs. For other loads, alternate values
of RSNUB can be determined empirically. The data for the curves in
the Typical Performance Characteristics section are derived using
a 20 Ω snubbing resistor.
The best way to avoid the effects of stray capacitance is to
exercise care in the PCB layout. Locate the passive components
or devices connected to the AD8337 output pins as close as
possible to the package.
Although a nonissue, the preamplifier output is also sensitive to
load capacitance. However, the series connection of RFB1 and
RFB2 is typically the only load connected to the preamplifier. If
overshoot appears, it can be mitigated by inserting a snubbing
resistor, the same way as the VGA output.
GAIN CONTROL CONSIDERATIONS
In typical applications, voltages applied to the GAIN input are dc
or relatively low frequency signals. The high input impedance of
the AD8337 enables several devices to be connected in parallel.
This is useful for arrays of VGAs, such as those used for calibra-
tion adjustments.
Under dc or slowly changing ramp conditions, the gain tracks
the gain control voltage, as shown in Figure 3. However, it is often
necessary to consider other effects influenced by the VGAIN input.
AD8337
Rev. C | Page 22 of 32
The offset voltage effect of the AD8337, as with all VGAs, can
appear as a complex waveform when observed across the range
of VGAIN voltage. Generated by multiple sources, each device has
a unique offset voltage (VOS) profile while the GAIN input is
swept through its voltage range. The offset voltage profile seen
in Figure 15 is a typical example. If the VGAIN input voltage is
modulated, the output is the product of the VGAIN and the dc
profile of the offset voltage. This is observed on a scope as a
small ac signal, as shown in Figure 74. In Figure 74, the signal
applied to the VGAIN input is a 1 kHz ramp, and the output voltage
signal is slightly less than 4 mV p-p.
Under certain circumstances, the product of VGAIN and the
offset profile plus spikes is a coherent spurious signal within the
signal band of interest and indistinguishable from desired
signals. In general, the slower the ramp applied to the GAIN
Pin, the smaller the spikes are. In most applications, these
effects are benign and not an issue.
THERMAL CONSIDERATIONS
The thermal performance of LFCSPs, such as the AD8337,
departs significantly from that of leaded devices such as the
larger TSSOP or QFSP. In larger packages, heat is conducted
away from the die by the path provided by the bond wires and
the device leads. In LFCSPs, the heat transfer mechanisms are
surface-to-air radiation from the top and side surfaces of the
package and conduction through the metal solder pad on the
mounting surface of the device.
OFFSET VOLTAGE (mV)
–4
6
10
0
4
8
–800
–2
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
2
–10
–8
–6
05575-075
V
S
=2.5
INPUT
OUTPUT
V
S
= ±2.5V
θJC is the traditional thermal metric used for integrated circuits.
Heat transfer away from the die is a three-dimensional dynamic,
and the path is through the bond wires, leads, and the six
surfaces of the package. Because of the small size of LFCSPs, the
θJC is not measured conventionally. Instead, it is calculated using
thermodynamic rules.
The θJC value of the AD8837 listed in Table 2 assumes that the
tab is soldered to the board and that there are three additional
ground layers beneath the device connected by at least four vias.
For a device with an unsoldered pad, the θJC nearly doubles,
becoming 138°C/W.
Figure 74. Offset Voltage vs. VGAIN for a 1 kHz Ramp
The profile of the waveform shown in Figure 74 is consistent
over a wide range of signals from dc to about 20 kHz. Above
20 kHz, secondary artifacts can be generated due to the effects
of minor internal circuit tolerances, as shown in Figure 75.
These artifacts are caused by settling and time constants of the
interpolator circuit and appear at the output as the voltage
spikes, as shown in Figure 75.
PSI (Ψ)
Table 2 lists a subset of the classic theta specification, ΨJT (Psi
junction to top). θJC is the metric of heat transfer from the die to
the case, involving the six outside surfaces of the package. Ψ(XY)
is a subset of the theta value and the thermal gradient from the
junction (die) to each of the six surfaces. Ψ can be different for
each of the surfaces, but since the top of the package is a fraction of
a millimeter from the die, the surface temperature of the package is
very close to the die temperature. The die temperature is calculated
as the product of the power dissipation and ΨJT. Since the top
surface temperature and power dissipation are easily measured, it
follows that the die temperature is easily calculated. For example,
for a dissipation of 180 mW and a ΨJT of 5.3°C/W, the die
temperature is slightly less than 1°C higher than the surface
temperature.
OFFSET VOLTAGE (mV)
–4
6
10
0
4
8
–800
–2
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
2
–10
–8
–6
V
S
= 2.5
INPUT
OUTPUT
05575-074
SPIKE
SPIKE
V
S
= ±2.5V
BOARD LAYOUT
Because the AD8337 is a high frequency device, board layout is
critical. It is very important to have a good ground plane
connection to the VCOM pin. Coupling through the ground
plane, from the output to the input, can cause peaking at higher
frequencies.
Figure 75. VOS Profile for a 50 kHz Ramp
AD8337
Rev. C | Page 23 of 32
EVALUATION BOARDS
The AD8337evaluation boards provide a family of platforms for
testing and evaluating the AD8337 VGA. Three circuit configu-
rations are available:
• AD8337-EVALZ, dc-coupled, with noninverting gain and
dual power supplies
• AD8337-EVALZ-INV, dc-coupled, with inverting gain and
dual power supplies
• AD8337-EVALZ-SS, ac-coupled, with noninverting gain
configuration and a single supply
These fully assembled and tested boards are ready to use. Only
the appropriate power supply and signal source connections
need to be made. SMA connectors are provided for the pream-
plifier (PrA) and VGA outputs. Photos of fully assembled boards
are shown in Figure 76 and Figure 77. The board component
side layouts are shown in Figure 78 and Figure 79.
05575-176
Figure 76. AD8337 Evaluation Board for dual Supplies
05575-177
Figure 77. AD8337 Evaluation Board for Single Supply
05575-178
Figure 78. Assembly, Dual-Supply Evaluation Board
05575-179
Figure 79. Assembly, Single-Supply Evaluation Board
Schematic diagrams of the dual-supply board for noninverting
and inverting configurations are shown in Figure 80 and Figure 81.
The dual-supply boards require ±2.5 V to ±5 V supplies capable
of supplying 20 mA or greater. A schematic diagram of the
single-supply board is shown in Figure 82. The single supply
version accepts a +5 V to +10 V supply with 20 mA or greater
capability.
AD8337
Rev. C | Page 24 of 32
IN
18
7
6
54
3
2
VOUT
VCOM
INPP
VPOS
GAIN
VNEG
PRAOINPN
U1
AD8337
TP1
VOUT
GND1 GND2GND GND3 GND4
R2
49.9Ω
RVO1
453Ω
R
FB2
100Ω
R
FB1
100Ω
R4
0Ω
RPO2
453Ω
PRAO
R1
49.9Ω
GAIN
RVO3
0Ω
L1
120nH
L2
120nH
J1
DO NOT INSTALL PARTS IN GRAY
C4
0.1µF
+
CG
1nF
R5
100Ω
C3
0.1µF
C1
10µF C2
10µF
+V
S
–V
S
+
05575-180
Figure 80. Schematic—AD8337-EVALZ - Noninverting Configuration
IN
18
7
6
54
3
2
VOUT
VCOM
INPP
VPOS
GAIN
VNEG
PRAOINPN
TP1
VOUT
R2
49.9Ω
RVO1
453Ω
R
FB2
100Ω
R
FB1
100Ω
R4
0Ω
RPO2
453Ω
PRAO
R1
49.9Ω
GAIN
RVO3
0Ω
L1
120nH
L2
120nH
J1
DO NOT INSTALL PARTS IN GRAY
C4
0.1µF
+
CG
1nF
R5
100Ω
100Ω
C3
0.1µF
C1
10µF
C2
10µF
+V
S
–V
S
+
05575-181
U1
AD8337
GND1 GND2GND GND3 GND4
Figure 81. Schematic—AD8337-EVALZ-INV Inverting Configuration
CIRCUIT OPTIONS
Part numbers for fully assembled boards are listed in Table 4.
Table 4. AD8337 Evaluation Board Variations
Part Number Configuration
AD8337-EVALZ Dual-supply noninverting
AD8337-EVALZ-INV Dual-supply inverting
AD8337-EVALZ-SS Single-supply noninverting
Figure 80, Figure 81, and Figure 82 are schematics for the
various circuit configurations. Within limits, the AD8337
preamplifier gain is controlled by Resistor RFB1 and Resistor
RFB2. For simple guidelines applying to the current-feedback
preamplifier, see the Theory of Operation section.
OUTPUT PROTECTION
The AD8337 VGA output stage is specified for driving loads of
500 Ω or greater. To protect the stage from an accidental
overload, a 453 Ω resistor is provided, which when connected to
50 Ω test equipment inputs, enables safe operation. In certain
high load impedance situations, the value of this resistor can be
reduced. However, if load capacitance values greater than
approximately 20 pF are anticipated, such as a BNC cable, the
minimum series resistor value is not to be less than 20 Ω.
An alternate test pin is also provided for direct access to the
output of the AD8337 VGA. The pin is typically used for a
probe, and a 0 Ω resistor is provided between the test loop and
the output pin. If the test loop is connected to loads ≤500 Ω,
then the 0 Ω resistor is to be changed to an appropriate value.
VOUTINPP
3
2
1
64
7
8
INPN PRAO
5
ADR391AUJZ-R2
GAIN
VCOM
+V
S
12
5
4
3
AD8541AR
2
3
4
6
7
VNEG
VPOS
U1
AD8337
L1
120nH FB
GND1
VOUT
GAIN
U2
GND2 GND3 GND4
IN
GND
VIN
VOUT
SHDN
05575-182
C4
0.1µF
C9
0.1µF
C10
0.1µF
C1
10µF
10V
+C3
0.1µF
RVO1
453Ω
CG
1nF
R
FB1
100Ω
R
FB2
100Ω
C5
0.1µF
C2
1µF
16V
C6
0.1µF
R6
100Ω
C7
0.1µF
R1
49.9Ω
R4
10kΩ
C8
0.22µF
U3
+
Figure 82. Evaluation Board Schematic—Single-Supply Version
AD8337
Rev. C | Page 25 of 32
POWER SUPPLY
+5V
TOP:
SIGNAL GENERATOR 10.05MHz, 500mV p-p
BOTTOM:
SIGNAL GENERATOR 9.95MHz, 500mV p-p
SIGNAL
INPUT
–5V
POWER
SPLITTER
PREAMP
OUTPUT
VGAIN
POWER
AMPLIFIERS SPECTRUM
ANALYZER
05575-183
Figure 83. Typical Board Test Connections
MEASUREMENT SETUP
Figure 83 shows board connections for two generators. In this
example, the experiment illustrates IMD measurements using
standard off-the-shelf test equipment used by Analog Devices.
However, any equivalent equipment can be used.
BOARD LAYOUT CONSIDERATIONS
The AD8337 evaluation board is designed using four layers.
Interconnecting circuitry is located on the component and
wiring sides, with the inner layers dedicated to power and
ground planes. Figure 84 through Figure 88 show the copper
layouts.
For ease of assembly, all board components are located on the
primary side and are 0603 size surface mounts. Higher density
applications may require components on both sides of the board
and present no problem to the AD8337, as demonstrated in
unreleased versions of the board that featured secondary-side
components and vias. Not evident in the figures are thermal
vias within the pad that solder to the mating pad of the AD8337
chip-scale package. These vias serve as a thermal path and are
the primary means of removing heat from the device. The thermal
specifications for the AD8337 are predicated on the use of multi-
layer board construction with these thermal vias to enable heat
conductivity from the die.
AD8337
Rev. C | Page 26 of 32
05575-109
Figure 84. Dual-Supply Component Side Copper
05575-110
Figure 85. Dual-Supply Wiring Side Copper
05575-111
Figure 86. Dual-Supply Component Side Silk-Screen
05575-112
Figure 87. Dual-Supply Ground Plane
0
5575-113
Figure 88. Dual-Supply Power Plane
05575-114
Figure 89. Single-Supply Component Side Copper
05575-115
Figure 90. Single-Supply Wiring Side Copper
05575-116
Figure 91. Single-Supply Component Side Silkscreen
AD8337
Rev. C | Page 27 of 32
05575-117
Figure 92. Single-Supply Ground Plane
05575-118
Figure 93. Single-Supply Power Plane
BILL OF MATERIALS
Table 5. Dual-Supply Noninverting Bill of Materials
Qty. Reference Designator Description Manufacturer Mfg. Part Number
1 +VS Red test loop, 0.125” diameter Bisco Industries TP-104-01-02
4 GND1 to GND4 Black test loop, 0.125” diameter Bisco Industries TP-104-01-00
1 −VS Blue test loop, 0.125” diameter Bisco Industries TP-104-01-06
1 TP1 Purple test loop, 0.125” diameter Bisco Industries TP-104-01-07
2 C3, C4 SM 0.1 μF, 16 V, 0603, X7R capacitors KEMET C0603C104K4RACTU
1 CG SM 1 nF, 50 V, X7R, 10%, 0603 capacitor Panasonic ECJ-1VB2A102K
2 C1, C2 SM tantalum, 10 μF, 10 V, A size capacitors Nichicon T491A106M010AS
1 U1 Integrated circuit VGA Analog Devices, Inc. AD8337BCPZ-WP
4 GAIN, IN, PRAO, VOUT SMA fem PC mount RA connectors Amphenol 901-143-6RFX
2 L1, L2 120 nH, 0603 ferrite beads Murata BLM18BA750SN1D
1 R2 49.9 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF49R9V
2 R4, RVO3 0 Ω, 5%, 1/10 W, 0603 resistors Panasonic ERJ-2GE0R00X
2 RFB1, RFB2 100 Ω, 1%, 1/16 W, 0603 resistors Panasonic ERJ-3EKF1000V
2 RPO2, RVO1 453 Ω, 1/16 W, 1%, 0603 resistors Panasonic ERJ-3EKF4530V
Table 6. Dual-Supply Inverting Gain Bill of Materials
Qty. Reference Designator Description Manufacturer Mfg. Part Number
1 +VS Red test loop, 0.125” diameter Bisco Industries TP-104-01-02
4 GND1 to GND4 Black test loop, 0.125” diameter Bisco Industries TP-104-01-00
1 −VS Blue test loop, 0.125” diameter Bisco Industries TP-104-01-06
1 TP1 Purple test loop, 0.125” diameter Bisco Industries TP-104-01-07
2 C3, C4 SM 0.1 μF, 16 V, 0603, X7R capacitors KEMET C0603C104K4RACTU
1 CG SM 1 nF, 50 V, X7R, 10%, 0603 capacitor Panasonic ECJ-1VB2A102K
2 C1, C2 SM tantalum, 10 μF, 10 V, A size capacitors Nichicon T491A106M010AS
1 U1 Integrated circuit VGA Analog Devices, Inc. AD8337BCPZ-WP
4 GAIN, IN, PRAO, VOUT SMA fem PC mount RA connectors Amphenol 901-143-6RFX
2 L1, L2 120 nH, 0603 ferrite beads Murata BLM18BA750SN1D
1 R2 49.9 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF49R9V
1 RVO3 0 Ω, 5%, 1/10 W, 0603 resistor Panasonic ERJ-2GE0R00X
3 RFB2, R5, J1 (J1 POSITION) 100 Ω, 1%, 1/16 W, 0603 resistors Panasonic ERJ-3EKF1000V
2 RPO2, RVO1 453 Ω, 1/16 W, 1%, 0603 resistors Panasonic ERJ-3EKF4530V
AD8337
Rev. C | Page 28 of 32
Table 7. Single-Supply Bill of Materials
Qty. Reference Designator Description Manufacturer Mfg. Part Number
1 +VS Red test point, 0.125” diameter Bisco Industries TP-104-01-02
1 C1 Tantalum, 10 μF, 10 V, A size capacitor Nichicon T491A106M010AS
1 C2 Tantalum, 1 μF, P size capacitor Nichicon F921C105MPA
7 C3, C4, C5, C6, C7, C9, C10 0.1 μF, 16 V, 0603, X7R capacitors KEMET C0603C104K4RACTU
1 C8 0.22 μF, 10%, 0603, X7R capacitor Panasonic ECJ-1VB1H223K
1 CG 1 nF, 50 V, X7R, 10%, 0603 capacitor Panasonic ECJ-1VB2A102K
3 GAIN, IN, VOUT SMA fem PC mount RA connectors Amphenol 901-143-6RFX
4 GND1 to GND4 Loop, 0.125” diameter, black test points Bisco Industries TP-104-01-00
1 L1 120 nH, 0603 ferrite bead Murata BLM18BA750SN1D
1 R1 49.9 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF49R9V
1 R4 10 kΩ, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF1002V
3 RFB1, RFB2, R6 100 Ω, 1%, 1/16 W, 0603 resistors Panasonic ERJ-3EKF1000V
1 RVO1 453 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF4530V
1 U1 VGA integrated circuit Analog Devices, Inc. AD8337BCPZ-WP
1 U2 2.5 V regulator integrated circuit Analog Devices, Inc. ADR391AUJZ-R2
1 U3 SS rail-to-rail op amp integrated circuit Analog Devices, Inc. AD8541AR
AD8337
Rev. C | Page 29 of 32
OUTLINE DIMENSIONS
072408-B
1
EXPOSED
PA D
(BOTTOM VIEW)
0.50
BSC
PIN 1
INDICATOR
0.50
0.40
0.30
TOP
VIEW
12° MAX 0.70 MAX
0.65 TYP
0.90 MAX
0.85 NOM 0.05 MAX
0.01 NOM
0.20 REF
1.89
1.74
1.59
4
1.60
1.45
1.30
3.25
3.00 SQ
2.75
2.95
2.75 SQ
2.55
58
PIN 1
INDICATOR
SEATING
PLANE
0.30
0.23
0.18
0.60 MAX
0.60 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 94. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8337BCPZ-R21
−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB
AD8337BCPZ-REEL1
−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB
AD8337BCPZ-REEL71
−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB
AD8337BCPZ-WP1
−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB
AD8337-EVALZ1
Evaluation Board with Noninverting Gain Configuration
AD8337-EVALZ-INV1
Evaluation Board with Inverting Gain Configuration
AD8337-EVALZ-SS1
Evaluation Board with Single-Supply Operation
1 Z = RoHS Compliant Part.
AD8337
Rev. C | Page 30 of 32
NOTES
AD8337
Rev. C | Page 31 of 32
NOTES
AD8337
Rev. C | Page 32 of 32
NOTES
©2005–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05575-0-9/08(C)
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Analog Devices Inc.:
AD8337BCPZ-WP AD8337-EVALZ AD8337-EVALZ-INV AD8337-EVALZ-SS AD8337BCPZ-R2 AD8337BCPZ-
REEL AD8337BCPZ-REEL7