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REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
8-Bit Octal, 4-Quadrant
Multiplying, CMOS TrimDAC
FEATURES
Low Cost
Replaces 8 Potentiometers
50 kHz 4-Quadrant Multiplying Bandwidth
Low Zero Output Error
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
±3 V Output Swing
Midscale Preset, Zero Volts Out
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Vertical Deflection Amplitude Adjustment
Waveform Generation and Modulation
GENERAL DESCRIPTION
The AD8842 provides eight general purpose digitally controlled
voltage adjustment devices. The TrimDAC® capability allows
replacement of the mechanical trimmer function in new designs.
The AD8842 is ideal for ac or dc gain control of up to 50 kHz
bandwidth signals. The four-quadrant multiplying capability is
useful for signal inversion and modulation often found in video
vertical deflection circuitry.
Internally the AD8842 contains eight voltage output digital-to-
analog converters, each with separate voltage inputs. A new
current conveyor amplifier design performs the four-quadrant
multiplying function with a single amplifier at the output of the
current steering digital-to-analog converter. This approach of-
fers an improved constant input resistance performance versus
previous voltage switched DACs used in TrimDAC circuits,
eliminating the need for additional input buffer amplifiers.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire serial
input digital interface. Twelve data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 4 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. A serial data output pin
at the opposite end of the serial register allows simple daisy
chaining in multiple DAC applications without additional exter-
nal decoding logic.
TrimDAC is a registered trademark of Analog Devices, Inc.
The current conveyor amplifier is a patented circuit belonging to Analog
Devices, Inc.
The AD8842 consumes only 95 mW from ±5 V power supplies.
For single 5 V supply applications consult the DAC-8841. The
AD8842 is pin compatible with the 1 MHz multiplying band-
width DAC8840. The AD8842 is available in 24-pin plastic
DIP and surface mount SOL-24 packages.
Figure 1. Functional Circuit of One 4-Quadrant
Multiplying Channel
Figure 2. Actual Current Conveyor Implementation of
Multiplying DAC Channel
AD8842
FUNCTIONAL BLOCK DIAGRAM
V
IN
RR
V
OUT
V
OUT
= V
IN
• (D/128 – 1)
VIN
CURRENT CONVEYOR
AMPLIFIER
I1
I2
(1- D)
256 VIN
R
D
256 VIN
R
REF
R
R
VOUT
= VIN (D/128–1)
LOGIC
SERIAL
REGISTER
DATA
8 X 8
DAC
R
E
G
I
S
T
E
R
S
DECODED
ADDRESS
48
8DAC A
8
AD8842
DAC H
8
VDD
LD
SDI
CLK
VINA
VOUTA
VINH
VOUTH
VSS
PRSDO
GND
G
G
A
781/329-4700
781/461-3113
AD8842–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H
Resolution N 8 Bits
Integral Nonlinearity Error INL ±0.2 ±1 LSB
Differential Nonlinearity DNL All Devices Monotonic ±0.4 ±1 LSB
Full-Scale Gain Error G
FSE
2 LSB
Output Offset V
BZE
PR = 0, Sets D = 80
H
525mV
Output Offset Drift TCV
BZ
PR = 0, Sets D = 80
H
5µV/°C
VOLTAGE INPUTS—Applies to All Inputs V
IN
x
Input Voltage Range
1
IVR ±3±4V
Input Resistance R
IN
12 19 kΩ
Input Capacitance C
IN
9pF
DAC OUTPUTS—Applies to All Outputs V
OUT
x
Voltage Range
1
OVR R
L
= 10 kΩ±3±4V
Output Current I
OUT
∆V
OUT
< 1.5 LSB ±3mA
Capacitive Load C
L
No Oscillation 500 pF
DYNAMIC PERFORMANCE—Applies to All DACs
Full Power Gain Bandwidth
1
GBW V
IN
x = ±3 V
P
, R
L
= 2 kΩ, C
L
= 10 pF 10 50 kHz
Slew Rate Measured 10% to 90%
Positive SR+ ∆V
OUT
x = +5.5 V 0.5 1.0 V/µs
Negative SR– ∆V
OUT
x = –5.5 V 1.0 1.8 V/µs
Total Harmonic Distortion THD V
IN
x = 4 V p-p, D = FF
H
, f = 1 kHz, 0.01 %
f
LPF
= 80 kHz, R
L
= 1 kΩ
Spot Noise Voltage e
N
f = 1kHz, V
IN
= 0 V 78 nV/√Hz
Output Settling Time t
S
±1 LSB Error Band, D = 00
H
to FF
H
2.9 µs
D = FF
H
to 00
H
5.4 µs
Channel-to-Channel Crosstalk C
T
Measured Between Adjacent
Channels, f = 100 kHz 72 dB
Digital Feedthrough Q V
IN
x = 0 V, D = 0 to 255
10
5 nV-s
POWER SUPPLIES
Positive Supply Current I
DD
PR = 0 V 10 14 mA
Negative Supply Current I
SS
PR = 0 V 9 13 mA
Power Dissipation
2
P
DISS
95 135 mW
Power Supply Rejection PSRR PR = 0 V, ∆V
DD
= ±5% 0.0001 0.01 %/%
Power Supply Range PSR V
DD
, |V
SS
| 4.75 5.00 5.25 V
DIGITAL INPUTS
Logic High V
IH
2.4 V
Logic Low V
IL
0.8 V
Input Current I
L
±10 µA
Input Capacitance C
IL
7pF
Input Coding Offset Binary
DIGITAL OUTPUT
Logic High V
OH
I
OH
= –0.4 mA 3.5 V
Logic Low V
OL
I
OL
= 1.6 mA 0.4 V
TIMING SPECIFICATIONS
1
Input Clock Pulse Width t
CH
, t
CL
60 ns
Data Setup Time t
DS
40 ns
Data Hold Time t
DH
20 ns
CLK to SDO Propagation Delay t
PD
80 ns
DAC Register Load Pulse Width t
LD
70 ns
Preset Pulse Width t
PR
50 ns
Clock Edge to Load Time t
CKLD
30 ns
Load Edge to Next Clock Edge t
LDCK
60 ns
NOTES
1
Guaranteed by design, not subject to production test.
2
Calculated
limit = 5 V × (I
DD
+ I
SS
).
Specifications subject to change without notice.
REV. –2–
(VDD = +5 V, VSS = –5 V, All VINx = +3 V, TA = –40°C to +85°C, unless otherwise noted.)
A
AD8842
REV. –3–
DETAIL SERIAL DATA INPUT TIMING (PR = “1”)
SDI 1
0A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
LD 1DAC REGISTER LOAD
VOUT 0V
+3V
CLK 1
0
tDS tDH
tPD
tCH
tCL tCKLD tLD tLDCK
tS±1 LSB
±1 LSB ERROR BAND
SDO
CLK
LD
VOUT
(DATA OUT)
Ax or Dx
SDI
(DATA IN) 1
0
1
0
1
0
1
0
+3V
0V
PRESET TIMING
tS±1 LSB
±1 LSB ERROR BAND
PR
VOUT
0
+3V
0V
1tPR
Figure 3. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
V
IN
x to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
, V
SS
V
OUT
x to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
, V
SS
Short Circuit I
OUT
x to GND . . . . . . . . . . . . . . . . . Continuous
Digital Input & Output Voltage to GND . . . . . . . . . . V
DD
, 0 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
Max) . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . .(T
J
Max–T
A
)/θ
JA
Thermal Resistance θ
JA,
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8842 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
A
VOUTC
VOUTB
VOUTD
VINC
VINB
GND
PR
SDI
VSS
SDO
VOUTA
VINA
VIND
VDD
VINE CLK
VINF LD
VOUTE VINH
VOUTF VING
VOUTG VOUTH
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8 17
9 16
10 15
11
TOP VIEW
(Not to Scale)
11
12 13
AD8842
AD8842
REV. –5–
Table I. Serial Input Decode Table
Table II. Input Logic Control Truth Table
CLK LD PR Input Shift Register Operation
L L H No Operation
↑L H Shift One Bit in from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18)
X L L All DAC Registers = 80
H
XΗH Load Serial Register Data into DAC(X) Register
X H X Serial Data Input Register Loading Disabled
*Data shifted into the SDI pin appears twelve clocks later at the SDO pin.
LSB
D0 D1 D2 D3 D4 D5 D6 MSB
D7 LSB
A0 A1 A2 MSB
A3
LAST FIRST
A3 A2 A1 A0
ADDRESSDATA
MSB LSB
DAC UPDATED
NO OPERATION
DAC A
DAC B
DAC C
DAC D
DAC H
NO OPERATION
NO OPERATION
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
1
D7 D6 D5 D4 D3 D2 D1 D0 DAC OUTPUT VOLTAGE
VOUT = (D/128 –1) x VIN
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
MSB LSB
–VIN
(1/128–1) x VIN
(127/128–1) x VIN
(128/128–1) x VIN = 0V; (PRESET VALUE)
(129/128–1) x VIN
(254/128–1) x VIN
(255/128–1) x VIN ≈ VIN
•
•
•
•
•
•
•
•
•
•
•
•
0
0
1
0
0
1
1
A
REV. –6–
AD8842–Typical Performance Characteristics
DIGITAL INPUT CODE – Decimal
LINEARITY ERROR – LSB
+1/2
–1/2
+1/2
0
–1/2
0
2560 19212864
DACs A, B, C, D SUPERIMPOSED
DACs E, F, G, H SUPERIMPOSED
TA = +25°C
VDD = +5V
VSS = – 5V
VINX = +3V
0 64 128
0.3
0.2
–0.1
0.1
0
–0.2
–0.3
–0.4
0.4
192 256
LINEARITY ERROR – LSB
DIGITAL INPUT CODE – Decimal
VDD = +5V
VSS = –5V
VINX = +3V
DAC A
TA = –55 °C
TA = +125 °C
TA = +25 °C
0
–10
–20
–30
–40
GAIN – dB
10k 10M
100k 1M
FREQUENCY – Hz
–180
–315
0
–90
–45
–135
–225
–270
–360
PHASE – Degrees
GAIN –FS
+FS
PHASE
CODE = ALL ONES
PHASE
CODE = ALL ZEROS
VIN = ± 100mV
TA = +25°C
1k 10k 100k 1M 10M
FREQUENCY – Hz
90
0
15
30
45
60
75
105
120
135
CROSSTALK – dB
V
IN
A = 100mV
pp
V
IN
B = 0V
T
A
= +25°C
dB
INPUT A
OUTPUT B
Figure 4. Linearity Error vs.
Digital Code
Figure 5. Linearity Error vs.
Digital Code vs. Temperature
Figure 6. V
OUT
Half Scale (80
H
)
vs. Temperature
Figure 7. Input Resistance (V
IN
)
vs. Temperature
Figure 8. Total Harmonic Distortion
vs. Frequency
Figure 9. V
OUT
Slew Rate
vs. Temperature
Figure 10. Gain and Phase vs.
Frequency (Code = 00
H
or FF
H
)
Figure 11. DAC Crosstalk
vs. Frequency
Figure 12. Voltage Noise Density
vs. Frequency
–75 –50 –25 0 25 50 75 100 125
TEMPERATURE – °C
8
0
VINX = –3V
6
4
2
–2
–4
–8
–10
VOUT HALF SCALE – mV
VINX = +3V
VDD = +4.75V
VSS = –4.75V
21
–75 –50 100 125
TEMPERATURE – °C
REFERENCE INPUT RESISTANCE – kΩ
VIN = +3V
20
19
18
17
16 –25 0 25 50 75
AVG
AVG +2σ
AVG –2σ
VDD = +4.75V
VSS = –4.75V
10 100 1k 10k 100k
FREQUENCY – Hz
0.001
100
10
1
0.1
0.01
TOTAL HARMONIC DISTORTION – %
RL = 2kΩ
VIN = +4Vp-p
fLPF = 80kHz
CODE = FFH
3
2
–75 –50 –25 25
VDD = +4.75V
VSS = –4.75V
∆VIN = ±3V
1
0
4
050 75 100 125
TEMPERATURE – °C
SR+
SR–
VOUT – SLEW RATE – V/µs
A
AD8842
REV. –7–
10
90
100
0%
2V
5µs
5µS
5µs
10
90
100
0%
2V 5µs
Figure 13. Pulse Response—Upper Trace V
IN
@ 2 V/Div
Lower Trace V
OUT
@2 V/Div
Figure 16. Settling Time—Upper Trace LD @ 5 V/Div,
Lower Trace V
OUT
@ 2 V/Div
Figure 17. Digital Feedthrough—V
OUT
@ 10 mV/Div,
V
IN
= 0 V; Code 7F
H
to 80
H
10
90
100
0%
2V
5µs
5µS
5µs
10
90
100
0%
5mV
5V
50ns
10
90
100
0%
5mV 2µs
Figure 15. Crosstalk—V
OUT
@ 5 mV/Div Figure 18. Clock Feedthrough—V
OUT
@ 5 mV/Div
Figure 14. Worst Case 1 LSB Step Change Code 80
H
to 7F
H
,
Upper Trace LD @ 5 V/Div, Lower Trace V
OUT
@ 50 mV/Div
10
90
100
0%
2V 5µs
5V
10
90
100
0%
2V
5µs
5µS
5µs
10
90
100
0%
500ns
50mV
5V
10
90
100
0%
50ns
10mV
A
REV. –8–
AD8842
40
30
20
10
0100 1k 10k 100k 1M
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
+ PSRR
–PSRR
+ PSRR: VDD = +5V±250mV
–PSRR: VSS = –5V±250mV
12
11
10
8
7
–75 –50 –25 0 25 50 75 100 125
TEMPERATURE – °C
SUPPLY CURRENT – mA
9
VIN X = +3V
–ISS @ VDD = +5V
AND VSS = –4V OR –6V
IDD @ VDD = +6V
AND VSS = –5V
IDD @ VDD = +4V
AND VSS = –5V
Figure 21. AC Sweep Frequency
500 mV p-p Amplitude Response Figure 22. Supply Current vs.
Voltage and Temperature
Figure 23. PSRR vs. Frequency
GAIN – dB
1k 10M10k 1M100k
FREQUENCY – Hz
24
–24
–72
–48
0
–12
–36
–60
12
DATA = ØØ H
CØH
AØH
9ØH
88H
84H
82H
81H
80H
VIN = 100mVAC
TA = +25°C
VDD = +5V
VSS = –5V
Figure 26. Output Voltage Drift
Accelerated by Burn-In
Figure 25. Short Circuit Limit
Output Current vs. Voltage
Figure 24. Gain (V
OUT
/V
IN
) and
Feedthrough vs. Frequency
80
–100 5
–40
–80
0
0
–20
20
40
60
4321
OUTPUT AMPLITUDE – mV
FREQUENCY – MHz
–3dB FREQUENCY
100 mVp-p INPUT AMPLITUDE
10
90
100
0%
2V 20µs
2V
Figure 20. AC Sweep Frequency 100 mV p-p Amplitude
Response
Figure 19. 10 kHz Sawtooth Waveform,
Upper Trace V
IN
, Lower Trace V
OUT
–400 5
–200
–300
0
0
–100
100
200
300
4321
OUTPUT AMPLITUDE – mV
FREQUENCY – MHz
–3dB FREQUENCY
500 mVp-p INPUT AMPLITUDE
–4 –3 –2 0–1 1 2 3 4
15
10
–5
5
0
–10
–15
IOUT – mA
SHORT CIRCUIT
CURRENT
LIMITING
SHORT CIRCUIT
CURRENT
LIMITING
TA = +25°C
VDD = +5V
VSS = –5V
CODE = 80H
VOUTX – Volts
5
4
1
3
2
0 100 300
0
–1
–6
6
200 400 500 600
T = HOURS OF OPERATION AT 150°C
HALF SCALE OFFSET – mV
–2
–3
–4
–5
χ
χ– 2σ
χ+ 2σ
VIN = +3V
A
AD8842
REV. –9–
CIRCUIT OPERATION
The AD8842 is a general purpose 8-channel ac or dc signal-
level adjustment device designed to replace potentiometers used
in the three-terminal connection mode. Eight independent
channels of programmable signal level control are available in
this 24-pin package device. The outputs are completely buffered
providing up to 3 mA of output drive-current to drive external
loads. The functional equivalent DAC and amplifier combina-
tion shown in Figure 27 produces four-quadrant multiplication
of the signal inputs applied to V
IN
times the digital input control
word. In addition the AD8842 provides a 50 kHz full power
bandwidth in each four-quadrant multiplying channel. Operat-
ing from plus and minus 5 V power supplies, analog inputs and
outputs of ±3 V are easily accommodated.
Figure 27. Functional Equivalent Circuit to the AD8842
Results in a 4-Quadrant Multiplying Channel
In order to simplify use with a controlling microprocessor a
PCB space saving three-wire serial data interface was chosen.
This interface can be easily adapted to almost all microcom-
puter and microprocessor systems. A clock (CLK), serial data
input (SDI) and a load (LD) strobe pins make up the three-wire
interface. The 12-bit input data word used to change the value
of the internal DAC registers contains a 4-bit address and 8-bits
of data. Using this word combination any DAC register can be
changed at a given time without disturbing the other channels.
A serial data output SDO pin simplifies cascading multiple
AD8842s without adding address decoder chips to the system.
During system power up a logic low on the preset PR pin forces
all DAC registers to 80
H
which in turn forces all the buffer am-
plifier outputs to zero volts. This asynchronous input pin PR
can be activated at any time to force the DAC registers to the
half-scale code 80
H
. This is generally the most convenient place
to start general purpose adjustment procedures.
Achieving 4-Quadrant Multiplying with a Current Conveyor
Amplifier
The traditional current output CMOS digital-to-analog con-
verter requires two amplifiers to perform the current-to-voltage
translation and the half-scale offset to achieve four-quadrant
multiplying capability. The circuit shown in Figure 28 shows
one such traditional connection.
Figure 28. One Traditional Technique to Achieve Four-
Quadrant Multiplying with a Complementary Current
Output DAC
A single new current conveyor amplifier design emulates ampli-
fiers A1 and A2 shown in Figure 28. Figure 29 shows the con-
nection and equations that define this new circuit that achieves
four-quadrant multiplication with only one amplifier.
Figure 29. Current Conveyor Amplifier
Using the equations given in Figure 29 one can calculate the
final output equation as follows:
VO=–1–
D
256
×VIN
R
×R––D
256 ×VIN
R
×R
D
256 –1
VIN +D
256 ×VIN
=2D
256 –1
VIN
=D
128 –1
VIN
V
IN
CURRENT CONVEYOR
AMPLIFIER
I
1
I
2
(1- D)
256
D
256 V
REF
R
REF
R
R
V
OUT
= V
IN
(D/128–1)
V
REF
R
V
OUT
X
4
2
0
–4 –2 0
–2
24
V
OUT – Volts
–4
VIN – Volts
VOUT = VIN (D/128 – 1), WHERE D = 0 TO 255
D = FFH
D = C0H
D = 80H
D = 40H
D = 00H
AD8842 INPUT-OUTPUT VOLTAGE RANGE
VDAC
VOUT
VIN
RR
V
DAC = D/256 × VIN
VOUT = 2 × VDAC – VIN
= 2 (D/256) × VIN – VIN
= (D/128 – 1) × VIN
R/2
A1
R
A2
R/2
CURRENT OUT
DAC
REF
GND
I1
I2
VIN
VO
A
REV. –10–
AD8842
ADJUSTING AC OR DC SIGNAL LEVELS
The four-quadrant multiplication operation of the AD8842 is
shown in Figure 27. For dc operation the equation describing
the relationship between V
IN
, digital inputs and V
OUT
is:
V
OUT
(D) = (D/128-1) × V
IN
(1)
where D is a decimal number between 0 and 255
The actual output voltages generated with a fixed 3 V dc input
applied to V
IN
are summarized in this table.
Table III.
Decimal Comments
Input (D) V
OUT
(D) (V
IN
= 3 V)
0 –3.00 V Inverted FS
1 –2.98
127 –0.02
128 0.00 Zero Output
129 0.02
254 2.95
255 2.98 Full Scale (FS)
Notice that the output polarity is the same as the input polarity
when the DAC register is loaded with 255 (in binary = all ones).
Also note that the output does not exactly equal the input volt-
age. This is a result of the R-2R ladder DAC architecture cho-
sen. When the DAC register is loaded with 0, the output
polarity is inverted and exactly equals the magnitude of the in-
put voltage V
IN
. The actual voltage measured when setting up a
DAC in this example will vary within the ±1 LSB linearity error
specification of the AD8842. The calculated voltage error would
be ±0.023 V (= ±3 V/128).
If V
IN
is an ac signal such as a sine wave, then we can use Equa-
tion 2 to describe circuit performance.
V
OUT
(t, D) = (D/128-1) × A sin (
ω
t) (2)
where
ω
= 2 πf, A = sine wave amplitude, and D = decimal
input code.
This transfer characteristic Equation 2 lends itself to amplitude
and phase control of the incoming signal V
IN
. When the DAC is
loaded with all zeros, the output sine wave is shifted by 180°
with respect to the input sine wave. This powerful multiplying
capability can be used for a wide variety of modulation, wave-
form adjustment and amplitude control.
SIGNAL INPUTS (V
IN
A, B, C, D, E, F, G, H)
The eight independent V
IN
inputs have a constant input-
resistance nominal value of 19 kΩ as specified in the electrical
characteristics table. These signal-inputs are designed to receive
not only dc, but ac input voltages. The signal-input voltage
range can operate to within one volt of either supply. That is,
the operating input-voltage-range is:
V
SS
+ 1 V < V
IN
x < (V
DD
– 1 V) (3)
DAC OUTPUTS (V
OUT
A, B, C, D, E, F, G, H)
The eight D/A converter outputs are fully buffered by the
AD8842’s internal amplifier. This amplifier is designed to drive
up to 1 kΩ loads in parallel with 100 pF. However, in order to
minimize internal device power consumption, it is recom-
mended whenever possible to use larger values of load resis-
tance. The amplifier output stage can handle shorts to GND;
however, care should be taken to avoid continuous short circuit
operation.
The low output impedance of the buffers minimizes crosstalk
between analog input channels. A graph (Figure 11) of analog
crosstalk between channels is provided in the typical perfor-
mance characteristics section. At 100 kHz 70 dB of channel-to-
channel isolation exists. It is recommended to use good circuit
layout practice such as guard traces between analog channels
and power supply bypass capacitors. A 0.01 µF ceramic in paral-
lel with a 1 µF–10 µF tantalum capacitor provides a good power
supply bypass for most frequencies encountered.
DIGITAL INTERFACING
The four digital input pins (CLK, SDI, LD, PR) of the AD8842
were designed for TTL and 5 V CMOS logic compatibility. The
SDO output pin offers good fanout in CMOS logic applications
and can easily drive several AD8842s.
The Logic Contro Input Truth Table II describes how to shift
data into the internal 12-bit serial input register. Note that the
CLK is a positive-edge sensitive input. If mechanical switches
are used for breadboard evaluation, they should be debounced
by a flipflop or other suitable means. The basic three-wire serial
data interface setup is shown in Figure 30.
Figure 30. Basic Three-Wire Serial Interface
The required address plus data input format is defined in the se-
rial input decode Table I. Note there are 8 address states that
result in no operation (NOP) or activity in the AD8842 when
the positive edge triggered load-strobe (LD) is activated. This
NOP can be used in cascaded applications where only one DAC
out of several packages needs updating. The packages not re-
quiring data changes would receive the NOP address, that is, all
zeros. It takes 12 clocks on the CLK pin to fully load the serial-
input shift-register. Data on the SDI input pin is subject to the
timing diagram (Figure 3) data setup and data hold time re-
quirements. After the twelfth clock pulse the processor needs to
activate the LD strobe to have the AD8842 decode the serial-
register contents and update the target DAC register with the 8-
bit data word. This needs to be done before the thirteenth
positive clock edge. The timing requirements are provided in
the electrical characteristic table and in the Figure 3 timing dia-
gram. After twelve clock edges, data initially loaded into the
shift register at SDI appears at the shift register output SDO. A
multiple package interface circuit is shown in Figure 31. In this
topology all the devices are clocked with the new data; however,
only the decoded package address signal updates the target
package LD strobe which is being used as a chip select.
AD8842
7
20
17
16
21
19
6
+5V
–5V
PR
SDI
CLK
LD
ZERO VOLTAGE
OUTPUT PRESET
SERIAL DATA
CLOCK
LOAD STROBE
A
AD8842
REV. –11–
Figure 32 shows a three-wire interface for a single AD8842 that
easily cascades for multiple packages. This circuit topology often
called daisy chaining requires preformating all the serial data for
each package in the chain. In the case of the 3 packages shown a
36 bit data word must be completely clocked into all the
AD8842 serial data input registers then the LD strobe would
transfer the data bits into the DAC registers updating one DAC
in each package.
Figure 32. Three-Wire Interface Updates Multiple
AD8842s
Figure 31. Addressing Multiple AD8842 Packages
There is some digital feedthrough from the digital input pins.
Operating the clock only when the DAC registers require updat-
ing minimizes the effect of the digital feedthrough on the analog
signal channels. Measurements of DAC switch feedthrough
shown in the electrical characteristics table were accomplished
by grounding the V
IN
x inputs and cycling the data codes be-
tween all zeros and all ones. Under this condition 5 nV-s of
feedthrough was measured on the output of the switched DAC
channel. An adjacent channel measured less than 1 nV-s of digi-
tal crosstalk. The digital feedthrough and crosstalk photographs
shown in the typical performance characteristics section display
these characteristics (Figures 15 and 17).
AD8842
#2
LD
CLK
SDI
AD8842
#1
LD
CLK
SDI
AD8842
#N
LD
CLK
SDI
•
•
•
CLOCK
DATA
CODED
PACKAGE
ADDRESS
WR
ADDRESSS
DECODE
EN
•
•
•
ANALOG CONNECTIONS OMITTED FOR CLARITY
µC
PA0
PA1
PA2
DATA
CLOCK
LD
DAC A
SDI
CLK
AD8842 #1
LD SDO DAC H
DAC ASDI
CLK
AD8842 #2
LD SDO DAC H
DAC ASDI
CLK
AD8842 #3
LD SDO DAC H
•
•
VO
U
V
O
•
•
•
A
AD8842
–12– REV. A
OUTLINE DIMENSIONS
CONTROL LING DIMENSIONS ARE IN INCHES; M ILLIME TER DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-O F F INCH EQUI VALENT S FOR
REF ERENCE ONLY AND ARE NOT APP ROPRIAT E FO R US E IN DESIGN.
CORNER LEADS MAY BE CONFI GURED AS WHOLE OR HALF LEADS.
COM P LIANT TO JEDEC STANDARDS MS-001
071006-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2. 92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
112
13
0.100 (2.54)
BSC
1.280 ( 32.51)
1.250 ( 31.75)
1.230 ( 31.24)
0.210 ( 5 .33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.00 5 (0.13)
MIN
0.280 (7. 11)
0.250 (6.35)
0.240 (6.10)
0.060 ( 1.52)
MAX
0.430 (10.92)
MAX
0.01 4 (0.36)
0.01 0 (0.25)
0.00 8 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 ( 0.38)
GAUGE
PLANE
0.195 ( 4 .95)
0.130 ( 3 .30)
0.115 (2.92)
Figure 33. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY ANDARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
24 13
12
1
1.27 (0.0500)
BSC
12-09-2010-A
Figure 34. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
AD8842
REV. A –13–
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8842AN −40°C to +85°C 24-Lead PDIP N-24-1
AD8842ANZ −40°C to +85°C 24-Lead PDIP N-24-1
AD8842AR −40°C to +85°C 24-Lead SOIC_W RW-24
AD8842AR-REEL −40°C to +85°C 24-Lead SOIC_W RW-24
AD8842ARZ −40°C to +85°C 24-Lead SOIC_W RW-24
AD8842ARZ-REEL −40°C to +85°C 24-Lead SOIC_W RW-24
1 Z = RoHS Compliant Part.
REVISION HISTORY
10/11—Rev. 0 to Rev. A
Changes to Pin 13 Mnemonic ......................................................... 4
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 13
4/94—Revision 0: Initial Version
©1994–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01904-0-10/11(A)