MC14044BCP - ON SEMICONDUCTOR

August, 2014 − Rev. 10 1Publication Order Number:

MC14043B/D

MC14043B, MC14044B

CMOS MSI

Quad R−S Latches

The MC14043B and MC14044B quad R−S latches are constructed

with MOS P−Channel and N−Channel enhancement mode devices in

a single monolithic structure. Each latch has an independent Q output

and set and reset inputs. The Q outputs are gated through three−state

buffers having a common enable input. The outputs are enabled with

a logical “1” or high on the enable input; a logical “0” or low

disconnects the latch from the Q outputs, resulting in an open circuit at

the Q outputs.

Features

•Double Diode Input Protection

•Three−State Outputs with Common Enable

•Outputs Capable of Driving Two Low−power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient) −0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin ±10 mA

PDPower Dissipation, per Package

(Note 1) 500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering) 260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING DIAGRAMS

SOIC−16

140xxBG

AWLYWW

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Indicator

SOEIAJ−16

MC14043B

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

1

16

1

16

SOIC−16

D SUFFIX

CASE 751B

SOEIAJ−16

F SUFFIX

CASE 966

MC14043B, MC14044B

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2

MC14043B

TRUTH TABLE

X = Don’t Care

MC14044B

SRE Q

High

Impedance

XX0

No Change

0

1

0

1

0

1

0

1

TRUTH TABLE

X = Don’t Care

S R EQ

High

Impedance

XX0

0

1

0

No Change

0

1

0

1

0

1

ENABLE

R3

S3

R2

S2

R1

S1

R0

S0 4

3

6

7

12

11

14

15

5

Q3

Q2

Q1

Q0

2

9

10

1

ENABLE

S3

R3

S2

R2

S1

R1

S0

R0 4

3

6

7

12

11

14

15

5

Q3

Q2

Q1

Q0

13

9

10

1

VDD = PIN 16

VSS = PIN 8

NC = PIN 2

VDD = PIN 16

VSS = PIN 8

NC = PIN 13

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

S2

NC

S3

R3

VDD

Q1

Q2

R2

S0

R0

Q0

Q3

VSS

R1

S1

E

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

R2

Q0

R3

S3

VDD

Q1

Q2

S2

R0

S0

NC

Q3

VSS

S1

R1

E

NC = NO CONNECTION

MC14043B MC14044B

MC14043B, MC14044B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbo

l

VDD

Vdc

− 55_C 25_C 125_C

Unit

Min Max Min Typ

(Note 2) Max Min Max

Output Voltage “0” Leve

l

Vin = VDD or 0

“1” Leve

l

Vin = 0 or VDD

VOL 5.0

10

15

−

0.05

−

0

0.05

−

0.05

Vdc

VOH 5.0

10

15

4.95

9.95

14.95

−

4.95

9.95

14.95

5.0

10

15

−

4.95

9.95

14.95

−

Vdc

Input Voltage “0” Leve

l

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Leve

l

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIL 5.0

10

15

−

1.5

3.0

4.0

−

2.25

4.50

6.75

1.5

3.0

4.0

−

1.5

3.0

4.0

Vdc

VIH 5.0

10

15

3.5

7.0

11

−

3.5

7.0

11

2.75

5.50

8.25

−

3.5

7.0

11

−

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sin

k

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOH 5.0

5.0

10

15

–3.0

–0.64

–1.6

–4.2

−

–2.4

–0.51

–1.3

–3.4

–4.2

–0.88

–2.25

–8.8

−

–1.7

–0.36

–0.9

–2.4

−

mAdc

IOL 5.0

10

15

0.64

1.6

4.2

−

0.51

1.3

3.4

0.88

2.25

8.8

−

0.36

0.9

2.4

−

mAdc

Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc

Input Capacitance

(Vin = 0) Cin − − − − 5.0 7.5 − − pF

Quiescent Current

(Per Package) IDD 5.0

10

15

−

1.0

2.0

4.0

−

0.002

0.004

0.006

1.0

2.0

4.0

−

30

60

120

mAdc

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs all

buffers switching)

IT5.0

10

15

IT = (0.58 mA/kHz) f + IDD

IT = (1.15 mA/kHz) f + IDD

IT = (1.73 mA/kHz) f + IDD

mAdc

Three−State Output Leakage

Current ITL 15 − ±0.1 − ±0.0001 ±0.1 − ±3.0 mAdc

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14043B, MC14044B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time

tTLH = (1.35 ns/pF) CL + 32.5 ns

tTLH = (0.60 ns/pF) CL + 20 ns

tTLH = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎÎ

tTLH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time

tTHL = (1.35 ns/pF) CL + 32.5 ns

tTHL = (0.60 ns/pF) CL + 20 ns

tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎÎ

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

tPLH = (0.90 ns/pF) CL + 130 ns

tPLH = (0.36 ns/pF) CL + 57 ns

tPLH = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎÎ

tPLH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

175

75

60

ÎÎÎÎ

350

175

120

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tPHL = (0.90 ns/pF) CL + 130 ns

tPHL = (0.90 ns/pF) CL + 57 ns

tPHL = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎÎ

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

175

75

60

ÎÎÎÎ

350

175

120

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Set, Set Pulse Width

ÎÎÎÎÎ

tW

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

200

100

70

ÎÎÎÎ

80

40

30

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset, Reset Pulse Width

ÎÎÎÎÎ

tW

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

200

100

70

ÎÎÎÎ

80

40

30

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Three−State Enable/Disable Delay

ÎÎÎÎÎ

tPLZ,

tPHZ,

tPZL,

tPZH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

150

80

55

ÎÎÎÎ

300

160

110

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

AC WAVEFORMS

MC14043B MC14044B

20 ns 20 ns

90%

10%

RESET

SET

Q

tPHL tPLH

20 ns 20 ns

50%

90%

50%

10%

tTHL tTLH

90%

50%

10%

VDD

VSS

VDD

VSS

VOH

VOL

RESET

SET

Q

20 ns 20 ns

90%

10%

50%

20 ns 20 ns

90%

10%

50%

tTLH tTHL

50% 10%

90%

tPLH tPHL

VDD

VSS

VDD

VSS

VOH

VOL

MC14043B, MC14044B

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5

THREE−STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3−State Tests

Test Enable S1 S2 Q

MC14043B MC14044B

S R S R

tPZH Open Closed A VDD VSS VSS VDD

tPZL Closed Open B VSS VDD VDD VSS

tPHZ Open Closed A VDD VSS VSS VDD

tPLZ Closed Open B VSS VDD VDD VSS

ENABLE

QA

QB

50%

tPZH

10%

tPZL

tPHZ

tPLZ

10%

90%

VDD

VSS

VDD

VOL

VOH

VSS

ORDERING INFORMATION

Device Package Shipping†

MC14043BDG SOIC−16

(Pb−Free) 48 Units / Rail

NLV14043BDG* SOIC−16

(Pb−Free) 48 Units / Rail

MC14043BDR2G SOIC−16

(Pb−Free) 2500 Units / Tape & Reel

NLV14043BDR2G* SOIC−16

(Pb−Free) 2500 Units / Tape & Reel

MC14043BFELG SOEIAJ−16

(Pb−Free) 2000 Units / Tape & Reel

MC14044BDG SOIC−16

(Pb−Free) 48 Units / Rail

NLV14044BDG* SOIC−16

(Pb−Free) 48 Units / Rail

MC14044BDR2G SOIC−16

(Pb−Free) 2500 Units / Tape & Reel

NLV14044BDR2G* SOIC−16

(Pb−Free) 2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

TO

OUTPUT

UNDER

TEST

VDD

S1

S2

1 k

CL

50 pF

VSS

MC14043B, MC14044B

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6

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

16

89

8X

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14043B, MC14044B

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7

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

CASE 966

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LEQ1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

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P

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Phone: 81−3−5817−1050

MC14043B/D

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