a Quad 3000 V/s, 35 mW Current Feedback Amplifier AD8004 GENERAL DESCRIPTION The AD8004 is a quad, low power, high speed amplifier designed to operate on single or dual supplies. It utilizes a current feedback architecture and features high slew rate of 3000 V/ms making the AD8004 ideal for handling large amplitude pulses. Additionally, the AD8004 provides gain flatness of 0.1 dB to OUTPUT 1 -IN 2 +VS 4 0.1 -1 5VS -2 +5VS -3 0 -4 -0.1 +5VS -5 5VS -0.2 -6 -0.3 -7 -0.4 -8 -0.5 1 10 40 FREQUENCY - MHz 100 NORMALIZED FREQUENCY RESPONSE - dB NORMALIZED FLATNESS - dB G = +2 VIN = 50mV rms RL = 100 RF = 1.10k R PACKAGE -9 500 Figure 1. Frequency Response and Flatness, G = +2 4 -IN 6 13 -IN 12 +IN AD8004 (TOP VIEW) +IN 5 11 -VS 10 +IN 2 3 9 -IN 8 OUTPUT OUTPUT 7 30 MHz while offering differential gain and phase error of 0.04% and 0.10. This makes the AD8004 suitable for video electronics such as cameras and video switchers. The AD8004 offers low power of 3.5 mA/amplifier and can run on a single +4 V to +12 V power supply, while being capable of delivering up to 50 mA of load current. All this is offered in a small 14-lead SOIC package. These features make this amplifier ideal for portable and battery powered applications where size and power are critical. The outstanding bandwidth of 250 MHz along with 3000 V/ms of slew rate make the AD8004 useful in many general-purpose, high speed applications where dual power supplies of up to 6 V and single supplies from 4 V to 12 V are needed. The AD8004 is available in the industrial temperature range of -40C to +85C in the R package. 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 1 0 14 OUTPUT 1 +IN 3 DIFF GAIN - % APPLICATIONS Image Scanners Active Filters Video Switchers Special Effects CONNECTION DIAGRAM SOIC (R) Package DIFF PHASE - Degrees FEATURES High Speed 250 MHz -3 dB Bandwidth (G = +1) 3000 V/s Slew Rate 21 ns Settling Time to 0.1% 1.8 ns Rise Time for 2 V Step Low Power 3.5 mA/Amp Power Supply Current (35 mW/Amp) Single Supply Operation Fully Specified for +5 V Supply Good Video Specifications (RL = 150 , G = +2) Gain Flatness 0.1 dB to 30 MHz 0.04% Differential Gain Error 0.10 Differential Phase Error Low Distortion -78 dBc THD at 5 MHz -61 dBc THD at 20 MHz High Output Current of 50 mA Available in a 14-Lead SOIC 80 IRE RL = 150 VS = 5V RF = 1.21k 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 80 IRE RL = 150 VS = 5V RF = 1.21k 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH Figure 2. Differential Gain/Differential Phase REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003-2015 Analog Devices, Inc. All rights reserved. AD8004-SPECIFICATIONS (@ T = +25C, V = 5 V, R = 100 , unless otherwise noted.) A Parameter S L Test Conditions/Comments AD8004A Min Typ Max AD8004S Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Rise and Fall Time (10% to 90%) NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, R Package, Worst Case Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Differential Gain Error Differential Phase Error G = +2 G = +2, VO = 4 V Step G = -2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step 30 3000 2000 21 1.8 30 3000 2000 21 1.8 MHz V/s V/s ns ns fC = 5 MHz, VO = 2 V p-p, RL = 1 k f = 5 MHz, G = +2, RL = 1 k f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, RL = 150 , RF = 1.21 k NTSC, G = +2, RL = 150 , RF = 1.21 k NTSC, G = +2, RL = 1 k, RF = 1.21 k NTSC, G = +2, RL = 1 k, RF = 1.21 k -78 -69 1.5 38 38 0.04 0.10 0.01 0.04 -78 1.5 38 38 0.04 0.10 0.01 0.04 dBc dB nV/Hz pA/Hz pA/Hz % Degree % Degree 1.0 3.5 1.5 5 15 35 90 110 40 110 120 290 220 1.0 3.5 1.5 6 15 35 90 120 40 110 130 290 220 mV mV V/C A A A A k k 2 50 1.5 3.2 M pF V 58 1 12 dB A/V A/V 3.9 50 180 V mA mA DC PERFORMANCE Input Offset Voltage TMIN to TMAX Offset Drift -Input Bias Current TMIN to TMAX +Input Bias Current Open-Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage -Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current TMIN to TMAX VO = 2.5 V TMIN to TMAX 170 +Input -Input +Input 2 50 1.5 3.2 VCM = 2.5 V VCM = 2.5 V, TMIN to TMAX VCM = 2.5 V, TMIN to TMAX 52 R L = 150 100 POWER SUPPLY Operating Range Total Quiescent Current Power Supply Rejection Ratio -Input Current +Input Current 170 58 1 12 3.9 50 180 2.0 TMIN to TMAX VS = 2 V TMIN to TMAX TMIN to TMAX 56 52 14 16 62 0.5 4 100 6.0 17 20 2.0 56 14 16 62 0.5 4 6.0 V 17 mA 23 mA dB A/V A/V Specifications subject to change without notice. -2- REV. D AD8004 SPECIFICATIONS (@ T = +25C, V = +5 V, R = 100 , unless otherwise noted.) A Parameter S L Test Conditions/Comments Min AD8004A Typ Max Min AD8004S Typ Max Unit DYNAMIC PERFORMANCE Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Rise and Fall Time (10% to 90%) NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, R Package, Worst Case Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Differential Gain Error Differential Phase Error G = +2 G = +2, VO = 2 V Step G = +2, VO = 2 V Step 30 1100 24 30 1100 24 MHz V/s ns G = +2, VO = 2 V Step 2.3 2.3 ns fC = 5 MHz, VO = 2 V p-p, RL = 1 k -65 -65 dBc f = 5 MHz, G = +2, RL = 1 k f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, RL = 150 , RF = 1.21 k NTSC, G = +2, RL = 150 , RF = 1.21 k NTSC, G = +2, RL = 1 k, RF = 1.21 k NTSC, G = +2, RL = 1 k, RF = 1.21 k -69 1.5 38 38 0.06 0.25 0.01 0.08 1.5 38 38 0.06 0.25 0.01 0.08 dB nV/Hz pA/Hz pA/Hz % Degree % Degree DC PERFORMANCE Input Offset Voltage 1.0 1 15 20 TMIN to TMAX Offset Drift -Input Bias Current TMIN to TMAX 35 +Input Bias Current Open Loop Transresistance INPUT CHARACTERISTICS Input Resistance TMIN to TMAX VO = +1.5 V to +3.5 V TMIN to TMAX 140 +Input -Input +Input Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage VCM = +1 V to +3 V -Input Current VCM = +1 V to +3 V, TMIN to TMAX +Input Current VCM = +1 V to +3 V, TMIN to TMAX 52 OUTPUT CHARACTERISTICS Output Voltage Swing R L = 150 Output Current Short Circuit Current 80 100 100 115 230 170 35 140 TMIN to TMAX VS = +1 V, VCM = +2.5 V TMIN to TMAX TMIN to TMAX 56 -3- 230 170 2.5 4 mV mV V/C 80 A 110 A 100 A 125 A k k 2 50 1.5 2 50 1.5 M pF 3.2 3.2 V 57 2 15 dB A/V A/V 0.9 to 4.1 50 95 V mA mA 57 2 15 0, +4 Specifications subject to change without notice. REV. D 1.0 1 15 20 52 0.9 to 4.1 50 95 POWER SUPPLY Operating Range Total Quiescent Current Power Supply Rejection Ratio -Input Current +Input Current 2.5 3 13 14.5 62 1 6 +12 14 15.5 0, +4 56 13 14.5 62 1 6 +12 14 17.5 V mA mA dB A/V A/V AD8004 ABSOLUTE MAXIMUM RATINGS1, 2 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . Note 2 Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (R) . . . . -65C to +125C Operating Temperature Range A Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C S Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C The maximum power that can be safely dissipated by the AD8004 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8004 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power ratings. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 14-Lead SOIC Package: JA = 140C/W, JC = 30C/W ORDERING GUIDE Model 1 Temperature Range Package Description Package Option AD8004ARZ-14 - 40C to +85C 14-Lead SOIC R-14 R-14 AD8004ARZ-14-REEL7 -40C to +85C AD8004AR-EBZ 1 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8004 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 604 604 50 SCOPE INPUT 249 499 50 SCOPE INPUT VIN 50 VIN 50 50 61.9 +VS +VS 0.1F 10F 0.1F 10F 0.1F 10F 0.1F 10F -VS -VS Figure 4. Test Circuit; Gain = -2 Figure 3. Test Circuit; Gain = -2 -4- REV. D Typical Performance Characteristics- AD8004 TPC 1.1 100 mV Step Response; G = +2, VS = 2.5 V or 5 V TPC 4.1 100 mV Step Response; G = -2, VS = 2.5 V or 5 V TPC 2.1 Step Response; G = +2, VS = 5 V TPC 5.1 Step Response; G = -2, VS = 5 V 1 G = +1, RF = 698 1 NORMALIZED FREQUENCY RESPONSE - dB NORMALIZED FREQUENCY RESPONSE - dB 2 0 RL = 100 VIN = 50mV (G = +1, +2) VIN = 5mV (G = +10) -1 -2 G = +2, RF = 604 -3 -4 -5 G = +10, RF = 499 -6 -7 -8 VS = 5V RF = 499 VIN = 50mV rms RL = 100 N PACKAGE -1 -2 -3 G = -2 G = -10 -4 -5 -6 -7 -8 -9 1 10 40 FREQUENCY - MHz 100 1 500 TPC 3. Frequency Response; G = +1, +2, +10; VS = 5 V 10 40 FREQUENCY - MHz 100 500 TPC 6.2 Frequency Response; G = -1, -2, -10 1 VS = 2.5 V operation is identical to VS = +5 V single-supply operation. 2 The N-14 package option is no longer available; the R-14 package performance may vary. REV. D G = -1 0 -5- AD8004 9 3 6 0 1V rms -3 3 OUTPUT LEVEL - dBV OUTPUT LEVEL - dBV 1V rms 0 -3 -6 -9 -12 G = +2 VS = 5V RF = 604 -15 -6 -9 -12 -15 -18 -24 -18 -21 1 10 40 FREQUENCY - MHz -27 500 100 TPC 7. Large Signal Frequency Response; VS = 5.0 V, G = +2, RF = 604 1 10 40 FREQUENCY - MHz 500 -40 G = +2 VO = 2V p-p RF = 698 -50 2ND RL = 150 -60 -70 -80 2ND RL = 1k -90 10 1 -70 -80 2ND RL = 1k -100 1 20 10 TPC 11. Distortion vs. Frequency; VS = +5 V -10 1 -2 -3 0 -4 -0.1 -5 +5VS 5VS -0.2 -6 -0.3 -7 -0.4 -8 -0.5 -9 500 1 10 40 FREQUENCY - MHz 100 -15 604 50 VIN -25 VOUT 154 -20 CMRR - dB 0.1 -1 5VS 604 NORMALIZED FREQUENCY RESPONSE - dB 0 5VS 20 FREQUENCY - MHz TPC 8. Distortion vs. Frequency; VS = 5 V +5VS 3RD RL = 150 3RD RL = 1k -60 FREQUENCY - MHz G = +2 VIN = 50mV rms RL = 100 RF = 1.10k R PACKAGE 2ND RL = 150 -90 3RD RL = 1k -100 G = +2 VO = 2V p-p RF = 698 3RD RL = 150 DISTORTION - dBc -50 NORMALIZED FLATNESS - dB 100 TPC 10. Large Signal Frequency Response; VS = +5.0 V, G = +2, RF = 604 -40 DISTORTION - dBc G = +2 VS = +5V RF = 604 -21 57.6 154 +5VS -30 -35 -40 -45 -50 +5VS -55 5VS -60 0.03 0.1 1 10 FREQUENCY - MHz 100 500 TPC 12. CMRR vs. Frequency; VS = 5 V or +5 V, VIN = 200 mV rms, Other Sides Are Equal, RTO TPC 9. Frequency Response and Flatness, G = +2 -6- REV. D AD8004 100 1000 200 10 100 70 + OR - INPUT CURRENT NOISE 50 40 30 20 VOLTAGE NOISE 1 10 100 1k 10k FREQUENCY - Hz 100k -20 G = +2 5VS OR 2.5VS RF = 1k 100mV rms ON TOP OF dc BIAS +PSRR -30 PSRR - dB 300 -10 INPUT CURRENT NOISE - pA/ Hz INPUT VOLTAGE NOISE - nV/ Hz 500 0 -40 -PSRR -50 -60 -70 10 1M -80 10k 100k TPC 13. Noise vs. Frequency, VS = +5 V or 5 VS 1M 10M FREQUENCY - Hz 100M 500M TPC 16. PSRR vs. Frequency -20 -30 G = +2 RF = 698 POWER = 0dBm (224mV rms) 10 +5VS 1 -40 RBT = 50 5VS OR +5VS CROSSTALK - dB IMPEDANCE - 100 RBT = 0 -50 -60 G = +2 RF = 1.10k 5VS VIN = 200mV rms INPUT TO SIDE 1 RL1 = 1k R PACKAGE OUTPUT = SIDE 2 OUTPUT = SIDE 4 -70 -80 OUTPUT = SIDE 3 -90 5VS 0.1 -100 -110 0.01 0.03 0.1 1 10 FREQUENCY - MHz 100 -120 0.03 500 TPC 14. Output Impedance vs. Frequency 0.1 1 10 FREQUENCY - MHz 100 500 TPC 17. Crosstalk (Output to Output) vs. Frequency 110 0 GAIN 60 100 50 90 40 80 20 10 -240 VIN = -40dBm VS = 5V -50 PHASE 60 -100 50 0 40 30 -150 20 0.1 1 10 FREQUENCY - MHz 100 10 100k 500 TPC 15. Open-Loop Voltage Gain and Phase REV. D 70 -10 -360 0.03 0 1M 10M FREQUENCY - Hz 100M -200 1G TPC 18. Open-Loop Transimpedance Gain -7- PHASE - Degrees 30 PHASE -180 GAIN - dB 90 GAIN - dB PHASE - Degrees GAIN AD8004 9 G = +2 RF = 1.21k 8 5VS 7 SWING - V p-p 6 5 4 3 +5VS 2 1 0 10 100 1000 LOAD RESISTANCE - 10000 TPC 22. Output Voltage Swing vs. Load TPC 19. Short-Term Settling Time 10 9 G = +2 RF = 1.21k f = 100kHz PEAK-TO-PEAK OUTPUT AT CLIPPING POINT - V 8 RL = 1k 7 6 RL = 100 5 4 3 2 1 0 5 6 7 8 9 10 TOTAL SUPPLY VOLTAGE - V 11 12 DIFF GAIN - % 0.03 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 80 IRE RL = 150 VS = 5V RF = 1.21k 80 IRE RL = 1k VS = 5V RF = 1.21k 0.02 0.01 0.00 -0.01 -0.02 -0.03 1ST 2ND 3RD 4TH 5TH 6TH 7TH 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 8TH 1ST 9TH 10TH 11TH DIFF PHASE - Degrees DIFF GAIN - % 4 TPC 23. Output Swing vs. Supply TPC 20. Long-Term Settling Time DIFF PHASE - Degrees 3 80 IRE RL = 150 VS = 5V RF = 1.21k 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 8TH 9TH 10TH 11TH 80 IRE RL = 1k VS = 5V RF = 1.21k 1ST 9TH 10TH 11TH 2ND 3RD 4TH 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 2ND 3RD 4TH 5TH 6TH 7TH TPC 24. Differential Gain/Phase, RL = 1 k TPC 21. Differential Gain/Differential Phase -8- REV. D AD8004 The more exact relationships that take into account open-loop gain errors are: THEORY OF OPERATION The AD8004 is a member of a new family of high speed currentfeedback (CF) amplifiers offering new levels of bandwidth, distortion, and signal-swing capability vs. power. Its wide dynamic range capabilities are due to both a complementary high speed bipolar process and a new design architecture. The AD8004 is basically a two stage (Figure 30) rather than the conventional one stage design. Both stages feature the current-on-demand property associated with current feedback amplifiers. This gives an unprecedented ratio of quiescent current to dynamic performance. The important properties of slew rate and full power bandwidth benefit from this performance. In addition the second gain stage buffers the effects of load impedance, significantly reducing distortion. AV = DC AND AC CHARACTERISTICS As with traditional op amp circuits the dc closed-loop gain is defined as: RF RN R AV = G = - F RN for inverting (G is negative) G RF G 1+ + AO (s) T O (s) for noninverting (G is positive) In these equations the open-loop voltage gain (AO(s)) is common to both voltage and current-feedback amplifiers and is the ratio of output voltage to differential input voltage. The open-loop transimpedance gain (TO(s)) is the ratio of output voltage to inverting input current and is applicable to current-feedback amplifiers. The open-loop voltage gain and open-loop transimpedance gain (TO(s)) of the AD8004 are plotted vs. frequency in TPCs 15 and 18. These plots and the basic relationships can be used to predict the first order performance of the AD8004 over frequency. At low closed-loop gains the term (RF/TO(s)) dominates the frequency response characteristics. This gives the result that bandwidth is constant with gain, a familiar property of current feedback amplifiers. A full discussion of this new amplifier architecture is available on the data sheet for the AD8011. This discussion only covers the basic principles of operation. AV = G = 1 + G RF 1- G 1+ + AO (s) T O (s) AV = noninverting operation An RF of 1 k has been chosen as the nominal value to give optimum frequency response with acceptable peaking at gains of +2/-1. As can be seen from the above relationships, at higher closed-loop gains reducing RF has the effect of increasing closedloop bandwidth. Table I gives optimum values for RF and RG for a variety of gains. inverting operation A1 CD IPP IPN IQ1 A2 C P1 Q3 CP2 Q1 ICQ + IO VN VP V O ZI A3 Q2 RF IE RG Q4 IQ1 A2 INP IPN A1 C P1 CD AD8004 Figure 5. Simplified Block Diagram REV. D VO RL Z2 -9- CL AD8004 DRIVING CAPACITIVE LOADS The AD8004 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in Figure 6. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. 1k RSERIES AD8004 1k RL 1k CL Figure 6. Driving Capacitive Load In noninverting gains, the effect of extra capacitance on summing junctions is far more pronounced than with inverting gains. Figure 9 shows an example of this. Note that only 1 pF of added junction capacitance causes about a 70% bandwidth extension and additional peaking on a gain = +2. For an inverting gain = -2, 5 pF of additional summing junction capacitance caused a small 10% bandwidth extension. Extra output capacitive loading also causes bandwidth extensions and peaking. The effect is more pronounced with less resistive loading from the next stage. Figure 10 shows the effect of direct output capacitive loads for gains of +2 and -2. For both gains CLOAD was set to 10 pF or 0 pF (no extra capacitive loading). For each of the four traces in Figure 10 the resistive loads were 100 . Figure 11 also shows capacitive loading effects with a lighter output resistive load. Note that even though bandwidth is extended 2, the flatness dramatically suffers. 2 40 RF = 698 1 RF = 1.1k 0 RF = 909 RSERIES - NORMALIZED GAIN - dB, G = +2 30 20 0 5 10 15 20 -2 RF = 604 G = +2 -3 0 -4 -1 VIN = 50mV rms VS = 5V RL = 100 R PACKAGE -2 -3 -5 -5 -6 RF = 845 -4 25 RF = 1.10k 1 10 40 FREQUENCY - MHz CL - pF -7 -8 500 100 Figure 8. RFEEDBACK vs. Frequency Response, G = +1/+2 Figure 7. Recommended RSERIES vs. Capacitive Load for 30 ns Settling to 0.1% 2 OPTIMIZING FLATNESS G = +2 The fine scale gain flatness and -3 dB bandwidth is affected by RFEEDBACK selection as is normal of current feedback amplifiers. With the exception of gain = +1, the AD8004 can be adjusted for either maximal flatness with modest closed-loop bandwidth or for mildly peaked-up frequency response with much more bandwidth. Figure 8 shows the effect of three evenly spaced R F changes upon gain = +1 and gain = +2. Table I shows the recommended component values for achieving maximally flat frequency response as well as a faster slightly peaked-up frequency response. CJ = 1pF CJ = 0 2 0 -2 NORMALIZED GAIN - dB, G = -2 G = -2 Printed circuit board parasitics and device lead frame parasitics also control fine scale gain flatness. In the printed circuit board environment, parasitics such as extra capacitance caused by two parallel and vertical flat conductors on opposite PC board sides in the region of the summing junction will cause some bandwidth extension and/or increased peaking. 0 -4 -6 -2 VIN = 50mV rms RL = 100 5VS -4 -6 -8 CJ = 5.1pF -10 -12 -8 NORMALIZED GAIN - dB, G = +2 10 1 -1 GAIN - dB, G = +1 G = +1 CJ = 0 -14 -10 -12 -14 1 10 40 FREQUENCY - MHz 100 500 Figure 9. Frequency Response vs. Added Summing Junction Capacitance -10- REV. D AD8004 2 CL = 10pF 0 CL = 0 -2 NORMALIZED GAIN - dB, G = -2 2 G = -2, RF = 698 0 -4 -6 -2 CL = 10pF -4 VIN = 50mV 5VS RL = 100 -6 -8 -8 -10 CL = 0 -12 through R2. This current flows toward the summing junction and requires that the output be 2 V higher than the summing junction or at 3.6 V. NORMALIZED GAIN - dB, G = +2 G = +2, RF = 1.10k When the input is at 1 V, there is 1.2 mA flowing into the summing junction through R3 and 1.2 mA flowing out through R1. These currents balance and leave no current to flow through R2. Thus the output is at the same potential as the inverting input or 1.6 V. The input of the AD876 has a series MOSFET switch that turns on and off at the sampling rate. This MOSFET is connected to a hold capacitor internal to the device. The on impedance of the MOSFET is about 50 , while the hold capacitor is about 5 pF. -14 -10 -12 -14 1 10 40 FREQUENCY - MHz 100 In a worst case condition, the input voltage to the AD876 will change by a full-scale value (2 V) in one sampling cycle. When the input MOSFET turns on, the output of the op amp will be connected to the charged hold capacitor through the series resistance of the MOSFET. Without any other series resistance, the instantaneous current that flows would be 40 mA. This would cause settling problems for the op amp. 500 Figure 10. Frequency Response vs. Capacitive Loading, RL = 100 Output 2 CL = 10pF NORMALIZED GAIN - dB, G = 2 0 G = +2 RL = 1k 5VS VIN = 50mV rms RF = 1.2k -2 -4 The series 100 resistor limits the current that flows instantaneously after the MOSFET turns on to about 13 mA. This resistor cannot be made too large or the high frequency performance will be affected. CL = 0 The sampling MOSFET of the AD876 is closed for only half of each cycle or for 25 ns. Approximately seven time constants are required for settling to 10 bits. The series 100 resistor along with the 50 on resistance and the hold capacitor, create a 750 ps time constant. These values leave a comfortable margin for settling. Obtaining the same results with the op amp A/D combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. -6 -8 -10 -12 -14 1 10 40 FREQUENCY - MHz 100 500 Overall the AD8004 provides adequate buffering for the AD876 A/D converter without introducing distortion greater than that of the A/D converter by itself. Figure 11. Flatness with 10 pF Capacitive Load DRIVING A SINGLE-SUPPLY A/D CONVERTER New CMOS A/D converters are placing greater demands on the amplifiers that drive them. Higher resolutions, faster conversion rates, and input switching irregularities require superior settling characteristics. In addition, these devices run off a single +5 V supply and consume little power, so good single-supply operation with low power consumption is very important. The AD8004 is well positioned for driving this new class of A/D converters. +5V R3 1.65k 0.1F 10F 0.1F 1V 0V Figure 12 shows a circuit that uses an AD8004 to drive an AD876, a single supply, 10-bit, 20 MSPS A/D converter that requires only 140 mW. Using the AD8004 for level shifting and driving, the A/D exhibits no degradation in performance compared to when it is driven from a signal generator. +3.6V R1 499k VIN REFT 100 1/4 AD8004 50 AD876 3.6V 0.1F 1.6V 1.6V REFB +1.6V Figure 12. AD8004 Driving the AD876 The analog input of the AD876 spans 2 V centered at about 2.6 V. The resistor network and bias voltages provide the level shifting and gain required to convert the 0 V to 1 V input signal to a 3.6 V to 1.6 V range that the AD876 wants to see. LAYOUT CONSIDERATIONS Biasing the noninverting input of the AD8004 at 1.6 V dc forces the inverting input to be at 1.6 V dc for linear operation of the amplifier. When the input is at 0 V, there is 3.2 mA flowing out of the summing junction via R1 (1.6 V/499 ). R3 has a current of 1.2 mA flowing into the summing junction (3.6 V - 1.6 V)/ 1.65 k. The difference of these two currents (2 mA) must flow REV. D R2 1k 3.6V The specified high speed performance of the AD8004 requires careful attention to board layout and component selection. Table I shows the recommended component values for the AD8004 and Figures 14-16 show the layout for the AD8004 evaluation board (14-lead SOIC). Proper RF design techniques and low parasitic component selection are mandatory. -11- AD8004 The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. RF RG RBT, 50 VIN VOUT RT 1/4 Chip capacitors should be used for supply bypassing (see Figure 13). One end should be connected to the ground plane and the other within 1/8" of each power pin. An additional (4.7 F to 10 F) tantalum electrolytic capacitor should be connected in parallel. C1 0.1F C3 10F C2 0.1F C4 10F +VS -VS INVERTING CONFIGURATION RF RG The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains. An example of extra inverting input capacitance can be seen on the plot of Figure 10. RBT, 50 VOUT 1/4 VIN RT C1 0.1F C3 10F C2 0.1F C4 10F +VS -VS Stripline design techniques should be used for long signal traces (greater than about 1"). These should be designed with the proper system characteristic impedance and be properly terminated at each end. NONINVERTING CONFIGURATION Figure 13. Inverting and Noninverting Configurations Table I. Recommended Component Values1 and Typical Bandwidths Gain AD8004 (SOIC) PACKAGE TYPE RF () RG () RT2 () Small Signal BW @ 5 VS (MHz) -10 -2 Alternate -2 -1 Alternate -1 499 49.9 None 698 348 57.6 499 249 61.9 750 750 53.6 499 499 54.9 155 130 190 125 Peaking @ 5 VS < 0.7 dB < 0.1 dB 0.5 dB None 0.1 dB Flatness @ 5 VS (MHz) Small Signal BW @ +5 VS (MHz) 35 135 115 +1 Alternate +1 +2 Alternate +2 +10 1.10 k 698 50 1.10 k 1.10 k 50 604 604 50 499 54.9 50 50 195 150 225 110 175 135 0.4 dB 1.3 dB 1.8 dB < 0.1 dB 0.5 dB < 0.2 dB 155 120 25 175 110 30 165 130 195 95 NOTES 1 Resistor values listed are standard 1% tolerance. 2 RT chosen for 50 characteristic input impedance. -12- REV. D AD8004 Figure 14.1 Evaluation Board Silkscreen (Top) 1 The DIP package option is no longer available. REV. D -13- AD8004 Figure 15 Evaluation Board Layout (Top Side) Figure 16.1 Evaluation Board Layout (Bottom Side, Looking Through the Board) 1 The DIP package option is no longer available. -14- REV. D AD8004 OUTLINE DIMENSIONS 14-Lead Standard Small Outline Package [SOIC] (R-14) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 14 8 1 7 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.33 (0.0130) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 45 0.25 (0.0098) 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.19 (0.0075) COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. D -15- AD8004 Revision History Location Page 12/15--Data Sheet changed from REV. C to REV. D. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3/03--Data Sheet changed from REV. B to REV. C. Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Added CERDIP (Q) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added text to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 D01045-0-12/15(D) Deleted 14-Lead PDIP and 14-Lead CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edited MAXIMUM POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Deleted Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edited Y axis of TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edited OPTIMIZING FLATNESS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PRINTED IN U.S.A. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 -16- REV. D