MC14043BCP - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATAMC14043B MC14044B

162

 

Quad R–S Latches

The MC14043B and MC14044B quad R–S latches are constructed with

MOS P–channel and N–channel enhancement mode devices in a single

monolithic structure. Each latch has an independent Q output and set and

reset inputs. The Q outputs are gated through three–state buffers having a

common enable input. The outputs are enabled with a logical “1” or high on

the enable input; a logical “0” or low disconnects the latch from the Q

outputs, resulting in an open circuit at the Q outputs.

•Double Diode Input Protection

•Three–State Outputs with Common Enable

•Outputs Capable of Driving Two Low–power TTL Loads or One Low–

Power Schottky TTL Load Over the Rated Temperature Range

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

MC14043B

TRUTH TABLE

X = Don’t Care

MC14044B

S R E Q

High

Impedance

X X 0

No Change

TRUTH TABLE

X = Don’t Care

S R E Q

High

Impedance

X X 0

No Change

ENABLE

S0 4

ENABLE

R0 4

VDD = PIN 16

VSS = PIN 8

NC = PIN 2

VDD = PIN 16

VSS = PIN 8

NC = PIN 13



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94





L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATA 163

MC14043B MC14044B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

– 55

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage

“0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

0.05

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

0.05

ÎÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOH

ÎÎÎ

5.0

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

—

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0

ÎÎÎ

3.5

7.0

ÎÎÎÎ

—

ÎÎÎ

3.5

7.0

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

—

ÎÎÎÎ

3.5

7.0

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎÎ

—

ÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎ

—

ÎÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0

ÎÎÎ

0.64

1.6

4.2

ÎÎÎÎ

—

ÎÎÎ

0.51

1.3

3.4

ÎÎÎÎ

0.88

2.25

8.8

ÎÎÎ

—

ÎÎÎÎ

0.36

0.9

2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

—

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

1.0

2.0

4.0

ÎÎÎ

—

ÎÎÎÎ

0.002

0.004

0.006

ÎÎÎ

1.0

2.0

4.0

ÎÎÎÎ

—

ÎÎÎ

120

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs all

buffers switching)

ÎÎÎÎ

ÎÎÎ

5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.58 µA/kHz) f + IDD

IT = (1.15 µA/kHz) f + IDD

IT = (1.73 µA/kHz) f + IDD

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Three–State Output Leakage

Current

ÎÎÎÎ

ITL

ÎÎÎ

—

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

± 0.0001

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

± 3.0

ÎÎÎ

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

**The formulas given are for the typical characteristics only at 25

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages – 12 mW/

C From 100

C To 125

MOTOROLA CMOS LOGIC DATAMC14043B MC14044B

164

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VDD

ÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎÎ

– 0.5 to + 18.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ

– 0.5 to VDD + 0.5

ÎÎÎ

ÎÎÎÎ

lin, lout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Current (DC or Transient),

per Pin

ÎÎÎÎÎÎ

± 10

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation, per Package†

ÎÎÎÎÎÎ

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature (8–Second Soldering)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time

tTLH = (1.35 ns/pF) CL + 32.5 ns

tTLH = (0.60 ns/pF) CL + 20 ns

tTLH = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎ

tTLH

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

100

ÎÎÎÎ

200

100

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time

tTHL = (1.35 ns/pF) CL + 32.5 ns

tTHL = (0.60 ns/pF) CL + 20 ns

tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎ

tTHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

100

ÎÎÎÎ

200

100

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

tPLH = (0.90 ns/pF) CL + 130 ns

tPLH = (0.36 ns/pF) CL + 57 ns

tPLH = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎ

tPLH

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

175

ÎÎÎÎ

350

175

120

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tPHL = (0.90 ns/pF) CL + 130 ns

tPHL = (0.90 ns/pF) CL + 57 ns

tPHL = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎ

tPHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

175

ÎÎÎÎ

350

175

120

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Set, Set Pulse Width

ÎÎÎÎ

ÎÎÎÎÎ

5.0

ÎÎÎÎ

200

100

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset, Reset Pulse Width

ÎÎÎÎ

ÎÎÎÎÎ

5.0

ÎÎÎÎ

200

100

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Three–State Enable/Disable Delay

ÎÎÎÎ

tPLZ,

tPHZ,

tPZL,

tPZH

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

150

ÎÎÎÎ

300

160

110

ÎÎÎ

*The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

AC WAVEFORMS

MC14043B MC14044B

20 ns 20 ns

90%

10%

RESET

SET

tPHL tPLH

20 ns 20 ns

50%

90%

50% 10%

tTHL tTLH

90%

50%

10%

VDD

VSS

VDD

VSS

VOH

VOL

RESET

SET

20 ns 20 ns

90%

10%

50%

20 ns 20 ns

90%

10%

50%

tTLH tTHL

50% 10%

90%

tPLH tPHL

VDD

VSS

VDD

VSS

VOH

VOL

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA 165

MC14043B MC14044B

THREE–STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3–State Tests

Test

Enable

MC14043B MC14044B

Test

Enable

S R S R

tPZH Open Closed A VDD VSS VSS VDD

tPZL Closed Open B VSS VDD VDD VSS

tPHZ Open Closed A VDD VSS VSS VDD

tPLZ Closed Open B VSS VDD VDD VSS

ENABLE

50%

tPZH

10%

tPZL tPHZ

tPLZ

10%

90%

VDD

VSS

VDD

VOL

VOH

VSS

PIN ASSIGNMENT

125

VDD

VSS

125

VDD

VSS

NC = NO CONNECTION

MC14043B MC14044B

OUTPUT

UNDER

TEST

VDD

1 k

50 pF

VSS

MOTOROLA CMOS LOGIC DATAMC14043B MC14044B

166

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

1 8

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

–T–

SEATING

PLANE

16 PLD

0.25 (0.010) T

16 PLJ

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.93

B0.240 0.295 6.10 7.49

C––– 0.200 ––– 5.08

D0.015 0.020 0.39 0.50

E0.050 BSC 1.27 BSC

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

H0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA 167

MC14043B MC14044B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided

in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,

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MC14043B/D

*MC14043B/D*

◊