USER MANU AL
Version 2.1
HVS/UM9704
Version 2.1
Philip s Sem iconductor s
User Manual
HVS/UM9704
2
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copy-
right owne r.
The information presented in this document does not form part of any quotation or contract, is believed to be
accurate and reliable and may be changed without notice. No liability will be accep ted by the publisher for any
consequence of its use. Publicati on thereof does not convey nor imply any license under pat ent- or other indus -
trial or intellectual property rights.
REVISION HISTORY
RemarksVersion
0.1 DRAFT; 14.08.96
0.2 Upd ate I IC RE Gs 24,25 ; 20.08. 96
0.3 Up d ate RE G7: ENA _HWE_ROUG H; 21.08.96
1.0 First Release; re fers to BES IC-SW from V0.34 until V1.0; 31.10.96
(Th is UM des cribes the iic inte rface of the B ESI C for a s ing le memory co ncept or a PR O -
ZONI C concept. The µC ROM of the first BE SIC samples co ntain this interface.
ME LZO NIC contro l (S AA 4991) is not possib le via the iic interface des c ribed in thi s docu-
ment )
2.0 Second R ele ase; re fers to BE S IC-SW start ing w ith V2.0; 28.02. 97
This documen t describes a new iic interface of the BE SIC in cluding the MELZO NIC c on-
tr o l in addition t o the fea tures des cri bed in th e firs t re lease docume nt. An e xternal µC
RO M of t he firs t BE S IC samples will contain thi s new ii c int erface. A new BESI C version,
which w il l be d ev e loped, contains t he new interface.
2.1 HV S/UM 9 70 4, 12. 12. 97, update of UM 9 70 1 V2. 0
Keywords
Philip s Sem iconductor s
I²C-bus Register Specification for the
SAA 4977 V1B User Manual
HVS/UM9704
3
USER MANU AL
I²C-b us Register Specification
for the SAA 4977 V1B
BESIC
Mem o r y Controlle r
I²C-Bus
PROZONIC
MELZONIC
Da te : 12th of december, 19 97
Re port No.: HVS/UM9704
HVS/UM9704
I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
User Manual
HVS/UM9704
4
Preface
The specification describes the I²C-bus register interface of an IPQ slave microcontroller (80C51 core), which is a
part of the BESIC (SAA 4977). The described inter face refe rs to a BESIC so ftware version which is not i mple-
mented in t he first B E S IC sam ples. (see Revision Histo ry). This int erface wil l replace the old one in f utu re .
The BESIC is a videoprocessi ng IC providing anal og interfacing, video enhan cing features, m emory cont rollin g
and the embedded 80C51 microprocessor core. The slave IPQ µC is used as an interpreter between a main
(master) µC and the Data path Con trol in BESIC as well as the direct contro l of the interna l mem ory controll er , in
case of a two fiel d mem ory concept, also the PRO ZONIC (SA A4990; externa l) or MELZO NIC (SAA 4991;exter-
nal).
I²C-bus Register Specification for the
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1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1 .1 Defini tio ns, Acronym s and Abb reviati on s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Definition of the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 .2 Sendi ng data to the IPQ µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 I²C transmission protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 I²C register tabl e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2. 3 I²C tra nslat er register dat a f orm at. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
3.2.4 Ack nowledgement of bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 .3 Receivi ng data f rom t he IPQ µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.1 Contents of status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3. 2 Content s of datapath read register s. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2
3.4 Timing aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4. Eva lu ation of I²C-bu s register data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 .1 Field m em o ry control mod e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1. 1 Priorit ies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1. 2 Field Cont rol mod es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AABB Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LFR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Natural Mo tion (Vide o and Movie) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6
ABAB Movie Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Sa te llit e M o d e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Generator Mode (G_Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Auto Movie Detectio n routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6
Multi-PIP (MPIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Vertical Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Still Picture Mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Non-Interlace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
IN I T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.3 Secondary control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9
4.1. 4 Selection of t he Hardware co nfigurat ion . . . . . . . . . . . . . . . . . . . . . . . . 4 2
4.1. 5 Datapat h translator regist e rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.1.6 SNE RT interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5. Default IIC control settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6. INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
User Manual
HVS/UM9704
1. Introduction
The UM9701 V2.1 describe s the II C interface of the SAA 4977 V1B. The software of this evalua tion sampl es is
not comp lete d to support all the possib le fu nctions as describe d in AN97057 and AN 97071. It mainly supp orts
the Melzonic concept. The single field concept runs if the Prozonic concept is chosen in the software. IIC register
37 cannot be controlled if the Prozonic opt ion is set.
The com pression mo des migh t show som e dat a fail ures in the lum inan ce signal. This pro blem can be eliminate d
if the supply voltage of BE SIC is reduced t o 4.2V . For VCR sources problem s with the picture stabil ity can occur.
The above ment ioned restriction s are solved in the next version of the SA A 4977 .
The IIC int erfa ce of the f inal S AA 4977 is described in the document HVS/CR9705 .
1.1 Definitions, Acronyms and Abbreviations
1.2 References
[1] Philips Semicondu ctors Software Crea tio n Process V1.0; Wilko van Asseldonk, M arc de Smet;
April 9t h, 1996
[2] Tenta tive Device S pecifi cati on for BES IC; 06.08.9 6; A. Kanneng iesser
[3] Tentative Device Specification Control Part BESIC; 24.06.96; G. Stäcker,
H. Waterholter
[4] 80C51 microcontroller order form
[5] 80C51 microcont roller Core Specifi cati on V1.2; 22 .02.96; P. Klapproth
[6] Datapat h Cont rol Register; 13.0 8.96; A. Kannengiesser
HEX Hexadecimal
HO ST interf a ce BESIC Interf ace towards 8051 microprocessor core
IPQCS Improved Picture Quality Control Software
IPQ µC Improved Picture Quality slave microcontroller
LFR Line Flicker Reducti on by media n f iltering
ME LZO NIC Mot ion Est im ati on/ compe nsati on, Lin e flicker reducti on, Z Oom and
Noise reduction IC
MP IP Multi picture in picture with external PIP processor
NR Noise reduction (adaptive)
PROZ ONI C Progressive Scan, Zoom and Noise Reduct ion IC
I²C-bus Register Specification for the
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[7] Application Note, MK8 Module, AN97057; H. Waterholter
[8] Application Note, MK9 Module, AN97071, H. Waterholter
2. General
The IPQ µ C reads regist er bytes via the I²C-bus f rom the m aster µC and s en ds itsel f 1 status byte pl us followin g
read registers wheneve r addressed with R/W = 1. The I²C register bytes receive d are written into the µCs RAM .
3. I²C-bus interface
3. 1 Defin ition of the inte rface
The interf ace of the I PQ µC is realize d with a hardware I²C-bus.
The slave address of the IPQ µC is 68h:
Slave address = 0 1 1 0 1 0 0 R/W.
The IPQ µC can either act as a slave receiver or a slave transmitter. In the slave receiver mode the IPQ µC reads
I²C reg ister data b ytes from the main cont roller which t hen acts as a mast er transmi tt er. In the slave transm itter
mod e the IPQ µ C se nds sta tus in form ation t o the main µC wh ich works as a mas ter rec eive r readin g the byte
information.
3.2 Sending data to the IPQ µC
3. 2.1 I²C transm ission protoco l
The transmi ssion pro tocol has the following fo rmat :
After having addressed the IPQ µC wit h its slave addre ss the master µC transm its the subaddress plus followin g
register bytes ove r the I²C-bus. T he number of register bytes which are tran smitt ed after the t ransmission of the
subaddress is free choosable. It is possible to transmit just one single register byte after having sent the slavead-
dress plus subaddress (3 bytes package).
The IPQ µC a cknowledg es alway s all registe r bytes independ ent of the ir contents. If the ma ster µC transmi ts
more than t he m axim um numb er of register bytes, the sla ve µC will acknowl edge the fol lowing bytes, but will not
store them in the inte rn al RAM.
Subaddresses start ing from 28h onwards indicate, t hat datapa th control registers are to be servi ced.
Start Slave
address 68h Ack Subad-
dress Ack REG1 Ack ..... Ack REGx Ack Stop
8
I²C-bus Register Specification for the
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HVS/UM9704
3. 2.2 I²C registe r tab les
[Defaul t hex values in brackets ]
Table 1: I²C-Register REG1 (FREQUENCY SELECT): Subad dress 00 hex [00]
Bit Name Function
0 reserved to be cleared
1 reserved to be cleared
2 G_MO D E 0: normal mod e
1 : generator mode on
3 reserved to be cleared
4 AFF a cquisit ion fi eld frequ ency (50/60 Hz): 0 = 5 0 Hz, 1 = 60 Hz
5 reserved
6 reserved
7 IN IT init iali ze the SAA4977 and MELZO NIC (if applied): 0 = off, 1 = on
Ta ble 2: I²C-Register REG2 (FIE LD CONTROL); Subaddress 01 hex [01]
Bit Name Function
0 LF R line flicker reduction mod e:
0 = off (AABB mode), 1 = on (AA*B*B, AB AB raster)
1 to be clea red
2 reserved
3 reserved
4 M OVIE Forced Movie mode (ABAB raster)
0: off
1: on
5 PHA SE Force d Phase Fla g to be se t in combination wit h CIN E
0: normal mode
1: 180 deg. phase shift (BCBC)
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6 AUTO_MOVIE 0: normal mode
1: automatic m ovie mode activated. In case of a detected movie
source, the field p roce ssing will swit ch to cine(m ovie) mode and t he
correct m ovie p hase will be processed (MOVIE, PHASE _FLAG are
readable via S T ATUS register)
7 STP still picture mode
0: off
1: on (one f ield out of AABB , f ull fram e m edian f iltered out of LFR)
Ta ble 3: I²C-Register REG3 (VZOOM): Subaddress 02 hex [10]
Bit Name Function
0 VZO OM _0 Vert ival zoom bit 0
1 VZO OM _1 Vert ical zoom bit 1
2 VZO OM _2 Vert ical zoom bit 2
3 VZO OM _3 Vert ical zoom bit 3
Ta ble 2: I²C-Register REG2 (FIE LD CONTROL); Subaddress 01 hex [01]
Bit Name Function
10
I²C-bus Register Specification for the
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Philip s Sem iconductor s
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HVS/UM9704
V3 V2 V1 V0 Conversion factor
00001,1
0 0 0 1 reserved
0 0 1 0 1,25
0 0 1 1 reserved
0 1 0 0 1,33
0 1 0 1 reserved
01101,5
0 1 1 1 reserved
10012
1 0 1 0 reserved
1 0 1 1 reserved
1 1 0 0 reserved
1 1 0 1 reserved
1 1 1 0 reserved
1 1 1 1 reserved
4 NA TURA L_MO TI ON 0: Natural Mot ion of f
1: Natu ra l Mot ion aktiv
5 to be cl eared
6 SAT _M ODE Sat elli te Mode (removes wipi ng dots)
0: off (LFR, AABB, AUTO_MOVIE or CINE mode active)
1: on (LFR, AABB, AUTO_MOVIE and CINE not active)
7 VZO OM 0: Ve rtical Zo om mode not active
1: Ve rtical Zo om mode acti ve
Ta ble 3: I²C-Register REG3 (VZOOM): Subaddress 02 hex [10]
Bit Name Function
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Table 4: I²C-Register REG4 (External Multi PIP): Subaddress 03 hex [00]
Bit Name Function
0 P OS0 PI P position bit 0
1 P OS1 PI P position bit 1
2 P OS2 PI P position bit 2
3 P OS3 PI P position bit 3
4 to be clear ed
5 NP IP nu mbe r of PIP’s: 0 = 3x3 PIP’s, 1 = 4x3 PIP’s
6 M PIP Ex te rn al Mul ti-P I P: 0 = off, 1 = on
7 SPIP NTSC PIP: 0 = 50 Hz PIP, 1 = 60 Hz PIP
Table 5: I²C-Register REG5 (NR, SCREEN FADE): S ubaddress 0 4 hex [02 ]
Bit Name Function
0 NR0 no ise reduction bit 0
1 NR1 no ise reduction bit 1
NR1 NR0 no ise redu ction
00 off
01 low
1 0 middle
11 high
2 SPS0 split screen bit 0
3 SPS1 split screen bit 1
SPS1 SPS0 spli t screen
0X off
1 0 horizontal
1 1 vertical
4 SCF0 screen fade bit 0
12
I²C-bus Register Specification for the
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HVS/UM9704
5 SCF1 screen fade bit 1
SCF1 SC F0 screen fade
0X OFF
1 0 fade in
1 1 fade out
6 reserved
7 to be clear ed
Table 6: I²C-Register REG6 (ENABLE DIRECT REG. ACCESS): Subaddress 05 hex [00]
Bit Name Function
0 SET_HO R_DEL 0: norma l mode (HOR_DELAYS=0)
1: HOR_DELAYS value taken from REG12 (direct PROZONIC/
ME LZONIC access).
1 SET_ HWE 0: norma l mode
1: take HWE STA /ST O settings from RE Gs 13, 14
2 SET_ HRE 0: norma l mode
1: take HRE STA /ST O set tings from REGs 15, 16
3 SET_HDDE L 0: norma l mode
1: take HDDE L setting from REG17
4 SET_HDM S B 0: normal mode
1: take HD M SB sett ing f rom RE G18
5 SET_V DMSB 0: norma l mode
1: take V DMS B sett ing from REG 19
6 SET_HB DA 0: norma l mode
1: set HBDAS T A/S TO E CO values direct via IIC REGs 20, 21
7 SET_HWE_MAIN_
DELAY 0: norma l mode
1: HWE main delay via REG 22
Table 5: I²C-Register REG5 (NR, SCREEN FADE): S ubaddress 0 4 hex [02 ]
Bit Name Function
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Table 7: I²C-Register REG7: Subaddress 06 hex [00]
Bit Name Function
0 SET _HB OX 0: defa ult mode
1: direct control of HB OX_ST ART/ST OP via IIC RE Gs 31,
32
1 to be cl eared
2 to be cl erared
3 SET _VB D A 0: default mode
1: direct V B DAS T A/S TO via REGs 29, 30
4 to be cl eared
5 to be cl eared
6 SET _HDA V 0: defa ult
1: direct HDA VST A/STO control via IIC REG s 25, 26
7 to be cl eared
Ta ble 8: I²C-Register REG8 (VWE DELAY): Subaddress 07 hex [00]
Bit Name Function
0 VWED0 VWE delay bit 0
1 VWED1 VWE delay bit 1
2 VWED2 VWE delay bit 2
3 VWED3 VWE delay bit 3
4 VWED4 VWE delay bit 4
5 VWED5 VWE delay bit 5
6 VWED6 VWE delay bit 6
7 VWEX 0 = off, normal mode
1 = on, reduced vertical writ e window shif tabl e by VWED0. ..D 6
14
I²C-bus Register Specification for the
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Philip s Sem iconductor s
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HVS/UM9704
Ta ble 9: I²C-Register REG9 (Test-REG: BLANK FIELDS): Subaddress 08 hex [80]
Bit Name Function
0 BLANK_F0 blank field 0
1 BLANK_F1 blank field 1
2 BLANK_F2 blank field 2
3 BLANK_F3 blank field 3
4...7 reserved
Tab le 10: I²C- Regis ter REG10: Subad dress 09 h ex [00]
Bit Name Function
0 to be cl eared
1 to be cl eared
2 to be cl eared
3 to be cl eared
4 DIGITAL_COLOR_
DECODER_
CONCEPT
0: Analog color decoder concept
1: Digital color decoder concept (internal acquisition PLL
switched of f; external clock, 16 MHz line locked exp ected)
5 CLR_M OVI E 0: default mode
1: clear AUT O_M OVI E flag (forced)
6 NPIP_ 4 x4 0: no 4x4 PIP, take NP IP
1: 4x4 P IP
7 to be cl eared
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Table 11: I²C-Register REG11 (Port Settings): Subaddress 0A hex [30]
Bit Name Function
0 P11 0: clear port pin P1. 1
1: set port pin P1.1
1 P12 0: clear port pin P1. 2
1: set port pin P1.2
2 P14 0: clear port pin P1. 4
1: set port pin P1.4
3 P15 0: clear port pin P1. 5
1: set port pin P1.5
4 MEL Z_P ROZ Software selecti on, only valid if SW_HW= 1
0: PR OZO NI C
1: M E LZON IC
5 SW _HW enable the soft ware select ion bet ween PR OZO NIC/ M ELZO NIC
0: Hardware selection via Pin P1.3
1: Software select ion wit h M ELZ _PR OZ
6 reserved
7 to be cleared
Ta ble 12: I²C Register REG12 (HOR_DELAYS): Subaddress 0B hex [28]
Bit Name Function
0...2 IN _DE L input lumina nce delay
3... 4 HD_DEL (Prozon ic) 1 to 4 clock shift f or the hor. reference
WE_HDE L (Me lzonic) 1 to 4 clock shift for WE2 output signal
5...6 WE 2_DE L (Pro zonic) 1 to 4 clock shift f or WE 2 output signal
RE_HDE L (Mel zoni c) 1 to 4 clock shift f or RE output signals
7 reserved
16
I²C-bus Register Specification for the
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Ta ble 13: I²C Register REG13 (HWESTA): Subaddress 0C hex [xx]
Bit Name Function
0 . . . 7 HWES TA start value for horizontal writ e enable (lower 8 bits)
Ta ble 14: I²C Register REG14 (HWESTO): Subaddress 0D hex [xx]
Bit Name Function
0 . . . 7 HWE STO stop value for horizont al write enable (lower 8 bits)
Table 15: I²C Register REG15 (HRESTA) : Su ba ddress 0E hex [1F]
Bit Name Function
0 . . . 7 HRES TA start value for horizont al read enable (lower 8 bits)
Table 16: I²C Register REG16 (HRES TO): Subad dress 0F hex [C3]
Bit Name Function
0 . . . 7 HRE STO stop value for horizont al read enabl e (lower 8 bits )
Ta ble 17: I²C Register REG17 (HDDEL): Subaddress 10 hex [00]
Bit Name Function
HDDEL: horizontal f ine dela y for the SAA 4977 display signal s
0 HDA V _DE L fine del ay of HDAV
0: no addit ional delay
1: signal del ayed b y one displ ay clock
I²C-bus Register Specification for the
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1 HB DA _DE L fine del ay of HBDA
0: no addit ional delay
1: signal del ayed b y one displ ay clock
2 HRE _DE L fine del ay of HRE
0: no addit ional delay
1: signal del ayed b y one displ ay clock
3 HBLND_DE L fine del ay of HBLND
0: no addit ional delay
1: signal del ayed b y one displ ay clock
Ta ble 18: I²C Register REG18 (HDMSB): Subaddress 11 hex [AA]
Bit Name Function
0 HD MSB MSB of HDAVSTA
1 MSB of HDAVSTO
2 MSB of HBDASTA
3 MSB of HBDASTO
4 MSB of HRESTA
5 MSB of HRESTO
6 MSB of HBLNDSTA
7 MSB of HBLNDSTO
Ta ble 17: I²C Register REG17 (HDDEL): Subaddress 10 hex [00]
Bit Name Function
18
I²C-bus Register Specification for the
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Philip s Sem iconductor s
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Ta ble 19: I²C Register REG19 (VDMSB): Subaddress 12 hex [0A]
Bit Name Function
0 VDMSB to be cl eared
1 t o be set
2 MSB of VBD AST A
3 MSB of VBD AST O
4...7 reserved
Ta ble 20: I²C Register REG20 (HBDASTA): Subaddress 13 hex [52]
Bit Name Function
0 . . . 7 HB DAST A start value of horizonta l blanking for t he DAC (low er 8 bits )
Ta ble 21: I²C Register REG21 (HBDASTO): Subaddress 14 hex [F2]
Bit Name Function
0 . . . 7 HBDA STO stop va lue of horizontal blanking for the DAC (lower 8 bits)
Ta ble 22: I²C Register REG22 (HWE MAIN DELAY): Subaddress 15 hex [32]
Bit Name Function
0 ... 7 HWE_MAIN_DELAY horizontal shift of the HWE signal
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Ta ble 23: I²C Register REG23 : Subaddress 16 hex [xx]
Bit Name Function
0 ... 7 reserved
Table 24: I²C Register REG24: Subaddress 17 hex [xx]
Bit Name Function
0 ... 7 reserved
Table 25: I²C Register REG25 (HDAVSTA): Subad dress 18 hex [05]
Bit Name Function
0 . . . 7 HDA VST A start value of gating signal for chrominance display dat a
(lower 8 bits)
Table 26: I²C Register REG26 (HDAVSTO): Subaddress 19 hex [A9]
Bit Name Function
0 . . . 7 HDAV STO stop value of gating signal for chrominance display data
(lower 8 bits)
Ta ble 27: I²C Register REG27 : Suba ddress 1A hex [xx]
Bit Name Function
0 ... 7 reserved
20
I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
User Manual
HVS/UM9704
Ta ble 28: I²C Register REG28 : Suba ddress 1B hex [xx]
Bit Name Function
0 ... 7 reserved
Ta ble 29: I²C Register REG29 (VBDASTA): Subaddress 1C hex [15]
Bit Name Function
0 . . . 7 VBD AST A st art value of vertical blankin g for the DAC (lower 8 bits)
Ta ble 30: I²C Register REG30 (VBDASTO): Subaddress 1D hex [31]
Bit Name Function
0 . . . 7 VBD AST O stop value of verti cal blanking for the DAC (lower 8 bits )
Table 31: I²C Register REG31 (HBOX_START): Subaddress 1E hex [00]
Bit Name Function
0 . . . 7 HBOX _STA RT direct PROZO NIC/ M ELZONI C regist er access
Ta ble 32: I²C Register REG32 (HBOX_STOP): Subad dress 1F hex [00]
Bit Name Function
0 . . . 7 HBOX _STO P dire ct PROZO NIC/ MEL ZONI C regist er access
I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
21
User Manual
HVS/UM9704
3.2.3 I²C translater register data format
Next subaddre ss for the following I ²C registers will be 28h !
Acquisition part:
Table 33: I²C Register REG33: Subaddress 20 hex [xx]
Bit Name Function
0 ... 7 reserved
Table 34: I²C Register REG34: Subaddress 21 hex [xx]
Bit Name Function
0 ... 7 reserved
Ta ble 35: I²C Translater Register 0 (ACQ_0): Subaddress 28 hex
Bit Name Ho st address
(hex)
Default
value (hex)
Function
0 ... 7 AGC_Y 0150 00 AGC gain for Y channel (2´s complement rel
0 dB): upper 8 bits
Ta ble 36: I²C Translater Register 1 (ACQ_1): Subaddress 29 hex
Bit Name Ho st address
(hex)
Default
value (hex)
Function
0 ... 7 A GC_UV 01 51 00 AGC gain for U and V channel (2 ´s com ple-
ment rel 0 dB): upper 8 bits
22
I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
User Manual
HVS/UM9704
Ta ble 37: I²C Translater Register 2 (ACQ_2): Subaddress 2A hex
Bit Name Ho st address
(hex)
Default
value (hex)
Function
0 AGC_Y _LS B 01 52 00 AGC gain fo r Y channel LS B
1 AGC_UV _LS B AGC gain fo r UV channel LS B
2 standby_f 1: frontend in standby mode
3 aaf_bypass 1: bypass for pref ilt er
4 reserved
5 reserved
6 reserved
7 reserved
I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
23
User Manual
HVS/UM9704
Ta ble 38: I²C Translater Register 3 (ACQ_3): Subaddress 2B hex
Bit Name Host address
(hex)
Default
value (hex)
Function
0..1 UVclcorrect_mode 0153 00 Bit1 Bit0 UV clamp mode
0 0 auto
0 1 fixed
1 0 keep
11-
2.. 4 Uclcorrect_fval 000 Bit2 Bit1 Bit0 fixed value cl amp co rr.
U ch annel
000
001
010
011
100
101
110
111
5..7 Vclcorrect_fval 000 Bit2 Bit1 Bit0 fi xed va lue cl amp c orr.
V channel
000
001
010
011
100
101
110
111
24
I²C-bus Register Specification for the
SAA 4977 V1B
Philip s Sem iconductor s
User Manual
HVS/UM9704
Ta ble 39: I²C Translater Register 4 (ACQ_4): Subaddress 2C hex
Bit Name Host address
(hex)
Default
value (hex)
Function
0..1 UVcoring 0 1 54 00 B it1 Bit0 UV coring level
00 0
0 1 +/- 0,5
10 +/- 1
11 +/- 2
2..3 mff_width 01 Bit1 Bit0 majority filter setting
00 1
01 3
10 5
11 7
4..5 UVcl_tau 00 Bit1 Bit0 ver tica l filterin g o f me a-
sured clamp
00
01
10
11
6 compress 0 0: compression off
1: compression on
7 comp_mode 0 0: 14:9 compression mode
1: 16:9 compression mode