User Manual - Philips Semiconductors / NXP Semiconductors

USER MANU AL

Version 2.1

HVS/UM9704

Version 2.1

Philip s Sem iconductor s

User Manual

HVS/UM9704

 Philips Electronics N.V. 1997

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copy-

right owne r.

The information presented in this document does not form part of any quotation or contract, is believed to be

accurate and reliable and may be changed without notice. No liability will be accep ted by the publisher for any

consequence of its use. Publicati on thereof does not convey nor imply any license under pat ent- or other indus -

trial or intellectual property rights.

REVISION HISTORY

RemarksVersion

0.1 DRAFT; 14.08.96

0.2 Upd ate I IC RE Gs 24,25 ; 20.08. 96

0.3 Up d ate RE G7: ENA _HWE_ROUG H; 21.08.96

1.0 First Release; re fers to BES IC-SW from V0.34 until V1.0; 31.10.96

(Th is UM des cribes the iic inte rface of the B ESI C for a s ing le memory co ncept or a PR O -

ZONI C concept. The µC ROM of the first BE SIC samples co ntain this interface.

ME LZO NIC contro l (S AA 4991) is not possib le via the iic interface des c ribed in thi s docu-

ment )

2.0 Second R ele ase; re fers to BE S IC-SW start ing w ith V2.0; 28.02. 97

This documen t describes a new iic interface of the BE SIC in cluding the MELZO NIC c on-

tr o l in addition t o the fea tures des cri bed in th e firs t re lease docume nt. An e xternal µC

RO M of t he firs t BE S IC samples will contain thi s new ii c int erface. A new BESI C version,

which w il l be d ev e loped, contains t he new interface.

2.1 HV S/UM 9 70 4, 12. 12. 97, update of UM 9 70 1 V2. 0

Keywords

Philip s Sem iconductor s

I²C-bus Register Specification for the

SAA 4977 V1B User Manual

HVS/UM9704

USER MANU AL

I²C-b us Register Specification

for the SAA 4977 V1B

BESIC

Mem o r y Controlle r

I²C-Bus

PROZONIC

MELZONIC

Da te : 12th of december, 19 97

Re port No.: HVS/UM9704

HVS/UM9704

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Preface

The specification describes the I²C-bus register interface of an IPQ slave microcontroller (80C51 core), which is a

part of the BESIC (SAA 4977). The described inter face refe rs to a BESIC so ftware version which is not i mple-

mented in t he first B E S IC sam ples. (see Revision Histo ry). This int erface wil l replace the old one in f utu re .

The BESIC is a videoprocessi ng IC providing anal og interfacing, video enhan cing features, m emory cont rollin g

and the embedded 80C51 microprocessor core. The slave IPQ µC is used as an interpreter between a main

(master) µC and the Data path Con trol in BESIC as well as the direct contro l of the interna l mem ory controll er , in

case of a two fiel d mem ory concept, also the PRO ZONIC (SA A4990; externa l) or MELZO NIC (SAA 4991;exter-

nal).

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1 .1 Defini tio ns, Acronym s and Abb reviati on s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2. General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3. I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Definition of the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 .2 Sendi ng data to the IPQ µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2.1 I²C transmission protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2.2 I²C register tabl e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2. 3 I²C tra nslat er register dat a f orm at. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

3.2.4 Ack nowledgement of bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3 .3 Receivi ng data f rom t he IPQ µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.1 Contents of status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3. 2 Content s of datapath read register s. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2

3.4 Timing aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4. Eva lu ation of I²C-bu s register data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4 .1 Field m em o ry control mod e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1. 1 Priorit ies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1. 2 Field Cont rol mod es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AABB Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

LFR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Natural Mo tion (Vide o and Movie) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6

ABAB Movie Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Sa te llit e M o d e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Generator Mode (G_Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Auto Movie Detectio n routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6

Multi-PIP (MPIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Vertical Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Still Picture Mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Non-Interlace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IN I T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.3 Secondary control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9

4.1. 4 Selection of t he Hardware co nfigurat ion . . . . . . . . . . . . . . . . . . . . . . . . 4 2

4.1. 5 Datapat h translator regist e rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.1.6 SNE RT interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5. Default IIC control settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6. INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

1. Introduction

The UM9701 V2.1 describe s the II C interface of the SAA 4977 V1B. The software of this evalua tion sampl es is

not comp lete d to support all the possib le fu nctions as describe d in AN97057 and AN 97071. It mainly supp orts

the Melzonic concept. The single field concept runs if the Prozonic concept is chosen in the software. IIC register

37 cannot be controlled if the Prozonic opt ion is set.

The com pression mo des migh t show som e dat a fail ures in the lum inan ce signal. This pro blem can be eliminate d

if the supply voltage of BE SIC is reduced t o 4.2V . For VCR sources problem s with the picture stabil ity can occur.

The above ment ioned restriction s are solved in the next version of the SA A 4977 .

The IIC int erfa ce of the f inal S AA 4977 is described in the document HVS/CR9705 .

1.1 Definitions, Acronyms and Abbreviations

1.2 References

[1] Philips Semicondu ctors Software Crea tio n Process V1.0; Wilko van Asseldonk, M arc de Smet;

April 9t h, 1996

[2] Tenta tive Device S pecifi cati on for BES IC; 06.08.9 6; A. Kanneng iesser

[3] Tentative Device Specification Control Part BESIC; 24.06.96; G. Stäcker,

H. Waterholter

[4] 80C51 microcontroller order form

[5] 80C51 microcont roller Core Specifi cati on V1.2; 22 .02.96; P. Klapproth

[6] Datapat h Cont rol Register; 13.0 8.96; A. Kannengiesser

HEX Hexadecimal

HO ST interf a ce BESIC Interf ace towards 8051 microprocessor core

IPQCS Improved Picture Quality Control Software

IPQ µC Improved Picture Quality slave microcontroller

LFR Line Flicker Reducti on by media n f iltering

ME LZO NIC Mot ion Est im ati on/ compe nsati on, Lin e flicker reducti on, Z Oom and

Noise reduction IC

MP IP Multi picture in picture with external PIP processor

NR Noise reduction (adaptive)

PROZ ONI C Progressive Scan, Zoom and Noise Reduct ion IC

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

[7] Application Note, MK8 Module, AN97057; H. Waterholter

[8] Application Note, MK9 Module, AN97071, H. Waterholter

2. General

The IPQ µ C reads regist er bytes via the I²C-bus f rom the m aster µC and s en ds itsel f 1 status byte pl us followin g

read registers wheneve r addressed with R/W = 1. The I²C register bytes receive d are written into the µCs RAM .

3. I²C-bus interface

3. 1 Defin ition of the inte rface

The interf ace of the I PQ µC is realize d with a hardware I²C-bus.

The slave address of the IPQ µC is 68h:

Slave address = 0 1 1 0 1 0 0 R/W.

The IPQ µC can either act as a slave receiver or a slave transmitter. In the slave receiver mode the IPQ µC reads

I²C reg ister data b ytes from the main cont roller which t hen acts as a mast er transmi tt er. In the slave transm itter

mod e the IPQ µ C se nds sta tus in form ation t o the main µC wh ich works as a mas ter rec eive r readin g the byte

information.

3.2 Sending data to the IPQ µC

3. 2.1 I²C transm ission protoco l

The transmi ssion pro tocol has the following fo rmat :

After having addressed the IPQ µC wit h its slave addre ss the master µC transm its the subaddress plus followin g

subaddress is free choosable. It is possible to transmit just one single register byte after having sent the slavead-

dress plus subaddress (3 bytes package).

The IPQ µC a cknowledg es alway s all registe r bytes independ ent of the ir contents. If the ma ster µC transmi ts

more than t he m axim um numb er of register bytes, the sla ve µC will acknowl edge the fol lowing bytes, but will not

store them in the inte rn al RAM.

Subaddresses start ing from 28h onwards indicate, t hat datapa th control registers are to be servi ced.

Start Slave

address 68h Ack Subad-

dress Ack REG1 Ack ..... Ack REGx Ack Stop

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

3. 2.2 I²C registe r tab les

[Defaul t hex values in brackets ]

Table 1: I²C-Register REG1 (FREQUENCY SELECT): Subad dress 00 hex [00]

Bit Name Function

0 reserved to be cleared

1 reserved to be cleared

2 G_MO D E 0: normal mod e

1 : generator mode on

3 reserved to be cleared

4 AFF a cquisit ion fi eld frequ ency (50/60 Hz): 0 = 5 0 Hz, 1 = 60 Hz

5 reserved

6 reserved

7 IN IT init iali ze the SAA4977 and MELZO NIC (if applied): 0 = off, 1 = on

Ta ble 2: I²C-Register REG2 (FIE LD CONTROL); Subaddress 01 hex [01]

Bit Name Function

0 LF R line flicker reduction mod e:

0 = off (AABB mode), 1 = on (AA*B*B, AB AB raster)

1 to be clea red

2 reserved

3 reserved

4 M OVIE Forced Movie mode (ABAB raster)

0: off

1: on

5 PHA SE Force d Phase Fla g to be se t in combination wit h CIN E

0: normal mode

1: 180 deg. phase shift (BCBC)

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

6 AUTO_MOVIE 0: normal mode

1: automatic m ovie mode activated. In case of a detected movie

source, the field p roce ssing will swit ch to cine(m ovie) mode and t he

correct m ovie p hase will be processed (MOVIE, PHASE _FLAG are

readable via S T ATUS register)

7 STP still picture mode

0: off

1: on (one f ield out of AABB , f ull fram e m edian f iltered out of LFR)

Ta ble 3: I²C-Register REG3 (VZOOM): Subaddress 02 hex [10]

Bit Name Function

0 VZO OM _0 Vert ival zoom bit 0

1 VZO OM _1 Vert ical zoom bit 1

2 VZO OM _2 Vert ical zoom bit 2

3 VZO OM _3 Vert ical zoom bit 3

Ta ble 2: I²C-Register REG2 (FIE LD CONTROL); Subaddress 01 hex [01]

Bit Name Function

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

V3 V2 V1 V0 Conversion factor

00001,1

0 0 0 1 reserved

0 0 1 0 1,25

0 0 1 1 reserved

0 1 0 0 1,33

0 1 0 1 reserved

01101,5

0 1 1 1 reserved

10012

1 0 1 0 reserved

1 0 1 1 reserved

1 1 0 0 reserved

1 1 0 1 reserved

1 1 1 0 reserved

1 1 1 1 reserved

4 NA TURA L_MO TI ON 0: Natural Mot ion of f

1: Natu ra l Mot ion aktiv

5 to be cl eared

6 SAT _M ODE Sat elli te Mode (removes wipi ng dots)

0: off (LFR, AABB, AUTO_MOVIE or CINE mode active)

1: on (LFR, AABB, AUTO_MOVIE and CINE not active)

7 VZO OM 0: Ve rtical Zo om mode not active

1: Ve rtical Zo om mode acti ve

Ta ble 3: I²C-Register REG3 (VZOOM): Subaddress 02 hex [10]

Bit Name Function

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Table 4: I²C-Register REG4 (External Multi PIP): Subaddress 03 hex [00]

Bit Name Function

0 P OS0 PI P position bit 0

1 P OS1 PI P position bit 1

2 P OS2 PI P position bit 2

3 P OS3 PI P position bit 3

4 to be clear ed

5 NP IP nu mbe r of PIP’s: 0 = 3x3 PIP’s, 1 = 4x3 PIP’s

6 M PIP Ex te rn al Mul ti-P I P: 0 = off, 1 = on

7 SPIP NTSC PIP: 0 = 50 Hz PIP, 1 = 60 Hz PIP

Table 5: I²C-Register REG5 (NR, SCREEN FADE): S ubaddress 0 4 hex [02 ]

Bit Name Function

0 NR0 no ise reduction bit 0

1 NR1 no ise reduction bit 1

NR1 NR0 no ise redu ction

00 off

01 low

1 0 middle

11 high

2 SPS0 split screen bit 0

3 SPS1 split screen bit 1

SPS1 SPS0 spli t screen

0X off

1 0 horizontal

1 1 vertical

4 SCF0 screen fade bit 0

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

5 SCF1 screen fade bit 1

SCF1 SC F0 screen fade

0X OFF

1 0 fade in

1 1 fade out

6 reserved

7 to be clear ed

Table 6: I²C-Register REG6 (ENABLE DIRECT REG. ACCESS): Subaddress 05 hex [00]

Bit Name Function

0 SET_HO R_DEL 0: norma l mode (HOR_DELAYS=0)

1: HOR_DELAYS value taken from REG12 (direct PROZONIC/

ME LZONIC access).

1 SET_ HWE 0: norma l mode

1: take HWE STA /ST O settings from RE Gs 13, 14

2 SET_ HRE 0: norma l mode

1: take HRE STA /ST O set tings from REGs 15, 16

3 SET_HDDE L 0: norma l mode

1: take HDDE L setting from REG17

4 SET_HDM S B 0: normal mode

1: take HD M SB sett ing f rom RE G18

5 SET_V DMSB 0: norma l mode

1: take V DMS B sett ing from REG 19

6 SET_HB DA 0: norma l mode

1: set HBDAS T A/S TO E CO values direct via IIC REGs 20, 21

7 SET_HWE_MAIN_

DELAY 0: norma l mode

1: HWE main delay via REG 22

Table 5: I²C-Register REG5 (NR, SCREEN FADE): S ubaddress 0 4 hex [02 ]

Bit Name Function

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Table 7: I²C-Register REG7: Subaddress 06 hex [00]

Bit Name Function

0 SET _HB OX 0: defa ult mode

1: direct control of HB OX_ST ART/ST OP via IIC RE Gs 31,

1 to be cl eared

2 to be cl erared

3 SET _VB D A 0: default mode

1: direct V B DAS T A/S TO via REGs 29, 30

4 to be cl eared

5 to be cl eared

6 SET _HDA V 0: defa ult

1: direct HDA VST A/STO control via IIC REG s 25, 26

7 to be cl eared

Ta ble 8: I²C-Register REG8 (VWE DELAY): Subaddress 07 hex [00]

Bit Name Function

0 VWED0 VWE delay bit 0

1 VWED1 VWE delay bit 1

2 VWED2 VWE delay bit 2

3 VWED3 VWE delay bit 3

4 VWED4 VWE delay bit 4

5 VWED5 VWE delay bit 5

6 VWED6 VWE delay bit 6

7 VWEX 0 = off, normal mode

1 = on, reduced vertical writ e window shif tabl e by VWED0. ..D 6

I²C-bus Register Specification for the

SAA 4977 V1B

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HVS/UM9704

Ta ble 9: I²C-Register REG9 (Test-REG: BLANK FIELDS): Subaddress 08 hex [80]

Bit Name Function

0 BLANK_F0 blank field 0

1 BLANK_F1 blank field 1

2 BLANK_F2 blank field 2

3 BLANK_F3 blank field 3

4...7 reserved

Tab le 10: I²C- Regis ter REG10: Subad dress 09 h ex [00]

Bit Name Function

0 to be cl eared

1 to be cl eared

2 to be cl eared

3 to be cl eared

4 DIGITAL_COLOR_

DECODER_

CONCEPT

0: Analog color decoder concept

1: Digital color decoder concept (internal acquisition PLL

switched of f; external clock, 16 MHz line locked exp ected)

5 CLR_M OVI E 0: default mode

1: clear AUT O_M OVI E flag (forced)

6 NPIP_ 4 x4 0: no 4x4 PIP, take NP IP

1: 4x4 P IP

7 to be cl eared

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

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HVS/UM9704

Table 11: I²C-Register REG11 (Port Settings): Subaddress 0A hex [30]

Bit Name Function

0 P11 0: clear port pin P1. 1

1: set port pin P1.1

1 P12 0: clear port pin P1. 2

1: set port pin P1.2

2 P14 0: clear port pin P1. 4

1: set port pin P1.4

3 P15 0: clear port pin P1. 5

1: set port pin P1.5

4 MEL Z_P ROZ Software selecti on, only valid if SW_HW= 1

0: PR OZO NI C

1: M E LZON IC

5 SW _HW enable the soft ware select ion bet ween PR OZO NIC/ M ELZO NIC

0: Hardware selection via Pin P1.3

1: Software select ion wit h M ELZ _PR OZ

6 reserved

7 to be cleared

Ta ble 12: I²C Register REG12 (HOR_DELAYS): Subaddress 0B hex [28]

Bit Name Function

0...2 IN _DE L input lumina nce delay

3... 4 HD_DEL (Prozon ic) 1 to 4 clock shift f or the hor. reference

WE_HDE L (Me lzonic) 1 to 4 clock shift for WE2 output signal

5...6 WE 2_DE L (Pro zonic) 1 to 4 clock shift f or WE 2 output signal

RE_HDE L (Mel zoni c) 1 to 4 clock shift f or RE output signals

7 reserved

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

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HVS/UM9704

Ta ble 13: I²C Register REG13 (HWESTA): Subaddress 0C hex [xx]

Bit Name Function

0 . . . 7 HWES TA start value for horizontal writ e enable (lower 8 bits)

Ta ble 14: I²C Register REG14 (HWESTO): Subaddress 0D hex [xx]

Bit Name Function

0 . . . 7 HWE STO stop value for horizont al write enable (lower 8 bits)

Table 15: I²C Register REG15 (HRESTA) : Su ba ddress 0E hex [1F]

Bit Name Function

0 . . . 7 HRES TA start value for horizont al read enable (lower 8 bits)

Table 16: I²C Register REG16 (HRES TO): Subad dress 0F hex [C3]

Bit Name Function

0 . . . 7 HRE STO stop value for horizont al read enabl e (lower 8 bits )

Ta ble 17: I²C Register REG17 (HDDEL): Subaddress 10 hex [00]

Bit Name Function

HDDEL: horizontal f ine dela y for the SAA 4977 display signal s

0 HDA V _DE L fine del ay of HDAV

0: no addit ional delay

1: signal del ayed b y one displ ay clock

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

1 HB DA _DE L fine del ay of HBDA

0: no addit ional delay

1: signal del ayed b y one displ ay clock

2 HRE _DE L fine del ay of HRE

0: no addit ional delay

1: signal del ayed b y one displ ay clock

3 HBLND_DE L fine del ay of HBLND

0: no addit ional delay

1: signal del ayed b y one displ ay clock

Ta ble 18: I²C Register REG18 (HDMSB): Subaddress 11 hex [AA]

Bit Name Function

0 HD MSB MSB of HDAVSTA

1 MSB of HDAVSTO

2 MSB of HBDASTA

3 MSB of HBDASTO

4 MSB of HRESTA

5 MSB of HRESTO

6 MSB of HBLNDSTA

7 MSB of HBLNDSTO

Ta ble 17: I²C Register REG17 (HDDEL): Subaddress 10 hex [00]

Bit Name Function

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

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HVS/UM9704

Ta ble 19: I²C Register REG19 (VDMSB): Subaddress 12 hex [0A]

Bit Name Function

0 VDMSB to be cl eared

1 t o be set

2 MSB of VBD AST A

3 MSB of VBD AST O

4...7 reserved

Ta ble 20: I²C Register REG20 (HBDASTA): Subaddress 13 hex [52]

Bit Name Function

0 . . . 7 HB DAST A start value of horizonta l blanking for t he DAC (low er 8 bits )

Ta ble 21: I²C Register REG21 (HBDASTO): Subaddress 14 hex [F2]

Bit Name Function

0 . . . 7 HBDA STO stop va lue of horizontal blanking for the DAC (lower 8 bits)

Ta ble 22: I²C Register REG22 (HWE MAIN DELAY): Subaddress 15 hex [32]

Bit Name Function

0 ... 7 HWE_MAIN_DELAY horizontal shift of the HWE signal

I²C-bus Register Specification for the

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HVS/UM9704

Ta ble 23: I²C Register REG23 : Subaddress 16 hex [xx]

Bit Name Function

0 ... 7 reserved

Table 24: I²C Register REG24: Subaddress 17 hex [xx]

Bit Name Function

0 ... 7 reserved

Table 25: I²C Register REG25 (HDAVSTA): Subad dress 18 hex [05]

Bit Name Function

0 . . . 7 HDA VST A start value of gating signal for chrominance display dat a

(lower 8 bits)

Table 26: I²C Register REG26 (HDAVSTO): Subaddress 19 hex [A9]

Bit Name Function

0 . . . 7 HDAV STO stop value of gating signal for chrominance display data

(lower 8 bits)

Ta ble 27: I²C Register REG27 : Suba ddress 1A hex [xx]

Bit Name Function

0 ... 7 reserved

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

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Ta ble 28: I²C Register REG28 : Suba ddress 1B hex [xx]

Bit Name Function

0 ... 7 reserved

Ta ble 29: I²C Register REG29 (VBDASTA): Subaddress 1C hex [15]

Bit Name Function

0 . . . 7 VBD AST A st art value of vertical blankin g for the DAC (lower 8 bits)

Ta ble 30: I²C Register REG30 (VBDASTO): Subaddress 1D hex [31]

Bit Name Function

0 . . . 7 VBD AST O stop value of verti cal blanking for the DAC (lower 8 bits )

Table 31: I²C Register REG31 (HBOX_START): Subaddress 1E hex [00]

Bit Name Function

0 . . . 7 HBOX _STA RT direct PROZO NIC/ M ELZONI C regist er access

Ta ble 32: I²C Register REG32 (HBOX_STOP): Subad dress 1F hex [00]

Bit Name Function

0 . . . 7 HBOX _STO P dire ct PROZO NIC/ MEL ZONI C regist er access

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

3.2.3 I²C translater register data format

Next subaddre ss for the following I ²C registers will be 28h !

Acquisition part:

Table 33: I²C Register REG33: Subaddress 20 hex [xx]

Bit Name Function

0 ... 7 reserved

Table 34: I²C Register REG34: Subaddress 21 hex [xx]

Bit Name Function

0 ... 7 reserved

Ta ble 35: I²C Translater Register 0 (ACQ_0): Subaddress 28 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 ... 7 AGC_Y 0150 00 AGC gain for Y channel (2´s complement rel

0 dB): upper 8 bits

Ta ble 36: I²C Translater Register 1 (ACQ_1): Subaddress 29 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 ... 7 A GC_UV 01 51 00 AGC gain for U and V channel (2 ´s com ple-

ment rel 0 dB): upper 8 bits

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Ta ble 37: I²C Translater Register 2 (ACQ_2): Subaddress 2A hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 AGC_Y _LS B 01 52 00 AGC gain fo r Y channel LS B

1 AGC_UV _LS B AGC gain fo r UV channel LS B

2 standby_f 1: frontend in standby mode

3 aaf_bypass 1: bypass for pref ilt er

4 reserved

5 reserved

6 reserved

7 reserved

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Ta ble 38: I²C Translater Register 3 (ACQ_3): Subaddress 2B hex

Bit Name Host address

(hex)

Default

value (hex)

Function

0..1 UVclcorrect_mode 0153 00 Bit1 Bit0 UV clamp mode

0 0 auto

0 1 fixed

1 0 keep

11-

2.. 4 Uclcorrect_fval 000 Bit2 Bit1 Bit0 fixed value cl amp co rr.

U ch annel

000

001

010

011

100

101

110

111

5..7 Vclcorrect_fval 000 Bit2 Bit1 Bit0 fi xed va lue cl amp c orr.

V channel

000

001

010

011

100

101

110

111

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Ta ble 39: I²C Translater Register 4 (ACQ_4): Subaddress 2C hex

Bit Name Host address

(hex)

Default

value (hex)

Function

0..1 UVcoring 0 1 54 00 B it1 Bit0 UV coring level

00 0

0 1 +/- 0,5

10 +/- 1

11 +/- 2

2..3 mff_width 01 Bit1 Bit0 majority filter setting

00 1

01 3

10 5

11 7

4..5 UVcl_tau 00 Bit1 Bit0 ver tica l filterin g o f me a-

sured clamp

6 compress 0 0: compression off

1: compression on

7 comp_mode 0 0: 14:9 compression mode

1: 16:9 compression mode

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Ta ble 40: I²C Translater Register 5 (ACQ_5): Subaddress 2D hex

Bit Name Host address

(hex)

Default

value (hex)

Function

0..2 ydelay 0155 000 Bit2 Bit1 Bit0 variable Y-delay

000-2

001-1

0100

0111

1002

101-

110-

111-

3. .4 overl_comp 01 Bit1 Bit0 overload threshold

00216

01224

10232

11240

5 fill_m em 0 : default

1 : fill memory wit h constant value

6 reserved

7 reserved

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Display part:

Ta ble 41: I²C Translater Register 6 (DCTI_0): Subaddress 2E hex

Bit Name Host address

(hex)

Default

value (hex)

Function

0..2 dcti_gain 01D1 010 Bit2 Bit1 Bit0 dcti gain

0000

0011

0102

0113

1004

1015

1106

1117

3..6 dcti_threshold 0000 DCTI threshold (0,1,2,...,14,15)

7 dcti_ddx_sel 1 DCTI ddx_sel

0: low

1 : high

Table 42: I²C Translater Register 7 (DCTI_1): Subaddress 2F hex

Bit Name Host address

(hex)

Default

value (hex)

Function

0..1 dcti lim it 0 1D2 10 B it1 Bi t0 DCTI lim it

00 0

01 1

10 2

11 3

2 dcti_separate 1 0: off

1: on

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

3 dcti_protection 1 0: off

1: on

4 dcti_filteron 1 0: off

1: on

5 dcti_superhill 1 0: off

1: on

6...7 nrln_0 00 DCTI num ber l ines (2 LSBs)

Table 43: I²C Translater Register 8 (DCTI_2): Subaddress 30 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 . . . 7 nrln_1 0 1 D3 0F F DCTI num ber lines upper 8 bits

Table 44: I²C Translater Register 9 (DCTI_3): Subaddress 31 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 . . . 7 nrpx 01 D4 0 D8 DCTI number of pixels / 4

Table 42: I²C Translater Register 7 (DCTI_1): Subaddress 2F hex

Bit Name Host address

(hex)

Default

value (hex)

Function

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Ta ble 45: I²C Translater Register 10 (SIDEP_OVL_UV): Subaddress 32 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 . .. 3 overlay_u 01D5 100 0 sidepanels overlay U 4 MSB

4 ... 7 overlay_v 1000 sidepanels overlay V 4 MSB

Ta ble 46: I²C Translater Register 11 (SIDEP_OVL_Y): Subaddress 33 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 ... 7 overlay_y 01D6 00 sidepanels overlay Y 8 MSB

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

The peaking funct ion will be improved in the next SAA 4977 version.

Ta ble 47: I²C Translater Register 12 (PEAKING): Subaddress 34 hex *)

Bit Name Host address

(hex)

Default

value (hex)

Function

0..1 peak_a 01D7 10 Bit1 Bit0 peaking a

00 0

01 1/2

10 1

11 2

2..3 peak_b 10 Bit1 Bit0 peaking b

00 0

01 1/2

10 1

11 2

4..5 peak_limit 10 B it1 Bit0 peak limiter setting

00 255

01 340

10 425

11 511

6..7 peak_coring 10 B it1 Bit0 peak coring sett ings

00 0

01 4

10 8

11 16

Ta ble 48: I²C Translater Register 13 (SIDEP_START) Subaddress 35 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 . . . 7 sidepanel_st a rt 01 D8 00 sidepanel start position (8 MSB)

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

*) The IIC register, subaddress 37 can only be controlled in the Melzonic mode (subaddress 0A hex, bit 4,

MELZ_PROZ = 1)

3.2.4 Acknowledgement of bytes

The IPQ µC acknowledges alwa ys all re gister bytes indep endent fro m t heir content s. If the mast er µC transmits

more than t he m axim um number of regist er bytes, the sla ve µC will acknowl edge the followin g bytes, but will not

store them in its internal RAM.

Ta ble 49: I²C Translater Register 14 (SIDEP_STOP): Subaddress 36 hex

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0 . . . 7 sidepanel_st op 01 D9 00 sidepanels stop posit ion (8 MS B)

Ta ble 50: I²C Translater Register 15 (SIDEP _FDEL): Subaddress 37 hex *)

Bit Name Ho st address

(hex)

Default

value (hex)

Function

0...1 sidepa nel_f del 01 DAh 00 B it1 Bit0 sidepan el fine delay

00 0

01 1

10 2

11 3

2 display_mode 0 display mo de

0: 9 bit, blanking level 288

1: 10 bit, blanking level 64

3 reserved

4 reserved

5 reserved

6 reserved

7 reserved

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

3.3 Receiving data from the IPQ µC

The IPQ µC i s able to transmit one stat us byte plus additiona l read bytes t o the mai n µC. The IP Q µC then works

as a slave transmitter.

The I²C -bus transmis sion protocol for transm itting the status byte plus read registers has the followi ng format:

3.3.1 Contents of status byte

The status byte cont ains the f ollowing inf orma tion:

Start Slave address 69h Ack Status byte ReadReg1 Ack ... Nack Stop

Ta ble 51: I²C Read Register 1 (STATUS): No Subaddress !

Bit Name Default

value (hex)

Function

0 NON_IL 0 0: non interlaced mode not active

1: non interlaced mode active

1 reserved

2 AUTO_MOVIE_FLAG 0 0: normal mode

1: autom atic movie m ode acti va ted

4 M OVIE 0: no movie mode dete cted

1: movie detected

4 PHA SE_F LA G 0 0: standard mode ( ABAB in case of MOVIE= 1)

1: 180° phase shift (B CBC, MO V IE=1)

5 P ORT 0 bit setting read from port bit P 2.4

0 : P2 .4 = 0

1 : P2 .4 = 1

6 REA DY 1 0: not ready to accept com ma nd

1: ready to accept co mm and

7 WATCH 0 Watchdog bit: will be toggled when status byte is

read by master µC, init ial ized with 0

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Bit 6 will be cleared af ter the IPQ µC has received I²C register bytes. I t will be set again af ter the eva luat ion of all

bytes is co mpl ete d and a n extern al interrupt (V 100) ini tiati ng data t ransfer from IPQ µC to ECO5, dat apat h addi-

tional regist ers, PROZO NIC/ M E LZO NIC is not currently serviced.

3.3.2 Contents of datapath read registers

Table 52: I²C Read Register 2 (MPD MSByte1): No Subaddress !

Bit Name Function

0...7 MO VIE_PHAS E_A direct PROZ ONIC regist er read, M SByte; Movie p hase de tec-

tion byte 1

Table 53: I²C Read Register 3 (MPD MSByte2): No Subaddress !

Bit Name Function

0...7 MOVI E_ PHA S E_ B direct P ROZ ONIC r egister read, M S B yte; M ovie phase detec -

tion byte 2

Table 54: I²C Read Register 4 (read_Uclerror): No Subaddress !

Bit Name Host

address

(hex)

Functio n (NOT YET IMP LEM E NTE D !!!)

0...6 read_Uclerror 0170 Read U c hannel clamp error (+3/-4 resolution 1/16

LSB)

7 reserved

Table 55: I²C Read Register 5 (read_Vclerror): No Subaddress !

Bit Name Host

address

(hex)

Functio n (NOT YET IMP LEM E NTE D !!!)

0...6 read_Vclerror 0171 Read V channel clamp error (+3/-4 resolution 1/16

LSB)

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

3.4 Timing aspects

The maximum allowed response time between accepting register bytes and the execution of the commands han-

dled by the IPQ µC is 90 m s. This time is only relevant when field m emory control modes are changed. Field

memory cont rol modes are: Ci ne, LFR, S till, Mu lti-PI P mo de. When a fie ld memory cont rol mode has been act i-

vated, the IPQ µC wai ts max. 40 m s until a new fram e starts in LFR m ode (4 x 100Hz field repet ition t ime ). Then

it takes anothe r 40 ms until one new frame has been com plet ely transm itted in order to run the new mode.

The maxim um allowed total clock stret ch time of the IP Q µC within one I²C message is 5 m s .

The minim um wait t im e between sending two I²C bus register data packages varies from 12 ms (no field mem or y

control modes have changed) to 90 ms (field m em or y control modes have changed ).

If the user wa nts to make sure that a complete I²C bu s r egister dat a packa ge is transmit ted witho ut b eing inter-

rupted by VDFL IRQ µC routine and the slave µC is free for I²C after the master µC transmits I²C data, the I²C

data package should be t ransmitted bet ween 3 and 5 ms after VDFL occured. The slave µC sets bit 6 of the sta-

tus byte when it is ready to accept I²C command s.

7 reserved

Ta ble 56: I²C Read Register 6 (read_Ygain): No Subaddress !

Bit Name Host

address

(hex)

Functio n (NOT YET IMP LEM E NTE D !!!)

0...7 read_Y gai n 0172 Read overflow indicat ion of Y channel

Ta ble 57: I²C Read Register 7 (AGC_Y_read): No Subaddress !

Bit Name Host

address

(hex)

Functio n (NOT YET IMP LEM E NTE D !!!)

0...7 AGC_Y _read 0173 AG C gain for Y chan nel, upp er 8 bi ts (fo r funct ional

test only)

Table 55: I²C Read Register 5 (read_Vclerror): No Subaddress !

Bit Name Host

address

(hex)

Functio n (NOT YET IMP LEM E NTE D !!!)

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Multi-PIP:

The tim e between one live PIP picture register comma nd to anot her should not be shorter than 120 m s.

Screen fade:

As long as this m ode is active (86 fields = 860 ms i n normal mode), all other mode changes are ignored.

4. Evaluation of I²C-bus register data

The evaluation of I²C bus register data is done with respect to a certain priority structure. In the following sections

certain restrict ions on bit setti ngs in the I²C regi ster byt es w hich limit the p ossibilities of combining f ield memo ry

control modes (Cine, LFR, Still, Mul ti-P IP mode) and/ or second ary control comm ands are liste d.

There are 3 different appli cation concep ts for BES IC, which are taken into account:

1. MELZO NIC concept:

- two field me mory concept with Nat ural Motion (Movem ent Estimat ion and Com pensation) , LFR, Adap tive NR,

External M ulti PIP

2. PROZ ONIC concept:

- t wo fie ld memory conce pt with LFR, Adap tive NR, Exte rn al Multi P IP

3. Singl e mem ory concept:

- simple AABB processing

All functions which are re lated to only one or two of the 3 concepts, are indicated .

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

4.1 Field memory control modes

4.1.1 Priorities

The different Field Control Modes of the IPQ module have different priorities. The following table shows which

mode has t he highest and wh ich mode has the lowe st priority. The pri ority structure m ust be taken into account

when activa ting f ield control m odes.

4.1.2 Field Control modes

AABB Mode

Software control: Mode with the lowest priority (all other field control bits switched off).

The AABB mode is the most simple conversion mode for 100 Hz. Only one field memory is implemented.

The video data of an incoming field are simply doubled in an AABB sequence. For the low-end concept

this mode is the default conversion mode.

This mode can also be used in the PROZONIC and MELZONIC concept. The mode even has to work cor-

rectly if the PROZONIC and MELZONIC is removed. This demand means that the vertical display read con-

trol has to be realized via the memory controller part of SAA 4977 and not by the VRE control of the

external processing ICs. In the live AABB mode the DR-Bit has to be toggled field by field to generate the

AABB raster with the fi eld length sequence 313, 312. 5, 312 and 312.5 lines.

LFR Mode

Software Control: I² C-Regist er subaddress 01, Bit 0 (LFR)

The Line Flicker Reduction (LFR) mode is the default control mode of the PROZONIC concept and can be

used with MELZONIC as well. It makes use of a m edianfil ter to generate the output sequence: original field

A, medianfilt ered A*, medianfiltered B* and original fi eld B.

Table 58 Mode Priorities

Mode Priority

INIT highest

SCREEN FADE (not yet implemented) .

MPIP .

VZOOM

GENERATOR mode .

FEATURE mode .

NON_IL mode .

Natu ra l Mo tion ( M E LZ O N I C co ncept) .

LFR mode (MELZONIC/PROZONIC concept) .

AABB mode lowest

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Natural Motion (Video and Movie)

Software Control: I² C-Regist er subaddress 02, Bit 4 (NATURAL_MOTION)

This function can only be realized in the high-end Melzonic concept. The MELZONIC will compensate

movement artef acts which are c aused by e.g. simple field doubling in the

100 Hz mode. For video sources with 50 Hz motion resolution a constant 100 Hz motion is calculated by a

vector based motion estimation and compensation. For movie sources which have a motion resolution of

only 25 Hz the MELZONIC is able to increase the motion frequency to 50 Hz. This provides a remarkable

improvement for the display of movies even compared to 50 Hz standard TVs. A recursive block matching

algorithm is implemented in the SAA 4991. Beside the simple field control of these two natural motion

modes the software has to check the quality of the motion compensation. The µC in the SAA 4977 reads

the MELZONIC register NR_BAD_RANGES. This register will be compared with the constant threshold

value BAD_LIMIT. If NR_BAD_RANGES is greater than BAD_LIMIT the Natural Motion Mode will be disa-

bled, even if the I²C-bus bit NATURAL_MOTION equals 1. The 100 Hz conversion mode will be switched

into the mode, which would have been chosen if NATURAL_MOTION is cleared (fallback mode). It is a

control mode with a lower priority, in which no vector based processing is performed.

As mentioned above the natural motion processing has to be adapted to the motion resolution of the

source. For this requirement it is necessary to detect if a movie or a video source has to be motion com-

pensated. The correct mode (video or movie processing) can be controlled by the user himself or by an

automatic routine (see AUTO_M OV IE).

ABAB Movie Mode

Software Control: I²C-Register subaddress 01, Bit 4 (MOVIE), NATURAL_MOTION cleared

This mode is supported by the PROZONIC and MELZONIC approach. The converter performs a frame rep-

etition. The phase relation between the movie pictures and the incoming video signal is not standardized.

Via the additional control bit PHASE (I²C-Register subaddress 01, bit 5) the processing is put into the cor-

rect phase relation to the incoming movie (ABAB or B CBC).

Satellite Mode

Software Control: I² C-Regist er subaddress 02, Bit 6 (SAT_MO DE )

In the satellite mode all the four 100 Hz display fields are derived from the output of the median filter. The

median filter will filter out details occurring in only one line. This fact can be used to attenuate typical FM

noise dropouts which normally occur uncorrelated in the field. A bad satellite signal reception can be

improved quite effectively in this mode without deteriorating the picture quality.

Generator Mode (G_Mode)

So ftware Cont ro l: I²C -Re gis te r subadd ress 00, Bit 2(G_MODE)

Th e bit G_M ODE activa tes a stable 10 0 Hz display wi th a fixe d field le ngth o f 3 12.5 lin es for AF F=0 an d 262.5

lines for AF F= 1. The di splay field length is not adapted accordin g to the video source. The conv e rs ion m ode is

reduced to a single field repetition mode (AAAA). This sp ecial mode can be used to get a stable OSD picture

without a source or with a v ery noisy sou r ce. It d oes also i m prove th e pi cture stab ilit y for a tuner channel search.

Auto Movie De tection routine

Software Control: I² C-Regist er subaddress 01, Bit 6 (AUTO_M OVIE)

-Aut o Movie Detecti on in the Melzoni c concept

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

The bit AUTO_MOVIE activates an automatic movie source detection if the natural motion mode is

switched on. The detection is based on the read values of the Melzonic registers “vector_sum”. This sum

of vector absolutes represents the amount of motion found between two incoming fields. The software

investigates the v ector sums of a whole frame to detect whether a video or a m ovie source is connec ted. If

the two values show a large difference the converter can be switched to a vector based movie processing

increasing the movement resolution from 25 Hz to 50 Hz. The annoying motion judder of movies is elimi-

nated. The phase relation between the movie pictures and the video fields is taken into account. In case of

a video source or scenes with no or small motion the video processing is active, increasing the movement

resolution from 50 Hz to 100 Hz. This removes the unsharpness of moving edges compared to a simple

fi eld repetition 100 Hz converter.

If the AUTO_MOVIE bit is set to zero, the converter is performing a motion compensation processing for

video sources as long as the bit MOVIE is cleared. If MOVIE is set a movie motion compensation is acti-

vated. The phase relation to the incoming movie can be adapted via the control bit MOVIE_PHASE. The

user is able to adapt the natural motion processing to the source via the bits MOVIE and MOVIE_PHASE

by himself if the autom atic movie detection routine has been switched off.

-Aut o Movie Detecti on in the Prozonic co ncept (not impl em ente d in t he S AA 4977 V1B )

If the bit AUTO_MOVIE is set in the Prozonic concept the same routine as descibed above will investigate

whether a movie source is applied and in which phase relation it is transmitted. The software uses the Pro-

zonic read register MPD to get a motion information which is not based on a vector sum but on a sum of

absolute differences in the luminance channel. With Prozonic the movie detection is not used to activate a

movie mode. The LFR sequence AA*B*B is adapted to the phase of a movie and can be switched to a

BB*C*C processing automatically. This results in an improved performance of vertical rolling titles. The

time constant of the Auto Movie routine is increased compared to the M elzonic approach. There is no need

for a fast detection because no severe artefacts occur if the detection has a delay .

Multi-PIP (MPIP)

Software Control: I² C-Regist er subaddress 03, Bit 6 (M PIP)

The field memories of the 100 Hz converter can be used to generate a MPIP picture if MPIP is set. It is

assumed that the TV set contains a PIP Module which generates a compressed PIP picture at the bottom

right side of the screen. The picture supplied by the PIP module is written into the field memories and

placed according to the chosen position of the MPIP control (I²C-Register subaddress 03, POS0-POS3).

The complete MPIP picture shows 3 x 3 or 4 x 3 small pict ures. One of those can display a l ive source, the

others are frozen. With the control bit SPIP (I²C register subaddress 03, bit 7) the PIP window can be

adapted to a 60 Hz PIP source. The vertical size of the PIP window is reduced if SPIP is set.The MPIP fea-

ture makes use of the boxing function of Prozonic or Melzonic. The noise reduction circuitry (k-factor con-

trol) together with the defined boxes support the PIP function. The MPIP feature can be used for a channel

overview or to show frozen motion phases of one channel (photo finish).

Vertical Zoom

Software Control: I²C-Register subaddress 02 (VZOOM _0 to V ZOOM_3, bit 0 to bit 3 and VZO OM, bit 7)

A vertical zoom function realized by an interpolation of lines can be activated via the control bit VZOOM.

The zoom factor is defined by the bits VZOOM_0 to VZOOM_3. The factors 1.1, 1.25, 1.33 and 1.5 are

supported by the control software. The zoom function can be combined with the LFR and the natural

motion feature (v ideo and movie source). If the AABB mode is chosen together with vert ical zoom the soft-

ware sw itches aut omatically to a LFR processing.

Still Picture Mode

Software Control I²C Register subaddress 01, bit 7(STP)

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

The Still Picture function can be combined with every conversion mode. For the modes LFR and Natural

Motion the frozen picture is processed based on a frame displaying the original field A and the median fil-

tered A*. In the AABB mode, MPIP, SAT Mode and Generator Mode only a one field still picture is gener-

ated.

Non-Interlace Mode

Software Control: no I²C control

If a non-i nterlace source is detect ed by the software the fi eld processing switches automatically into a Non-

Interlace Mode. The detection criteria is a field length which is N complete lines. As the memory controller

counts half lines starting with zero a non-interlace source will set the LSB of the field length read register

(PAL standard = 270 hex, NTSC standard = 20C hex). A non-interlace source is additionally indicated in

bit 0 of the status read register 1 (NON_IL).

INIT

Software Control I²C Register subaddress 0, bit 7 (INIT)

If the Init bit is set the SAA 4977 modul e will be initialized with the default values.

The module is initialized in the Melzonic concept in the natural motion mode with AUTO_MOVIE=1. Fur-

thermore the SAA 4977 is initialized in the digital colour deccoder mode. For this reason the picture will

appear disturbed in the analog concept after an initialization has been done.

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

4.1.3 Secondary control commands

The secondary control commands c an be combined with the abov e des cribed field control modes

Acquisition Field Frequency selection (AFF)

Software Control I²C Register subaddress 0, bit 4(AFF)

The bit AFF is set by the user according to the vertical frequency of the incoming source. In case of a 50

Hz source the bit is cleared, for 60 Hz sources it is set. The vertical writing window is adapted (VWE1STA

and VWE1STO). The bit also c hanges the reference field length for the feature mode detection. In the gen-

erator mode the field length i s set to 312.5 lines for AFF=0 and 262.5 lines f or A FF=1.

Horizontal Compression

Software Control: not yet directly s upported

The SAA 4977 supports two different compression modes for 14:9 and 16:9 display modes (1.17 and

1.33). These modes can be activated via the datapath register subaddress 2C, bits 6 and 7. Additionally a

correct s etting of the horizontal m emory controller settings has t o be done ( see control table in c hapter 5)

Noise reduction

So ftware Control: I²C-Registe r, subaddress 04, bit 0 and 1 (NR0, NR1)

The recursiv e noise reduction can be s et t o three le ve ls ( low, m ediu m, hig h). F or in ve stiga tio n purposes a direct

control of the PROZONI C/M E LZ ONI C noise redu ction regi sters is pos si ble.

Split Screen

So ftware Cont ro l: I²C -Re gis te r subadd ress 04, Bit s 2, 3 (SP S 0, S PS1)

The s c reen can be s pli t int o t w o h a lves by the S plit Screen fea ture. One half is showing a noise reduced pictur e

the other the perfo rmance of the original source. The splitting can be done in horizontal or vertical direct ion. The

mode allow s a direct c o mparison o f the original and nois e reduced picture on the screen.

Screen fade

Software Control: I²C-Register subaddress 04, Bit 4, 5 (SCF0, SCF1)

The screen fade feature can be used to “fade out” a picture like closing curtains. This is done by the con-

trol SW by continuously changing the setting of the side panel start and stop values of SAA 4977 until a

homogenous coloured picture is visible. The function is also available the other way round where the pic-

ture is “faded in” starting from a complete t he display.

HWE Delay

Software Control: I²C-Register subaddress 05, bit 7 (SET_HWE_MAIN_DELAY), subaddress 15 Hex

(HWE_MAIN_DELAY)

The horizontal writing window can be delayed via the I²C register HWE_MAIN_DELAY if the control bit

SET _ H WE_MA IN _ D EL AY i s se t .

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

VWE Delay

Software Control: I²C-Register subaddress 07,bits VWE1D0 - VWE1D6 and VWEX

The vertical writing window can be delayed in steps of lines via the I²C register VWE Delay register if the

bit VWEX is set. The possible delay range is 0 to127 lines. The delay function is needed to centre a verti-

cal zoomed picture.

Blank Field Mode

Software Control: I²C-Register subaddress 08, bits 0-3, (BLANK_F0 - B LANK_F3)

The Blank Field Mode allows the user to define which fields of the sequence of the 100 Hz display fields

are displayed or blanked. If all the four control bits are cleared the normal active display appears. If one bit

is set the corresponding display field will be blanked.

In the AABB mode a blanking of every second field generates a display which is similar to a normal 50 Hz

screen. The elimi nation of the large area f li cker can be demonstrated by switching from this m ode to a nor-

mal 100 Hz display . The blank f ield m ode is normally used for testing purposes.

Selection of the Colour Decoder Concept

Software Control: I²C-Register subaddress 09, bit 4 (DIGITAL_COLOR_DECODER_CONCEPT)

Norma lly the SAA 4977 is im plemented in a concept with an analog co lo ur decoder. In thi s ca se the a cquisitio n

clock is generated by the SAA 4977 and the internal ADC is used. If the control bit (Digital_

Colour_Decoder_Concept) is set the acquisition clock has to be suppli ed from external. The digital data are

direct ly fed into the first field memory . From the point of software contr o l all horizont a l acquis ition r eg ister v alues

hav e to be div id ed by the factor t wo. The analog fronten d part of SAA 4977 V1B shou ld to be switched i nto the

stand -by mode.

Port Pin Control

Software Control: I²C-Register subaddress 0A hex , bit 0 - bit 3

The free port pins of the µ-Controller core in the SAA 4977 can be controlled via I²C bus. The polarity of

the port pins is switched synchronized to VDFL this means synchronized to the display. The port pins

P1.1, P1.2, P1 .4 and P1.5 can be controlled.

Direct control of the PROZONIC/MELZONIC register HOR_DEL

Software Control: I²C-Register subaddress 05, bit 0 (SET_ HOR_DEL)

If the control bit SET_HOR_DEL is set a direct control of the PROZONIC/MELZONIC register

HOR_DELAY is enabled (see Prozonic/Melzonic data sheet) via the I²C register subaddress 0B hex. This

further more allows an adjustment of the chrominance reformatting for a correct internal chroma process-

ing. The correct setup should be checked with nois e reduction switched on.

Direct control of the PROZONIC/MELZONIC register HBOX_START/STOP

Software Control: I²C-Register subaddress 06, bit 0 (SET_ HBOX)

If the control bit SET_HBOX is set a direct control of the PROZONIC/MELZONIC registers HBOXSTART

and HBOXSTOP is enabled (see Prozonic/Melzonic data sheet) via the I²C registers subaddress 1E and

1F hex. The box set tings are us ed for the split screen function and Multi PIP.

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Direct change of the memory controller settings in the SAA 4977

Via enable bits the most important signals of the memory controller can be defi ned by the user. This allow s

a very flexible use of the SAA 4977 also for changed conditions in the application. Many signals are 9 bit

values. If one signal is switched to a direct user control the corresponding I²C registers for the signal start

and stop values are enabled. These registers define the lower 8 bit of the com plete 9 bi t values. The MSBs

are defined via an additional MSB register which has to be enabl ed if necess ary.

DAC blanking control

Software Control: I²C-Register subaddress 06, bit 3 (SET_VBDA) , subaddress 05, bit 6 (SET_HBDA)

The bit SET_VBDA enables the direct control of the vertical blanking t ime for the DAC of the S AA 4977 via

the I²C registers subaddress 1C hex (VBDASTA, start value) and subaddress 1D hex (VBDASTO, stop

value). The sensible program ming range of VBDA depends on the field length of the source (PAL 0 to 138

hex, NTSC 0 to 106 hex). If the programmed values are higher than the number of lines of the source

(V CR fast f orwar d) the memory controller stops the s ignal automatically .

The horizontal signal part of the blanking can be controlled in the same way. The bit SET_HBDA enables

the direct control of the horizontal blanking time for the DAC via the I²C registers subaddress 13 hex

(HBDASTA, start value) and subaddress 14 hex (HBDASTO, stop value). The programming range of

HBDA is 0 to 1FF hex. The programming step width is two display clocks. The signal refers to the rising

edge of the HDFL signal.

The MSBs of the start and stop values are controlled via additional MSB registers (see chapter MSB con-

trol). Normally the user does not have to c hange the MSB settings as long as small changes are done com-

pared to the default settings.

HWE control

Software Control: I²C-Register subaddress 05 hex, bit 1 (SET_HWE)

If the control bit SET_HWE is set a di rect control of the horizontal write enable signal fed to to the fi rst field

memory is enabled. The start value is defined via I²C register subaddress 0C hex (HWESTA). The stop

value is defined via I²C register subaddress 0D hex (HWESTO). The HWESTA/STO values are 9 bit val-

ues. Only the lower 8 bits can be changed by the user. The program ming steps have 2 clock accuracy of

the acquisition clock. The signal refers to the ri sing edge of the horizontal reference to the SAA 4977 (HA,

pin 22).

HRE control

Software Control: I²C-Register subaddress 05 hex, bit 2 (SET_HRE)

If the control bit SET_HRE is set a direct control of the horizontal read enable signal fed to PROZONIC,

MELZONIC or to the firs t field memory in the single fi eld concept is enabled. The start value is defined via

I²C register subaddress 0E hex (HRESTA). The stop value is defined via I²C register subaddress 0F hex

(HRESTO). The M SBs ar e controlled via t he I IC register HDM SB ( see c hapter M SB control).

HDAV control

Software Control: I²C-Register subaddress 06 hex, bit 6 (SET_HDAV)

The control bit SET_HDAV enables the direct control of the horizontal display signal HDAV (Horizontal

Data Valid Chrominance). The signal gates the chrominance display signals. A wrong setting results in a

partly uncoulored picture. The start value is defined via I²C register subaddress 18 hex (HDAVSTA). The

stop value is defined via I²C register subaddress 19 hex (HDAVSTO). The signal refers to the rising edge

of HRDFL.

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

HDDEL control

Software Control: I²C-Register subaddress 05 hex, bit 3 (SET_HDDEL)

A direct control of the memory controller register HDDEL via I²C register subaddress 10 hex is enabled if

the control bit SET_HDDEL is set. The register HDDEL defi nes a fine delay of the horizontal output signals

of the SAA 4977 with display clock accuracy. The delay adjustment may be necessary for changes in the

concept to ensure a correct processing of the colour difference signals which are coded in a serial format

(4:1:1). Every signal can be shifted by one clock or none.

HDMSB control

Software Control: I²C-Register subaddress 05 hex, bit 4 (SET_HDMSB)

If the bit SET_HDMSB is set the memory controller register HDMSB can be directly controlled via IIC bus

subaddress 11 hex. It contains the MSBs of the start and stop values of the display related hori zontal con-

trol signals. The det ailes definition of the register bits is described in the I IC table.

VDMSB control

Software Control: I²C-Register subaddress 05 hex, bit 5 (SET_VDMSB)

If the bit SET_VDMSB is set the memory controller register VDMSB can be directly controlled via IIC bus

subaddress 12 hex. It contains the MSBs of the start and stop values of the display related vertical control

signals. The detailes definition of the register bit s is desc ribed in the IIC table.

4.1.4 Selection of the Hardware configuration

Software Control: I²C-Register subaddress 0A hex , bit 4 (MELZ_PROZ), bit5 (SW_H W)

The hardware conf iguration is se lected via the port pin P1.3 if the control bit SW _HW is clea red. In case P1.3 is

on low level the Prozonic and s ingle field concept is chosen. If P1.3 is on high level the Melzonic concept is

active .

If the control bit SW_HW is set the concept is determined by the control bit MELZ_PROZ. For MELZ_PROZ

cleared the Prozoni c and single fiel d concept is chosen. If ME LZ_PR OZ is set the Melzoni c concept is active.

4.1.5 Datapath translator registers

Software Control: I²C-Register subaddress 30 - 3F hex

Via the I²C registers with subaddress 30 to 3F hex the SAA 4977 datapath registers can be directly

accessed. The datapath registers are initiali zed after power-on but not changed by any other routines than

the I²C bus.

For a detailed functional description of the datapath please refer to the application notes AN97057 and

AN97071.

4.1.6 SNERT interface

Via the SNERT interface all register data for PROZONIC, MELZONIC or LIMERIC dependant on the cho-

sen hardware configuration is transmitted. The internal SNERT pins of the µC Core of the SAA4977 are

directly connected to the pins of the S AA4977 V 1C.

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

5. Defau lt IIC control sett ing s

Table 59: Default IIC settings

II C reg.

subaddr.

(hex)

Single field concept Prozoni c concept Melzon ic concept

standard comp.

1.10 comp.

1.33 standard comp.

1.10 comp.

1.33 standard comp.

1.10 comp.

1.33

00 00 00 00 00 00 00 00 00 00

01 00 00 00 01 01 01 41 41 41

02 00 00 00 00 00 00 10 10 10

03 00 00 00 00 00 00 00 00 00

04 00 00 00 01 01 01 01 01 01

05 C4 C6 C4 CD CF CD CD CF CD

06 40 40 40 40 40 40 40 40 40

07 00 00 00 00 00 00 00 00 00

08 00 00 00 00 00 00 00 00 00

09 00 00 00 00 00 00 00 00 00

0A 20 20 20 20 20 20 30 30 30

0B 00 00 00 A0 A0 A0 28 28 28

0C 00 02 00 00 02 00 00 02 00

0D 00 A5 00 00 A5 00 00 A5 00

0E 3B 53 6D 21 39 51 15 31 49

0F DF C0 AD C5 A6 91 B9 9E 89

10 00 00 00 04 04 04 00 00 00

11 00 00 00 00 00 00 00 00 00

12 00 00 00 00 00 00 00 00 00

13 57 57 57 57 57 57 57 57 57

14 F4 F4 F4 F4 F4 F4 F4 F4 F4

15 26 26 26 27 26 26 27 26 26

16 00 00 00 00 00 00 00 00 00

17 00 00 00 00 00 00 00 00 00

18 21 21 21 21 21 21 21 21 21

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

19 E0 E0 E0 E0 E0 E0 E0 E0 E0

1A 00 00 00 00 00 00 00 00 00

1B 00 00 00 00 00 00 00 00 00

1C 00 00 00 00 00 00 00 00 00

1D 00 00 00 00 00 00 00 00 00

1E 00 00 00 00 00 00 00 00 00

1F 00 00 00 00 00 00 00 00 00

20 00 00 00 00 00 00 00 00 00

21 00 00 00 00 00 00 00 00 00

28 00 00 00 00 00 00 00 00 00

29 00 00 00 00 00 00 00 00 00

2A 00 00 00 00 00 00 00 00 00

2B 00 00 00 00 00 00 00 00 00

2C 04 44 C4 04 44 C4 04 44 C4

2D 08 08 08 08 08 08 08 08 08

2E 82 82 82 82 82 82 82 82 82

2F 32 32 32 32 32 32 32 32 32

30 FF FF FF FF FF FF FF FF FF

31 D8 D8 D8 D8 D8 D8 D8 D8 D8

32 88 7A 7A 88 7A 7A 88 7A 7A

33 00 4D 4D 00 4D 4D 00 4D 4D

34 AA AA AA AA AA AA AA AA AA

35 00 EA E2 00 E8 E0 00 EB DF

36 00 3C 4A 00 3B 47 00 3E 48

37 - - - - - - 00 00 00

Table 59: Default IIC settings

II C reg.

subaddr.

(hex)

Single field concept Prozoni c concept Melzon ic concept

standard comp.

1.10 comp.

1.33 standard comp.

1.10 comp.

1.33 standard comp.

1.10 comp.

1.33

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

6. INDEX

aaf_bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ACQ_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ACQ_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ACQ_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ACQ_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ACQ_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ACQ_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

AGC_UV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AGC_UV_LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AGC_Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AGC_Y_LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AGC_Y_read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AUT O_MOVIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

AUT O_MOVIE_FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

BLANK FIELDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

comp_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

compress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

dcti limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DCTI _0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DCTI _1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DCTI _2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DCTI _3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

dcti_ddx_sel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

dcti_f ilteron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

dcti_gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

dcti_pr otection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

dcti_separate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

dcti_superhill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

dcti_thr eshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

display_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

EN ABLE DIRECT REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

External Multi PIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

FIELD CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Field memory control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

field memory control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

fill_mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FREQUENCY SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

HBDASTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

HBDASTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

HDDEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

HDMSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

HOR_DELAYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

HRES TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

HRES TO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

HWE MAIN DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

I NIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

LFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

mff_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

MOVIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 31

MOVIE_ PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MPD MSByte1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MPIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Multi- PIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

NON_IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

NPIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

NR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

n rl n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

nr ln_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

nrpx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

overl_comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

overl ay_u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

overl ay_v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

overl ay_y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

peak_a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

peak_b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

peak_coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

peak_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PEAKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PHAS E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PHAS E_FL AG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Port Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

read_Uclerror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

read_Vclerror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

read_Ygain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Receiving data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SAT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SCREE N FADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Scr een fade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_HBDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_HBOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SET_HDAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SET_HDDE L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_HDMSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_HOR_DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_HRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_HWE _ MAIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SET_VDMSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SI DEP_F DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SIDEP_OVL _UV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SIDEP_OVL _Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SIDEP_START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

sidepanel_fdel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

sidepanel_start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

sidepanel _stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SPIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

standby_f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2

STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

STP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

I²C-bus Register Specification for the

SAA 4977 V1B

Philip s Sem iconductor s

User Manual

HVS/UM9704

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Uclcorr ect_fval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

UVcl_tau . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

UVclcorr ect_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

UVcoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

VAMSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 20

Vclcorr ect_fval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

VDMSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VWE1 DEL AY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

VZOOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 1 0

WATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ydelay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25