This is information on a product in full production.
January 2017 DocID025014 Rev 3 1/9
ESDARF02-1BU2CK
Single-line bidirectional ESD protection for high speed interface
Datasheet production data
Figure 1. Functional diagram (top view)
Features
Bidirectional device
Extra low diode capacitance: 0.2 pF
Very high bandwidth: 30 GHz
Low leakage current
0201 SMD package size compatible
Ultra small PCB area: 0.18 mm2
ECOPACK®2 and RoHS compliant component
Complies with the following standards:
IEC 61000-4-2 level 4
– 15 kV (air discharge)
– 8 kV (contact discharge)
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
Smartphones, mobile phone and accessories
Tablet PCs, netbooks and notebooks
Portable multimedia devices and accessories
Digital cameras and camcorders
Communication and highly integrated systems
Description
The ESDARF02-1BU2CK is a bidirectional single
line TVS diode designed to protect the data lines
or other I/O ports against ESD transients.
The device is ideal for applications where both
reduced line capacitance and board space saving
are required.
Pin1 available in different shapes
ST0201 package
Pin1
www.st.com
Characteristics ESDARF02-1BU2CK
2/9 DocID025014 Rev 3
1 Characteristics
Note: For a surge greater than the maximum values, the diode will fail in short-circuit
Figure 2. Electrical characteristics (definitions)
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol Parameter Value Unit
VPP
Peak pulse voltage:
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
8
20
kV
PPP Peak pulse power (8/20 µs) 20 W
IPP Peak pulse current (8/20 µs) 1.5 A
TjOperating junction temperature range -40 to +150 °C
Tstg Storage temperature range -65 to +150 °C
TLMaximum lead temperature for soldering during 10 s 260 °C
Symbol Parameter
V = Breakdown voltage
I = Leakage current @ V
V = Stand-off voltage
I = Peak pulse current
C = Parasite capacitance
R
BR
RM RM
RM
PP
d= Dynamic impedance
aT = Voltage temperature coefficient
Table 2. Electrical characteristics (values, Tamb = 25 °C)
Symbol Test Condition Min. Typ. Max. Unit
VBR IR = 1 mA 5 6.6 V
IRM VRM = 3.6 V 5 100 nA
VCL IPP = 1 A, 8/20 µA 10 12 V
RdDynamic resistance, pulse duration 100 ns 1.3 Ω
Cline F = (200 MHz- 3000 MHz), VR = 0 V 0.2 0.3 pF
fc -3 dB 30 GHz
DocID025014 Rev 3 3/9
ESDARF02-1BU2CK Characteristics
9
Figure 3. Leakage current versus junction
temperature (ty pical values) Figure 4. Junction capacitance versus
frequency (typica l values)
1
10
100
25 50 75 100 125 150
VR= VRM = 3.6 V
I/O / GND
Tj(°C)
IR(nA)
0,0
0,1
0,2
0,3
0,4
0,5
1,00 10,00 100,00 1000,00
F(MHz)
C(pF)
Tj= 25 °C
Vosc = 30mV
Direct Reverse
Figure 5. ESD response to IEC 61000-4- 2
(+8 kV contact discharge) Figure 6. JESD response to IEC 61000-4-2
(-8 kV contact discharge)
50 V/div
20 ns/div
242 V 1
19 V 217 V 315 V 4
V : ESD peak voltage
PP
V :clamping voltage at 30 ns
CL
V :clamping voltage at 60 ns
CL
V :clamping voltage at 100 ns
CL
1
2
3
4
50 V/div
-241 V 1
-20 V 2-16 V 3
-12 V4
V : ESD peak voltage
PP
V :clamping voltage at 30 ns
CL
V :clamping voltage at 60 ns
CL
V :clamping voltage at 100 ns
CL
1
2
3
4
20 ns/div
Figure 7. S21 attenuation measurement results Figure 8. TLP measurements
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035
540
15 50
20 55
10 45
25 60
30
0
5
10
15
20
25
Positive polarity
Negative polarity
IPP(A)
VCL(V)
Package information ESDARF02-1BU2CK
4/9 DocID025014 Rev 3
2 Package information
Epoxy meets UL94, V0
Bar indicates pin 1
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
2.1 ST0201 package information
Figure 9. ST0201 packag e outline
Table 3. 0201 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.23 0.28 0.33 0.0091 0.0110 0.0130
b1 0.20 0.25 0.30 0.0079 0.0098 0.0118
b2 0.20 0.25 0.30 0.0079 0.0098 0.0118
D 0.55 0.60 0.65 0.0217 0.0236 0.0256
E 0.25 0.30 0.35 0.0099 0.0118 0.0138
e 0.35 0.0138
L1 0.13 0.18 0.23 0.0052 0.0071 0.0091
L2 0.14 0.19 0.24 0.0055 0.0075 0.0095
DocID025014 Rev 3 5/9
ESDARF02-1BU2CK Package information
9
Note: Product marking may be rotated by 180° for assembly plant differentiation. In no case
should this product marking be used to orient the component for its placement on a PCB.
Only pin 1 mark is to be used for this purpose.
Figure 12. Tape and reel outline
Figure 10. Footprint, dimensions in mm
(inches) Figure 11. Marking
0.243
(0.0096)
0.170
(0.0067)
0.300
(0.0118)
0.243
(0.0096)
0.656
(0.0258)
Pin2 Pin 1
Z3
Bar indicates Pin 1
User direction of unreeling
All dimensions are typical values in mm
4.0
2.0
2.0
8.0
0.67
1.75
3.5
Ø 1.55
0.34
0.38
0.22
Z3
Z3
Z3
Z3
Z3
Z3
Recommendation on PCB assembly ESDARF02-1BU2CK
6/9 DocID025014 Rev 3
3 Recommendation on PCB assembly
3.1 Stencil opening design
Figure 13. Recommended stencil windows-opening 90%/Thickness 80µm (all
dimensions are in mm)
3.2 Solder paste
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component displacement during PCB movement.
4. Use solder paste with fine particles: Type4 (powder particle size is 20-45 µm).
0.230
(0.0091) 0.183
(0.0072)
0.170
(0.0067)
0.300
(0.0118)
0.285
(0.0112)
0.656
(0.0258)
0.643
(0.0253)
Footprint Stencil window
0.007
(0.00027)
0.007
(0.00027)
0.008
(0.0003) 0.008
(0.0003)
mm
(inches)
0.243
(0.0096)
DocID025014 Rev 3 7/9
ESDARF02-1BU2CK Recommendation on PCB assembly
9
3.3 Placement
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering
3. Standard tolerance of ±0.05 mm is recommended.
4. 1.0 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
3.4 PCB design preference
1. To control the solder paste amount, the closed via is recommended instead of open
vias.
2. The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
3.5 Reflow profile
Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Note: Minimize air convection currents in the reflow oven to avoid component movement.
Maximum soldering profile corresp onds to the latest IPC/JEDEC J-STD-020.
250
0
50
100
150
200
240210180150120906030 300
270
-6°C/s
240-245 °C
2 - 3 °C/s
Temperature (°C) -2 °C/s
-3 °C/s
Time (s)
0.9 °C/s
60 sec
(90 max)
Ordering information ESDARF02-1BU2CK
8/9 DocID025014 Rev 3
4 Ordering information
Figure 15. Ordering information scheme
5 Revision history
Table 4. Ordering information
Order code Marking Weight Base qty. Delivery mode
ESDARF02-1BU2CK Z3(1)
1. The marking can be rotated by 180° to differentiate assembly location
0.124 mg 15000 Tape and reel
ESDA RF 02 - 1B U2 CK
ESDA array
Application
RF antenna
Number of lines
Direction
B = Bidirectional
Package
U2 = ST0201
C = Low clamping ESD protection
Table 5. Document revision history
Date Revision Changes
25-Feb-2015 1Initial release.
02-Jun-2016 2 Updated Features.
Updated Table 2 and reformatted to current standard.
23-Jan-2017 3 Updated Table 3.
DocID025014 Rev 3 9/9
ESDARF02-1BU2CK
9
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