19-4325; Rev 0; 7/91 Quad, High-Side MOSFET Drivers General Description The MAX620/MAX621 incorporate four MOSFET drivers and a charge-pump high-side power supply to power high-side switching and control circuits. The charge pump delivers a regulated output voltage 11V greater than Vcc to the drivers, which then translate a TTL/CMOS input signal to a noninverted output that swings from ground to the high-side voltage. The out- puts drive N-channel FETs in high-side or low-side switching applications, including a wide range of line- and battery-powered applications. The MAX620/MAX621 are microprocessor compatible and feature undervoltage lockout capability. This lockout feature inhibits the FET driver outputs until the high-side voltage reaches the proper level, as indicated by a Power-Ready output. The MAX620 requires three inexpensive charge-pump capacitors. The MAX621 has internal capacitorsno external components are needed. Applications Portable Computer Battery Load Management High-Side Power, N-Channel MOSFET Switching Low-Side Switching from Low Supply Voltages Quad-Latching Level Translators H-Bridge Motor Drivers MA AAI Features # Wide Operating Voltage Range @ Minimum Component Count @ Output Voltage Regulated to Vcc Plus 11V (Typ) @ Low Quiescent Current 70,A (Typ) @ Undervoltage Lockout @ Power-Ready Output @ Internal Quad Latch Ordering Information PART TEMP. RANGE PIN-PACKAGE | MAX620CPN OC to +70C 18 Plastic OIP MAX620CWN OC to +70C 18 Wide SO MAX620C/D OC to 470C Dice* MAX620EPN -40C to +85C 18 Plastic DIP MAX620EWN -40C to +85C 18 Wide SO MAX620MJN 55C 10 +125C 18 CERDIP MAX621CPN OC to +70C 18 Plastic DIP MAX621EPN -40C to +85C 18Plastic DIP Contact factory for dice specifications. Typical Operating Circuit Stepper Motor Drivers +5V - = ria Pin Configurations tie Sh je Te Veo V+ sy i= C+ C2+ Pe wrven Shale |i om Le cr ce ie > TOLOAD ours 7 ours [i] Lift OUTS (2] ouT3 [2] > 15 J INt OUT! #18 T IN3 [3] IN3 [3 a 7 TOLOAD 4 El nanan NS CE] eaccian 16 f IN2 OUT2 917 : TT ce LS] CE [8] MAX621 o- m TOLOAD PR [6] pp [8] Lit GNO [7] eno FF] 3 INs ours f2 T ve GI 2s - o-oo TO.LOAD Cas fa] ci- [2] ct 4] ina oura | TT DIP/SO DIP Sia 6 m4 CE GND PR |- 7 NOTE: MAX621 CONTAINS C1, C2 = AND C3 INTERNALLY SAA XI svi Maxim integrated Products 4-19 JWIA AI is aregistered trademark of Maxim Integrated Products LEOXVW/OCOXUNMAX620/MAX621 Quad, High-Side MOSFET Drivers ABSOLUTE MAXIMUM RATINGS 640mWw 762mW 0C to +70C A oc 17V Continuous Power Dissipation (Ta = +70C) V4 toGND 000 cet 30V Plastic DIP (derate 8mW/C above + 70C) Inputs and Driver Outputs ........ (GND-0.3V) to (V+ + 0.3V) Wide SO (derate 9.52mW/C above +70C)} PR Output ......0...0..00008. (GND-0.3V) to (Vcc + 0.3V) Operating Temperature Ranges: Continuous Driver Output Current .....0..00..000.... 25mA MAX6G2 _C en V+ Output Current (MAX620 Only) .................. 25mA MAX62 _E__ ow. eee Storage Temperature Range Lead Temperature (Soldering, 10sec) ... -40C to +85C -65C to +160C +300C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage ta the device. These are stress ratings only, and functional operation o: absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vcc = +5V, Ta = TmIN to TMax, unless otherwise noted.) the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS Supply Voltage Voc 45 16.5 Vv louT = 0, Vcc = 4.5V C1 =C2 = 0.047pF, C3 = pF 45 155 17.5 lout = 9, Vcc = 16.5V 26.5 27.56 29.5 High-Side Voltage (Note 1) v+ Lt = C2 = O.01pF. C3 = IHF (Note 2) v touT = 250uA. Voc = 5V, C1 =C2 = 0.047pF, C3 = 1pF 18 16 18 louT = 500A, Voc = 16.5V, C1 =C2 = 0.01pF, C3 = pF (Note 2) 25 275 29.5 Power-Ready Threshold PRT louT = 0 (Note 3) (Note 4) 12.0 13.5 145 Vv Power-Ready Output High PRoH ISOURCE = 100HA (Note 4) 3.8 47 5.0 Vv Power-Ready Output Low PRot ISINK = ImA (Note 4) 0.1 0.4 Vv Switching Frequency fo lout = 0, Ta = +25C 70 kHz Vec = 5V, MAX620 | C1 = C2 = 0.047pF, C3 = IpF, Ta = +25C, lout = 0 70-500 Quiescent Supply Current la MAX621_| Vcc = 5V, Ta = +25C, lout = 0 HA Vcc = 16.5V, MAX620 | C1=C2 = 0.01pF, C3 = 1pF, Ta = +25C, lout = 0 (Note 5) sO 350 MAX621 | Voc = 16.5V, Ta = +25C, lout = 0 4-20 MAKI sviQuad, High-Side MOSFET Drivers ELECTRICAL CHARACTERISTICS (continued) (Vcc = +5V, Ta = TMIN to TMAX, unless otherwise noted.) PARAMETER [ SYMBOL | CONDITIONS |_MIN TYP MAX | UNITS HIGH-SIDE DRIVERS _ Input Threshold Low VIL 0.8 v | Input Threshold High WH 24 Vv Input Bias Current IB OV < Vin < 5V -100 100 nA Chip Enable Threshold Low CELo 08 Vv _ Chip Enable Threshold High CEH! 2.4 Vv Minimum CE Pulse Duration TCE _ 100 50 ns Pull-Down Current ICE 10 BHA Data-Hold Time ToOH -10 10 ns Data Set-Up Time Tsu 50 100 ns Data-Delay Time Too Vce = OV, Cy, = 12pF 150 ns Driver Output Rise Time TR CL = 1000pF 1.7 us Driver Output Fall Time TF CL = 1000pF 2.5 us Note 1: measured at an unloaded output. Capacitor values listed in the test concitions apply to the MAX620 only. Note 2: Note 3: Note 4: Note 5: above +13V, C1 and C2 must not exceed 0.01pF. For Vcc > +13V, on the MAX620 only, use C1 = C2 = 0.01pF, C3 = 1pF. Paower-Ready Threshold is the voltage with respect to GND at V+ when PR switches high (PRoH = Vcc). For the MAX621, the Power-Ready levels are tested at wafer sort only. The MAX620 is tested for quiescent current at +16.5V using C1 = C2 = 0.047pF to minimize test time. In normal operation MAX620 QUIESCENT SUPPLY CURRENT vs. C3 CAPACITANCE MAX621 MAXIMUM SWITCHING RATE vs. Vcc SYNCHRONOUSLY DRIVING ALL FOUR INPUTS 300 | | 50 Y Tee | Ast =z Vee = +5V = | S250 ei Co oar = Coan = tcompr | = =C2= pet = b+ j = Tyee = s1V = 40 |(EACH DRIVER) = 909 C1=C2=0.01pF = f sS 2 30 | 2 y = 150 / Lata Noes ev 5 / 1 a C1=C2 =0047pF = : zB / iY) Ve AR 2 4 & 10 }|A2t oat 2 NOTE: THE MAXIMUM SWITCH- oa ae A > 3 Ta=+25C = ING RATE OCCURS JUST BELOW gg lour=0 = 10 THE POINT WHERE DRIVER 4 3 ALL INPUTS = 0 = / OUTPUT AND V+ LOADING 0 ALL DRIVERS UNLOADED Q PULLS V+ TOPRT (Vcc + 8.5) 12 3 4 5 6 7 @ 9 10 305 7 9 Tt 13 15 Voc {) sVIsALAISVI C3 CAPACITANCE (uF) V7 MAXIMUM SWITCHING RATE (kHz) Ry High-Side Voltage (V+) is available only on the MAX620 and is measured with respect to GND. V+ on the MAX621 is Typical Operating Characteristics MAX620 MAXIMUM SWITCHING RATE vs. Vcc SYNCHRONOUSLY DRIVING ALL FOUR INPUTS 90 Tye 25C CLoao = 1500pF 40 LEACH DRIVER) 4 ws Se = C2 = 0.047 uF C3 = IF Ate =(2=002yF C3=1y1F 20 L 30 aT LACE 02 C3 = tl I =001yF F T F T NOTE: THE MAXIMUM SWITCH- ING RATE OCCURS JUST BELOW THE POINT WHERE DRIVER QUTPUT AND V+ LOADING PULLS V+ TO PRT (Vcc + 8.5V} 3 5 7 9 1 13 15 17 Voc () 4-21 LEOXVW/0OZ9OXVNMAX620/MAX621 QUIESCENT SUPPLY CURRENT (A) Quad, High-Side MOSFET Drivers MAXIMUM SWITCHING RATE (kHz) MAXIMUM lout (mA) 4-22 MAX620 QUIESCENT SUPPLY CURRENT vs. C3 CAPACITOR VALUE 400 | c+ octuF MAX620 V+ vs. louT Vec = +12V C3 = 10uF Vcc = +5V, lour = 0, 350 Ta= 425C, C1=C2=C* Ta= 425C 300 Cr = 0.022uF C* = 0033uF 250 s 200 = x 150 = OApF C* =0.068uF 400 a C* = 0.047yF 50 v 7234 5 6 7 8 9 10 01 2345 67 8 910 C3 CAPACITOR VALUE (uF) lout (mA) MAXIMUM SWITCHING RATE MAX620/MAX621 DRIVER RISE vs. CLoapD SINGLE DRIVER AND FALL TIME vs. 400 ; TA= 25C, vec=45V | | | ETT 45 |. Veo =+5V 350 NOTE. THE MAXIMUM SWITCH- Ta= 425C ING RATE OCCURS JUST _ 40 300 BELOW THE POINT WHERE B 3. ORIVER OUTPUT LOADING = 3 FALL 250 PULLS V+ TO PRT (Vcc + 8.5V) 2 30 IN ii Porpaiid = RISE TIME 200 I MAX620. 4 2 5 AQ [cr =62 = 0047p, 2 150 C3 = (uF, V+ UNLOADED 0 20 NON @ 15 100 = 14 MAX621 44 BN) 50 PS 08 L| oh 0 tL 0 04 1 10 01 1 10 CLOAD (nF) Coan (nF) Vcc TO POWER-READY MAX620 MAXIMUM IouT vs. C1 = C2 HIGH DELAY vs. Vcc 10 Tt Veco = +5V =0 0.9 Ta=+25C | A= 425C 08 C3=ipF J : ALL DRIVER _ 7 \NPUTS = OV - @ 06 05 z L m4 : g 03 + 2 02. NOTE. MAXIMUM lour IS THE L040 _| | CURRENT AT THE POINT WHERE V+ 0.1 [BEGINS TOLOSEREGULATION = 4 0 l oo 001 01 C1 = C2 CAPACITANCE (uF) Ve(Y} DRIVER OUTPUT RIPPLE {V) QUIESCENT SUPPLY CURRENT {mA} Typical Operating Characteristics (continued) MAX620 V+ vs. louT 7 Voc = +5V C3 = 10uF 16 \ Ta=+25C 4 8 N ci=c2-\ hk o0a7F TN tab Oe Doon mM 13 tt S Ke \\ +t 12 _ \ 0 02 04 0608 1012141618 20 lout (mA) MAX621 DRIVER OUTPUT 15 RIPPLE vs. ALL DRIVER 1.25 1 0.75 05 0.25 0 3.5 7 9 It 13 15 17 Voc (V) MAX621 QUIESCENT SUPPLY CURRENT vs. Vcc 12 ALL =0V 10 DRIVER OUTPUTS UNLOADED Ta= 425C 08 0.6 04 02 0 3.5 7 9 1 130415 = Veo (V) SULA KISVIMAX620 QUIESCENT SUPPLY CURRENT vs. Vcc 21nF E 2 425C a = 3 > z a 2 ra] = (2=0.01yF B tt s = C2=0.047pF 3 5 7 9 Tt 13 #15 17 Vec (V) DRIVER OUTPUT SWITCHING WAVEFORM Vee = +12V = 425C CLOAD = 5V/div ov 5us/div SAA AISVI QUIESCENT SUUPLY CURRENT (4A) MAX620/621 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE 120 iour = 0 110 400 90 =+5V 80 Voc =+16.5V 70 60 50 40 -78 -80 -25 0 2 50 75 100 125 TEMPERATURE (C) DRIVER OUTPUT SWITCHING WAVEFORM Voc = 45V Ta= +25C Cloao = 1500pF SV/div ov 5us/div MAXIMUM SWITCHING RATE (kHz) Quad, High-Side MOSFET Drivers Typical Operating Characteristics (continued) MAX620 MAXIMUM SWITCHING RATE vs. ADDITIONAL V+ LOAD CURRENT (IOUT) | 1 Se Croan = 1500pF Vee = +15V (EACH DRIVER) 30 | C1 = C2=0.01pF LY | t NT rain Cee osu Ni = C2 = 0.0471 20 C3 = IF ' ih L_vee = +15V IN 0 oie =0oa7uF | [AIT NY C3 = (pF , | Ju 10 100 +000 +0000 {out (WA) NOTE: THE MAXIMUM SWITCHING RATE OCCURS JUST BELOW THE POINT WHERE DRIVER OUTPUT AND V+ LOADING PULLS V+ T0 PRT (VCC + 8 5V) 7 z 2 DRIVER OUTPUT SWITCHING WAVEFORM Voc = +15V Ta= 425C Cioao = 1500pF 5V/div av Sps/div 4-23 LZ9XVW/0OC9OXVNMAX620/MAX621 Quad, High-Side MOSFET Drivers Pin Description PIN NAME FUNCTION MAX620 | MAX621 1 1 OUT4 Driver Output 4 2 2 OUT3 Driver Output 3 3 3 IN3 TTLICMOS Compatible Input to Driver 3. Connect to GND if unused. 4 4 IN4 TTLICMOS Compatible Input to Driver 4. Connect to GND if unused. __ Chip Enable. Logic high inhibits input data. Logic low transfers input data to the quad latch and 5 5 CE driver outputs. CE pulse must be at Jeast 100ns. Connect to GND for direct data transfer to driver outputs. 6 6 PR Power-Ready Output is a logic high equal to Vcc when V+ 2 (Vcc plus 8.5V). 7 7 GND Ground V+ High-side voltage out. Equal to approximately Voc plus 11V. 8 C2+ Internally connected to secondary charge-pump capacitor. Make no connection to this pin. 9 C24 Positive terminal to secondary charge-pump capacitor. Connect to 0.047uF capacitor. For Vcc > 13V, connect to 0.0 1pF. 9 C1- Internallly connected to primary charge-pump capacitor. Make no connection to this pin. 10 C1. Negative terminal to primary charge-pump capacitor. Connect to 0.047uF capacitor, For Voc > 13V, connect to 0.01pF. 10-12 Ci+ Internally connected to primary charge-pump capacitor. Make no connection to these pins. 11 Ct+ Positive terminal to primary charge-pump capacitor. Connect to 0.047uF capacitor. For Vcc > 13V, connect to 0.01pF 12 13 Voc Supply Voltage. Connect to positive supply. 13 C2- Negative terminal to secondary charge-pump capacitor. Connect to 0.047uF capacitor. For Vcc > 13V, connect to 0.01pF. 14 14 LC. Internal Connection. Make no connection to this pin 15 15 IN4 TTLICMOS Compatible Input to Driver 1. Connect to GND if unused. 16 16 IN2 TTLICMOS Compatible Input to Driver 2. Connect to GND if unused. 17 17 OUT2 Driver Output 2 18 18 OUT1 Driver Output 1 4-24 MMUAXI VIQuad, High-Side MOSFET Drivers Detailed Description TSL/GMOS INPUT DRIVER INPUT LEVEL TRANSLATOR QUAD LATCH Figure 1 shows the MAX620/MAX621 functional diagram. TueMes Aregulated multi-stage charge pump supplies four MOS- INI ueus So FET drivers with Vcc plus 11V for driving external MOS- wo rune S0 | FETS (Figure 2). The logic inputs to the four drivers are ing mw TL/CMOS > ouTt stored in a quad latch. Data is latched by pulling CE high. An undervoltage lockout feature prevents the driver out- puts from going high until V+ reaches the power-ready threshold (PRT) voltage (Vcc plus 8.5V) and Vcc is greater than +3V. OUT2 yyy OUTS : So) N : : 8 The Dual Charge Purnp 14 wm TL/CMOS, The high-side voltage of approximately 11V above Vcc > OuT4 is generated by a multi-stage charge pump (Figure 2). QUADLATCH] $ Although the charge pump is capable of multiplying Vcc INHIBIT _ > by up to four times, the output is regulated to Vcc plus a= , TTCMOS CE LEVEL. PR 11V by an internal feedback circuit. The charge pump ce UNDERVOLTAGE typicaily operates at 70kHz, but regulates by pulse-skip- CHARGE PUMPS ping. When V+ exceeds Vcc plus 11V, the charge pump AND Ve shuts off. As V+ falls below Vcc plus 11V, the charge UNDER VOLTAGE 03/4 cmarea0 pump turns on. Goo Tt The MOSFET Drivers C1 c2 0 The four MOSFET drivers level shift TTL/CMOS input signals to output levels that switch between ground and Figure 1. MAX620/MAX621 Functional Diagram Vcc plus 11V. These outputs can drive N-channel power MOSFETs in either high-side or low-side switching ap- ft + - Vout $8 WW av x Ss? POWER-READY cs k RC OSCILLATOR COMPARATOR T Vint == C2 < + 6 CONTROL LOGIC $4 OVERVOLTAGE COMPARATOR Voc Ciz= $2 PR s! (a PR DRIVER Y GND rn TWO-STAGE CHARGE PUMP Figure 2. MAX620/MAX621 Charge Pump Block Diagram MAXI VI 4-25MAX620/MAX621 Quad, High-Side MOSFET Drivers plications (a bridge arrangement would contain two high- side and two low-side N-channel MOSFET switches- see Figure 4). Data Input Latch The driver outputs are separated from the data inputs by a quad latch. When CE is pulled low, the latch becomes transparent and data transfers directly to the outputs. When CE goes high, the latch enters hold mode and new input data is not transferred to the driver outputs. Input data must be valid typically 100ns before the rising edge of CE, and held for 10ns (max over temp). The minimum CE pulse width is 100ns (Figure 3). If latched operation is not required, connect CE to GND. NE a tsu (oH 1 J INPUT too 4 (IN1-IN4) ~ DRIVER QUTPUTS DATA Figure 3. Digital Interface Timing Diagram Undervoitage Latch Inhibit If Voc falis below +3V due to a power failure or while powering down, or V+ falls below Vcc plus 8.5V, the quad latch immediately resets, forcing the driver outputs low. The quad latch remains reset until Vcc rises above +3V with the high-side voltage present. This prevents the latch fram being corrupted with erroneous data in a momentary power failure by ensuring that it will be reset. Undervoitage Detector The MAX620/MAX621 each contain an undervoltage detector, which forces all driver outputs low when the high-side voltage (V+) is less than the PRT or when Vcc is less than +3V. This ensures that the external N-channel MOSFET power transistors have sufficient gate drive to operate without dissipating excessive power. On power- up, the quad latch remains reset until the charge pump boosts the high-side voltage to the PRT. As soon as V+ reaches the PRT, the undervoltage lockout disables, the quad latch is enabled, and Power Ready (PR) goes high. 4-26 The undervoltage lockout feature also forces the driver outputs low if V+ is pulled below PRT, e.g., if the driver output(s) or V+ are overloaded. Power-Ready Output The MAX620/MAX621's PR output is a direct extension of the undervoltage lockout feature. When power is applied, PR remains a logic low until V+ reaches the PRT and Vcc exceeds +3V The PR output high level is Vcc Capacitor Selection for the MAX620 Capacitor type is not critical for the MAX620. However, if operation with Vcc exceeding +13V is expected, C1 and C2 must be no greater than 0.01pF. Larger value capacitors, with Vcc above +13V, dissipate excessive energy in the internal switches during charge-pump cycles. Sourcing Current From V+ (MAX620 Only) Asmalt amount of current may be sourced from V+ (pin 8) to drive other circuitry. The amount of current is a function of Vcc, the gate capacitance of all MOSFETs being driven, and the driver switching rate (MAX620 Maximum Switching Rate vs. Additional V+ Load Current, Typical Operating Characteristics). The MAX620 V+ output ig not internally short-circuit protected. In applications where V+ is susceptible to short circuiting, external output short-circuit protection must be provided Accomplish this by connecting a resistor between V+ and the load to limit the V+ current to less than 25mA. The resistor value is determined by the following formula: Vcc > a. RCL? bem Application Information Data Input Transition Time The MAX620/MAX621 are microprocessor compatible and easy to interface. However, the driver input voltage must not remain between ViL and VIH for more than 500ns. In clocked data-bus systems, this is most easily accomplished by setting data on the driver input lines before clocking CE low. However, most CMOS and TTL gates meet the 500ns transition speed requirement. Connect unused driver inputs to GND. Maximum Driver Switching Rate The maximum driver switching rate occurs when loading causes V+ to fall to the PRT (Vcc plus 8 5V) and the driver outputs go low. It is a function of the total gate capacitance of all MOSFETs being driven and the maxi- mum available charge-pump output current at a given SVIA KI sviQuad, High-Side MOSFET Drivers supply voltage. For example, for Voc = +5V with no external load on V+, the maximum switching rate while driving four 1500pF loads is 15kHz for the MAX620 (C1 = C2 = 0.047pF) and 14kHz for the MAX621 (Maxi- mum Switching Rate vs. Vcc," Typical Operating Characteristics). Typical Application Circuits H-Bridge Motor Driver Figure 4 shows a MAX620 driving an H-bridge switch that controls the direction of a +5V DC motor. By toggling between the FORWARD and REVERSE inputs as shown, each MOSFET driver-output pair turns on its associated MOSFET pair, which passes current through the motor, causing rotation in the desired direction. In order to prevent all four MOSFETs from switching on at once, the FORWARD/REVERSE inputs should be updated before clocking CE low. Of course, FORWARD and REVERSE must not be asserted simultaneously. Do not use a supply voltage that will cause the gate drive to exceed the absolute maximum gate-to-source voltage of the low-side switch. Stepper Motor Driver A MAX620, clock source, pulse control network, and translator logic form a compiete stepper motor driver (Figure 5). TTL/CMOS signals from the logic network are translated to high-side levels that drive four N-channel power MOSFETs, supplying current to each of four step- per motor phases. Diodes provide a discharge current path for the stepper motor windings. Logic-Controiled, +5V Regulated Power Distribution A MAX620, LM10 reference and op-amp combination, and an |IRFZ40 N-channel MOSFET comprise an ultra-low dropout +5V regulator that supplies power to four IRFZ40 high-side switches (Figure 6) When the power switch, Sp, is closed, V+ quickly pumps up to Vcc plus 11V. PR remains low and holds the output of the +5V regulator near zero until V+ has reached the PRT, (Vcc plus 8.5V--4ms typ). At the same time, the undervoltage lockout feature of the MAX620 forces the driver outputs low until the PRT is reached. Capacitor C4 suppresses load-switching transients. Its size depends on the largest load being switched. With C4 = 1000pF, the peak transient for a 1A switched load is less than 150mvV. The circuit provides a single continuous +5V output and four switched +5V supply lines. The regulator is capable of supplying several amps with a typical dropout voltage of 28mV at 1A (Q1=IRFZ40). peg 0 spe 142 tT C3 CERAMIC. > a The 7 Veo y, PB * mu Ctt C24. 9 ct Lt MAAXIAA L 2 0.047 pF MAX620 [2]. co. fF _ 1s | Sour fia 7 FORWARD pm 16 Jing [\. oure fa7 TOT INe ee a 3hins | yee 2 : | REVERSE -@ Lo (AP ING | OS 0UTA a | sl : - fe | 7 | we | J IRFZ40 . IRF240 a +0V zee | Figure 4. H-Bridge DC Motor Controller MWA AIL SV 4-27 LZ9XVW/0C9OXVNMAX620/MAX621 Quad, High-Side MOSFET Drivers POWER SUPPLY CLOCK SOURCE Ci Ly AXIAA C1 0.04? uF T.19] MAX620 8 c2 CI- PULSE CONTROL | 16 BIN2 OUuT2| \ > oural N3 na_| Ours 1SBING | OuTt CONTROL SIGNALS Figure 5. Four-Phase Stepper Motor Drive System 4-28 MIA XKIsvilQuad, High-Side MOSFET Drivers sce, _[+ NICAD STACK ~~ _ - ON/OFF a SP _, [ IRFzaO C3 > we +5V tur = + 4 + . . 1000,F jr 4, 1 4 ce = cay Pa a 2 MAAXLAA : c2 0.047uF MAX620 0047uF Fol oops J 24 vee pa} > o- == O1pF INg14 TL -| iRF240 SW pe 150 int ours | 12 ad e OW? pe 16] ine oure | 17 | inFz40 +5V SW8 pe 3h ins outa] 2 7; dy IRF 240 cw w 4] ins outa 1 - +5V ___ si CHIPENABLE M1 CE gun L 7 + IRFZ40 +5V Figure 6. Logic-Controlled, +5V Regulated Power Distribution System MAAKIsvV1 : g 2 E : mi,Quad, High-Side MOSFET Drivers Chip Topography IN4 CE PR GND MAX620/MAX621 0.084" _ > (2.134 mm} NOTE: Connect substrate to V+. MAX620 transistor count: 303 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Product. No circuit patent licenses are implied. Maxim reserves the right to change the circurtry and specificatians without notice at any time. 4-30 IJUA KI sVI