A1133APS3B - Advanced Micro Devices

Preliminary Information

AMD Athlon

Processor Model 4

Data Sheet

Publication # 23792 Rev: I

Issue Date: June 2001

Preliminary Information

Trademarks

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Advanced Micro Devices, Inc.

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AMD reserves the right to discontinue or make changes to its products at any

Contents iii
23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet
Preliminary Information
Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 AMD Athlon™ Processor Model 4 Microarchitecture 
Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Interface Signals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4 AMD Athlo n  S ys t e m Bu s  Sign a ls   . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Management   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Power Management States  . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Wo rking  St a te  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop G rant Sta t e s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Probe Sta t e.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1
2 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Connect State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3 Clock  C on t r o l  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Thermal Design  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CPUID Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1 Con v e n ti on s   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Inte rf a c e  Sig n a l  Gr o u p in g s   . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3
3 Voltage Iden tification (VID[4: 0 ])  . . . . . . . . . . . . . . . . . . . . . .24
4 Freq u e n c y  Id e n tifica tion  (F I D [ 3 :0 ]) . . . . . . . . . . . . . . . . . . . . 24
5 VCCA  AC  a n d  DC  Ch arac t e ri stics   . . . . . . . . . . . . . . . . . . . . . 25
6 Decoupling   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7 Operating  R a n g e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
8 Abs o lu t e R a t in gs   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 6
9 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . .27
10 SYSCLK and SYSCLK# AC and DC Characteristics  . . . . . .28
11 AMD Athlon System Bus AC and DC Characteristics   . . . . .30
12 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32
13 API C  Pi n s A C and DC  C h arac te r istic s .  . . . . . . . . . . . . . . . . .34

iv Contents
AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001
Preliminary Information
8 Signal and Power-Up Requirements  . . . . . . . . . . . . . . . . . . . . 35
8.1 Powe r -U p  R e q u ir e m e n ts   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 5
Sign a l S e q uen c e  an d  Timing De s cr ip t io n. . . . . . . . . . . . . . . .35
Clock Mult ip lier S e le c ti o n  (F ID [ 3 :0 ] ) .  . . . . . . . . . . . . . . . . . .37
Seri a l Initia l i z a tion Packet (SIP) Proto co l . . . . . . . . . . . . . . .38
8.2 Processor Warm Reset Requirements  . . . . . . . . . . . . . . . . . . 38
The AMD Athlon Processor Model 4 and Northbridge 
Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9 Mechanical Data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1 Intr od u c t io n    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.2 Die Lo a d in g  .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.3 Pinou t Diag ra m  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
9.4 Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . . 42
10 Pin Descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 Pin Dia g ram an d  P in  N a me  A b brev ia t io n s   . . . . . . . . . . . . . .45
10.2 Pin List   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3 Det ai le d  P in  D e sc r i p t io n s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
AMD Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AMD A t h lo n  S ys t e m  Bus  P in s  . . . . . . . . . . . . . . . . . . . . . . . . .62
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . . . . 62
CLKF WDRS T  P in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CLKI N, RST C L K (S YS C L K) Pin s. . . . . . . . . . . . . . . . . . . . . . . 62
CONNEC T P in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2
COREFB and COREFB# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 63
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DBRDY  an d  DB R E Q# Pin s . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
FID [3:0] P in s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
FLUS H #  P in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IGNN E #  P in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
K7CLKOUT and K7CLK OUT# Pins. . . . . . . . . . . . . . . . . . . . .65
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
NC Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
NMI Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PGA O r ie n t ation  Pi n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PLL Bypass and Test Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . . . . 66
Scan Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SCHE C K[7: 0] #  P in  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 6
SMI# Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
STPC L K #  Pi n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Contents v

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

SYSCLK an d SYSC LK # P in s . . . . . . . . . . . . . . . . . . . . . . . . . .66

SYSVREFMODE Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

VID[4 :0] Pi n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

VREF S YS Pi n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

ZN, VCC_Z, ZP, and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . . . . 68

11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Stan d a r d AMD A th l on Pr o ce s s or Mo d e l 4 P rod uc t s . . . . . . . . . . . . .71

Appendix A Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 73

Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Abbrevi a tion s a nd Acron y ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

vi Contents

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

List of Figures vii
23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet
Preliminary Information
List of Figures
Figure 1. Typical AMD Athlon™ Processor Model 4 System 
Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. AMD Athlon Processor Model 4 Power Management States. . .9
Figu r e  4. Exa mp l e  S y st e m  B u s D is c o n nect  Se q u e n c e  . . . . . . . . . . . . . . .13
Figure 5. Exiting Stop Grant Stat e/Bus Reconnect Sequence . . . . . . . . . 14
Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Processor Connect State Diagram  . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . .28
Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 10. Signal Relationshi p  Requ irements During Power-Up 
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. PGA Package, Top, Side, and Bottom Views. . . . . . . . . . . . . . . 41
Figure 12. Socket A with Outline of Socket and Heatsink Tab. . . . . . . . .42
Figure 13. Socket A Heatsink Tab Side View . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. AMD Athlon Processor Model 4 Pin Diagram—
Topside View  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. AMD Athlon Processor Model 4 Pin Diagram—
Bott o mside  V ie w. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 16. PGA OPN Example for the AMD Athlon Processor 
Model 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

viii List of Figures

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

List of Tables ix

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

List of Tables

Table 1. Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Tabl e 2. In terf a c e Sig n a l Grou p i n g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3

Tabl e 3. VID[4 :0] DC C h arac te r istics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Tabl e 4. F ID[3:0] DC Ch a r a c te rist i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Tabl e 5. V C C A AC a n d DC C h a ra c t e ristic s . . . . . . . . . . . . . . . . . . . . . . . 25

Tabl e 6. O p e ratin g R a n g e s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5

Table 7. Abs o lu t e R a t in g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 8. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . .27

Tabl e 9. SYSC L K a n d SY S C L K# DC C h a ra cter istic s . . . . . . . . . . . . . . .28

Tabl e 10 . S YSCLK a n d SY S C L K# AC Chara c t er istic s . . . . . . . . . . . . . . .29

Table 11. AMD Athlon™ System Bus DC Characteristics . . . . . . . . . . . . 30

Table 12 . A MD Ath lo n S ys t e m Bus AC Ch a r a c te r istic s . . . . . . . . . . . . . .31

Table 13. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 32

Tabl e 14 . AP IC Pi n s A C and D C C h ar a cter istic s. . . . . . . . . . . . . . . . . . . .34

Table 15 . C P GA Me c h a n ic a l L o a d in g 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 16. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Tabl e 17 . C r os s -R e fer en c e by P in L o ca tion . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 18. FID [3 :0] C lo c k Mu ltipli e r E n c od i n g s . . . . . . . . . . . . . . . . . . . . .64

Table 19. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 68

Tabl e 20 . Ab b revi a tion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5

Table 21. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

xList of Tables

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Revision History xi
23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet
Preliminary Information
Revision History
Date Rev Description
June 2001 I
This revision is for the 1400 M Hz  AMD Athlon™ Processor Model 4 and covers changes since 
March 2001 that include the following:
■In Chapter 4, in cluded APIC information  in “Halt St ate” on page 10 and  “Stop Gr ant  States ”
on page 10
■In Chapter 5, updated Table 1, “Thermal Design Power,” on page 2 0
■In Chapter 7, updated Table 8, “VCC_C ORE V oltage and Current,”  on page 27
■In Chapter 10, revised description of “FERR Pin” on page 63 and in Table 17 on page 54
March 2001 H
This revision is for the 1333 MHz speed grade and covers changes since October 2000.
■In Chapter 1, revised descri ption on the AMD Athlon™ syst em bus.
■In Chapter 4, revised Figure 3, "AMD Athlon™ Processor Model 4 Power Management
States‚" on page 9
■In Chapter 5, updated Table 1, “Thermal Design Power,” on page 20
■In Chapter 7, updated IoL specification to 12 mA in Table 14, “APIC Pins AC and DC
Characteristics,” on page 34. Updated Table 8, “ VCC_COR E Voltage and Current,” on page
27, revised Table 10, “SYSCLK and SYSCLK#  AC Characteristics,” on page 29, and revised
Note 1 in Table 11, “AMD Athlon™ S ystem Bus DC Char acteristics,” on page 3 0.
■In Chapter 8, revised description of “Serial Initialization P acket (SIP) Protocol” on page 3 8
■In Chapter 10, revised Table 16, “Pin Name Abbreviations,” on page 48, added description
of “APIC Pins, PICCLK, PICD[1:0]#” on page 62, and revised description of “AMD Pin” on
page 62
October 2000 G
Added information about the 133 MHz front side bus (FS B ) as follows:
■“AMD Athlon™ Processor Mo del 4 Microarchitectur e Summary” on page 2
■Table 1, “Thermal Design Power,” on page 20
■Table 8, “VCC_CORE V olt age and Current,” on  page 27
■Table 10, “SYSCLK and SYSCLK# AC Char acteristics,” on page 29
■Chapter 11, “Ordering Information” on page 71
October 2000 F Revised VID[4:0] information in Table 3 on page 24 and “VID[4:0] Pins” on page 67

xii Revision History

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

October 2000 E

Added Information about the 1.2 GHz AMD Athlon™ Processor Model 4 as follows:

■Chapter 1, “Overview” on page 3

■Table 1, “Thermal Design P ower,” on page 21

■Table 6, “Oper ating Ranges,” on page 2 5

■Table 8, “VC C_C ORE Voltage and Current,” on page 2 7

■Revised OPN to include the new 1200 MHz speed grade in Chapter 10, “Ordering

Information” on page 71

■Revised Maximum and Typical Thermal Power numbers in Table 1, “Thermal Design

Power,” on page 20.

■Added note to Table 6 for new Die temper ature.

■Revised table note 2 as “The Sleep Voltage is used for the S1 sleep state and as the Power-

up voltage before PWROK and PWRGD are asserted." Table 6, “Operating Ranges,” on page

25.

■Updated “Motherboard PGA Design Guide, order# 90009” with new document name of

“Socket A Motherboard Design Guide, order# 243 63” throughout book.

■Added SAI#[0] pin in location AJ29 to Figure 15, "AMD Athlon™ Processor Model 4 Pin

Diagram—Topside View‚" on page 46.

Added the AMD Pin (AH6) to Table 16, “Pin Name Abbreviations,” on page 47, Table 17,

“Socket A Pin Cross-Ref erence by Pin Location, ” on page 55Revised all no connect (NC) pins on

the pin grid array (PGA) as follows:

●Figure 15, "AMD Athlon™ Process or Model 4 Pin Diagram—Topside View‚" on page 46.

●Table 15, “Pin Name Abbreviations,” on page 4 7.

●Table 16, “SocketA Pin Cross-Refer ence by Pin L ocation,” on page 55.

■Revised KL CK OUT/K CLKOUT# verbiage in C hapter , “K7 CLKOU T a nd K7 CLKOUT # P in s” on

page 65.

August 2000 D

Added information about the 1.1-GHz AMD Athlon™ Processor Model 4 as follows:

■Chapter 1, “Overview” on page 3

■Table 1, “Thermal Design P ower,” on page 21

■Table 6, “Oper ating Ranges,” on page 2 5

■Table 8, “VC C_C ORE Voltage and Current,” on page 2 7

■Revised and reorganized the A C and DC characteristics for SYSCLK and SYSCLK#. See Table

10, “SYSCLK and SYSCLK# AC Characteristics,” on page 28, and Table 9, “SYSCLK and

SYSCLK# DC Characteristics,” on page 27.

Date Rev Description

Revision History xiii

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

August 2000 C

Added Table 1, “Thermal Design Power,” on page 21 to Chapter 5, “Thermal Design”.

Revised Chapter 6, “Electrical Data” on page 23 as follows:

■Added JTAG, AP IC, Te st, Miscellaneous rows to Table 2, “AMD Athlon™ Processor Model 4

Interface Signal Groupings,” on page 2 3. Reorganized signals into their correct categories.

■Added “Conventions” on page 23.

■Revised information in Table 3, “VID[4:0] DC Characteristics,” on page 2 4.

■Revised information in Table 4, “FID[3:0] DC Characteristics,” on page 24.

■Added and revised information in Table 6, “SYSCLK/SYSCLK# AC and DC Characteristics,”

on page 23.

■Revised IVCCA information in Table 5, “VC CA AC and DC Characteris tics,” on page 25.

■Revised maximum values in Table 7, “Absolute Ratings ,” on page 2 6.

■Revised and reorganiz ed information in Table 8, “VCC_C ORE V oltage and Current,” on page

27. For thermal informatio n, see Table 1, “Thermal Design Power,” on page 21.

■Changed VC C_C ORE to 1.75V for all speed gr ades.

Made the following changes in Chapter 7:

■Changed PLL power source signal name from V DDA to VC CA.

■Revised Figure 10, “Signal Relationship Requirements durin g Power-Up Sequence” on page

36.

■Revised the timing requirem ents in Step 4 o n page 37.

■Revised and reorganized Table 11, “SYSCLK and S YSCLK# AC and DC Characteristics,” on

page 27.

■Added VCROSS symbol to this table.

Revisions continued on next page.

Date Rev Description

xiv Revision History

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

August 2000 C

Continued:

Revised all figures and information in Chapter 8, “Mechanical Data” on page 41.

Revised Chapter 9, “Pin Descriptions” on page 45 as follows:

■Changed FERR# to FERR in Figure 15, “AMD Athlon™ Processor Model 4 Pin Diagram —

Topside View” on page 46. See “FERR Pi n ” on page 63 for more information .

■Revised definition of the Reference column in Table 17, “Socket A Pin Cross-Reference by

Pin Location,” on page 5 5 in “Pin List” on page 53.

■In Table 17, “Socket A Pin Cross-Reference by Pin Location,” on page 55, revised

information for the f ollowing pin locations:

●N1 (PICCLK), N3 (PIC[0]#), N5 (PIC[1]#), A C7 (VC C_ Z), AE33 ( SADDIN[5]#),

AE35 (SDATAOUTCLK[0]#), AE37 (SDATA[9]#), AG1 (FER R), A J21 (CLKFWDRST), A J23

(VCCA), AN13 (PLLMON1), AN15 (PLLBYPASSCLK), AN21 (K7CLKOUT#), AN29

(SADINN[12]#),

AN31 (SADINN[14]#), AN33 (SDATAINVAL#), AN35 (SADINN[13]#), AN37

(SADINN[9]#)

■Revised information in “K7CLKOU T and K7CLK OUT# Pins ” on page 65.

■Removed all specific resistor values in “Detailed Pin Descriptions” on page 62. For specific

implementation information, see the Motherboard PGA Design Guide, order# 90009.

Revised Chapter 10, “Ordering Information” on page 71.

June 2000 B Initial public release.

Date Rev Description

Chapter 1 Overview 1

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

1 Overview

The AMD Athlon™ Processor Model 4 powers the next generation in

computing platforms, delivering compelling performance for

cutting-edge applications and an unprecedented computing

experience.

The AMD Athlon processor with performance-enhancing cache

memory is the latest member of the AMD Athlon™ family of

processors designed to meet the computation-intensive

requirements of cutting-edge software applications running on

high-performance desktop systems, wor kstations, and serv er s.

Delivered in a PGA package and achieving frequencies of

1.4-GHz (1400 MHz) , the AMD Athlon processor delivers the

integer, floating-point and 3D multimedia performance for the

most demanding applications running on x86 system platforms.

For cutting-edge software applications, including digital

content creation, digital photo editing, digital video, image

compression, vi deo enc oding for streaming over the int ernet,

soft DVD, commercial 3D modeling, workstation-class

computer-aided design (CAD), commercial desktop publishing,

and speech recognition, the AMD Athlon processor delivers

compelling performance. It also offers the scalability and

‘peace-of-mind’ reliability that IT managers and business users

r equir e f or enter prise computing.

The AMDAthlon processor features the seventh-generation

microarchitecture with an integrated L2 cache, which supports

the growing process or and system bandwidth requirements of

emerging software, graphics, I/O, and memory technologies.

The AMD Athlon processor's high-speed execution core

includes multiple x86 instruction decoders, a dual-ported

128-Kbyte split level-one (L1) cache, a 256-Kbyte on-chip L2

cache, three independent integer pipelines, three address

calculation pipelines, and a superscalar, fully pipelined,

out-of-or der, thr ee - w ay floating-poi nt engine. T h e floating -point

engine is capable of delivering superior performance on

numericall y complex applications.

2Overview Chapter 1

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

The AMD Athlon processor microarchitecture incorporates

enhanced 3DNow!™ technology, a high-performance cache

architectu re , and both a 200-MHz, 1.6-Gigabyte pe r second

system bus, and a 266 MHz, 2.1-Gigabyte per second system bus.

The AMD Athlon system bus combines the latest technological

advances, such as point-to-point topology, source-synchronous

packet-based transfers, and low-voltage signaling, to provide

the most pow erful, scalable bus a vailable for any x86 processor.

In addition, combined with the AMD 760 chipset, the

AMD Athlon system bus interfaces with double-data rate

(DDR) memory subsystems.

The AMD Athlon processor is binary-compatible with existing

x86 software and backwards compatible with applications

optimiz ed for MMX™ and 3DNow! instructions. Using a data

format and sing le-instructio n multiple-data (SIMD) operations

based on the MMX instruction model, the AMD Athlon

processor can produce as many as four, 32-bit, single-precision

floating-point results per clock cycle. The enhanced 3DNow!

technolo g y implemented in the AMD Athlon pr ocessor includes

new integer multimedia instructions and software -directed

data mo vement instructions f or optimizing such applications as

digital content cre ation and str eaming vi deo f or the internet, as

well as new instructions for digital signal processing

(DSP)/comm unications applications.

1.1 AMD Athlon™ Processor Model 4 Microarchitecture Summary

The following features summarize the AMD Athlon processor

microarchitecture:

■The industry’s first nine-issue, superpipelined, superscalar

x86 processor microarchitecture designed for high clock

frequencies

■Multiple x86 instruction decoder s

■Three out-of-order, superscalar, fully pipelined

floating-point execution units, which execute all x87

(floating-point), MMX and 3DNo w! instructions

■T hr ee out-of-or der, super scalar, pipelined intege r units

■Three out-of-order, superscalar, pipelined address

calculation units

■72-entr y instruction control unit

■Ad v anced d ynamic br anc h pr ediction

■Enhanced 3DNow! technology with new instructions to

enable improved integer math calculations for speech or

video encoding and improved data movement for internet

plug-ins and other str eaming applications

Chapter 1 Overview 3

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

■200-MHz and 266 MHz AMD Athlon system bus (scalable

beyond 400 MHz) enabling leading-edge system bandwidth

f or data mo v ement-intensive applications

■High-performance cache architecture featuring an

integrated 128-Kbyte L1 cache and a 16-way, on-chip

256-Kbyte L2 cache for a total of 384-Kbytes of on-chip cache

The AMD Athlon processor delivers superior system

performance in a cost-effective, industry-standard form factor.

The AMD Athlon processor is compatible with motherboards

based on AMD’s Socket A. Figure 1 on pag e 3 shows a typical

AMD Athlon processor system bloc k diagr am.

Figure 1. Typical AMD Athlon™ Processor Model 4 System Block Diagram

DRAM

AGP Bus

Memory Bus

AGP

PCI Bus

LAN SCSI

System

Management

BIOS

I SA Bus

USB

Dual EIDE

AMD Athlon™

Processor

System

Controller

(Northbridge)

Peripheral Bus

Controller

(Southbridge)

4Overview Chapter 1

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Chapter 2 Interface Signals 5

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

2 Inter face Signals

2.1 Overview

Th e A MD A th l on ™ system bus architecture is designed to

deliver unprecedented data movement bandwidth for

next-generation x86 platforms, as well as the high performance

required by enterprise-class application software. The system

bus architecture consists of three high-speed channels (a

unidirectional processor request channel, a unidirectional

probe channel, and a 72-bit bidirectional data channel,

including 8-bit error code correction [ECC] protection),

source-synchronous clocking, and a packet-based protocol. In

addition, the system bus supports several control, clock, and

legacy signals. The interface signals use an impedance

controlled push-pull low-voltage swing signaling technology

contained within the Socket A socket. For more information,

see “AMD Athlon™ System Bus Signals ” on page 6, C hapter 10,

“Pin Descriptions” on page 45, and the AMD Athlon™ and

AMD Duron™ Sy stem Bus Sp ecific ation , or der# 21902.

2.2 Signaling Technolo gy

T he AMD Athlon system bus uses a low-v oltage, swing signaling

technology, which has been enhanced to provide larger noise

margins, reduce d ringing, a nd var iable voltage levels. The

signals are push-pull and impedance compensated. The signal

inputs use differential rec eivers, which require a reference

voltage (VREF). The reference signal is used by the receivers to

determine if a signal is asserte d or deass erted by the source.

Termination resistors are not needed because the driver is

impedance matched to the motherboard and a high impedance

reflection is used at the receiver to bring the signal past the

input thr eshold.

For more information about pins and signals, see Chapte r 10,

“Pin Descriptions” on page 45.

6Interface Signals Chapter 2

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

2.3 Push-Pull (PP) Drivers

The Socket A AMD Athlon Processor Model 4 supports

Push-Pull (PP) drivers. The system logic configures the

AMDAthlon Processor Model 4 with the configuration

parameter called SysPushPull (1=PP). The impedance of the PP

drivers is set to match the impedance of the motherboard by

two external resistors connected to the ZN an d ZP pins. See

“ZN, VCC_Z, ZP, and VSS_Z Pins” on page 68 for more

information.

2.4 AMD Athlon™ System Bus Signals

The AMD Athlon system bus is a clock-forwarded,

point-to-point interface with the following three point-to-point

channels:

■A 13-bit unidir ectional output addr ess/command c hannel

■A 13-bit unidir ectional input addr ess/command channel

■72-bit bidir ectional data c hannel

For mor e inf ormation, see Chapter 7, “Electrical Data” on page

23 and the AMD Athlon™ and AMD Duron™ System Bus

Specification, or der# 2 1902.

Chapter 3 Logic Symbol Diagram 7

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

3 Logic Symbol Diagr am

Figure 2. Logic Symbol Diagram

PICCLK

PICD[1:0]# APIC

SDATA[63:0]#

SDATAINCLK[3:0]#

SDATAOUTCLK[3:0]#

SCHECK[7:0]#

Data

SADDIN[14:2]#

SADDINCLK#

Probe/SysCMD

SADDOUT[14:2]#

SADDOUTCLK#

VID[4:0]

FID[3:0]

A20M#

CLKFWDRST

CONNECT

COREFB

COREFB#

FERR

IGNNE#

INIT#

INTR

NMI

PROCRDY

PWROK

RESET#

SFILLVAL#

SMI#

STPCLK#

SYSCLK#SYSCLK

Clock

Voltage

Control

Frequency

Control

Legacy

Request

AMD Athlon™

Processor Model 4

SDATAINVAL#

SDATAOUTVAL#

Power

and Initialization

Management

8Logic Symbol Diagram Chapter 3

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Chapter 4 Power Management 9

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

4 Power Ma nagement

4.1 Powe r Management State s

The AMD Athlon™ Processor Model 4 supports low-power Halt

and Stop Grant states. These states are used by Advanced

Configuration and Power Interface (ACPI) enabled operating

systems for processor power management. Figure 3 shows the

power management states of the AMDAthlon Processor Model

4. The figure includes the ACPI “Cx” naming convent ion for

these states.

Figure 3. AMD Athlon™ Processor Model 4 Power Management States

Halt C0

Working

Execute HLT

SMI#, INTR, NMI, INIT#, RESET#

Incoming Pro be

Probe Serviced

STPCLK# asserted

STPCLK# deasserted

Stop Grant

Cache Snoopable

Incoming Probe

Probe Se rvice d

Probe

State1

STPCLK# deasserted

(Read PLVL2 register

or t h rottling)

C3/S1

Stop Gran t

Cach e Not Snoopable

Sleep

STPCLK# asserted

STPCLK#deasserted

Legend: Ha rdware transitions

Soft wa re tra nsi tio ns

Legend: Ha rdware transitions

Soft wa re tra nsi tio ns

The AMD System Bus is connected during the following states:

1) The Probe state

2) During transitions from Halt state to Stop Grant state

3) Stop Grant state to the Halt state

4) The C0 Working State

2) During transitions from the Halt state to the Stop Grant state

3) During transitions from Stop Grant state to the Halt State

The AMD Athlon™ System Bus is connected during the following states:

10 Power Management Chapter 4

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

The following paragraphs describe each of the power

manageme nt states.

Note: In all power management states, the system must not

disable the system clock (SYSCLK/SYSCLK#) to the

processor.

Working State The Working state refers to the state in which the processor is

executing instructions.

Halt State When the A MD Athlo n Processor Model 4 execut es the HLT

instruction, the pro cessor issues a Halt special cycle to the

system bus. The phase-lock loop (PLL) continues to run,

enabling the processor to monitor bus activity and provide a

quick resume from the Halt state. The processor enters a lowe r

power state if the system logic (Northbridge) disconne cts the

AMD Athlon system bus in response to the Halt special cycle.

The Halt state is exited when the processor detects the

assertion of INIT #, RESET#, SMI#, or an inter rupt via the INTR

or NMI pins, or via a local APIC interrupt mes sage.

Stop Grant States T he AMD Athlon Processor Model 4 enter s the Stop Grant state

upon recognition of assertion of STPCLK# input. There are two

mechanisms for asserting STPCLK# – h a rd wa re an d software.

The Southbridge can force STPCLK# assertion for throttling to

protect the processor from exceeding its maximum case

temperature. This task is accomplished by asserting the

THERM# input to the Southbridge. Throttling asserts

STPCLK # for a percenta ge of a predefined throttling pe riod:

STPCLK# is repetitively asserted and deasserted unti l the

THERM# pin is deasserted.

Software can force the processor into the Stop Gra nt state by

accessing ACPI-defined registers typically located in the

Southbridge. Software places the processor in C2 by reading

the PLVL_2 register in the Southbridge. In C2, probes are

allow ed, as shown in F igur e 3 on page 9.

If an ACPI Thermal Zone is defined for the processor, the OS

can initiate throttling with STPCLK# using the ACPI defined

P_CNT register in the Southbridge. The processor enters the

Probe state to service cache snoops initiated by the

Northbridge during Stop Grant f or C2 or thr ottling.

Chapter 4 Power Management 11

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

The Stop Grant state is also entered for the S1 syste m sleep

state based on a write to the SLP_TYP field in the A CPI-defined

power management 1 control register. During the S1 sleep

state, syst em soft ware ensures no bus master or probe activity

occurs.

After recognizing the assertion of STPCLK#, the AMD Athlon

Processor Model 4 completes all pending and in-progress bus

cycles and acknow ledges t he STPCLK# asse rtion by issuing a

Stop Grant special bus cycle to the AMD Athlon system bus.

After the Northbridge disconnects the AMD Athlon syste m bus

in response to the Stop Grant special bus cycle, the processor

enters a low-power state dictated by the CLK_Ctl register.

During the Stop Grant states, the processor latches INIT#,

INTR, NM I, and SMI#, or a local APIC interrupt me ssage if the y

are asserted.

The Stop Grant state is exited upon the deassertion of

STPCLK# or the assertion of RESET#. When STPCLK# is

deasserted, the processor initiates a connection of the

AMD Athlon system bus if it is disconnected. After the

processor enters the Working state, any pending interrupts are

recogniz ed and serviced and the processor resumes execution

at the instruction boundary where STPCLK# was initially

recognized.

If RESET # is sam pled as sert ed during the Stop Grant state, the

processor returns to the Working state and the reset proc ess

begins.

Probe State The Probe state is e ntered when t he No rthbridge initiat es an

AMD Athlon system bus connect as required to probe the

processor. If the processor has been dis connect ed from the

system bus, the Northbridge must initiate a system bus

connection prior to probing the processor to snoop the

processor’s caches for example. When in the Probe state, the

processor responds to a probe cycle in the same manner as

when it is in the Wor king st ate.

When the probe ha s be en s ervice d, the pr o c ess or returns to the

same state as when it entered the Probe state (Halt or Stop

Grant state). Once in the Halt or St op Grant state, a low-power

state is only achieved if the Northbridge initiates a

disconnection fr om the system bus.

12 Power Management Chapter 4

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

4.2 Connect an d Disconn e ct Protocol

Significant po wer sa vings of the AMD Athlon pr ocessor model 4

only occurs if the processor is disconnected from the system bus

by the Northbridge while in the Halt or Stop Grant state. The

Northbridge can optionally initiate a bus disconnect upon the

receipt of a Halt or Stop Grant special cycle. The option of

disconnecting is contro lled by an ena ble bit in the Northbridge.

If the Northbridge requires the processor to service a probe

after the system bus has been disconnected, it must first

initiate a system bus connect.

Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop

Grant special cycles, the AMDAthlon system bus connect

pr otocol includes the CONNECT, PR OCRDY, and CLKFWDRST

signals and a Connect special cycle.

AMD Athlon system bus disconnects are initiated by the

Northbridge in response to the receipt of a Halt or Stop Grant

special cycle. Reconnect is initiated by the processor in

response to an interrupt for Halt, STPCLK# deassertion, or by

the Northbridge to service a probe.

The Northbri dge contains BIOS programmable registers to

enable the system bus disconnect in response to Halt and Stop

Grant special cycles. When the Northbridge receives the Halt or

Stop Grant speci al cycle fr om the processor and, if there ar e no

outstanding probes or data movements, the Northbridge

deasserts CONNECT a minimum of eight SY SCLK periods after

the last command sent to the processor. The processor detects

the deassertion of CONNE CT on a rising edge of SYSCLK, and

deasserts PROCRDY to the Northbridge. In return, the

Northbridge asserts CLKFWDRST in anticipation of

r eestablishing a connection at some later point.

Note: The Northbridge must disconnect the processor from the

AMD Athlon system bus before issuing the Stop Grant

special cycle to the PCI bus, or passing the Stop Grant

special cycle to the Southbridge for systems that connect to

the Southbridge with HyperTranspor t™ technology.

This note applies to current chipset implementation:

alternate chipset implementations that do not require this

are possible.

Chapter 4 Power Management 13

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

Note: In respo nse to Halt special cycles, the Northbridge pa sses the

Halt special cycle to the PCI bus or Southbridge

immediately.

The p roces sor ca n receive an in terrupt a fter it sends a Ha lt

special cycle, or STPCLK# deassertion after it sends a Stop

Grant special cycle to the Northbridge but before the

disconnect actuall y occur s. In this case, the processor sends the

Connect special cycle to the Northbridge, rather than

conti nuing with th e disco nnect sequenc e. In response t o the

Connect special cycle, the Northbridge cancels the disconnect

request.

The system is required to assert the CONNECT signal before

returning the C-bit for the connect special cycle (assuming

CON NECT has b een deas serted). For mor e informatio n, see th e

AMD Athlon™ and AMD Duron™ System Bus Specification,

order# 21902 for the definition of the C-bit and the Connect

special cycle.

Figure 4 shows the sequence of events from a Northbridge

perspective, which leads to disconnecting the processor from

the AMD Athlon system bus an d placing the processor in the

Stop Grant state.

Figure 4. Example of an AMD Athlon™ System Bus Disconnect Sequence

T he following sequence of ev ents describes how the processor is

placed in the Stop Grant state when bus disconnect is enabled

within the Northbridge:

1. The Southbridge asserts STPCLK# to place the processor in

the Stop Grant state.

2. When the processor recognizes STPCLK# asserted, the

processor enters the Stop Grant State, then issues a Stop

Grant special cycle on the AMD Athlon system bus.

Stop Grant

STPCLK#

CONNECT

PROCRDY

CLKFWDRST

PCI Bu s

Syste m Bus

14 Power Management Chapter 4

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

3. When the Stop Grant special cycle is received by the

Northbridge and no probe traffic is pending, the

Northbridge deasserts CONNECT, initiating a bus

disconnect to the processor.

4. The processor responds to the Northbridge by deasserting

PROCRDY, acknowledging the bus disconnect request.

5. The Northbridge asserts CLKFWDRST to complete the bus

disconnect sequence.

6. After the processor is disconnected from the bus, the

Northbridge passes the Stop Grant special cycle to the

Southbridge.

Figure 5 shows the signal sequence of events that take the

processor out of the Stop Grant state, reconnect the processor

to the AMDAthlon system bus, and put the processor into the

Working state.

Figure 5. Exiting Stop Grant State/Bus Reconnect Sequence

The following sequence of event s removes the processor from

the Stop Grant state and reconnects it to the AMD Athlon

system bus:

1. The Southbridge deasserts STPCLK# in response to a

resume event.

2. When the processor recognizes STPCLK# deassertion, it

asserts PROCRDY, notifying the Northbridge to reconnect

to the bus.

3. The Northbridge asserts CON NECT.

4. The Northbridge finally deasserts CLKFWDRST, which

synchronizes the forwarded clocks between the processor

and the Nor thbri dge .

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

Chapter 4 Power Management 15

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

Connect State

Diagram

Figure 6 below and Figure 7 on page 16 describe the

Northbridge and processor connect state diagr ams, r espectiv el y.

Figure 6. Northbridge Connect State Diagram

Condition

1 A disconnect is requested and probes are still pending

2 A disconnect is requested and no probes are pending

3 A CONNECT special cycle from the processor

4 No probes are pending

5 PRO CRDY is deasserted

6 A probe needs service

7 P ROCRDY is asserted

3 SYSCLK periods after CLKFWDRST is deasserted.

Although reconnected to the system interface, the

Northbridge must not issue any non-NOP SysDC

commands for a minimum of four S YSCLK periods after

deasserting CLKF WDRST.

Action

ADeassert CONNECT 8 SYSCLK periods after

last SysDC sent

BAssert CLKFWDRST

C Assert CONNECT

D Deassert CLKFWDRST

Disconnect

Pending Connect Disconnect

Requested

Reconnect

Pending Probe

Pending 2

Disconnect

Probe

Pending 1

2/A

4/A

5/B 3/C

7/D,C

6/C 7/D

16 Power Management Chapter 4

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Figure 7. Processor Connect State Diagram

Condition

1CONNECT is deasserted by the Northbridge (for a

previously sent Halt or Stop Grant special cycle).

2Processor receives a wake-up event and must cancel

the disconnect request.

3 Deassert PROCRDY and slow do wn internal clock s.

4Processor wake-up event or CONNECT ass erted by

Northbridge.

5 CLKFWDRST is deasserted by the Northbridge.

6Forward clocks start 3 SYSCLK periods after

CLKFWDRST is deasserted.

Action

A CLKFWDRST is asserted by the Northbridge.

B Issue a CONN ECT special c ycle.*

CReturn internal clocks to full speed and assert

PROCRDY

* The Connect special cycle is only issued after a

processor wake-up event (interrupt or STPCLK#

deassertion) occurs. If the AMD Athlon system bus

is connected so the Northbridge can probe the

processor a Connect special cycle is not issued at

that time (it is only issued after a subsequent

processor wake-up event).

Connect

Disconnect

Pending

Disconnect

Connect

Pending 1

Connect

Pending 2

3/A

4/C

6/B

2/B

Chapter 4 Power Management 17

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

4.3 Clock Control

The processor implem ents a Clock Control (CLK_Ctl ) MSR

(address C001_001Bh) that determines the internal clock

divisor when the AMD Athlon system bus is disconnected.

Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,

Software, and Debug Developers Guide, order# 21656, for more

details on the CLK_Ctl r egister.

18 Power Management Chapter 4

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Chapter 5 Thermal Design 19

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

5 Thermal Design

For information about thermal design for the AMD Athlon™

Pr ocessor Model 4, including la yout and airflow consider ations,

see the AMD Thermal, Mechanical, and Chassis Cooling Design

Guide, order# 23794, and the cooling guidelines on

www.amd.com.

Table 1 on page 20 shows the thermal design power. The

thermal design power represents the maximum sustained

po w er dissipated while executing publicly a v aila ble softwar e or

instruction sequences under normal system operation at

nominal VCC_CORE. Thermal solutions must monitor the

pr oces sor temper a tur e to prevent the pr oces sor fr om e xceedin g

its maxi mum di e temper atur e.

The maximum die temperature is specified through

characterization at 90 °C for frequencies up to 1000 MHz, and

95°C fo r fr e quencies 1100 MHz a nd ab o v e.

20 Thermal Design Chapter 5

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Table 1. Thermal Design Power

Frequency

(MHz) Nominal

Voltage Maximum Thermal

Power Typical Thermal

Power Max Die

Temperature

650

1.75 V

38 W 34 W

90ºC

700 40 W 36 W

750 43 W 38 W

800 45 W 40 W

850 47 W 42 W

900 50 W 44 W

950 52 W 47 W

1000 54 W 49 W

1100 60 W 54 W

95ºC

1133 63 W 56 W

1200 66 W 59 W

1300 68 W 61 W

1333 70 W 63 W

1400 72 W 65 W

Chapter 6 CPUID Support 21

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

6 CPUID Support

AMD Athlon™ Processor Model 4 version and feature set

recognition can be performed through the use of the CPUID

instruction, that provides complete information about the

processor—vendor, type, name, etc., and its capabilities.

Software can make use of this information to accurately tune

the system for maxim um performance and benef it to users.

For info rmation on the use of the CPUID instruction, see the

AMD Processor Recognition Application Note , or der# 20 734.

22 CPUID Support Chapter 6

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

Chapter 7 Electrical Data 23
23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet
Preliminary Information
7 Electrical Data
7.1 Conventions
T he con v en tions used in thi s c hapter are as f ollo ws:
■Current specified as being sourced by the processor is
negative.
■Curr ent specified as being sunk b y the pr ocessor is positive.
7.2 Interface Signal Groupings
The electrical data in this chapter is present ed separately for
each signal group. Table 2 defines each group and the signals
contained in ea ch  group.
Table 2. Interface Signal Groupings
Signal Group Signals Notes
Power VID[4:0], VCC_CORE, VCC A, COREFB, COREFB#
See “Vo ltage Identification (VID[4:0])” 
on page 24, “VID[4:0] Pins” on page 67, 
and “VCCA AC and DC Characteristics” 
on page 25.
Frequency FID[3:0] See “Frequency Identification 
(FID[3:0])” on page 24 and “FID[3:0] 
Pins” on page 63.
System Clocks SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and 
RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK See “SYSCLK and SYSCLK# DC 
Characteristics” on page 28.
AMD Athlon™ 
System Bus
SADDIN[14 :2]#, SADDOUT[14:2]#, SADDINCLK#, 
SADDOUTCLK#, SF ILLVAL#, SDATAINVAL#, 
SDATAOUTVAL#, SDATA[63:0]#, SDATAINCLK[3:0]#, 
SDATAOUTCLK[3:0]#, SCHECK[7:0]#, CLKFWDRST, 
PROCRDY, CONNECT
See “AMD Athlon™ System Bus AC and 
DC Characteristics” on page 30.
Southbridge RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, 
STPCLK#, FLUSH# See “General AC and DC 
Characteristics” on page 32.
JTAG TMS, TCK, TRST#, TDI, TDO See “General AC and DC 
Characteristics” on page 32.
AP IC P ICD[1:0]#, PICCLK See “APIC Pins AC and DC 
Characteristics” on page 34 and “APIC 
Pins, P ICCLK, PICD[1:0]#” on page 62

24 Electrical Data Chapter 7

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

7.3 Voltage Identification (VID[4:0])

Table 3 shows the VID[4:0] DC characteristics. For more

information, see “VID[4:0] Pins” on page 67.

7.4 Fre quency Identification (FID[3:0])

Table 4 shows the FID[3:0] DC characteristics. For more

information, see “FID[3:0] Pins” on page 63.

Test PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2,

SCANSHIFTEN, SCAN INTEVAL, ANALOG See “General AC and DC

Characteristics” on page 32.

Miscellaneous DBREQ#, DBRDY, PWROK, PLLBYPASS# See “General AC and DC

Characteristics” on page 32.

Table 2. Interface Signal Groupings (continued)

Signal Group Signals Notes

Table 3. VID[4:0] DC Characteristics

Parameter Description Min Max

IOL Output Current Low 16 mA

VOH Output High Voltage 2.625 V *

Note:

* The VID pins must not be pulled above this voltage by an external pullup resistor.

Table 4. FID[3:0] DC Characteristics

Parameter Description Min Max

IOL Output Current Low 16 mA

VOH Output High Vo ltage 2.625 V *

Note:

* The FID pins must not be pulled above this voltage by an external pullup resistor.

Chapter 7 Electrical Data 25

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

7.5 VCCA AC and DC Characteristics

Table 5 shows the AC and DC characteristics for VCCA. For

mor e information, see “VCCA Pin” on page 67.

7.6 Decoupling

See the AMD Athlon™ Processor-Based Motherboard Design

Guide, order# 24363, or contact your local AMD office for

inf or mation about the decoupling required on t he mo therboard

f or use with the AMD Athlon™ Pr oces sor Mod el 4.

7.7 Operating Ran ges

The AMDAthlon Processor Model 4 is designed to provide

functional oper ation if the voltage and temperatur e par ameters

ar e within the limits defined in Table 6.

Table 5. VCCA AC and DC Characteristics

Symbol Parameter Min Nominal Max Units Notes

VVCCA VCCA Pin Vo ltage 2.25 2.5 2.75 V 1

IVCCA VCCA Pin Current 0 50 mA/GHz 2

Notes:

1. Minimum and maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.

2. Measured at 2.5 V.

Table 6. Operating Ranges

Parameter Description Min Nominal Max Notes

VCC_CORE Processor core supply 650-1400 MHz 1.65 V 1.75 V 1.85 V 1

VCC_CORESLEEP Processor core supply in Sleep state 1.2 V 1.3 V 1.4 V 2

TDIE Temperature of processor die 95º C3

Notes:

1. For normal operating conditions (nominal VCC_CORE is 1.75 V)

2. Sleep Voltage can be used for the S1 sleep state.

For more information see the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order#

21656.

3. Die temperature is 90º C for frequencies 1000 MHz and lower.

26 Electrical Data Chapter 7

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

7.8 Abso lut e Ratings

The AMDAthlon Processor Model 4 should not be subjected to

conditions exceeding the absolute ratings listed in Table 7, as

such conditions can adversely affect long-term reliability or

r esu lt in funct ional dam age.

Table 7. Absolute Ratings

Parameter Description Min Max

VCC_CORE AMD Athlon™ Processor Model 4 core supply –0.5 V VCC_CORE Max + 0.5 V

VCCA AMD Athlon Processor Model 4 PLL Supply –0.5 V VCCA Max + 0.5 V

VPIN Voltage on any signal pin –0.5 V VCC _CORE Max + 0.5 V

TSTORAGE Storage temperature of processor –40º C100º C

Chapter 7 Electrical Data 27

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

7.9 VCC_CORE Voltage and Current

Table 8 shows the power and current of the processor during

normal and r educed pow er states.

Table 8. VCC_CORE Voltage and Current

Frequency

(MHz) Nominal

Voltage Maximum

Voltage Stop Grant

(Maximum)1Maximum ICC (Power

Supply Current)2Die Temperature

650

1.75 V 1.85 V 5 W

22 A

90°C

700 23 A

750 25 A

800 26 A

850 27 A

900 29 A

950 30 A

1000 31 A

1100 34 A

95°C

1133 36 A

1200 38 A

1300 39 A

1333 40 A

1400 42 A

Notes:

1. Measured at 1.3V for Sleep state operating conditions. The BIOS must program the CLK_Ctrl MSR to fff0_d22fh for the

AMD Athlon™ Processor Model 4.

2. Measured at Nominal voltage. of 1.75 V.

28 Electrical Data Chapter 7

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

7.10 SYSCLK and SYSCLK# AC and DC Char acteristics

Table 9 shows the DC characteristics of the SYSCLK and

SYSCLK# differential clocks. The SYSCLK signal represents

CLKIN and RST CLK t ied together while the SYSCLK# signal

r epr esents CLKIN# and RSTCLK # tied tog ether. Figure 8 sho ws

this condition.

Figure 8. SYSCLK and SYSCLK# Differential Clock Signals

Table 9. SYSCLK and SYSCLK# DC Characteristics

Symbol Description Min Max Units

VThreshold-DC Crossing before transition is detected (DC) 400 mV

VThreshold-AC Crossing before transition is detected (AC) 450 mV

ILEAK_P Leakage current through P-channel pullup to VCC_CORE —1mA

ILEAK_N Leakage current through N-channel pulldown to VSS (Ground) 1 m A

VCROSS D ifferential signal crossover VCC_CORE/2

+/– 100 mV

CPIN Capacitance 4 12 pF

VCROSS VThreshold-DC = 400mV VThreshold-AC = 450mV

Chapter 7 Electrical Data 29

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

Table 10 shows the SYSCLK/SYSCLK# differential clock AC

characteristics of the AMD Athlon Processor Model 4. Figure 9

sho ws a sampl e w a v e f orm.

Figure 9. SYSCLK Waveform

Table 10. SYSCLK and SYSCLK# AC Characteristics

Symbol Parameter Description Min @ Max @ Units Notes

Clock Frequency 100 133 100 133 MHz

Duty Cycle 30% 30% 70% 70%

t1Period 10 7.5 ns 1, 2

t2High Time 1.8 1.05 nS

t3Low Time 1.8 1.05 ns

t4Fall Time 2 2 ns

t5Rise Time 2 2 ns

Period Stability ± 300 ± 300 ps

Notes:

1. Circuitry driving the SYSCLK & SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow

the PLL to track the jitter. The –20 dB attenuation point, as measured into a 1 0-pF or 20-pF load must be less than

500 kHz.

2. Circuitry driving the SYSCLK & SYSCLK# inputs can purposely alter the SYSCLK & SYSCLK# period (spread

spectrum clock generators). In no cases can the SYSCLK & SYSCLK# period violate the minimum specification

above. SYSCLK & SYSCLK# inputs can vary from 100% of the specified period to 99% of the specified period at

a maximum rate of 100 kHz.

VCROSS

VThreshold-AC

30 Electrical Data Chapter 7

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

7.11 AMD Athlon™ System Bus AC and DC Chara cteristics

Table 11 shows the DC characteristics of the AMD Athlon

system bus used by the AMD Athlon Processor Model 4.

Table 11. AMD Athlon™ System Bus DC Characteristics

Symbol Parameter Condition Min Max Units Notes

VREF DC Input Reference Voltage (0.5*VCC_CORE)

–50 (0.5*VCC_CORE)

+50 mV 1

IVREF_LEAK_P VREF Tristate Leakage Pullup VIN = VREF Nominal –100 µA

IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal +100 µA

VIH Input High Voltage VREF + 200 VCC_CORE +

500 mV

VIL Input Low Voltage –500 VREF – 200 mV

VOH Output High Voltage IOUT = –200µA0.85*VCC_CORE VCC_CORE+500 mV 2

VOL Output Low Voltage IOUT = 1 mA –500 400 mV 2

ILEAK_P Tristate Leakage Pullup VIN = VSS (Ground) –1mA

ILEAK_N Tristate Leakage Pulldown VIN = VCC_CORE

Nominal +1 mA

CIN Input Pin Capacitance 4 12 pF 3

Notes:

1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be

created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed above.

2. Specified at TDIE given in Table 6, and VCC_CORE in Table 8

3. The following processor inputs have twice the listed capacitance because they connect to two input pads— SYSCLK, and SYSCLK#.

SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#. For more information, see Table 16 on page 48 .

Chapter 7 Electrical Data 31

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

The AC characteristics of the AMD Athlon system bus are

shown in Table 12 on page 31. The parameters are grouped

based on the s our ce or dest ination of the signals inv olv ed.

Table 12. AMD Athlon™ System Bus AC Characteristics

Group Symbol Parameter Min Max Units Notes

All Signals TRISE Output Rise Slew Rate 1 3 V/ns 1

TFALL Output Fall Slew Rate 1 3 V/ns 1

Forward Clocks

TSKEW-

SAMEEDGE Output skew with respect to

the same clock edge 385 ps 2

TSKEW-

DIFFEDGE Output skew with respect to a

different clock edge 770 ps 2

TSU Input Data Setup Time 300 ps 3

THD Input Data Hold Time 300 ps 3

CIN Capacitance on input Clocks 4 12 pF

COUT Capacitance on output Clocks 4 12 pF

Sync

TVAL RSTCLK to Output Valid 250 2000 ps 5

TSU Setup to RSTCLK 500 ps 6

THD Hold from RSTCLK 1000 ps 6

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and

its forward clock, as measured at the package, with respect to the same clock edge.

TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and

its forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, CLKFWDRST.

5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25pF.

6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNE CT/CLKFWDRST from rising edge

of RSTCLK.

32 Electrical Data Chapter 7

AMD Athlon™ Processor Model 4 Data Sheet 23792I—June 2001

Preliminary Information

7.12 General AC and DC Characteristics

Table 13 shows the AMD Athlon Processor Model 4 AC and DC

characteristics of the Southbridge, JTAG, test, and

miscellaneous pins.

Table 13. General AC and DC Characteristics

Symbol Parameter Description Condition Min Max Units Notes

VIH Input High Voltage (VC C_C ORE/2) +

200mV VC C_CORE +

300mV V1,2

VIL Input Low Voltage –300 350 mV 1,2

VOH Output High Voltage VCC_CORE –

400 VCC_C ORE +

300 mV

VOL Output Low Voltage –300 400 mV

ILEAK_P Tristate Leakage Pullup VIN = VSS

(Ground) –1mA

ILEAK_N Tristate Leakage Pulldown VIN = VCC_CORE

Nominal 600 µA

IOH Output High Current –16 mA 3

IOL Output Low Current 16 mA 3

TSU Sync Input Setup Time 2.0 ns 4, 5

THD Sync Input Hold Time 0.0 ps 4, 5

TDELAY Output Delay with respect to RSTCLK 0.0 6.1 ns 5

TBIT Input Time to Acquire 20.0 ns 7,8

TRPT Input Time to Reacquire 40.0 ns 9-13

Notes:

1. Characterized across DC supply voltage range.

2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.

3. IOL and IOH are measured at VOL max and VOH min, respectively.

4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

5. These are aggregate numbers.

6. Edge rates indicate the range over which inputs were characterized.

7. In asynchronous operation, the signal must persist for this time to guarantee capture.

8. This value assumes RSTCLK frequency is 10ns ==> TBIT = 2*fRST.

9. The approximate value for standard case in normal mode operation.

10. This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency.

11. Reassertions of the signal within this time are not guaranteed to be seen by the core.

12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

configurations.

Chapter 7 Electrical Data 33

23792I—June 2001 AMD Athlon™ Processor Model 4 Data Sheet

Preliminary Information

TRISE Signal Rise Time 1.0 3.0 V/ns 6

TFALL Signal Fall Time 1.0 3.0 V/ns 6

CPIN Pin Capacitance 4 12 pF

Table 13. General AC and DC Characteristics (continued)