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M16C/26A Group(M16C/26A,M16C/26T)
16
Rev. 1.00
Revision date: Mar.15, 2005
Hardware Manual
www.renesas.com
Before using this material, please visit our website to verify that this is the most
current document available.
REJ09B0202-0100
Keep safety first in your circuit designs!
Notes regarding these materials
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Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
• These materials are intended as a reference to assist our customers in the selection of the
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• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-
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programs, algorithms, or circuit application examples contained in these materials.
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due to product improvements or other reasons. It is therefore recommended that custom-
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listed herein.
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he products contained therein.
How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M16C/26 group (M16C/26A, M16C/26T) microcom-
puters. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
Function
XXX Register
Bit Name
Bit Symbol
Symbol Address After Reset
XXX XXX 00h
RW
RW
RW
WO
RO
XXX0
XXX1
(b2)
(b4 - b3)
XXX Bit
Reserved Bit
XXX7
Set to "0"
0: XXX
1: XXX
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
XXX Bit
0 0: XXX
0 1: XXX
1 0: Do not set a value
1 1: XXX
b1b0
XXX Bit
Function varies depending on mode
of operation
XXX5
XXX6
0
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0 *1
*2
*4
*3
0*5
*1 Blank:Set to "0" or "1" according to the application
0: Set to "0"
1: Set to "1"
X: Nothing is assigned
*2 RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*3 • Reserved bit
Reserved bit. Set to specified value.
*4 • Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to "0" when writing to this bit.
• Do not set a value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
3. M16C Family Documents
The following documents were prepared for the M16C family. (1)
Document Contents
Short Sheet Hardware overview
Data Sheet Hardware overview and electrical characteristics
Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts)
Software Manual Detailed description of assembly instructions and microcomputer perfor-
mance of each instruction
Application Note • Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE
Preliminary report about the specification of a product, a document, etc.
NOTES :
1. Before using this material, please visit the our website to verify that this is the most current document
available.
A-1
Table of Contents
Quick Reference by Address _____________________ B-1
1. Overview _____________________________________ 1
1.1 Applications.................................................................................................................1
1.2 Performance Outline...................................................................................................2
1.3 Block Diagram .............................................................................................................4
1.4 Product List .................................................................................................................6
1.5 Pin Configuration ........................................................................................................9
1.6 Pin Description.......................................................................................................... 11
2. Central Processing Unit (CPU)___________________ 13
2.1 Data Registers (R0, R1, R2 and R3).........................................................................13
2.2 Address Registers (A0 and A1)................................................................................13
2.3 Frame Base Register (FB) ........................................................................................14
2.4 Interrupt Table Register (INTB) ................................................................................14
2.5 Program Counter (PC) ..............................................................................................14
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................14
2.7 Static Base Register (SB) .........................................................................................14
2.8 Flag Register (FLG)...................................................................................................14
2.8.1 Carry Flag (C Flag).............................................................................................14
2.8.2 Debug Flag (D Flag) ...........................................................................................14
2.8.3 Zero Flag (Z Flag)..............................................................................................14
2.8.4 Sign Flag (S Flag)...............................................................................................14
2.8.5 Register Bank Select Flag (B Flag) ..................................................................14
2.8.6 Overflow Flag (O Flag).......................................................................................14
2.8.7 Interrupt Enable Flag (I Flag) ............................................................................14
2.8.8 Stack Pointer Select Flag (U Flag)....................................................................14
2.8.9 Processor Interrupt Priority Level (IPL)...........................................................14
2.8.10 Reserved Area ..................................................................................................14
3. Memory______________________________________ 15
4. Special Function Register (SFR) _________________ 16
5. Reset________________________________________ 22
5.1 Hardware Reset .........................................................................................................22
5.1.1 Hardware Reset 1...............................................................................................22
5.1.2 Hardware Reset 2...............................................................................................22
A-2
5.2 Software Reset ..........................................................................................................23
5.3 Watchdog Timer Reset .............................................................................................23
5.4 Oscillation Stop Detection Reset.............................................................................23
5.5 Voltage Detection Circuit..........................................................................................25
6. Processor Mode ______________________________ 31
7. Clock Generation Circuit ................................................ 32
7.1 Main Clock .................................................................................................................39
7.2 Sub Clock...................................................................................................................40
7.3 On-chip Oscillator Clock ..........................................................................................41
7.4 PLL Clock...................................................................................................................41
7.5 CPU Clock and Peripheral Function Clock.............................................................43
7.5.1 CPU Clock...........................................................................................................43
7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32) ........43
7.5.3 ClockOutput Function .......................................................................................43
7.6 Power Control............................................................................................................44
7.6.1 Normal Operation Mode ....................................................................................44
7.6.2 Wait Mode ...........................................................................................................45
7.6.3 Stop Mode..........................................................................................................47
7.7 System Clock Protective Function ..........................................................................51
7.8 Oscillation Stop and Re-oscillation Detect Function.............................................51
7.8.1
Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset) ......
52
7.8.2
Operation When the CM27 bit is set to "1" (Oscillation Stop and Re-oscillation Detect Interrupt) ...
52
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function.................53
8. Protection____________________________________ 54
9. Interrupt _____________________________________ 55
9.1 Type of Interrupts ......................................................................................................55
9.1.1 Software Interrupts ............................................................................................56
9.1.2 Hardware Interrupts...........................................................................................57
9.2 Interrupts and Interrupt Vector ................................................................................58
9.2.1 Fixed Vector Tables ...........................................................................................58
9.2.2 Relocatable Vector Tables.................................................................................59
9.3 Interrupt Control........................................................................................................60
9.3.1 I Flag....................................................................................................................63
9.3.2 IR Bit....................................................................................................................63
9.3.3 ILVL2 to ILVL0 Bits and IPL...............................................................................63
A-3
9.4 Interrupt Sequence ...................................................................................................64
9.4.1 Interrupt Response Time...................................................................................65
9.4.2 Variation of IPL when Interrupt Request is Accepted.....................................65
9.4.3 Saving Registers................................................................................................66
9.4.4 Returning from an Interrupt Routine................................................................68
9.5 Interrupt Priority........................................................................................................68
9.5.1 Interrupt Priority Resolution Circuit.................................................................68
______
9.6 INT Interrupt...............................................................................................................70
______
9.7 NMI Interrupt..............................................................................................................71
9.8 Key Input Interrupt ....................................................................................................71
9.9 Address Match Interrupt...........................................................................................72
10. Watchdog Timer _____________________________ 74
10.1 Count source protective mode ..............................................................................75
10.2 Cold start / Warm start............................................................................................76
11. DMAC ______________________________________ 77
11.1 Transfer Cycles.......................................................................................................82
11.2. DMA Transfer Cycles..............................................................................................84
11.3 DMA Enable..............................................................................................................85
11.4 DMA Request ...........................................................................................................85
11.5 Channel Priority and DMA Transfer Timing .........................................................86
12. Timer_______________________________________ 87
12.1 Timer A ....................................................................................................................89
12.1.1. Timer Mode......................................................................................................92
12.1.2. Event Counter Mode .......................................................................................93
12.1.3. One-shot Timer Mode .....................................................................................98
12.1.4. Pulse Width Modulation (PWM) Mode.........................................................100
12.2 Timer B..................................................................................................................103
12.2.1 Timer Mode....................................................................................................106
12.2.2 Event Counter Mode ......................................................................................107
12.2.3 Pulse Period and Pulse Width Measurement Mode...................................108
12.2.4 A/D Trigger Mode .......................................................................................... 110
12.3 Three-phase Motor Control Timer Function ....................................................... 112
12.3.1 Position-data-retain Function .......................................................................123
12.3.2 Three-phase/Port Output Switch Function..................................................125
A-4
13. Serial I/O___________________________________ 127
13.1. UARTi (i=0 to 2) ....................................................................................................127
13.1.1. Clock Synchronous serial I/O Mode............................................................137
13.1.2. Clock Asynchronous Serial I/O (UART) Mode............................................145
13.1.3 Special Mode 1 (I2C bus mode)(UART2) ......................................................153
13.1.4 Special Mode 2 (UART2)................................................................................163
13.1.5 Special Mode 3 (IE Bus mode )(UART2) .....................................................168
13.1.6 Special Mode 4 (SIM Mode) (UART2) ..........................................................170
14. A/D Converter ______________________________ 175
14.1 Operation Modes...................................................................................................181
14.1.1 One-Shot Mode ..............................................................................................181
14.1.2 Repeat mode ..................................................................................................183
14.1.3 Single Sweep Mode ......................................................................................185
14.1.4 Repeat Sweep Mode 0 ...................................................................................187
14.1.5 Repeat Sweep Mode 1 ...................................................................................189
14.1.6 Simultaneous Sample Sweep Mode.............................................................191
14.1.7 Delayed Trigger Mode 0.................................................................................194
14.1.8 Delayed Trigger Mode 1.................................................................................200
14.2 Resolution Select Function..................................................................................206
14.3 Sample and Hold ...................................................................................................206
14.4 Power Consumption Reducing Function............................................................206
14.5 Output Impedance of Sensor under A/D Conversion ........................................207
15. CRC Calculation Circuit______________________ 208
15.1. CRC Snoop ...........................................................................................................208
16. Programmable I/O Ports ______________________ 211
16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)...................................... 211
16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)......................................................... 211
16.3
Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers) ........
211
16.4 Port Control Register............................................................................................212
16.5 Pin Assignment Control register (PACR)............................................................212
16.6 Digital Debounce function....................................................................................212
17. Flash Memory Version _______________________ 225
17.1 Flash Memory Performance .................................................................................225
17.2 Memory Map ..........................................................................................................227
A-5
17.3 Functions To Prevent Flash Memory from Rewriting ........................................230
17.3.1 ROM Code Protect Function .........................................................................230
17.3.2 ID Code Check Function ...............................................................................230
17.4 CPU Rewrite Mode ................................................................................................232
17.4.1 EW0 Mode.......................................................................................................233
17.4.2 EW1 Mode.......................................................................................................233
17.5 Register Description .............................................................................................234
17.5.1 Flash memory control register 0 (FMR0) .....................................................234
17.5.2 Flash memory control register 1 (FMR1) .....................................................235
17.5.3 Flash memory control register 4 (FMR4) .....................................................235
17.6 Precautions in CPU Rewrite Mode ......................................................................240
17.6.1 Operation Speed ............................................................................................240
17.6.2 Prohibited Instructions..................................................................................240
17.6.3 Interrupts ........................................................................................................240
17.6.4 How to Access................................................................................................240
17.6.5 Writing in the User ROM Space ....................................................................240
17.6.6 DMA Transfer..................................................................................................241
17.6.7 Writing Command and Data..........................................................................241
17.6.8 Wait Mode .......................................................................................................241
17.6.9 Stop Mode.......................................................................................................241
17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low
Power Consumption Mode..........................................................................241
17.7 Software Commands ............................................................................................242
17.7.1 Read Array Command (FF16)........................................................................242
17.7.2 Read Status Register Command (7016).......................................................242
17.7.3 Clear Status Register Command (5016).......................................................243
17.7.4 Program Command (4016) ............................................................................243
17.7.5 Block Erase ....................................................................................................244
17.8 Status Register......................................................................................................246
17.8.1 Sequence Status (SR7 and FMR00 Bits ).....................................................246
17.8.2 Erase Status (SR5 and FMR07 Bits).............................................................246
17.8.3 Program Status (SR4 and FMR06 Bits)........................................................246
17.8.4 Full Status Check...........................................................................................247
17.9 Standard Serial I/O Mode......................................................................................249
17.9.1 ID Code Check Function ...............................................................................249
17.9.2 Example of Circuit Application in Standard Serial I/O Mode .....................253
17.10 Parallel I/O Mode .................................................................................................255
17.10.1 ROM Code Protect Function .......................................................................255
A-6
18. Electrical Characteristics _____________________ 256
18.1. Normal version .....................................................................................................256
18.2. T version ...............................................................................................................275
19. Usage Precaution ___________________________ 294
19.1 SFR .........................................................................................................................294
19.1.1 Precaution for 48 pin version .......................................................................294
19.1.2 Precaution for 42 pin version .......................................................................294
19.2 PLL Frequency Synthesizer .................................................................................295
19.3 Power Control........................................................................................................296
19.4 Protect....................................................................................................................298
19.5 Interrupts ...............................................................................................................299
19.5.1 Reading address 0000016 .............................................................................299
19.5.2 Setting the SP.................................................................................................299
_______
19.5.3 The NMI Interrupt ...........................................................................................299
19.5.4 Changing the Interrupt Generation Factor ..................................................300
19.5.6 Rewrite the Interrupt Control Register.........................................................301
19.5.7 Watchdog Timer Interrupt .............................................................................302
19.6 DMAC .....................................................................................................................303
19.6.1 Write to DMAE Bit in DMiCON Register .......................................................303
19.7 Timer.......................................................................................................................304
19.7.1 Timer A............................................................................................................304
19.7.2 Timer B............................................................................................................308
19.8 Serial I/O (Clock-synchronous Serial I/O) ........................................................... 311
19.8.1 Transmission/reception................................................................................. 311
19.8.2 Transmission..................................................................................................312
19.8.3 Reception........................................................................................................313
19.9 Serial I/O (UART Mode).........................................................................................314
19.9.1 Special Mode 1 (I2C bus Mode).....................................................................314
19.9.2 Special Mode 2 ...............................................................................................314
19.9.3 Special Mode 4 (SIM Mode)...........................................................................314
19.10 A/D Converter ......................................................................................................315
19.11 Programmable I/O Ports .....................................................................................317
19.12 Electric Characteristic Differences Between Mask ROM and Flash
Memory Version Microcomputers .....................................................................318
19.13 Mask ROM Version..............................................................................................318
19.13.1 Internal ROM area ........................................................................................318
19.13.2 Reserve bit....................................................................................................318
A-7
19.14 Flash Memory Version ........................................................................................319
19.14.1 Functions to Inhibit Rewriting Flash Memory ...........................................319
19.14.2 Stop mode ....................................................................................................319
19.14.3 Wait mode .....................................................................................................319
19.14.4
Low power dissipation mode, on-chip oscillator low power dissipation mode ......
319
19.14.5 Writing command and data.........................................................................319
19.14.6 Program Command......................................................................................319
19.14.7 Operation speed...........................................................................................319
19.14.8 Instructions prohibited in EW0 Mode ........................................................320
19.14.9 Interrupts ......................................................................................................320
19.14.10 How to access ............................................................................................320
19.14.11 Writing in the user ROM area....................................................................320
19.14.12 DMA transfer...............................................................................................320
19.14.13 Regarding Programming/Erasure Times and Execution Time ..............321
19.14.14 Definition of Programming/Erasure Times..............................................321
19.14.15 Flash Memory Version Electrical Characteristics 10,000 E/W
cycle products (U7, U9) .............................................................................321
19.14.16 Boot Mode ..................................................................................................321
19.15 Noise ....................................................................................................................322
19.16 Instruction for a Device Use...............................................................................323
Appendix 1. Package Dimensions_________________ 324
Appendix 2. Functional Difference ________________ 325
Appendix 2.1 Differences between M16C/26A and M16C/26T...................................325
Appendix 2.2 Differences between M16C/26A and M16C/26.....................................326
Register Index _________________________________ 327
B-1
Quick Reference by Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Address
Note: The blank areas are reserved and cannot be accessed by users.
Register Symbol Page
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Watchdog timer start register WDTS
Watchdog timer control register WDC
Processor mode register 0 PM0
System clock control register 0 CM0
System clock control register 1 CM1
Address match interrupt enable register AIER
Protect register PRCR
Processor mode register 1 PM1
Oscillation stop detection register CM2
PLL control register 0 PLC0
Processor mode register 2 PM2
Address match interrupt register 0 RMAD0
Address match interrupt register 1 RMAD1
DMA0 control register DM0CON
DMA0 transfer counter TCR0
DMA1 control register DM1CON
DMA1 source pointer SAR1
DMA1 destination pointer DAR1
DMA0 destination pointer DAR0
DMA0 source pointer SAR0
Voltage detection register 1 VCR1
Voltage detection register 2 VCR2
Voltage down detection interrupt register D4INT
UART0 transmit interrupt control register
S0TIC
UART0 receive interrupt control register
S0RIC
UART1 transmit interrupt control register
S1TIC
UART1 receive interrupt control register
S1RIC
DMA1 transfer counter TCR1
INT3 interrupt control register INT3IC
INT5 interrupt control register INT5IC
INT4 interrupt control register INT4IC
UART2 Bus collision detection interrupt control register
BCNIC
DMA0 interrupt control register DM0IC
DMA1 interrupt control register DM1IC
Key input interrupt control register KUPIC
A/D conversion interrupt control register ADIC
UART2 transmit interrupt control register
S2TIC
UART2 receive interrupt control register
S2RIC
Timer A0 interrupt control register TA0IC
Timer A1 interrupt control register TA1IC
Timer A2 interrupt control register TA2IC
Timer A3 interrupt control register TA3IC
Timer A4 interrupt control register TA4IC
Timer B0 interrupt control register TB0IC
Timer B2 interrupt control register TB2IC
INT0 interrupt control register INT0IC
INT1 interrupt control register INT1IC
INT2 interrupt control register INT2IC
Timer B1 interrupt control register TB1IC
31
31
34
35
73
54
36
75
75
73
73
26
26
38
37
26
81
81
81
80
81
81
81
80
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
Address
Register Symbol Page
B-2
Quick Reference by Address
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
008016
008116
008216
008316
008416
008516
008616
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
033D16
033E16
033F16
Peripheral clock select register PCLKR
Flash memory control register 0 FMR0
Flash memory control register 1 FMR1 236
236
37
(Note 2)
(Note 2)
Address
Register Symbol Page
(Note 2)
Flash memory control register 4 FMR4 237
Pin assignment control register PACR
On-chip oscillator control register ROCR 134, 221
35
P1
7
digital debounce register P17DDR
NMI digital debounce register NDDR 222
222
Three phase protect control register TPRC
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Timer A1-1 register TA11
Timer A2-1 register TA21
Dead time timer DTT
Timer B2 interrupt occurrence frequency set counter
ICTB2
Three-phase PWM control register 0 INVC0
Three-phase PWM control register 1 INVC1
Three-phase output buffer register 0 IDB0
Three-phase output buffer register 1 IDB1
Interrupt request cause select register
IFSR
UART2 special mode register U2SMR
UART2 receive buffer register
U2RB
UART2 transmit buffer register
U2TB
UART2 transmit/receive control register 0
U2C0
UART2 transmit/receive mode register
U2MR
UART2 transmit/receive control register 1
U2C1
UART2 bit rate generator
U2BRG
Timer A4-1 register TA41
UART2 special mode register 2 U2SMR2
UART2 special mode register 3 U2SMR3
UART2 special mode register 4 U2SMR4
117
117
117
114
115
116
116
116
116
136
136
135
135
132
131
131
133
134
131
62, 70
Address
Register Symbol Page
Position-data-retain function contol register
PDRF 124
Port function contol register PFCR
Interrupt request cause select register 2
IFSR2A 62
126
126
B-3
Quick Reference by Address
Note : The blank areas are reserved and cannot be accessed by users.
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
Count start flag TABSR
Trigger select register TRGSR
Timer A0 register TA0
Timer A1 register TA1
Timer A2 register TA2
Timer B0 register TB0
Timer B1 register TB1
Timer B2 register TB2
One-shot start flag ONSF
Timer A0 mode register TA0MR
Timer A1 mode register TA1MR
Timer A2 mode register TA2MR
Timer B0 mode register TB0MR
Timer B1 mode register TB1MR
Timer B2 mode register TB2MR
Up-down flag UDF
Timer A3 register TA3
Timer A4 register TA4
Timer A3 mode register TA3MR
Timer A4 mode register TA4MR
Clock prescaler reset flag CPSRF
UART0 transmit/receive mode register
U0MR
UART0 transmit buffer register U0TB
UART0 receive buffer register U0RB
UART1 transmit/receive mode register
U1MR
UART1 transmit buffer register U1TB
UART1 receive buffer register U1RB
UART0 bit rate generator U0BRG
UART0 transmit/receive control register 0
U0C0
UART0 transmit/receive control register 1
U0C1
UART1 bit rate generator U1BRG
UART1 transmit/receive control register 0
U1C0
UART1 transmit/receive control register 1
U1C1
DMA1 request cause select register DM1SL
DMA0 request cause select register DM0SL
UART transmit/receive control register 2
UCON
Timer B2 special mode register TB2SC
90, 105,
119
91
91, 105
91, 119
90
105
105
105, 119
89
89, 120
89
104
104
111, 118
132
131
131
133
134
131
132
131
131
133
134
131
133
79
80
90
90, 117
90, 117
90
90, 117
89, 120
89, 120
104, 120
Address
Register Symbol Page
CRC snoop address register CRCSAR
CRC mode register CRCMR
CRC data register CRCD
CRC input register CRCIN
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
A/D control register 1 ADCON1
Port P9 register P9
Pull-up control register 0 PUR0
Port control register PCR
A/D register 7 AD7
A/D register 0 AD0
A/D register 1 AD1
A/D register 2 AD2
A/D register 3 AD3
A/D register 4 AD4
A/D register 5 AD5
A/D register 6 AD6
A/D control register 0 ADCON0
A/D control register 2 ADCON2
Port P1 register P1
Port P1 direction register PD1
Port P6 register P6
Port P6 direction register PD6
Port P7 register P7
Port P7 direction register PD7
Port P8 register P8
Port P8 direction register PD8
Port P9 direction register PD9
Port P10 register P10
Port P10 direction register PD10
Pull-up control register 1 PUR1
Pull-up control register 2 PUR2
179
179
179
179
179
179
179
179
177
177
177
219
218
219
219
218
218
219
219
218
218
219
218
220
220
220
221
Address
Register Symbol Page
A/D convert status register 0 ADSTAT0 179
A/D trigger control register ADTRGCON 178
209
209
209
209
M16C/26A Group(M16C/26A, M16C/26T)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ09B0202-0100
Rev.1.00
Mar. 15, 2005
page 1
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1. Overview
The M16C/26A group(M16C/26A, M16C/26T) of single-chip microcomputers is built using the high-perfor-
mance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 42-pin and 48-
pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featur-
ing a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing
instructions at high speed. In addition, this microcomputer contains a multiplier and a DMAC which com-
bined with fast instruction processing capability, makes it suitable for control of various OA, communication,
and industrial equipment which requires high-speed arithmetic/logic operations.
There is a Normal-ver. for M16C/26A and T-ver. and V-ver. for M16C/26T.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, home appliances
(inverter solution), auotmotives, motor control, etc
1. Overview
page 2
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Item Performance
CPU Number of Basic Instructions 91 instructions
Minimun Instruction Execution
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
(M16C/26A, M16C/26T(T-ver.))
Time
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
(M16C/26A)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C)
(M16C/26T(V-ver.))
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C)
(M16C/26T(V-ver.))
Operation Mode Single chip mode
Address Space 1M byte
Memory Capacity ROM/RAM : See the product list
Peripheral Port Input/Output : 39 lines
function Multifunction Timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
Serial I/O 2 channels (UART, clock synchronous serial I/O)
1 channel
(UART, clock synchronous, I2C bus(1) , or IEBus(2))
A/D Converter 10 bit A/D Converter : 1 circuit, 12 channels
DMAC 2 channels
CRC Calcuration Circuit
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt
20 internal and 8 external sources, 4 software sources, 7 levels
Clock Generation Circuit 4 circuits
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)These circuit contain a built-in feedback resister.
Oscillation Stop Detection Main clock oscillation stop, re-oscillation detection function
Voltage Detection Circuit Available(M16C/26A, Option(4)), Absent(M16C/26T)
Electrical
Power Supply Voltage VCC=3.0V to 5.5V (
f(BCLK)=20MHZ) (M16C/26A)
Characteristics
VCC=
2.7V to 5.5V (
f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
(M16C/26T(T-ver.))
VCC=4.2V to 5.5V
(M16C/26T(V-ver.))
Power Consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz, in wait mode)
0.7 µA
(Vcc=3V, in stop mode)
Flash memory Program/Erase Supply Voltage
2.7V to 5.5V (M16C/26A)
Version 3.0V to 5.5V (M16C/26T(T-ver.)) 4.2V to 5.5V (M16C/26T(V-ver.))
Program and Erase Endurance 100 times (all area)
or 1,000 times (block 0 to 3) / 10,000 times
(block A, block B)(3)
Operating Ambient Temperature -20 to 85°C / -40 to 85°C (3) (M16C/26A)
-40 to 85°C (M16C/26T(T-ver.))
-40 to 105°C / -40 to 125°C (M16C/26T(V-ver.))
Package 48-pin plastic molded QFP
Notes:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.6 Product Code
for the program and erase endurance, and operating ambient temperature.
4. The option is on a request basis.
Table 1.1. Performance outline of M16C/26A group(M16C/26A, M16C/26T) (48-pin device)
1.2 Performance Outline
Table 1.1 lists performance outline of M16C/26A group 48-pin device.
Table 1.2 lists performance outline of M16C/26A group 42-pin device.
1. Overview
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Table 1.2. Performance outline of M16C/26A group (M16C/26A) (42-pin device)
Item Performance
CPU Number of Basic Instructions 91 instructions
Minimun Instruction Execution
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
Time
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
Operation Mode Single chip mode
Address Space 1M byte
Memory Capacity ROM/RAM : See the product list
Peripheral Port Input/Output : 33 lines
function Multifunction Timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
Serial I/O 1 channel (UART, clock synchronous serial I/O)
1 channel (UART, clock synchronous, I2C bus(1) , or IEBus(2))
A/D Converter 10 bit A/D Converter : 1 circuit, 10 channels
DMAC 2 channels
CRC Calcuration Circuit
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt
18 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit 4 circuits
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)These circuit contain a built-in feedback resister.
Oscillation Stop Detection Main clock oscillation stop, re-oscillation detection function
Voltage Detection Circuit Available (option(4))
Electrical
Power Supply Voltage VCC=3.0V to 5.5V (
f(BCLK)=20MHZ)
Characteristics
VCC=
2.7V to 5.5V (
f(BCLK)=10MHZ)
Power Consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz, in wait mode)
0.7 µA
(Vcc=3V, in stop mode)
Flash memory Program/Erase Supply Voltage
2.7V to 5.5V
Program and Erase Endurance 100 times (all area)
or 1,000 times (block 0 to 3) / 10,000 times
(block A, block B)(3)
Operating Ambient Temperature -20 to 85°C / -40 to 85°C (3)
Package 42-pin plastic molded SSOP
Notes:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.6 Product Code
for the program and erase endurance, and operating ambient temperature.
4. The option is on a request basis.
1. Overview
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I/O
Ports
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
Watchdog Timer
(15bits)
A/D converter
(10bits x 12 channels) U(S)ART/SIO (channel 0)
Serial Ports System Clock Generator
X
IN
-X
OUT
X
CIN
-X
COUT
On-chip Oscillator
M16C/60 series 16-bit CPU Core
R0LR0H
R1LR1H
R2
R3
A0
A1
FR
R0LR0H
R1LR1H
R2
R3
A0
A1
FB
Registers
SB
PC
ISP
USP
Program Counter
Stack Pointers
INTB
V ector Table
FLG
Flag Register
Memory
Multiplier
Flash ROM
RAM
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I
2
C bus/IEbus
(channel 2)
3-phase PWM
Port P1
3
Port P6
8
Port P7
8
Port P8
8
Port P9
4
Port P10
8
Flash ROM
(Data Flash)
DMAC (2 channels) PLL frequency synthesizer
CRC calculation circuit
(CCITT, CRC-16)
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/26A group, 48-pin device.
Figure 1.1. M16C/26A Group(M16C/26A, M16C/26T), 48-pin version Block Diagram
1. Overview
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Figure 1.2 is a block diagram of the M16C/26A group, 42-pin device.
Figure 1.2. M16C/26A Group(M16C/26A), 42-pin version Block Diagram
I/O
Ports
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
Watchdog Timer
(15bits)
A/D converter
(10bits x 10 channels) U(S)ART/SIO (channel 0)
Serial Ports System Clock Generator
X
IN
-X
OUT
X
CIN
-X
COUT
On-chip Oscillator
M16C/60 series 16-bit CPU Core
R0LR0H
R1LR1H
R2
R3
A0
A1
FR
R0LR0H
R1LR1H
R2
R3
A0
A1
FB
Registers
SB
PC
ISP
USP
Program Counter
Stack Pointers
INTB
V ector Table
FLG
Flag Register
Memory
Multiplier
Flash ROM
RAM
U(S)ART/SIO/I
2
C bus/IEbus
(channel 2)
3-phase PWM
Port P1
3
Port P6
4
Port P7
8
Port P8
8
Port P9
2
Port P10
8
Flash ROM
(Data Flash)
DMAC (2 channels) PLL frequency synthesizer
CRC calculation circuit
(CCITT, CRC-16)
1. Overview
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1.4 Product List
Tables 1.3 to 1.5 list the M16C/26A group products and Figure 1.3 shows the type numbers, memory sizes
and packages. Table 1.6 lists the product code of flash memory version and masked ROM version for
M16C/26A, and figure 1.4 shows the marking diagram of flash memory version and masked ROM version.
Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor
for the product code and the marking diagram of M16C/26T
Table 1.3. Product List (1) -M16C/26A
As of March 2005
Type No. ROM capacity RAM capacity Package type Remarks
M30260M3A-XXXGP (D) 24K byte 1K byte
M30260M6A-XXXGP (D) 48K byte 2K byte 48P6Q
M30260M8A-XXXGP (D) 64K byte 2K byte
M30263M3A-XXXFP (D) 24K byte 1K byte
M30263M6A-XXXFP (D) 48K byte 2K byte 42P2R
M30263M8A-XXXFP (D) 64K byte 2K byte
M30260F3AGP (D) 24K + 4K byte 1K byte
M30260F6AGP (D) 48K + 4K byte 2K byte 48P6Q
M30260F8AGP (D) 64K + 4K byte 2K byte
M30263F3AFP (D) 24K + 4K byte 1K byte
M30263F6AFP (D) 48K + 4K byte 2K byte 42P2R
M30263F8AFP (D) 64K + 4K byte 2K byte
(P) : under planning (D) : under development
Table 1.4. Product List (2) -M16C/26T T-ver.
As of March 2005
(P) : under planning (D) : under development
NOTES. The specification of M16C/26T varies from the one of M16C/26A.
Table 1.5. Product List (3) -M16C/26T V-ver.
As of March 2005
(P) : under planning (D) : under development
NOTES. The specification of M16C/26T varies from the one of M16C/26A.
Mask ROM Version
Flash ROM Version
Type No. ROM capacity RAM capacity Package type Remarks
M30260M3T-XXXGP (P) 24K byte 1K byte
M30260M6T-XXXGP (P) 48K byte 2K byte 48P6Q Mask ROM Version
M30260M8T-XXXGP (P) 64K byte 2K byte
M30260F3TGP (D) 24K + 4K byte 1K byte
M30260F6TGP (D) 48K + 4K byte 2K byte 48P6Q Flash ROM Version
M30260F8TGP (D) 64K + 4K byte 2K byte
Type No. ROM capacity RAM capacity Package type Remarks
M30260M3V-XXXGP (P) 24K byte 1K byte
M30260M6V-XXXGP (P) 48K byte 2K byte 48P6Q Mask ROM Version
M30260M8V-XXXGP (P) 64K byte 2K byte
M30260F3VGP (D) 24K + 4K byte 1K byte
M30260F6VGP (D) 48K + 4K byte 2K byte 48P6Q Flash ROM Version
M30260F8VGP (D) 64K + 4K byte 2K byte
1. Overview
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Package type:
GP : Package 48P6Q (M16C/26A, M16C/26AT)
FP : Package 42P2R (M16C/26A)
Version:
A : M16C/26A
T : M16C/26AT T-ver.
V : M16C/26AT V-ver.
ROM / RAM capacity:
3: (24K+4K) bytes (Note 1) / 1K bytes
6: (48K+4K) bytes (Note 1) / 2K bytes
8: (64K+4K) bytes (Note 1) / 2K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Memory type:
M: Mask ROM version
F: Flash memory version
Type No. M 3 0 2 6 0 M 8 A - XXX G P - U3
M16C/26A Group
M16C Family
Shows pin count,
(The value itself has no specific meaning)
Product code:
See Table 1.6 Product code
ROM number:
ROM number is omitted in flash memory version
Figure 1.3. Type No., Memory Size, and Package
Product
Code Package Internal ROM (Program area)
Program and
Erase Endurance Temperature
Range
Internal ROM (Data area) Operating Ambient
Temperature
Temperature
Range
Lead-free
U3
U5
U7
U9
100
1,000 0°C to 60°C
100
10,000
0°C to 60°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
Program and
Erase Endurance
Product
Code Package Operating Ambient
Temperature
Lead-free
U3
U5
-40°C to 85°C
-20°C to 85°C
Table 1.6 Product Code (Flash Memory version, M16C/26A)
(Mask ROM version, M16C/26A)
Note 1: The lead contained products, D3, D5, D7 and D9, are put together with U3, U5, U7 and U9
respectively. Lead-free (Sn-Cu plating) products can be mounted by both conventional Sn-Pb
paste and Lead-free paste.
1. Overview
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0260F8A
A U3
XXXXX
(1) Flash memory version, 48P6Q, M16C/26A
M30263F8AFP
A U3
XXXXXXX
(2) Flash memory version, 42P2R, M16C/26A
0260M8A
001A U3
XXXXX
(3) MASK ROM version, 48P6Q, M16C/26A
M30263M8A-001FP
A U3
XXXXXXX
(4) MASK ROM version, 42P2R, M16C/26A
Product Name : indicates M30260F8AGP
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates Product code (see Table 1.6 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
Product Name : indicates M30260M8AGP
ROM number, Chip Version and Product Code:
001: Indicates ROM Number
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates Product code (see Table 1.6 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
Product Name : indicates M30263F8AFP
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates Product code (see Table 1.6 Product Code)
Date Code (7 digits) fi indicates manufacturing management code
Product Name and ROM number
M30263M8A and FP are indicated of Produnct name
001 is indicated of ROM number
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates Product code (see Table 1.6 Product Code)
Date Code (7 digits) fi indicates manufacturing management code
Figure 1.4 Marking Diagram (Top Vier, M16C/26A)
1. Overview
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24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
P9
2
/TB2
IN
/AN
32
P9
1
/TB1
IN
/AN
31
CNV
SS
P1
7
/INT
5
/IDU
P1
6
/INT
4
/IDW
P1
5
/INT
3
/AD
TRG
/IDV
P10
7
/AN
7
/KI
3
P7
0
/TxD
2
/TA
0OUT
/SDA
2
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
X
OUT
V
SS
X
IN
P8
5
/NMI/SD
V
CC
P6
7
/TxD
1
P6
6
/RxD
1
P6
5
/CLK
1
RESET
P7
1
/RxD
2
/TA0
IN
/SCL
2
/CLK
1
P7
2
/CLK
2
/TA1
OUT
/V/RxD
1
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V/TxD
1
P7
4
/TA2
OUT
/W
P7
5
/TA2
IN
/W
P7
6
/TA3
OUT
P7
7
/TA3
IN
P8
0
/TA4
OUT
/U
P8
1
/TA4
IN
/U
P8
2
/INT
0
P8
3
/INT
1
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P6
3
/TxD
0
P6
2
/RxD
0
P6
1
/CLK
0
P6
0
/CTS
0
/RTS
0
P9
0
/TB0
IN
/AN
30
/CLK
OUT
P8
7
/X
CIN
P8
6
/X
COUT
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4
/KI
0
P10
3
/AN
3
P10
2
/AN
2
P10
1
/AN
1
AV
ss
P10
0
/AN
0
V
REF
AV
cc
P9
3
/AN
24
P8
4
/INT
2
/ZP
Note. Set PACR2 to PACR0 bit in the PACR register
to "100
2
" before you input and output it after
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the
p
ins are disabled.
Package: 48P6Q
Figure 1.5. Pin Configuration (Top View) of M16C/26A Group, 48-pin Package
PIN CONFIGURATION (top view)(Note)
1.5 Pin Configuration
Figures 1.5 and 1.6 show the pin configurations (top view).
1. Overview
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Figure 1.6. Pin Configuration (Top View) of M16C/26A Group, 42-pin Package
PIN CONFIGURATION (top view)(Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RESET
AV
SS
P10
0
/AN
0
V
REF
X
IN
X
OUT
V
SS
V
CC
P8
6
/X
COUT
P6
5
/CLK
1
P8
3
/INT
1
P8
2
/INT
0
P8
1
/TA4
IN
/U
P8
0
/TA4
OUT
/U
P7
7
/TA3
IN
P7
6
/TA3
OUT
P7
5
/TA2
IN
/W
P7
4
/TA2
OUT
/W
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P7
0
/TxD
2
/SDA
2
/TA0
OUT
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P7
1
/RxD
2
/SCL
2
/TA0
IN
/CLK
1
P7
2
/CLK
2
/TA1
OUT
/V/RxD
1
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V/TxD
1
AV
CC
P9
1
/TB1
IN
/AN
31
P9
0
/TB0
IN
/AN
30
/CLK
out
CNV
SS
P8
7
/X
CIN
P6
6
/RxD
1
P6
7
/TxD
1
P8
5
/NMI/SD
P8
4
/INT
2
/ZP
P1
7
/INT
5
/IDU
P1
6
/INT
4
/IDW
P1
5
/INT
3
/AD
TRG
/IDV
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4
/KI
0
P10
3
/AN
3
P10
2
/AN
2
P10
1
/AN
1
Note. Set PACR2 to PACR0 bit in the PACR register
to "001
2
" before you input and output it after
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the
p
ins are disabled.
Package: 42P2R
1. Overview
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Table 1.7. Pin Description(1)
1.6 Pin Description
Table 1.7 and 1.8 describes the available pins.
Pin name Signal name I/O type Function
VCC,VSS Power supply Apply 0V to the Vss pin, and the following voltage to the Vcc pin.
input 2.7 to 5.5V (M16C/26A)
3.0 to 5.5V (M16C/26T T-ver.)
4.2 to 5.5V (M16C/26T V-ver.)
CNVSS CNVSS Input Connect this pin to Vss.
____________
RESET Reset input Input "L" on this input resets the microcomputer.
XIN Clock input Input These pins are provided for the main clock generating circuit input/output.
XOUT Clock output Output Connect a ceramic resonator or crystal between the XIN and the XOUT pins.
To use an externally derived clock, input it to the XIN pin and leave the XOUT
pin open. If XIN is not used (for external oscillator or external clock)
connect XIN pin to VCC and leave XOUT pin open.
AVCC Analog power This pin is a power supply input for the A/D converter. Connect this
supply input pin to VCC.
AVSS Analog power This pin is a power supply input for the A/D converter. Connect this
supply input pin to VSS.
VREF Reference Input This pin is a reference voltage input for the A/D converter.
Voltage input
P15~P17I/O port P1 Input/ This is an 3-bit CMOS I/O port. It has an input/output port direction
output register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
entire group of three pins. Additional software selectable secondary
______
functions are: 1) P15 to P17 can be configured as external INT interrupt
pins; 2) P15 to P17 can be configured as position-data-retain function
input pins,and; 3) P15 can input a trigger for the A/D converter.
P60~P67I/O port P6 Input/ This is an 8-bit CMOS I/O port. It has an input/output port direction
output register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
entire group of four pins. Pins in this port also function as UART0 and
UART1 I/O, as selected by software. P60 to P63 are not available in the 42
pin version.
P70~P77I/O port P7 Input/ This is an 8-bit I/O port equivalent to P6. P7 can also function as I/O for
output timer A0 to A3, as selected by software. Additional programming options
are: P70 to P73 can assume UART1 I/O or UART2 I/O capabilities, and
P72 to P75 can function as output pins for the three-phase motor control
timer.
1. Overview
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Table 1.8. Pin Description(2)
Pin name Signal name I/O type Function
P80~P87I/O port P8 Input/ This is an 8-bit I/O port equivalent to P6. Additional software-selectable
output secondary functions are: 1) P80 and P81 can act as either I/O for Timer
A4, or as output pins for the three-phase motor control timer; 2) P82 to
______
P84 can be configured as external INT interrupt pins. P84 can be used for
_______ _____
Timer A Zphase function; 3) P85 can be used as NMI/SD. P85 can not be
used as I/O port while the three-phase motor control is enabled. Apply a
stable "H" to P85 after setting the direction register for P85 to "0" when
the three-phase motor control is enabled, and; 4) P86 and P87 can serve
as I/O pins for the sub-clock generation circuit. In this latter case, a quartz
oscillator must be connented between P86 (XCOUT pin) and P87 (XCIN pin).
P90~P93I/O port P9 Input/ This is an 4-bit I/O port equivalent to P6. Additional software-selectable
output secondary functions are: 1) P90 to P92 can act as Timer B0 to B2 input
pins, and; 2) P90 to P93 can act as A/D converter input pins.
P90 outputs a no-divide, divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program. P92 to P93
are not available in the 42 pin version.
P100~P107I/O port P10 Input/ This is an 8-bit I/O port equivalent to P6. This port can also function as
output A/D converter input pins, as selected by software. Furthermore, P104 to
P107 can also function as input pins for the key input interrupt function.
2. Central Processing Unit(CPU)
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Data registers (Note)
Address registers (Note)
Frame base registers (Note)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Note: These registers comprise a register bank. There are two register banks.
R0H(R0's high bits)
b15 b8 b7 b0
R3
INTBH
USP
ISP
SB
AA
AA
A
A
AA
AA
AA
AA
AAAAAA
AAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL
R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15 b0
PC
b19 b0
b15 b0
FLG
b15 b0
b15 b0
b7 b8
Reserved area
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
2. Central Processing Unit(CPU)
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2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to
“1”
when an arithmetic operation resulted in a negative value; otherwise, it is
“0”
.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
3. Memory
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3. Memory
Figure 3.1 is a memory map. The linear address space of 1M bytes extends from address 0000016 to
FFFFF16. The internal ROM is allocated in a lower address direction beginning with address FFFFF16 . For
example, a 64-Kbyte internal ROM is allocated to the address from F000016 to FFFFF16.
In the flash memory version, internal ROM area (data area) contain two blocks of Flash ROM as data area
to store data. These two blocks of 2K bytes are located from 0F00016 to 0FFFF16.
The fixed interrupt vector table is allocated to the address from FFFDC16 to FFFFF16. Therefore store the
start address of each interrupt routine here. For details, refer to the "Interrupt".
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the address from 0040016 to 007FF16. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the address from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software
Manual".
Figure 3.1. Memory Map
SFR
Internal RAM
Reserved area
Internal ROM
(Program area)
(Note 2)
Reset
Watchdog timer
Single step
Address match
BRK instruction
Overflow
Undefined Instruction
Special page
vector table
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
FFFFF
16
FFFDC
16
FFE00
16
DBC
NMI
Internal ROM
(Data area)
(Note 1)
0F000
16
0FFFF
16
Reserved area
Note 1: Shown here is a Block A (2K bytes) and Block B (2K bytes).
(in the flash memory version)
Note 2: When using the masked ROM version, write nothing to
internal ROM area.
Size Address YYYYY
16
Size Address XXXXX
16
Internal RAM Intrnal ROM
2K byte 00BFF
16
48K byte F4000
16
64K byte F0000
16
1K byte 007FF
16
24K byte FA000
16
4. Special Function Register (SFR)
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4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Table 4.1 to 4.6 list the SFR
information.
Table 4.1 SFR information (1)
Processor mode register 0 PM0 00
16
Processor mode register 1 PM1 00001000
2
System clock control register 0 CM0 01001000
2
(M16C/26A)
01101000
2
(M16C/26T)
System clock control register 1 CM1 00100000
2
Address match interrupt enable register AIER XXXXXX00
2
Protect register PBCR XX000000
2
Oscillation stop detection register (Note 2) CM2 0X000010
2
Watchdog timer start register WDTS XX
16
Watchdog timer control register WDC 00XXXXXX
2
(Note3)
Address match interrupt register 0 RMAD0 00
16
00
16
X0
16
Address match interrupt register 1 RMAD1 00
16
00
16
X0
16
Voltage detection register 1 (Note 4,5) VCR1 00001000
2
Voltage detection register 2 (Note 4,5) VCR2 00
16
PLL control register 0 PLC0 0001X010
2
Processor mode register 2 PM2 XXX00000
2
Voltage down detection interrupt register (Note 5) D4INT 00
16
DMA0 source pointer SAR0 XX
16
XX
16
XX
16
DMA0 destination pointer DAR0 XX
16
XX
16
XX
16
DMA0 transfer counter TCR0 XX
16
XX
16
DMA0 control register DM0CON 00000X00
2
DMA1 source pointer SAR1 XX
16
XX
16
XX
16
DMA1 destination pointer DAR1 XX
16
XX
16
XX
16
DMA1 transfer counter TCR1 XX
16
XX
16
DMA1 control register DM1CON 00000X00
2
Note 1: Blank spaces are reserved. No access is allowed.
Note 2: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset..
Note 3: The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program.
The WDC5 bit is not supported for M16C/26T.
Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 5: This register is not supported for M16C/26T.
X : Indeterminate
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Address Register Symbol After reset
4. Special Function Register (SFR)
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Note 1: Blank spaces are reserved. No access is allowed.
X : Indeterminate
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Address Register Symbol After reset
INT3 interrupt control register INT3IC XX00X000
2
INT5 interrupt control register INT5IC XX00X000
2
INT4 interrupt control register INT4IC XX00X000
2
UART2 Bus collision detection interrupt control register BCNIC XXXXX000
2
DMA0 interrupt control register DM0IC XXXXX000
2
DMA1 interrupt control register DM1IC XXXXX000
2
Key input interrupt control register KUPIC XXXXX000
2
A/D conversion interrupt control register ADIC XXXXX000
2
UART2 transmit interrupt control register S2TIC XXXXX000
2
UART2 receive interrupt control register S2RIC XXXXX000
2
UART0 transmit interrupt control register S0TIC XXXXX000
2
UART0 receive interrupt control register S0RIC XXXXX000
2
UART1 transmit interrupt control register S1TIC XXXXX000
2
UART1 receive interrupt control register S1RIC XXXXX000
2
TimerA0 interrupt control register TA0IC XXXXX000
2
TimerA1 interrupt control register TA1IC XXXXX000
2
TimerA2 interrupt control register TA2IC XXXXX000
2
TimerA3 interrupt control register TA3IC XXXXX000
2
TimerA4 interrupt control register TA4IC XXXXX000
2
TimerB0 interrupt control register TB0IC XXXXX000
2
TimerB1 interrupt control register TB1IC XXXXX000
2
TimerB2 interrupt control register TB2IC XXXXX000
2
INT0 interrupt control register INT0IC XX00X000
2
INT1 interrupt control register INT1IC XX00X000
2
INT2 interrupt control register INT2IC XX00X000
2
Table 4.2 SFR information (2)(1)
4. Special Function Register (SFR)
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0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
01B0
16
01B1
16
01B2
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
0250
16
0251
16
0252
16
0253
16
0254
16
0255
16
0256
16
0257
16
0258
16
0259
16
025A
16
025B
16
025C
16
025D
16
025E
16
025F
16
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
16
033F
16
Note 1: Blank spaces are reserved. No access is allowed.
Note 2: This register is included in the flash memory version.
X : Indeterminate
Address Register Symbol After reset
Flash memory control register 4 (Note 2) FMR4 01000000
2
Flash memory control register 1 (Note 2) FMR1 000XXX0X
2
Flash memory control register 0 (Note 2) FMR0 01
16
Three phase protect control register TPRC 00
16
On-chip oscillator control register ROCR 00000101
2
Pin assignment control register PACR 00
16
Peripheral clock select register PCLKR 00000011
2
NMI digital debounce register NDDR FF
16
Port1
7
digital debounce register P17DDR FF
16
~
~
~
~
~
~
~
~
~
~
~
~
Table 4.3 SFR information (3)(1)
4. Special Function Register (SFR)
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Address Register Symbol After reset
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
Note 1 : Blank spaces are reserved. No access is allowed.
X : Indeterminate
Timer A1-1 register TA11 XX
16
XX
16
Timer A2-1 register TA21 XX
16
XX
16
Timer A4-1 register TA41 XX
16
XX
16
Three phase PWM control register 0 INVC0 00
16
Three phase PWM control register 1 INVC1 00
16
Three phase output buffer register 0 IDB0 3F
16
Three phase output buffer register 1 IDB1 3F
16
Dead time timer DTT XX
16
Timer B2 Interrupt occurrence frequency set counter ICTB2 XX
16
Position-data-retain function control register PDRF XXXX0000
2
Port function control register PFCR 00111111
2
Interrupt request cause select register 2 IFSR2A XXXXXXX0
2
Interrupt request cause select register IFSR 00
16
UART2 special mode register 4 U2SMR4 00
16
UART2 special mode register 3 U2SMR3 000X0X0X
2
UART2 special mode register 2 U2SMR2 X0000000
2
UART2 special mode register U2SMR X0000000
2
UART2 transmit/receive mode register U2MR 00
16
UART2 bit rate register U2BRG XX
16
UART2 transmit buffer register U2TB XXXXXXXX
2
XXXXXXXX
2
UART2 transmit/receive control register 0 U2C0 00001000
2
UART2 transmit/receive control register 1 U2C1 00000010
2
UART2 receive buffer register U2RB XXXXXXXX
2
XXXXXXXX
2
Table 4.3 SFR information (4)(1)
4. Special Function Register (SFR)
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0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
Note 1 : Blank spaces are reserved. No access is allowed.
X : Indeterminate
Address Register Symbol After reset
Count start flag TABSR 00
16
Clock prescaler reset flag CPSRF 0XXXXXXX
2
One-shot start flag ONSF 00
16
Trigger select register TRGSR 00
16
Up-dowm flag UDF 00
16
Timer A0 register TA0 XX
16
XX
16
Timer A1 register TA1 XX
16
XX
16
Timer A2 register TA2 XX
16
XX
16
Timer A3 register TA3 XX
16
XX
16
Timer A4 register TA4 XX
16
XX
16
Timer B0 register TB0 XX
16
XX
16
Timer B1 register TB1 XX
16
XX
16
Timer B2 register TB2 XX
16
XX
16
Timer A0 mode register TA0MR 00
16
Timer A1 mode register TA1MR 00
16
Timer A2 mode register TA2MR 00
16
Timer A3 mode register TA3MR 00
16
Timer A4 mode register TA4MR 00
16
Timer B0 mode register TB0MR 00XX0000
2
Timer B1 mode register TB1MR 00XX0000
2
Timer B2 mode register TB2MR 00XX0000
2
Timer B2 special mode register TB2SC X0000000
2
UART0 transmit/receive mode register U0MR 00
16
UART0 bit rate register U0BRG XX
16
UART0 transmit buffer register U0TB XXXXXXXX
2
XXXXXXXX
2
UART0 transmit/receive control register 0 U0C0 00001000
2
UART0 transmit/receive control register 1 U0C1 00000010
2
UART0 receive buffer register U0RB XXXXXXXX
2
XXXXXXXX
2
UART1 transmit/receive mode register U1MR 00
16
UART1 bit rate register U1BRG XX
16
UART1 transmit buffer register U1TB XXXXXXXX
2
XXXXXXXX
2
UART1 transmit/receive control register 0 U1C0 00001000
2
UART1 transmit/receive control register 1 U1C1 00000010
2
UART1 receive buffer register U1RB XXXXXXXX
2
XXXXXXXX
2
UART transmit/receive control register 2 UCON X0000000
2
CRC snoop address register CRCSAR XX
16
00XXXXXX
2
CRC mode register CRCMR 0XXXXXX0
2
DMA0 request cause select register DM0SL 00
16
DMA1 request cause select register DM1SL 00
16
CRC data register CRCD XX
16
XX
16
CRC input register CRCIN XX
16
Table 4.3 SFR information (5)(1)
4. Special Function Register (SFR)
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03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Note 1 : Blank spaces are reserved. No access is allowed.
X : Indeterminate
Register Symbol After reset
A/D register 0 AD0 XXXXXXXX2
XXXXXXXX2
A/D register 1 AD1 XXXXXXXX2
XXXXXXXX2
A/D register 2 AD2 XXXXXXXX2
XXXXXXXX2
A/D register 3 AD3 XXXXXXXX2
XXXXXXXX2
A/D register 4 AD4 XXXXXXXX2
XXXXXXXX2
A/D register 5 AD5 XXXXXXXX2
XXXXXXXX2
A/D register 6 AD6 XXXXXXXX2
XXXXXXXX2
A/D register 7 AD7 XXXXXXXX2
XXXXXXXX2
A/D trigger control register ADTRGCON 0016
A/D status register 0 ADSTAT0 00000X002
A/D control register 2 ADCON2 0016
A/D control register 0 ADCON0 00000XXX2
A/D control register 1 ADCON1 0016
Port P1 register P1 XX16
Port P1 direction register PD1 0016
Port P6 register P6 XX16
Port P7 register P7 XX16
Port P6 direction register PD6 0016
Port P7 direction register PD7 0016
Port P8 register P8 XX16
Port P9 register P9 XXXXXXXX2
Port P8 direction register PD8 0016
Port P9 direction register PD9 XXXX00002
Port P10 register P10 XX16
Port P10 direction register PD10 0016
Pull-up control register 0 PUR0 0016
Pull-up control register 1 PUR1 0016
Pull-up control register 2 PUR2 0016
Port control register PCR 0016
Address
Table 4.3 SFR information (6)(1)
5. Reset
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5. Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-
tion stop detection reset.
5.1 Hardware Reset
There are two types of hardware resets: a hardware reset 1 and a hardware reset 2.
5.1.1 Hardware Reset 1 ____________ ____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
____________
Table 5.1.1.1 Pin Status When RESET Pin Level is “L”). The internal on-chip oscillator is initialized
and used as sysem clock. ____________
When the input level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized,
and the program is executed starting from the address indicated by the reset vector. The internal RAM
____________
is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM
becomes indeterminate.
Figure 5.1.1.1 shows the example reset circuit. Figure 5.1.1.2 shows the reset sequence. Table
____________
5.1.1.1 shows the status of the other pins while the RESET pin is “L”. Figure 5.1.1.3 shows the CPU
register status after reset. Refer to “SFR Map” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Wait td(ROC) or more. ____________
(3) Apply an “H” signal to the RESET pin.
2. Power on ____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait td(ROC) or more. ____________
(5) Apply an “H” signal to the RESET pin.
5.1.2 Hardware Reset 2
Note
M16C/26T does not use this function.
This reset is generated by the microcomputer’s internal voltage detection circuit. The voltage detec-
tion circuit monitors the voltage supplied to the VCC pin.
If the VC26 bit in the VCR2 register is set to “1” (reset level detection circuit enabled), the microcom-
puter is reset when the voltage at the VCC input pin drops below Vdet3.
Conversely, when the input voltage at the VCC pin rises to Vdet3r or more, the pins and the CPU and
SFR are initialized, and the program is executed starting from the address indicated by the reset
vector. It takes about td(S-R) before the program starts running after Vdet3r is detected. The initialized
pins and registers and the status thereof are the same as in hardware reset 1.
The microcomputer cannot exit stop mode by voltage down detection reset (hardware reset 2).
5. Reset
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5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
The device will reset using on-chip oscillator as the system clock.
At software reset, some SFR’s are not initialized. Refer to “SFR”.
5.3 Watchdog Timer Reset
When the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer
initializes its pins, CPU and SFR if the watchdog timer underflows.
The device will reset using on-chip oscillator as the system clock. Then the program is executed starting
from the address indicated by the reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”.
5.4 Oscillation Stop Detection Reset
When the CM20 bit in the CM2 register is set to “1”(oscillation stop, re-oscillation detection function
enabled) and the CM27 bit is set to “0” (reset at oscillation stop detection), the microcomputer initializes
its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to the section
“oscillation stop, re-oscillation detection function”.
At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”.
Figure 5.1.1.1. Example Reset Circuit
RESET V
CC
RESET
V
CC
0V
0V
More than td(ROC) + td(P-R)
Equal to or less
than 0.2V
CC
Equal to or less
than 0.2V
CC
Recommended
operating
voltage
5. Reset
page 24
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
____________
Table 5.1.1.1. Pin Status When RESET Pin Level is “L”
Status
Pin name
P1, P6 to P10 Input port (high impedance)
Figure 5.1.1.3. CPU Register Status After Reset
b15 b0
Data register(R0)
Address register(A0)
Frame base register(FB)
Program counter(PC)
Interrupt table register(INTB)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Flag register(FLG)
0000
16
0000
16
0000
16
AA
AA
A
A
AA
AA
AA
AA
AAAAAA
AAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL
0000
16
0000
16
0000
16
0000
16
0000
16
b19 b0
Content of addresses FFFFE
16
to FFFFC
16
b15 b0
b15 b0
b15 b0
b7 b8
00000
16
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A1)
0000
16
0000
16
0000
16
Figure 5.1.1.2. Reset Sequence
td(P-R)
More than
td(ROC)
CPU clock
Address
ROC
RESET
content of reset vector
CPU clock 28cycles
FFFFE
16
FFFFC
16
V
CC
5. Reset
page 25
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Figure 5.5.1. Voltage Detection Circuit Block
b
7 b
6
V
C
R
2
R
e
g
i
s
t
e
r
R
E
S
E
T
CM10 Bit=1
(Stop Mode)
+
≥
V
d
e
t
3
+
≥Vdet4
ENoise Rejection V
o
l
t
a
g
e
D
o
w
n
D
e
t
e
c
t
S
i
g
n
a
l
b3
V
C
R
1
R
e
g
i
s
t
e
r
V
C
1
3
B
i
t
Write to WDC register S
R
QW
A
R
M
/
C
O
L
D
>T
Q
1
s
h
o
t
Internal Reset Signal
(“L” active)
W
D
C
5
B
i
t
E
(
C
o
l
d
s
t
a
r
t
,
w
a
r
m
s
t
a
r
t
)
V
C
C
Internal power on reset
t
d
(
S
-
R
)
Voltage Down Detect Reset
(Hardware Reset 2
Release Wait Time)
5.5 Voltage Detection Circuit
Note
Using the voltage detection circuit with VCC=5V is assumed. The M16C/26T do not use this function.
The voltage detection circuit has circuits to monitor the input voltage at the VCC pin, each checking the input
voltage with respect to Vdet3, and Vdet4, respectively. Use the VC26 to VC27 bits in the VCR2 register to
select whether or not to enable these circuits.
Use the reset level detection circuit for hardware reset 2.
The voltage down detection circuit can be set to detect whether the input voltage is equal to or greater than
Vdet4 or less than Vdet4 by monitoring the VC13 bit in the VCR1 register. Furthermore, a voltage down
detection interrupt can be generated.
5. Reset
page 26
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Figure 5.5.2. VCR1 Register, VCR2 Register, and D4INT Register
V
C
1
3
V
o
l
t
a
g
e
d
e
t
e
c
t
i
o
n
r
e
g
i
s
t
e
r
1
Symbol Address After reset (Note 2)
VCR1 0019
16
00001000
2
V
o
l
t
a
g
e
d
o
w
n
m
o
n
i
t
o
r
f
l
a
g
(
N
o
t
e
1
)
Bit name Function
B
i
t
s
y
m
b
o
lRW
b
7b
6b
5b
4b
3b2b
1b
0
Note 1: The VC13 bit is useful when the VC27 bit of VCR2 register is set to “1” (voltage down detection circuit
enable). The VC13 bit is always “1” (V
CC
≥ Vdet4) when the VC27 bit in the VCR2 register is set to “0” (voltage
down detection circuit disable).
Note 2: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
0
:
V
C
C
<
V
d
e
t
4
1
:
V
C
C
≥
V
d
e
t
4RO
0000 000
RW
RW
Reserved bit
Reserved bit
M
u
s
t
se
t
t
o
“
0
”
M
u
s
t
s
e
t
t
o
“
0
”
V
o
l
t
a
g
e
d
e
t
e
c
t
i
o
n
r
e
g
i
s
t
e
r
2
(
N
o
t
e
1
)
Symbol Address After reset (Note 5)
VCR2 001A
16
00
16
Bit name
B
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b2b
1b
0
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
Note 3: VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc pin
becomes lower than Vdet3.)
Note 4: When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1”
(voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
Note 5: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 6: The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit are set to “1”.
V
C
2
6
V
C
2
7
RW
RW
RW
RW
00000
Function
Reserved bit M
u
s
t
s
e
t
t
o
“
0
”
Re
s
e
t
l
e
v
e
l
m
o
n
i
t
o
r
b
i
t
(
N
o
t
e
s
2
,
3
,
6
)0: Disable reset level detection
circuit
1: Enable reset level detection
circuit
V
o
l
t
a
g
e
d
o
w
n
m
o
n
i
t
o
r
b
i
t
(
N
o
t
e
4
,
6
)0: Disable voltage down
detection circuit
1: Enable voltage down
detection circuit
(
b
2
-
b
0
)
(
b
7
-
b
4
)
(
b
5
-
b
0
)
0
D40
V
o
l
t
a
g
e
d
o
w
n
d
e
t
e
c
t
i
o
n
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
(
N
o
t
e
1
)
Symbol Address After reset
D4INT 001F
16
00
16
V
o
l
t
a
g
e
d
o
w
n
d
e
t
e
c
t
i
o
n
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
N
o
t
e
5
)
Bit name
B
i
t
s
y
m
b
o
l
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
0 : Disable
1 : Enable
D41 S
T
O
P
m
o
d
e
d
e
a
c
t
i
v
a
t
i
o
n
c
o
n
t
r
o
l
b
i
t
(
N
o
t
e
4
)
0
:
D
i
s
a
b
l
e
(
d
o
n
o
t
u
s
e
t
h
e
v
o
l
t
a
g
e
d
o
w
n
d
e
t
e
c
t
i
o
n
i
n
t
e
r
r
u
p
t
t
o
g
e
t
o
u
t
o
f
s
t
o
p
m
o
d
e
)
1
:
E
n
a
b
l
e
(
u
s
e
t
h
e
v
o
l
t
a
g
e
d
o
w
n
d
e
t
e
c
t
i
o
n
i
n
t
e
r
r
u
p
t
t
o
g
e
t
o
u
t
o
f
s
t
o
p
m
o
d
e
)
D42 V
o
l
t
a
g
e
c
h
a
n
g
e
d
e
t
e
c
t
i
o
n
f
l
a
g
(
N
o
t
e
2
)0: Not detected
1: Vdet4 passing detection
D43 W
D
T
o
v
e
r
f
l
o
w
d
e
t
e
c
t
f
l
a
g0: Not detected
1: Detected
DF0 S
a
m
p
l
i
n
g
c
l
o
c
k
s
e
l
e
c
t
b
i
t00 : CPU clock divided by 8
01 : CPU clock divided by 16
10 : CPU clock divided by 32
11 : CPU clock divided by 64
DF1
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
Note 3: This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
Note 4: If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
Note 5: The D40 bit is effective when the VC27 bit in the VCR2 register is set to “1”. To set the D40 bit to “1”,
follow the procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).
(4) Set the D40 bit to “1”.
b
5
b
4
RW
RW
RW
RW
(
N
o
t
e
3
)
RW
R
W
R
W
(b7-b6)
Function
(
N
o
t
e
3
)
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
W
h
e
n
w
r
i
t
e
,
s
e
t
t
o
“
0
”
.
W
h
e
n
r
e
a
d
,
i
t
s
c
o
n
t
e
n
t
i
s
“
0
”
.
5. Reset
page 27
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Figure 5.5.3. Typical Operation of Hardware Reset 2
Vdet4
Vdet3
5.0V 5.0V
VCC
Internal Reset Signal
VC13 bit in
VCR1 register
VC26 bit in
VCR2 register
(1)
VC27 bit in
VCR2 register
Set to “1” by program (reset level detect circuit enable)
Set to “1” by program
(voltage down detect circuit enable)
VSS
Indefinite
Indefinite
Indefinite
RESET
Vdet3s
Vdet3r
NOTES :
1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC pin
becomes lower than Vdet3).
5. Reset
page 28
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5.5.1 Voltage Down Detection Interrupt
If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage
down detection interrupt request is generated when the voltage applied to the VCC pin crosses the
Vdet4 voltage level. The voltage down detection interrupt shares the same interrupt vector with the
watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the voltage down detection interrupt to exit
stop mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC pin reaches
Vdet4 due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the voltage down
detection interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41
bit is set to “1” and the microcomputer is in stop mode, the voltage down detection interrupt request is
generated regardless of the D42 bit state if the voltage applied to the VCC pin is detected to be above
Vdet4. The microcomputer then exits stop mode.
Table 5.5.1.1 shows how the voltage down detection interrupt request is generated.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage
applied to the VCC pin reaches Vdet4. Table 5.5.1.2 shows the sampling periods.
CPU
Clock
(MHz) DF1 to DF0=00
(CPU clock divided by 8)
Sampling Period (µs)
16 3.0 6.0 12.0 24.0
DF1 to DF0=01
(CPU clock divided by 16) DF1 to DF0=10
(CPU clock divided by 32) DF1 to DF0=11
(CPU clock divided by 64)
Table 5.5.1.1 Voltage Down Detection Interrupt Request Generation Conditions
D41 BitVC27 BitOperation Mode D40 Bit D42 Bit CM02 Bit VC13 Bit
Normal
Operation
Mode(1)
Wait Mode(2)
Stop Mode(2)
NOTES:
1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 7. Clock generating circuit)
2. Refer to 5.5.2 Limitations on stop mode, 5.5.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
See the Figure 5.5.1.2 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.
0 to 1(3)
10
1
1
0
1 to 0(3)
0 to 1(3)
1 to 0(3)
0 to 1
0 to 1
0 to 1
0 to 1
1
– : “0”or “1”
Table 5.5.1.2 Sampling Periods
5. Reset
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Figure 5.5.1.1 Power Supply Down Detection Interrupt Generation Block
Figure 5.5.1.2 Power Supply Down Detection Interrupt Generation Circuit Operation Example
Output of the digital filter (2)
D42 bit in D4INT register
NOTES :
1. D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled).
2. Output of the digital filter is shown in Figure 5.5.1.1.
Voltage down detection
interrupt signal
No voltage down detection interrupt signals are
generated when the D42 bit is “H”.
sampling
VC13 bit in VCR1 register
VCC
sampling sampling sampling
Set to “0” by program (not detected)
Voltage down detection interrupt generation circuit
Watchdog
timer interrupt
signal
VC27
VC13
Voltage Down Detection Circuit
D4INT clock(the
clock with which it
operates also in
wait mode)
D42
DF1, DF0
1/2
00b
01b
10b
11b
1/2
1/21/8
Non-maskable
interrupt signal
Oscillation stop,
re-oscillation
detection
interrupt signal
Voltage down
detection
interrupt signal
Watchdog Timer Block
This bit is set to “0”(not detected) by program.
Watchdog timer
underflow signal
D43
D41
CM02
WAIT instruction(wait mode)
D40
VCC
VREF
+
-
Noise
Rejection
(Rejection Range:200 ns)
Voltage down
detection signal
The Voltage down detection
signal becomes “H” when the
VC27 bit is set to “0” (disabled)
Noise Rejection
Circuit Digital
Filter
CM10
The D42 bit is set to “0” (not detected)
by program. the VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.
5. Reset
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5.5.2 Limitations on Exiting Stop Mode
The voltage down detection interrupt is immediately generated and the microcomputer exits stop
mode if the CM10 bit in the CM1 register is set to “1” under the conditions below.
• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit stop
mode), and
• the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)
If the microcomputer is set to enter stop mode when the voltage applied to the VCC pin drops below
Vdet4 and to exit stop mode when the voltage applied rises to Vdet4 or above, set the CM10 bit to “1”
when VC13 bit is “0” (VCC < Vdet4).
5.5.3 Limitations on Exiting Wait Mode
The voltage down detection interrupt is immediately generated and the microcomputer exits wait
mode If WAIT instruction is executed under the conditions below.
• the CM02 bit in the CM0 register is set to “1” (stop peripheral function clock),
• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit wait
mode), and
• the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)
If the microcomputer is set to enter wait mode when the voltage applied to the VCC pin drops below
Vdet4 and to exit wait mode when the voltage applied rises to Vdet4 or above, perform WAIT instruc-
tion when VC13 bit is “0” (VCC < Vdet4).
6. Processor Mode
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6. Processor Mode
This device functions in single-chip mode only. Figures 6.1 and 6.2 detail the associated registers.
Figure 6.2. PM1 Register
Processor mode register 1 (Note 1)
Symbol Address After reset
PM1 000516 000010002
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Flash data block access
bit (Note 2) 0: Disabled
1: Enabled (Note 3)
PM10
RW
PM17 Wait bit (Note 5) 0 : No wait state
1 : With wait state (1 wait)
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
Watchdog timer function
select bit
PM12
RW
RW
RW
RW
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: To access the two 2K-byte data areas in data block A and data block B, this bit must be set to "1".
Note 3: When CPU rewrite mode (FMR01="1"), this bit is automatically set to "1" during that time.
Note 4: PM12 bit is set to 1 by writing a 1 in a program. (Writing a 0 has no effect.)
Note 5: When PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM or
the internal ROM.
Should be set to "0".
(b1) Reserved bit
Should be set to "1".Reserved bit
Should be set to "0".
(b6-b4) Reserved bit
(b3)
010
00
Figure 6.1. PM0 Register
Processor mode register 0 (Note)
Symbol Address After reset
PM0 000416 000000002
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Setting this bit to "1" resets the
microcomputer.
When read, its content is "0".
Software reset bitPM03
RW
RW
RW
Note: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Should be set to "0".
(b2-b0) Reserved bit
Should be set to "0".
(b7-b4) Reserved bit
0000000
7. Clock Generation Circuit
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• CPU clock source
• Peripheral function
clock source
Use of clock
Main clock
oscillation circuit Sub clock
oscillation circuit
Item
• CPU clock source
• Timer A, B’s clock
source
Clock frequency 0 to 20 MHz 32.768 kHz
• Ceramic oscillator
• Crystal oscillator
Usable oscillator • Crystal oscillator
X
IN
, X
OUT
Pins to connect
oscillator X
CIN
, X
COUT
Presence
Oscillation stop,
restart function Presence
Oscillating(M16C/26A)
Stopped(M16C/26T)
Oscillator status
after reset Stopped
Externally derived clock can be input
Other
PLL frequency
synthesizer
10 to 20 MHz
Presence
Stopped
On-chip oscillator
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function
clock sources when the main
clock stops oscillating
• Selectable source frequency:
f
1(ROC)
, f
2(ROC)
, f
3(ROC)
• Selectable divider:
by 2, by 4, by 8
Presence
Oscillating
• CPU clock source
• Peripheral function clock
source
(CPU clock source)
7. Clock Generation Circuit
The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) On-chip oscillator (available at reset, oscillation stop detect function)
(4) PLL frequency synthesizer
Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit.
Figures 7.2 to 7.6 show the clock-related registers.
Table 7.1. Clock Generation Circuit Specifications
7. Clock Generation Circuit
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f
C3
2
CM00, CM01, CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1, PCLK5: PCLKR register bits
CM21, CM27 : CM2 register bits
1/32
Main clock
generating circuit
f
C
CM02
CM04
CM10=1(stop mode) Q
S
R
WAIT instruction
CM05
QS
R
NMI
Interrupt request level judgment output
RESET
Software reset
f
C
CPU clock
CM07
=
0
CM07
=
1
a
d
1/2 1/2 1/2 1/2
CM06=0
CM17-CM16=00
2
CM06=0
CM17-CM16=01
2
CM06=0
CM17-CM16=10
2
CM06=1
CM06=0
CM17-CM16=11
2
d
a
Details of divider
Sub-clock
generating circuit
X
CIN
X
COUT
X
OUT
X
IN
f
8
f
32
c
b
b
1/2
c
f
32SIO
f
8S
I
O
f
AD
f
1
e
e
1/2 1/4 1/8 1/16 1/32
P
C
LK
0
=
1
PLL
frequency
s
y
nt
h
es
i
z
e
r
0
1
C
M21=
1
C
M11
C
M21=
0
PL
L
cloc
k
Sub-clock
O
n-chi
p
oscillato
r
cloc
k
P
C
LK
0
=
0
f
2
f
1
S
I
O
P
C
LK1=1
P
C
LK1=
0
f
2
S
I
O
Main
clock
Oscillation
stop, re-
oscillation
detection
circuit
D4INT clock
CLK
OUT
I/O ports PCLK5=0,CM01-CM00=00
2
PCLK5=0,CM01-CM00=01
2
PCLK5=1,
CM01-CM00=00
2
PCLK5=0,
CM01-CM00=10
2
PCLK5=0,
CM01-CM00=11
2
CM21
Figure 7.1. Clock Generation Circuit
Phase
comparator Charge
pump
Voltage
control
oscillator
(VCO)
PLL clock
Main clock
1/2
Programmable
counter
Internal low-
pass filter
PLL frequency synthesizer
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
Charge,
discharge
circuit
Reset
generating
circuit
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Main
clock
Oscillation stop
detection reset
CM27=0
CM21 switch signal
Oscillation stop,
re-oscillation
detection signal
Oscillation stop, re-oscillation detection circuit
CM27=1
1/2 1/2 1/2
ROCR3-ROCR2=11
2
On-chip
oscillator
clock
1/8
1/4
1/2
ROCR3-ROCR2=10
2
ROCR3-ROCR2=01
2
ROCR1-ROCR0=00
2
f
1(ROC)
f
2(ROC)
f
3(ROC)
ROCR1-ROCR0=01
2
ROCR1-ROCR0=11
2
On-chip Oscillator
7. Clock Generation Circuit
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System clock control register 0 (Note 1)
Symbol Address After reset
CM0 000616
01001000
2
(M16C/26A)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM07
CM05
CM04
CM03
CM02
CM06
WAIT peripheral function
clock stop bit (Note 10) 1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2) 1 : HIGH
Main clock stop bit
(Notes 3, 10, 12, 13) 0 : On
1 : Off (Note 4, Note5)
Main clock division select
bit 0 (Notes 7, 13, 14) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Notes 6, 10, 11, 12)
0 : Main clock, PLL clock, or ring oscillator clock
1 : Sub-clock
Note 1: Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
Note 2: The CM03 bit is set to "1" (high) when the CM04 bit is set to "0" (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipation mode
is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the
following setting is required:
(1) Set the CM07 bit to "1" (Sub-clock select) or the CM21 bit in the CM2 register to "1" (Ring oscillator select) with the
sub-clock stably oscillating.
(2) Set the CM20 bit in CM2 register to "0" (Oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to "1" (Stop).
Note 4: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted.
Note 5: When CM05 bit is set to "1", the X
OUT
pin goes ìHî. Furthermore, because the internal feedback resistor remains connected,
the X
IN
pin is pulled "H" to the same level as X
OUT
via the feedback resistor.
Note 6: After setting the CM04 bit to "1" (X
CIN
-X
COUT
oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from "0" to "1" (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the CM06
bit is set to "1" (divide-by-8 mode).
Note 8: The f
C32
clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1" (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to "1". Also make sure ports P8
6
and P8
7
are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to "1" (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to "1", set the CM07 bit to "0"(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to "0" (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to "0".
Note 13: When the CM21 bit is set to "0" (ring oscillaor turned off) and the CM05 bit is set to "1" (main clock turned off), the CM06 bit
is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Note 14: To return from ring oscillator mode to high-speed or middle-speed mode set the CM06 and CM15 bits both to "1".
RW
Port X
C
select bit
(Note 2)
RW
RW
RW
RW
RW
RW
RW
Refer to Table 7.5.3.1 Function of the CLKout pin
01101000
2
(M16C/26T)
CM00
CM01
Clock output function
select bit
0 : Do not stop peripheral function clock in wait mode
0 : LOW
0 : I/O port P8
6
, P8
7
1 : X
CIN
-X
COUT
generation function (Note 9)
RW
Figure 7.2. CM0 Register
7. Clock Generation Circuit
page 35
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System clock control register 1 (Note 1)
Symbol Address After reset
CM1 000716 001000002
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Notes 4, 6) 0 : Clock on
1 : All clocks off (stop mode)
Note 1: Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), X OUT goes “H” and the internal feedback resistor is disconnected. The X CIN and XCOUT
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register
is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
Note 5: After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11
bit to “1” (PLL clock).
Note 6: When the PM21 bit in the PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no
effect. When the PM22 bit in the PM2 register is set to “1” (watchdog timer count source is on-chip oscillator clock), writing to
the CM10 bit has no effect.
Note 7: Effective when CM07 bit is “0” and CM21 bit is “0” .
CM15 XIN-XOUT drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
RW
CM16
CM17
Reserved bit Must set to
“0”
Main clock division
select bits (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
000
CM11 System clock select bit 1
(Notes 6, 7) 0 : Main clock
1 : PLL clock (Note 5)
RW
RW
RW
RW
RW
RW
(b4-b2)
Figure 7.3. CM1 Register
Figure 7.4. ROCR Register
b7 b6 b5 b4 b3 b2 b1 b0
RW
ROCR0
ROCR1
On-chip Oscillator Control register (Note 1)
Symbol Address After reset
ROCR 025C
16
00000101
2
Bit name Function
Bit symbol
Frequency select bits RW
RW
Reserved bit When write, set to “0”.
When read, its content is “0”.RO
0000
0 0 : f1 (ROC)
0 1 : f2 (ROC)
1 0 : not supported
1 1 : f3 (ROC)
b1 b0
ROCR2
ROCR3
Divider select bits RW
RW
0 0 : not supported
0 1 : divide by 2
1 0 : divide by 4
1 1 : divide by 8
b3 b2
Note 1 : Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
(b5-b4)
Reserved bit Set to “0”.RW(b6)
Reserved bit When write, set to “0”. When read,
its content is indeterminate. RO(b7)
7. Clock Generation Circuit
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b7 b6 b5 b4 b3 b2 b1 b0
RW
CM20
CM21
Oscillation stop detection register (Note 1)
Symbol Address After reset
CM2 000C16 0X0000102(Note 11)
Bit name Function
Bit symbol
System clock select bit 2
(Notes 2, 3, 6, 8, 11, 12 )
0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled
0: Main clock or PLL clock
1: On-chip oscillator clock
(On-chip oscillator oscillating)
Oscillation stop, re-
oscillation detection bit
(Notes 7, 9, 10, 11)
Note 1: Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
Note 2: When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is
automatically set to “1” (on-chip oscillator clock) if the main clock stop is detected.
Note 3: If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock not oscillating), do not set the CM21 bit to “0”.
Note 4: This flag is set to “1” when the main clock is detected to have stopped or when the main clock is detected to have
restarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop,reoscillation detection interrupt is
generated. Use this flag in an interrupt routine to discriminate the causes of interrupts between the oscillation stop,
reoscillation detection interrupts and the watchdog timer interrupt. The flag is cleared to “0” by writing a “0” in a
program. (Writing a “1” has no effect. Nor is it cleared to “0” by an oscillation stop or an oscillation restart detection
interrupt request acknowledged.)
If when the CM22 bit is set to "1" an oscillation stop or an oscillation restart is detected, no oscillation stop, reoscillation
detection interrupts are generated.
Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock
status.
Note 6: Effective when the CM07 bit in the CM0 register is set to “0”.
Note 7: When the PM21 bit in the PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no effect.
Note 8: When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set
to “1” (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is set to “0” under
these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore,
necessary to set the CM21 bit to “1” (on-chip oscillator clock) inside the interrupt routine.
Note 9: Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to
1” (enable).
Note 10: Set the CM20 bit to “0” (disable) before setting the CM05 bit in the CM0 register.
Note 11: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Note 12: When the CM21 bit is set to "0" (on-chip oscillator turned off) and the CM05 bit is set to "1" (main clock turned off),
the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
CM22
CM23
Oscillation stop, re-
oscillation detection flag 0: Main clock stop or re-oscillation
not detected
1: Main clock stop or re-oscillation
detected
0: Main clock oscillating
1: Main clock not oscillating
XIN monitor flag
(Note 4)
CM27 0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(Note 11)
RW
RW
RW
RW
RO
(b6)
(Note 5)
Reserved bit
(b5-b4) Must set to “0”RW
00
Figure 7.5. CM2 Register
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Figure 7.6. PCLKR Register and PM2 Register
Function
Bit symbol
Bit name
Peripheral clock select register (Note)
Symbol Address When reset
PCLKR 025E
16
00000011
2
RW
b7 b6 b5 b4 b3 b2 b1 b0
PCLK0 Timers A, B clock select bit
(Clock source for the
timers A, B, and the dead
timer)
0 : f
2
1 : f
1
000
Reserved bit
Must set to
“0”
Note: Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
00
PCLK1 SI/O clock select bit
(Clock source for UART0
to UART2)
0 : f
2SIO
1 : f
1SIO
RW
RW
RW
(b4-b2)
Reserved bit
Must set to
“0” RW
(b7-b6)
RW
PCLK5 Clock output function
expansion select bit Refer to Table 7.5.3.1 Function
of CLKOUT pin
Function
Bit symbol
Bit name
Processeor mode register 2 (Note 1)
Symbol Address When reset
PM2 001E16 XXX000002
RW
b7 b6 b5 b4 b3 b2 b1 b0
PM20 Specifying Wait when
Accessing SFR at PLL
Operation
0 : 2 wait
1 : 1 wait
0
Nothing is assigned. When write, set to
“0”
. When read,
its content is indeterminate.
PM21 System clock protective bit 0 : Clock is protected by PRCR
register
1 : Clock modification disabled
RW
RW
RW
(b7-b5)
PM22
PM24
(b3)
WDT count source
protective bit
Reserved bit
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip oscillator clock is used
for the watchdog timer count
source
Must set to “0”
P8
5
/NMI configuration bit
RW
RW
(Note 2)
(Note 3,4)
(Note 3,5)
(Note 6,7)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is “0” (PLL turned off). Also, set the PM20 bit to “0” (2 wait)
when PLL clock > 16MHz. Note that if the clock source for the CPU clock is to be changed from PLL clock
to another, the PLC07 bit must be set to "0" before setting the PM20 bit.
Note 3: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 4: If the PM21 bit is set to “1”, writing to the following bits has no efftect:
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
Be aware that the WAIT instruction cannot be executed when the PM21 bit is set to "1".
Note 5: Setting the PM22 bit to “1” results in the following conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
source.
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Note 6: For NMI function, the PM24 bit must be set to “1”(NMI function) in first instruction after rest. Once this bit is
set to “1”, it cannot be cleared to “0” in a program. When the PM24 bit is set to “1”, the P85 direction register
must be “0”(input mode).
Note 7: SD input is valid regardless of the PM24 setting.
0 : P8
5
function (NMI disable)
1 : NMI function
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Figure 7.7. PLC0 Register
PLC00
PLC01
PLC02
PLC07
(Note 3)
(Note 4)
Function
Note 1: Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
Note 2: When the PM21 bit in the PM2 register is "1" (clock modification disable), writing to this register has no effect.
Note 3:
These three bits can only be modified when the PLC07 bit is set to "0" (PLL turned off). The value once written to this bit
cannot be modified.
Note 4: Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 and CM16 bits to "002"
(main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).
PLL control register 0
(Note 1, Note 2)
PLL multiplying factor
select bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved bit
Operation enable bit
0 0 0:
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
1 0 0:
1 0 1:
1 1 0:
1 1 1:
0: PLL Off
1: PLL On
Must set to "1"
Bit name
Bit
symbol
Symbol Address After reset
PLC0 001C16 0001 X0102
RW
b1b0b2
Reserved bit Must set to "0"
Do not set
RW
RW
RW
RW
RW
RW
Do not set
(b4)
(b6-b5)
(b3)
b7 b6 b5 b4 b3 b2 b1 b0
0 10
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Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
V
CC
Vss
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Figure 7.1.1. Examples of Main Clock Connection Circuit
The following describes the clocks generated by the clock generation circuit.
7.1 Main Clock
The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for
the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a
resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor,
which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power
consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 7.1.1 shows the examples of main clock connection circuit.
The main clock after reset oscillates in the M16C/26A, but stop in the M16C/26T.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains
on, XIN is pulled “H” to XOUT via the feedback resistor.
During stop mode, all clocks including the main clock are turned off. Refer to 7.6 power control.
If the main clock is not used, it is recommended to connect the XIN pin to VCC to reduce power consump-
tion during reset.
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Microcomputer
(Built-in feedback resistor)
XCIN XCOUT
Externally derived clock
Open
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
CIN
and X
COUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
XCIN XCOUT
(Note)
CCIN CCOUT
RCd
V
CC
Figure 7.2.1. Examples of Sub Clock Connection Circuit
7.2 Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the
CPU clock, as well as the timer A and timer B count sources.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT
pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator
circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock
oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure
7.2.1 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator
circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 7.6 Power Control.
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7.3 On-chip Oscillator Clock
This clock is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and
peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for
the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to
10.1 Count source protective mode).
The on-chip oscillator clock after reset oscillates. The on-chip oscillator clock f2(ROC) divided by 16 is used
for the CPU clock. It can also be turned off by setting the CM21 bit in the CM2 register to “0” (main clock or
PLL clock). If the main clock stops oscillating when the CM20 bit in the CM2 register is “1” (oscillation stop,
re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-oscillation detection
interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the micro-
computer.
7.4 PLL Clock
The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the
clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL
frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is
used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 7.4.1 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register
(However, 10 MHz ≤ PLL clock frequency ≤ 20 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 7.4.1 shows the example for setting PLL
clock frequencies.
X
IN
(MHz) PLC02 PLC01 PLC00 Multiplying factor PLL clock
(MHz)(Note)
10 0 0 1 2 20
50 1 0 4
Note: 10MHz ≤ PLL clock frequency ≤ 20MHz.
Table 7.4.1. Example for Setting PLL Clock Frequencies
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Figure 7.4.1. Procedure to Use PLL Clock as CPU Clock Source
START
Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “002”(main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled). (Note)
Set the PLC02 to PLC00 bits (multiplying factor).
(To select a 16 MHz < PLL clock)
Set the PM20 bit to “0” (2-wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
Note : PLL operation mode can be entered from high speed mode.
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7.5 CPU Clock and Peripheral Function Clock
The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph-
eral functions.
7.5.1 CPU Clock
This is the operating clock for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 and CM16 bits to “002” (undivided).
After reset, the on-chip oscillator clock divided by 16 provides the CPU clock.
Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).
7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator clock
by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/
D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can only be used
when the sub clock is on.
7.5.3 ClockOutput Function
The f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use the PCLK5 bit in the PCLKR register and
CM01 to CM00 bits in the CM0 register to select. Table 7.5.3.1 shows the function of the CLKOUT pin.
Table 7.5.3.1 The function of the CLKOUT pin
PCLK5 CM01 CM00 The function of the CLKOUT pin
0 0 0 I/O port P90
001fC
010f8
011f32
100f1
1 0 1 Do not set
1 1 0 Do not set
1 1 1 Do not set
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7.6 Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
7.6.1 Normal Operation Mode
Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low speed or low power dissipation mode to
on-chip oscillator or on-chip oscillator low power dissipation mode. Nor can operation modes be changed
directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low speed or low power
dissipation mode. When the CPU clock source is changed from the on-chip oscillator to the main clock,
change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided
by 8 (the CM06 bit in the CM0 register was set to “1”) in the on-chip oscillator mode.
7.6.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
7.6.1.2 PLL Operation Mode
The main clock multiplied by 2 or 4 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.
7.6.1.3 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
7.6.1.4 Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to “0” (on-chip oscillator turned off), and the on-chip oscillator
clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
7.6.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B. Peripheral function
clock can use only fC32.
Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes “1” (divided by
8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
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7.6.1.6 On-chip Oscillator Mode
The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock.
The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock
is on, fC32 can be used as the count source for timers A and B. The on-chip oscillator frequency can be
selected ROCR3 to ROCR0 bits in ROCR register. When the operation mode is returned to the high
and medium speed modes, set the CM06 bit to “1” (divided by 8 mode).
7.6.1.7 On-chip Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be
selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the
peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and
B.
1(Note 1)
Modes CM2 register
CM21 CM1 register
CM11 CM17, CM16 CM0 register
CM07 CM06 CM05 CM04
PLL operation mode 01002 00
High-speed mode 0 0 002 000
Medium-
speed
mode
0001
2 000
0010
2 000
divided by 2
00 01
0
0011
2 000
Low-speed mode 1 0 1
Low power dissipation mode 11
On-chip
oscillator
mode
(Note 3)
1
divided by 4
divided by 8
divided by 16
On-chip oscillator low power
dissipation mode
Note 1: When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
Note 2: The divide-by-n value can be selected the same way as in on-chip oscillator mode.
0
0
101
2 000
110
2 000
110
111
2 000
100
2 000
(Note 2)
divided by 2
divided by 4
divided by 8
divided by 16
divided by 1 1(Note 1)
(Note 2) 1
Note 3: On-chip oscillator frequency can be any of those described in the section 7.6.1.6 On-chip Oscillator Mode.
0
0
7.6.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watch-
dog timer count source), the watchdog timer remains active. Because the main clock, sub clock, on-chip
oscillator clock and PLL clock all are on, the peripheral functions using these clocks keep operating.
7.6.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
7.6.2.2 Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit is set to “1” (CPU clock source is the PLL clock), be sure to clear the CM11 bit to
“0” (CPU clock source is the main clock) before going to wait mode. The power consumption of the
chip can be reduced by clearing the PLC07 bit to “0” (PLL stops).
Table 7.6.1.1. Setting Clock Related Bit and Modes
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Interrupt CM02=0 CM02=1
NMI interrupt Can be used
Serial I/O interrupt Can be used when operating
with internal or external clock Can be used when operating
with external clock
key input interrupt Can be used Can be used
A/D conversion
interrupt Can be used in one-shot mode
or single sweep mode
Timer A interrupt Can be used in all modes Can be used in event counter
mode or when the count
source is fC32
Timer B interrupt
INT interrupt
Can be used
Can be used
(Do not use)
Can be used
Table 7.6.2.4.1. Interrupts to Exit Wait Mode
7.6.2.3 Pin Status During Wait Mode
Table 7.6.2.3.1 lists pin status during wait mode.
Table 7.6.2.3.1 Pin Status in Wait Mode
Pin Status
I/O ports Retains status before wait mode
When fC selected Does not stop
CLKOUT When f1, f8, f32 selected Does not stop when the CM02 bit is set to “0”.
Retains status before wait mode when the CM02 bit is set to “1”
.
7.6.2.4 Exiting Wait Mode ______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt. ______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before execut-
ing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is set to “0” (peripheral
function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit
wait mode. If the CM02 bit is set to “1” (peripheral function clocks turned off during wait mode), the
peripheral functions using the peripheral function clocks stop operating, so that only the peripheral
functions clocked by external signals can be used to exit wait mode.
Table 7.6.2.4.1 lists the interrupts to exit wait mode.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
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7.6.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal
RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• Voltage down detection interrupt
(refer to 5.5.1 Voltage Down Detection Interrupt for an operating condition)
7.6.3.1 Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all
clocks turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode)
and the CM15 bit in the CM10 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disable).
Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for
the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.
7.6.3.2 Pin Status during Stop Mode
The I/O pins retain their status held just prior to entering stop mode.
7.6.3.3 Exiting Stop Mode ______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt. ______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the
peripheral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
If the CPU clock before entering stop mode was derived from the sub clock :
sub clock
If the CPU clock before entering stop mode was derived from the main clock :
main clock divide-by-8
If the CPU clock before entering stop mode was derived from the on-chip oscillator clock: on-chip oscillator clock
divide-by-8
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Figure 7.6.1. State Transition to Stop Mode and Wait Mode
Reset
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
Stop mode Wait mode
Interrupt
CM10=1
Interrupt
Low-speed, low power
dissipation mode
CM10=1
Stop mode
Interrupt
Wait mode
Interrupt
CM10=1
Stop mode
All oscillators stopped
Interrupt
Wait mode
WAIT
instruction
Interrupt
CPU operation stopped
When
low-
speed
mode
When
low power
dissipation
mode
PLL operation
mode
Notes 1, 2
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
Note 1: Do not go directly from PLL operation mode to wait or stop mode.
Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
Note 3: When the PM21 bit is set to "0" (system clock protective function unused).
Note 4: The on-chip oscillator clock divided by 8 provides the CPU clock.
Note 5: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 bit is set to "1" (on-chip oscillator
turned off). When the clock generated externally is input to the X
CIN
pin, transit to stop mode with this process.
Note 6: Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to "0" (oscillation stop and oscillation restart detection
function disabled).
Wait mode
Interrupt
CM10=1
Interrupt
(Note 4)
Stop mode
WAIT
instruction
WAIT
instruction
WAIT
instruction
On-chip oscillator mode
(selectable frequency)
On-chip oscillator
mode (f2(ROC)/16)
Normal operation mode
CM21=1
CM21=0
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1
(Note 5)
On-chip oscillator low power
dissipation mode
CM10=1
Stop mode
Interrupt
Wait mode
Interrupt
WAIT
instruction
Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.6.1.1 shows the state transition in normal operation mode.
Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
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Figure 7.6.1.1. State Transition in Normal Mode
CM04=0
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
PLL operation mode
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=1
CM07=0
CM17=1
CM06=0
CM16=0
CM07=0
CM06=1
CM07=0
CM17=1
CM06=0
CM16=1
High-speed mode
CM07=0
CM17=0
CM06=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=1
CM07=0
CM17=1
CM06=0
CM16=0
CM07=0
CM06=1
CM07=0
CM17=1
CM06=0
CM16=1
CM07=0
Low-speed mode
CM07=0
Low power dissipation mode
CM06=1
CM15=1
On-chip oscillator mode
CPU clock
On-chip oscillator
mode
CPU clock
CPU clock
On-chip oscillator
low power
dissipation mode
CPU clock
CM07=0
Low-speed mode
PLC07=1
CM11=1
(Note 6)
PLC07=0
CM11=0
(Note 7)
CM04=0
PLC07=1
CM11=1
PLC07=0
CM11=0
CM04=0CM04=1CM04=1 CM04=1 CM04=0CM04=1
CM07=0
(Note 2, Note 4)
CM07=1
(Note 3)
CM05=1
(Note 1, Note 9) CM05=0
CM21=0
(Note 8)
CM21=1
CM21=0
(Note 8)
CM21=1
CM21=0
CM21=1
Main clock oscillation On-chip oscillator clock
oscillation
Sub clock oscillation
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
PLL operation
mode
CPU clock: f(PLL)
CPU clock: f(X
IN
)
High-speed mode Middle-speed mode
(divide by 2)
CPU clock: f(X
IN
)/2 CPU clock: f(X
IN
)/4 CPU clock: f(X
IN
)/8 CPU clock: f(X
IN
)/16
CPU clock: f(X
CIN
)
CPU clock: f(X
CIN
)
CPU clock: f(X
CIN
)
CM05=0
M0
M
CM05=1
(Note 1)
CM05=1
(Note 1)
CM05=0
(Note 6)
(Note 7)
Middle-speed mode
(divide by 4) Middle-speed mode
(divide by 8) Middle-speed mode
(divide by 16)
Middle-speed mode
(divide by 2) Middle-speed mode
(divide by 4) Middle-speed mode
(divide by 8) Middle-speed mode
(divide by 16)
CPU clock: f(X
IN
)
CPU clock: f(X
IN
)/2 CPU clock: f(X
IN
)/4 CPU clock: f(X
IN
)/8 CPU clock: f(X
IN
)/16
On-chip oscillator low power
dissipation mode
Notes:
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
1: Avoid making a transition when the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2: Wait for the main clock oscillation stabilization time before switching over.
3: Switch clock after oscillation of sub-clock is sufficiently stable.
4: Change CM17 and CM16 before changing CM06.
5: Transit in accordance with arrow.
6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes.
To select PLL clock > 16MHz, set the PM20 bit to “0” (SFR accessed with two wait states) before setting PLC07 to “1” (PLL operation).
7: PLL operation mode can only be changed to high speed mode. If the PM20 bit is set to "0" (SFR accessed with two wait states), set PLC07 to “0” (PLL turned off)
before setting the PM20 bit to “1” (SFR accessed with one wait state).
8: Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
9: When the CM21 bit is set to "0" (on-chip oscillator turned off) and the CM05 bit is set to "1" (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
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Table 7.6.1. Allowed Transition and Setting
High-speed mode,
middle-speed mode
On-chip oscillator mode
Stop mode
Wait mode
On-chip oscillator
low power dissipation
mode
PLL operation mode2
Low power dissipation
mode
Low-speed mode2
Current state
State after transition
See Table A8
--
(8)
(18)
5
(9)
7
--
(10)
(11)
1, 6
(12)
3
(14)
4
--
--
--
--
--
(13)
3
(15) --
--
--
--
--
--
--
(10)
--
--
--
-- -- --
--
--
(18)(18) --
--
(16)
1
(17)
(16)
1
(17)
(16)
1
(17)
(16)
1
(17)
(16)
1
(17)
-- --
(18)
5
(18)
5
(18)(18)(18)(18)(18)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
Setting Operation
CM04 = 0 Sub clock turned off
CM04 = 1 Sub clock oscillating
CM06 = 0, CPU clock no division mode
CM17 = 0 , CM16 = 0
CM06 = 0, CPU clock division by 2 mode
CM17 = 0 , CM16 = 1
CM06 = 0, CPU clock division by 4 mode
CM17 = 1 , CM16 = 0
CM06 = 1 CPU clock division by 8 mode
CM06 = 0, CPU clock division by 16 mode
CM17 = 1 , CM16 = 1
CM07 = 0 Main clock, PLL clock,
or on-chip oscillator clock selected
CM07 = 1 Sub clock selected
CM05 = 0 Main clock oscillating
CM05 = 1 Main clock turned off
PLC07 = 0,
CM11 = 0 Main clock selected
PLC07 = 1,
CM11 = 1 PLL clock selected
CM21 = 0
Main clock or PLL clock selected
CM21 = 1 On-chip oscillator clock selected
CM10 = 1 Transition to stop mode
wait instruction Transition to wait mode
Hardware interrupt
Exit stop mode or wait mode
Notes:
1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
--: Cannot transit
(11)
1
High-speed mode,
middle-speed mode On-chip oscillator
mode Stop mode Wait mode
On-chip oscillator
low power
dissipation mode
PLL operation
mode2
Low power
dissipation mode
Low-speed mode2
See Table A8
See Table A8
(3)
(3)
(3)
(3)
(4)
(4)
(4)
(4)
(5) (7)
(7)
(5)
(5)
(5)
(7)
(7)
(6)
(6)
(6)
(6)
No
division Divided
by 2
(3)
(3)
(3)
(3)
(4)
(4)
(4)
(4)
(5)
(5)
(5)
(5) (7)
(7)
(7)
(7)
(6)
(6)
(6)
(6)
(1) (1) (1) (1) (1)
(2) (2) (2) (2) (2)
-- --
-- --
--
--
----
--
--
-- --
--
--
--
-- -- --
-- --
--
--
--
-- --
--
-- --
--
--
-- --
--
--
--
--
--
--
--
--
Sub clock oscillating Sub clock turned off
--: Cannot transit
Divided
by 4 Divided
by 8 Divided
by 16 No
division Divided
by 2 Divided
by 4 Divided
by 8 Divided
by 16
No division
Divided by 4
Sub clock
oscillating
Sub clock
turned off
Divided by 8
Divided by 16
Divided by 2
No division
Divided by 4
Divided by 8
Divided by 16
Divided by 2
9. ( ) : setting method. Refer to following table.
CM04, CM05, CM06, CM07 : bits in the CM0 register
CM10, CM11, CM16, CM17 : bits in the CM1 register
CM20, CM21 : bits in the CM2 register
PLC07 : bit in the PLC0 register
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7.7 System Clock Protective Function
When the main clock is selected for the CPU clock source, this function protects the clock from modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit in the PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit in the CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for
the CPU clock source):
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit in the PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is set to “1”.
7.8 Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and
reoscillation. At oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection
interrupt are generated. Depending on the CM27 bit in the CM2 register. The oscillation stop detection
function can be enabled and disabled by the CM20 bit in the CM2 register. Table 7.8.1 lists a specification
overview of the oscillation stop and re-oscillation detect function.
Table 7.8.1. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item Specification
Oscillation stop detectable clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop, Set the CM20 bit to “1”(enable)
re-oscillation detection function
Operation at oscillation stop, •Reset occurs (when the CM27 bit is set to "0")
re-oscillation detection •
Oscillation stop, re-oscillation detection interrupt occurs(when the CM27 bit is
set to "1")
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7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset)
When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR,
5. Reset).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During
main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”.)
7.8.2
Operation When the CM27 bit is set to "1" (Oscillation Stop and Re-oscillation Detect
Interrupt)
When the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the CPU clock and
clock source for peripheral functions in place of the main clock.
• CM21 bit is set to "1" (on-chip oscillator clock for CPU clock source)
• CM22 bit is set to "1" (main clock stop detected)
• CM23 bit is set to "1" (main clock stopped)
When the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit is set to "1" (main clock stop detected)
• CM23 bit is set to "1" (main clock stopped)
• CM21 bit remains unchanged
When the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from the
stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit is set to "1" (main clock re-oscillation detected)
• CM23 bit is set to "0" (main clock oscillation)
• CM21 bit remains unchanged
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7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function
• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter-
rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read
the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, return the main clock to the CPU clock and
peripheral function clock source in the program. Figure 7.8.3.1 shows the procedure for switching the
clock source from the on-chip oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit be-
comes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are dis-
abled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscilla-
tion detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating.
In this case, although the CPU clock is derived from the sub clock as it was before the interrupt oc-
curred, the peripheral function clocks now are derived from the on-chip oscillator clock.
• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to
“0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop
due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function dis-
abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit
to “0”.
Figure 7.8.3.1.
Procedure to Switch Clock Source From On-chip Oscillator to Main Clock
Main clock switch
Inspect the CM23 bit
Do this check a number of times
Set the CM22 bit to 0 (main clock stop,
re-oscillation not detected).
Set the CM21 bit to 0
(main clock for the CPU clock source)(Note)
1(Main clock stop)
0(Main clock oscillation)
The main clock is confirmed to be active a number of times.
All of CM21-23 are the CM2 register bits
End
Note: If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation
mode after set to high-speed mode.
8. Protection
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8. Protection
Note The M16C/26T do not use the PRC3 bit in the PRCR register.
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by
the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0, ROCR and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
• Registers protected by PRC2 bit: PD9, PACR and NDDR registers
• Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-
cally cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
Symbol Address After reset
PRCR 000A
16
XX000000
2
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Write protected
1 : Write enabled
PRC1
PRC0
PRC2
Function RW
Note: The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0"
by writing to any address, and must therefore be set in a program.
0
RW
RW
RW
Nothing is assigned. When write, set to "0". When read, its
content is indeterminate.
Reserved bit Must set to "0"
RW
Protect bit 0
Protect bit 1
Protect bit 2
Enable write to CM0, CM1, CM2,
ROCR, PLC0 and PCLKR registers
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1, PM2,
TB2SC, INVC0 and INVC1
registers
0 : Write protected
1 : Write enabled
Enable write to PD9, PACR and
NDDR registers
PRC3
RW
Protect bit 3
0 : Write protected
1 : Write enabled
Enable write to VCR2 and D4INT
registers
(b5-b4)
(b7-b6)
0
Figure 8.1. PRCR Register
9. Interrupt
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• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 9.1.1. Interrupts
Interrupt
Software
(Non-maskable interrupt)
Hardware
Special
(Non-maskable interrupt)
Peripheral function (Note 1)
(Maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
_______
NMI
________
DBC (Note 2)
Watchdog timer
Oscillation stop and re-oscillation
detection
Voltage down detection
Single step (Note 2)
Address match
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2:
Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
9. Interrupt
Note
M16C/26A(42-pin version) do not use UART0 transmission interrupt and UART0 reception interrupt
of peripheral function.
M16C/26T do not use voltage down detection interrupt.
9.1 Type of Interrupts
Figure 9.1.1 shows types of interrupts.
9. Interrupt
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9.1.1 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
9.1.1.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
9.1.1.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-
tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS,
ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
9.1.1.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
9.1.1.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 4, 8 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.
9. Interrupt
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9.1.2 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
9.1.2.1 Special Interrupts
Special interrupts are non-maskable interrupts.
_______
9.1.2.1.1 NMI Interrupt
_______ _______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
_______ _______
about the NMI interrupt, refer to the section 9.7 NMI Interrupt.
________
9.1.2.1.2 DBC Interrupt
This interrupt is exclusively for debugger, do not use in any other circumstances.
9.1.2.1.3 Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section 10. Watchdog Timer.
9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-
tion stop and re-oscillation detection function, refer to the section 7. Clock Generating Circuit.
9.1.2.1.5 Voltage Down Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the
section 5.5 Voltage Detection Circuit.
9.1.2.1.6 Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
9.1.2.1.7 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 or RMAD1 register, if the corresponding enable bit (the AIER0 or AIER1 bit
in the AIER register) is set to “1”. For details about the address match interrupt, refer to the section
9.9 Address Match Interrupt.
9.1.2.2 Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 9.2.2.1
Relocatable Vector Tables. For details about the peripheral functions, refer to the description of
each peripheral function in this manual.
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Interrupt source Vector table addresses Remarks Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction serise software
BRK instruction FFFE416 to FFFE716 maual
Address match FFFE816 to FFFEB16
Address match interrupt
Single step (Note1) FFFEC16 to FFFEF16
Watchdog timer FFFF016 to FFFF316 Watchdog timer
Oscillation stop and
re-oscillation detection Clock generating circuit
Voltage down
detection
Voltage detection circuit
________
DBC (Note1) FFFF416 to FFFF716
_______
NMI FFFF816 to FFFFB16 _______
NMI interrupt
Reset (Note 2) FFFFC16 to FFFFF16 Reset
Note 1:
Do not normally use this interrupt because it is provided exclusively for use by development support tools.
Note 2: The b3 to b0 in address 0FFFFF16 are reserve bits. Set these bits to “11112”.
Figure 9.2.1. Interrupt Vector
AAAAAAAAA
AAAAAAAAA
Mid address
AAAAAAAAA
AAAAAAAAA
Low address
AAAAAAAAA
AAAAAAAAA
0 0 0 0 High address
AAAAAAAAA
AAAAAAAAA
0 0 0 0 0 0 0 0
Vector address (L)
LSB
MSB
Vector address (H)
9.2 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.
Table 9.2.1.1. Fixed Vector Tables
If the contents of address
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
9.2.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 9.2.1.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section 17.3 Flash Memory
Rewrite Disabling Function.
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Table 9.2.2.1. Relocatable Vector Tables
Software interrupt
number Reference
Note 1: Address relative to address in INTB.
Note 2: Set the IFSR6 and IFSR7 bits in the IFSR register.
Note 3: During I
2
C bus mode, NACK and ACK interrupts comprise the interrupt source.
Note 4: These interrupts cannot be disabled using the I flag.
Note 5: Bus collision detection : During IEBus mode, this bus collision detection constitutes the cause of an interrupt.
During I
2
C bus mode, however, a start condition or a stop condition detection constitutes
the cause of an interrupt.
Vector address (Note 1)
Address (L) to address (H)
0
11
12
13
14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
63
to
10
15
16
5 to 7
8
4
9
1 to 3
Interrupt source
BRK instruction
INT3
INT4
INT5 (Note 2)
(Note 2)
DMA0
DMA1
Key input interrupt
A/D
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
Software interrupt
UART 2 bus collision detection
UART2 transmit, NACK2 (Note 3)
UART2 receive, ACK2 (Note 3)
M16C/60, M16C/20
series software
manual
INT interrupt
INT interrupt
Serial I/O
DMAC
Key input interrupt
A/D convertor
Serial I/O
Timer
INT interrupt
M16C/60, M16C/20
series software
manual
(Note 4)
(Reserved)
+0 to +3 (0000
16
to 0003
16
)
+44 to +47 (002C
16
to 002F
16
)
+48 to +51 (0030
16
to 0033
16
)
+52 to +55 (0034
16
to 0037
16
)
+56 to +59 (0038
16
to 003B
16
)
+68 to +71 (0044
16
to 0047
16
)
+72 to +75 (0048
16
to 004B
16
)
+76 to +79 (004C
16
to 004F
16
)
+80 to +83 (0050
16
to 0053
16
)
+84 to +87 (0054
16
to 0057
16
)
+88 to +91 (0058
16
to 005B
16
)
+92 to +95 (005C
16
to 005F
16
)
+96 to +99 (0060
16
to 0063
16
)
+100 to +103 (0064
16
to 0067
16
)
+104 to +107 (0068
16
to 006B
16
)
+108 to +111 (006C
16
to 006F
16
)
+112 to +115 (0070
16
to 0073
16
)
+116 to +119 (0074
16
to 0077
16
)
+120 to +123 (0078
16
to 007B
16
)
+124 to +127 (007C
16
to 007F
16
)
+128 to +131 (0080
16
to 0083
16
)
+252 to +255 (00FC
16
to 00FF
16
)
+40 to +43 (0028
16
to 002B
16
)
+60 to +63 (003C
16
to 003F
16
)
+64 to +67 (0040
16
to 0043
16
)
+32 to +35 (0020
16
to 0023
16
)
+16 to +19 (0010
16
to 0013
16
)
+36 to +39 (0024
16
to 0027
16
)
to
(Note 4)
(Note 5)
(Reserved)
9.2.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
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9.3 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to
enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 9.3.1 shows the interrupt control registers.
Figure 9.3.2 shows the IFSR, IFSR2A registers.
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Figure 9.3.1. Interrupt Control Registers
Symbol Address After reset
INT3IC 0044
16
XX00X000
2
INT5IC 0048
16
XX00X000
2
INT4IC 0049
16
XX00X000
2
INT0IC to INT2IC 005D
16
to 005F
16
XX00X000
2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A
AA
ILVL0
IR
POL
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge (Notes 3, 4)
1 : Selects rising edge
Must always be set to “0”
ILVL1
ILVL2
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
Note 3: If the IFSRi bit (i = 0 to 5) in the IFSR register is “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
edge).
(Note 1)
Interrupt control register (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
A
A
AA
AA
Bit name FunctionBit symbol
RW
Symbol Address After reset
BCNIC 004A
16
XXXXX000
2
DM0IC, DM1IC 004B
16
, 004C
16
XXXXX000
2
KUPIC 004D16 XXXXX000
2
ADIC 004E16 XXXXX000
2
S0TIC to S2TIC 005116, 005316, 004F16 XXXXX000
2
S0RIC to S2RIC 005216, 005416, 005016 XXXXX000
2
TA0IC to TA4IC 005516 to 005916 XXXXX000
2
TB0IC to TB2IC 005A16 to 005C16 XXXXX000
2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(Note 1)
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
RW
RW
RW
RW
(b7-b4)
RW
RW
RW
RW
RW
RW
RW
RW
(b7-b6)
(b5)
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Figure 9.3.2. IFSR Register and IFSR2A Register
Interrupt request cause select register
Bit name Function
Bit symbol
RW
Symbol Address After reset
IFSR 035F
16
00
16
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
A
A
INT0 interrupt polarity
switching bit
0 : Reserved
1 : INT4
0 : Reserved
1 : INT5
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit 0 : One edge
1 : Both edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
RW
RW
RW
RW
RW
RW
RW
RW
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Note 1: When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register
is set to “0” (= falling edge).
Interrupt request cause select register 2
Bit name Function
Bit symbol RW
Symbol Address After reset
IFSR2A 035E16 XXXXXXX02
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
AA
AA
Must be set to “1”.
(b7-b1) Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
IFSR20
1
Reserved bit RW
(Note 1)
Note 1: Set this bit to "1" before you enable interrupt after resetting.
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9.3.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
9.3.2 IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
9.3.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3.3.1 shows the settings of interrupt priority levels and Table 9.3.3.2 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag is set to “1”
· IR bit is set to “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 9.3.3.2. Interrupt Priority Levels
Enabled by IPL
Table 9.3.3.1. Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits Interrupt priority
level Priority
order
000
2
001
2
010
2
011
2
100
2
101
2
110
2
111
2
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
Enabled interrupt priority levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
000
2
001
2
010
2
011
2
100
2
101
2
110
2
111
2
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9.4 Interrupt Sequence
An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the inter-
rupt routine is executed) is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.4.1 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading
the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not
requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register(Note).
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register (Note) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
Indeterminate
(1)
123456789 101112 13 14 15 16 17 18
Indeterminate
(1)
SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
000016 Indeterminate
(1)
SP-2 SP-4 vec vec+2 PC
CPU clock
Address bus
Data bus
WR
(2)
RD
(2)
NOTES:
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the
instruction queue buffer is ready to accept instructions.
2. RD is the internal signal which is set to “L” when the internal memory is read out and WR is the
internal signal which is set to “L” when the internal memory is written.
Figure 9.4.1. Time Required for Executing Interrupt Sequence
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Interrupt sources
7
Level that is set to IPL
_______
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
voltage down detection _________
Software, address match, DBC, single-step Not changed
9.4.2 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.4.2.1 is set in the IPL. Shown in Table 9.4.2.1 are the IPL values of software and special
interrupts when they are accepted.
Table 9.4.2.1. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
(a) The time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) The time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address
Even
Even
Odd
Odd
SP value
Even
Odd
Even
Odd
Without wait
18 cycles
19 cycles
19 cycles
20 cycles
Figure 9.4.1.1. Interrupt response time
9.4.1 Interrupt Response Time
Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated till
when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time during which the
interrupt sequence is executed ((b) in Figure 9.4.1.1).
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9.4.3 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
9.4.3.1 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
Content of previous stack
Stack
[SP]
SP value before
interrupt request is
accepted.
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB LSB
m
m – 1
m – 2
m – 3
m – 4
Address
FLG
L
Content of previous stack
Stack
FLG
H
PC
H
[SP]
New SP value
Content of previous stack
m + 1
MSB LSB
PC
L
PC
M
Figure 9.4.3.1. Stack Status Before and After Acceptance of Interrupt Request
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Figure 9.4.3.2. Operation of Saving Register
(2) SP contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) SP contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
PC
M
Stack
FLG
L
PC
L
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
PC
M
Stack
FLG
L
PC
L
Saved, 8 bits at a time
FLG
H
PC
H
FLG
H
PC
H
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 9.4.3.2 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
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9.5 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.5.1
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
9.4.4 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
9.5.1 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 9.5.1.1 shows the circuit that judges the interrupt priority level.
Figure 9.5.1. Hardware Interrupt Priority
Reset
W atchdog Timer ,
Oscillation stop and re-oscillation
detection,
voltage down detection
Peripheral function
Single step
Address match
High
Low
NMI
DBC
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Figure 9.5.1.1. Interrupts Priority Select Circuit
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
UART2 reception, ACK2
A/D conversion
DMA1
UART 2 bus collision
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission, NACK2
Key input interrupt
DMA0
IPL
I flag
INT1
INT2
INT0
Watchdog timer
DBC
NMI
Interrupt
request
accepted
Level 0 (initial value)
Priority level of each interrupt
Highest
Lowest
Priority of peripheral function interrupts
(if priority levels are same)
INT3
INT5
INT4
Address match
Interrupt request level resolution output to clock
generating circuit (Fig.7.1.)
Oscillation stop and
re-oscillation detection
Voltage down detection
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______
9.6 INT Interrupt
_______
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSRi bit in the IFSR register.
________ ________ ________
To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (=INT4). To use the INT5 interrupt, set
________
the IFSR7 bit in the IFSR register to "1" (=INT5).
After modifiying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (=interrupt not requested)
before enabling the interrupt.
________
The INT5 input has an effective digital debounce function for a noize rejection. Refer to 16.6 Digital
Debounce function for this detail.
Figure 9.6.1 shows the IFSR register.
Figure 9.6.1. IFSR Register
Interrupt request cause select register
Bit name Function
Bit symbol RW
Symbol Address After reset
IFSR 035F
16
0016
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
A
A
INT0 interrupt polarity
switching bit
0 : Reserved
1 : INT4
0 : Reserved
1 : INT5
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit 0 : One edge
1 : Both edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
RW
RW
RW
RW
RW
RW
RW
RW
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Note 1: When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register
is set to “0” (= falling edge).
9. Interrupt
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Interrupt control circuit
KUPIC register
Key input interrupt
request
KI
3
KI
2
KI
1
KI
0
PU25 bitinthe
PD10 register
PD10_7 bitinthe
PD10 register
Pull-up
transistor
PD10_7 bitinthePD10 register
PD10_6 bitinthe
PD10 register
PD10_5 bitinthe
PD10 register
PD10_4 bitinthe
PD10 register
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Figure 9.8.1. Key Input Interrupt
______
9.7 NMI Interrupt
_______ _______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
_______ ______
NMI interrupt was enabled by writing a “1” to PM24 bit in the PM2 register. The NMI interrupt is a non-
maskable interrupt, once it is enabled.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
_______
NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using PM24 bit in the
PM2 register. Once enabled, it can only be disabled by a reset signal.
_______
The NMI input has an effective digital debounce function for a noise rejection. Refer to 16.6 Digital
Debounce Function for this detail.
9.8 Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10_4 to PD10_7 bits in the PD10 register set to “0” (= input) goes low. Key input interrupts can
be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure
9.8.1 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which
has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port
are not detected as interrupts.
9. Interrupt
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Table 9.9.2. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
9.9 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the
PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving
Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.9.1 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 9.9.1 shows the AIER, RMAD0 and RMAD1 registers.
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (However, dest=A0 or A1)
Instructions other than the above
Instruction at the address indicated by the RMADi register
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Table 9.9.1. Value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
9. Interrupt
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Bit nameBit symbol
Symbol Address After reset
AIER 0009
16
XXXXXX00
2
Address match interrupt enable register
Function RW
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
Address match interrupt 0
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol Address After reset
RMAD0 0012
16
to 0010
16
X00000
16
RMAD1 0016
16
to 0014
16
X00000
16
b7 b6 b5 b4 b3 b2 b1 b0
Address setting register for address match interrupt
Function Setting range
Address match interrupt register i (i = 0 to 1)
00000
16
to FFFFF
16
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0b3
(b19) (b16) b7 b0
(b15) (b8)
b7
(b23)
RW
RW
(b7-b2)
RW
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 9.9.1. AIER Register, RMAD0 and RMAD1 Registers
10. Watchdog Timer
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10. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit in the PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot
be set to “0” (watchdog timer interrupt) in a program. Refer to 5.3 Watchdog Timer Reset for the details of
watchdog timer reset.
When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the WDC7 bit
value in the WDC register for prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU
clock, the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be
calculated as given below. The period of watchdog timer is, however, subject to an error due to the
prescaler.
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and when erase/program opration is excuting in EW1 mode without erase sus-
pend requeired, the watchdog timer and prescaler are stopped. Counting is resumed from the held value
when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period = Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
Prescaler dividing (2) X Watchdog timer count (32768)
CPU clock
Figure 10.1. Watchdog Timer Block Diagram
CPU
clock
Write to WDTS register
RESET
PM12 = 0
Watchdog timer
Set to
“7FFF16”
1/128
1/16
CM07 = 0
WDC7 = 1
CM07 = 0
WDC7 = 0
CM07 = 1
1/2
Prescaler
PM12 = 1
Watchdog timer
interrupt request
Reset
PM22 = 0
PM22 = 1
On-chip oscillator clock
10. Watchdog Timer
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10.1 Count source protective mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit to “1” results in the following conditions
• The on-chip oscillator starts oscillating, and the in-chip oscillator clock becomes the watchdog timer count
source.
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Figure 10.2 WDC Register and WDTS Register
Watchdog timer start register (Note)
Symbol Address After reset
WDTS 000E16 Indeterminate
WO
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
RW
Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Watchdog timer control register
Symbol Address After reset
WDC 000F
16
00XXXXXX
2
(Note 2)
FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Reserved bit Must set to “0”
0
RO
RW
RW
RW
Cold start / warm start
discrimination flag
(Note 1,2,3)
0 : Cold start
1 : Warm start
WDC5
Note 1: Writing to the WDC register causes the WDC5 bit to be set to “1” (warm start). IfthevoltageappliedtoVcc
islessthan4.0V,eitherwritetothisregisterwhentheCPUclockfrequencyis2MHzorwritetwice.
Note2:TheWDC5bitissetto"0"(coldstart)whenpoweristurnedonandcanbesetto"1"byprogramonly.
Note 3: Do not use in M16C/26T.
(b4-b0)
(b6)
Watchdog timer period = Watchdog timer count (32768)
on-chip oscillator clock
10. Watchdog Timer
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Figure 10.3 Typical Operation of Cold start / Warm start
10.2 Cold start / Warm start
The M16C/26T does not use this function.
The WDC5 flag in the WDC register indicates the last reset by power on (cold start) or by reset signal (warm
start).
The WDC5 flag is set "0" at power on, and is set "1" at writing any data to the WDC register. The flag is not
set to "0" by the software reset and the input of reset signal. Figure 0.3 shows the operation of cold start/
warm start.
“1” is held even if
RESET becomes 0 V.
T2
Program start
T1
Pch transistor ON (about 4V)
CPU reset exited
Set to “1” by program
Becomes “0” on the rising
edge of VCC
T > 100 µsec.
5V
0V
5V
0V
“1”
“0”
VCC
RESET
Reset Sequence
WDC5 Flag
NOTES:
1. The timing of which WDC5 is set is affected by how the RESET signal rises (Time lag between T1 and T2).
Note
11. DMAC
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A
A
A
A
A
A
AA
AA
AA
AA
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
Data bus low-order bits
(EC-01-UM60)
DMA latch high-order bits DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
Data bus high-order bits
A
A
A
A
A
A
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
AAAAAAA
Address bus
A
A
A
A
A
A
A
A
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20) (Note)
A
A
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
A
A
A
A
(addresses 0029
16
, 0028
16
)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
(addresses 0026
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
(addresses 0036
16
to 0034
16
)
Note: Pointer is incremented by a DMA request.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AA
AA
AA
A
A
A
A
11. DMAC
Note
The M16C/26A(42-pin version) do not use UART0 transfer and UART0 reception interrupt request as
a DMA reqest.
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the
DMAC specifications. Figures 11.2 to 11.4 show the DMAC-related registers.
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0,1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I
flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt
request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not
affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON
register is set to “1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster
than the DMA transfer cycle, the number of transfer requests generated and the number of times data is
transferred may not match. For details, refer to 11.4 DMA Requests.
Figure 11.1 DMAC Block Diagram
11. DMAC
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Table 11.1 DMAC Specifications
Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space •From any address in the 1M bytes space to a fixed address
•From a fixed address to any address in the 1M bytes space
•From a fixed address to a fixed address
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors ________ ________
Falling edge of INT0 or INT1
(Note 1, Note 2) ________ ________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
A/D conversion interrupt requests
Software triggers
Channel priority DMA0 > DMA1 (DMA0 takes precedence)
Transfer unit 8 bits or 16 bits
Transfer address direction forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1)
underflows after reaching the terminal count.
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing
When the DMAi transfer counter underflowed
DMA startup Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register is set to “1” (enabled).
DMA shutdown
Single transfer •When the DMAE bit is set to “0” (disabled)
•After the DMAi transfer counter underflows
Repeat transfer When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1” (en
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.
11. DMAC
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Figure 11.2 DM0SL Register
DMA0 request cause select register
Symbol Address After reset
DM0SL 03B816 0016
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0
RW
DSEL1
DSEL2
DSEL3
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Software DMA
request bit A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
DSR
DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)
0 0 0 0
2
Falling edge of INT0 pin –
0 0 0 1
2
Software trigger –
0 0 1 0
2
Timer A0 –
0 0 1 1
2
Timer A1 –
0 1 0 0
2
Timer A2 –
0 1 0 1
2
Timer A3 –
0 1 1 0
2
Timer A4 Two edges of INT0 pin
0 1 1 1
2
Timer B0 –
1 0 0 0
2
Timer B1 –
1 0 0 1
2
Timer B2 –
1 0 1 0
2
UART0 transmit –
1 0 1 1
2
UART0 receive –
1 1 0 0
2
UART2 transmit –
1 1 0 1
2
UART2 receive –
1 1 1 0
2
A/D conversion –
1 1 1 1
2
UART1 transmit –
Bit name
DMA request cause
expansion select bit
DMS 0: Basic cause of request
1: Extended cause of request
RW
RW
RW
RW
RW
RW
(b5-b4)
Refer to note
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
11. DMAC
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Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Register
DMAi control register
(i=0,1) Symbol Address After reset
DM0CON 002C
16
00000X00
2
DM1CON 003C
16
00000X00
2
Bit name FunctionBit symbol
Transfer unit bit select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit 0 : Single transfer
1 : Repeat transfer
DMA request bit 0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 2)
Destination address
direction select bit (Note 2) 0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).
(Note 1)
DMA1 request cause select register
Symbol Address After reset
DM1SL 03BA
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0 RW
DSEL1
DSEL2
DSEL3
Software DMA
request bit
DSR
DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)
0 0 0 0
2
Falling edge of INT1 pin –
0 0 0 1
2
Software trigger –
0 0 1 0
2
Timer A0 –
0 0 1 1
2
Timer A1 –
0 1 0 0
2
Timer A2 –
0 1 0 1
2
Timer A3 –
0 1 1 0
2
Timer A4 –
0 1 1 1
2
Timer B0 Two edges of INT1
1 0 0 0
2
Timer B1 –
1 0 0 1
2
Timer B2 –
1 0 1 0
2
UART0 transmit –
1 0 1 1
2
UART0 receive –
1 1 0 0
2
UART2 transmit –
1 1 0 1
2
UART2 receive/ACK2 –
1 1 1 0
2
A/D conversion –
1 1 1 1
2
UART1 receive –
Bit name
DMA request cause
expansion select bit
DMS
RW
RW
RW
RW
RW
RW
(b5-b4)
RW
RW
RW
RW
RW
RW
RW
(b7-b6)
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “0001
2
”
(software trigger).
The value of this bit when read is “0” .
0: Basic cause of request
1: Extended cause of request
Refer to note
11. DMAC
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Figure 11.4 SAR0 and SAR1, DAR0 and DAR1, TCR0 and TCR1 Registers (EC-03-UM60)
b7 b0 b7 b0
(b8)(b15)
Function
Set the transfer count minus 1. The written value is
stored in the DMAi transfer counter reload register, and
when the DMAE bit in the DMiCON register is set to “1”
(DMA enabled) or the DMAi transfer counter
underflows when the DMASL bit in the DMiCON
register is “1” (repeat transfer), the value of the DMAi
transfer counter reload register is transferred to the
DMAi transfer counter. When read, the DMAi transfer
counter is read.
Symbol Address After reset
TCR0 002916, 002816 Indeterminate
TCR1 003916, 003816 Indeterminate
DMAi transfer counter (i = 0, 1)
Setting range
000016 to FFFF16
b7
(b23) b3 b0 b7 b0 b7 b0
(b8)(b16)(b15)(b19)
Function RW
Set the source address of transfer
Symbol Address After reset
SAR0 002216 to 002016 Indeterminate
SAR1 003216 to 003016 Indeterminate
DMAi source pointer (i = 0, 1) (Note)
Setting range
0000016 to FFFFF16
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Symbol Address After reset
DAR0 002616 to 002416 Indeterminate
DAR1 003616 to 003416 Indeterminate
b3 b0 b7 b0 b7 b0
(b8)(b15)(b16)(b19)
Function
Set the destination address of transfer
DMAi destination pointer (i = 0, 1)(Note)
Setting range
0000016 to FFFFF16
b7
(b23)
RW
RW
RW
RW
RW
Note: If the DSD bit in the DMiCON register is “0” (fixed), this register can only be written to when theDMAE bit in the
DMiCON register is “0” (DMA disabled).
If the DSD bit is set to “1” (forward direction), this register can be written to at any time.
If the DSD bit is set to “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit in the DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is “0”(DMA disabled).
If the DAD bit is set to “1” (forward direction), this register can be written to at any time.
If the DAD bit is set to “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
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11.1 Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)
bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of
transfer. Furthermore, the bus cycle itself is extended by a software wait.
11.1.1 Effect of Source and Destination Addresses
If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source
read cycle consists of one more bus cycle than when the source address of transfer begins with an even
address.
Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address,
the destination write cycle consists of one more bus cycle than when the destination address of transfer
begins with an even address.
11.1.2 Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus
cycles required for that access increases by an amount equal to software wait states.
Figure 11.1.1 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating transfer cycles, take into consideration each condition for the
source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit
units and when both the source address and destination address are an odd address ((2) in Figure 11.1.1),
two source read bus cycles and two destination write bus cycles are required.
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Figure 11.1.1 Transfer Cycles for Source Read
CPU clock
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(3) When the source read cycle under condition (1) has one wait state inserted
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(4) When the source read cycle under condition (2) has one wait state inserted
Note: The same timing changes occur with the respective conditions at the destination as at the source.
CPU clock
CPU clock
CPU clock
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11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the
number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2.1 DMA Transfer Cycles
Table 11.2.2 Coefficient j, k
Transfer unit Access address No. of read cycles No. of write cycles
8-bit transfers Even 1 1
(DMBIT= “1”) Odd 1 1
16-bit transfers Even 1 1
(DMBIT= “0”) Odd 2 2
Internal area
Internal ROM, RAM SFR
No wait With wait
1
12
22
2
j
k
1 wait 2 wait
3
3
(Note) (Note)
Note: Depends on the set value of PM20 bit in PM2 register.
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11.3 DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON
register is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
11.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS
and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 11.4.1 shows the timing
at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set
to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a
program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 11.4.1 Timing at Which the DMAS Bit Changes State
DMA factor
Software trigger
Peripheral function
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
DMAS bit in the DMiCON register
When the DSR bit in the DMiSL
register is set to “1”
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits in the DMiSL register
has its IR bit set to “1”
• Immediately before a data transfer starts
• When set by writing “0” in a program
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11.5 Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de-
tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU
clock), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC
operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 11.5.1
shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 11.5.1, occurs more than one time, the DAMS bit is set to "0" as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Figure 11.5.1 DMA Transfer by External Factors
AAAA
AAAA
DMA0
AAAA
AAAA
DMA1
DMA0
request bit
DMA1
request bit
AAA
AAAAA
AA
AA
AAAAA
AA
AA
CPU
INT0
INT1
Obtainment
of the bus
right
An example where DMA requests for external causes are detected active at the same
CPU clock
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• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
• Timer mode
• One-shot timer mode
• PWM mode
• Timer mode
• One-shot timer mode
• PWM mode
• Timer mode
• One-shot timer mode
• PWM mode
• Timer mode
• One-shot timer mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
f8 f32 fC32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/32 fC32
1/8
1/4
f1 or f2
f8
f32
• Main clock
• PLL clock
• On-chip
oscillator clock
XCIN
Set the CPSR bit inthe
CPSRF register to “1”
(= prescaler reset)
Reset
Clock prescaler
Timer B2 overflow or underflow
1/2
f1
f2PCLK0 bit = "0"
PCLK0 bit = "1"
f1 or f2
Figure 12.1. Timer A Configuration
12. Timer
Note
The M16C/26A (42-pin version) do not include TB2IN pin. Do not use the function which needs this
pin.
Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as
either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of timer A and
timer B configuration, respectively.
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Figure 12.2. Timer B Configuration
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
TB0IN
TB1IN
TB2IN
Timer B0
Timer B1
Timer B2
f8 f32 fC32
Timer B0 interrupt
Noise
filter
Noise
filter
Noise
filter
1/32 fC32
XCIN Reset
Clock prescaler
Timer B2 overflow or underflow ( to Timer A count source)
Timer B1 interrupt
Timer B2 interrupt
1/8
1/4
f8
f32
1/2 f1 or f2
• Main clock
• PLL clock
• On-chip
oscillator clock Set the CPSR bit inthe
CPSRF register to “1”
(= prescaler reset)
f1
f2PCLK0 bit = "0"
PCLK0 bit = "1"
f1 or f2
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12.1 Timer A
Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Figure 12.1.2. TA0MR to TA4MR Registers
TABSR register
Up-count/down-count
TAi Addresses TAj TAk
Timer A0 0387
16
- 0386
16
Timer A4 Timer A1
Timer A1 0389
16
- 0388
16
Timer A0 Timer A2
Timer A2 038B
16
- 038A
16
Timer A1 Timer A3
Timer A3 038D
16
- 038C
16
Timer A2 Timer A4
Timer A4 038F
16
- 038E
16
Timer A3 Timer A0
Always counts down except
in event counter mode
Reload register
Counter
Low-order
8 bits
AAAA
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
f
1
or f
2
f
8
f
32
TAi
IN
(i = 0 to 4)
TB2 overflow
• Event counter
f
C32
Clock selection
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Pulse output
Toggle flip-flop
TAi
OUT
(i = 0 to 4)
Data bus low-order bits
Data bus high-order bits
A
A
UDF register
Down count
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Polarity
selection
To external
trigger circuit
(Note)
(Note)
Note: Overflow or underflow
Clock selection
Timer Ai mode register (i=0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each
operation mode
Count source select bit
Operation mode select bit RW
RW
RW
RW
RW
RW
RW
RW
Function varies with each
operation mode
Figure 12.1.1. Timer A Block Diagram
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Figure 12.1.3. TA0 to TA4 Registers, TABSR Register, and UDF Register
Symbol Address After reset
TA0 0387
16
, 0386
16
Indeterminate
TA1 0389
16
, 0388
16
Indeterminate
TA2 038B
16
, 038A
16
Indeterminate
TA3 038D
16
, 038C
16
Indeterminate
TA4 038F
16
, 038E
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Ai register (i= 0 to 4) (Note 1)
RW
Divide the count source by n + 1 where n =
set value
Function Setting range
Divide the count source by FFFF
16
– n + 1
where n = set value when counting up or
by n + 1 when counting down
Divide the count source by n where n = set
value and cause the timer to stop
Modify the pulse width as follows:
PWM period: (2
16
– 1) / fj
High level PWM pulse width: n / fj
where n = set value, fj = count source
frequency
0000
16
to FFFE
16
(Note 3, 4)
Note 1: The register must be accessed in 16 bit units.
Note 2: If the TAi register is set to ‘0000
16
,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘0000
16
,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘001
6’ while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
00
16
to FE
16
(High-order address)
00
16
to FF
16
(Low-order address)
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol Address After reset
UDF 0384
16
00
16
TA4P
TA3P
TA2P
Up/down flag (Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Symbol Address After reset
TABSR 0380
16
00
16
Count start flag
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2
IN
to TA4I
N
and TA2
OUT
to TA4
OUT
pins are set to
“0” (input mode).
Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit to “0”.
RW
RW
WO
WO
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
Timer
mode
Event
counter
mode
One-shot
timer mode
Pulse width
modulation
mode
(16-bit PWM)
Pulse width
modulation
mode
(8-bit PWM)
0000
16
to FFFF
16
0000
16
to FFFF
16
0000
16
to FFFF
16
(Notes 2, 4)
Mode
Modify the pulse width as follows:
PWM period: (2
8
– 1) x (m + 1)/ fj
High level PWM pulse width: (m + 1)n / fj
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency (Note 3, 4)
(Notes 2, 3)
(Note 5)
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Symbol Address After reset
CPSRF 038116 0XXXXXXX2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
CPSR
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
TA1TGL
Symbol Address After reset
TRGSR 038316 0016
Timer A1 event/trigger
select bit 0 0 : Input on TA1IN is selected (Note 1)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Input on TA2IN is selected (Note 1)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 : Input on TA3IN is selected (Note 1)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Input on TA4IN is selected (Note 1)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b1 b0
b3 b2
b5 b4
b7 b6
Note 1: Make sure the port direction bits for the TA1 IN to TA4IN pins are set to “0” (= input mode).
Note 2: Overflow or underflow
TA1OS
TA2OS
TA0OS
One-shot start flag Symbol Address After reset
ONSF 038216 0016
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA3OS
TA4OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA0TGL
TA0TGH
0 0 : Input on TA0IN is selected
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
RW
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits intheTAiMR register
(i = 0 to 4) issetto ‘102’ (= one-
shot timer mode) and the MR2 bit
inthe TAiMR register issetto “0”
(=TAiOS bit enabled). When read,
its content is “0”.
Z-phase input enable bit
TAZIE 0 : Z-phase input disabled
1 : Z-phase input enabled
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(b6-b0)
(Note 2)
(Note 2)
(Note 2)
Note 1: Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Figure 12.1.4. ONSF Register, TRGSR Register, and CPSRF Register
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Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Down-count
•
When the timer underflows, it reloads the reload register contents and continues counting
Divide ratio 1/(n+1) n: set value of TAi register (i= 0 to 4) 000016 to FFFF16
Count start condition Set TAiS bit in the TABSR register to “1” (= start counting)
Count stop condition Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer underflow
TAiIN pin function I/O port or gate input
TAiOUT pin function I/O port or pulse output
Read from timer Count value can be read by reading TAi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
12.1.1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1
shows TAiMR register in timer mode.
Table 12.1.1.1. Specifications in Timer Mode
Note 1: The port direction bit for the TAi
IN
pin must be set to “0” (= input mode).
Timer Ai mode register (i=0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output
(TA
iOUT
pin is a pulse output pin)
Gate function select bit 0 0 :
Gate function not available
0 1 : (TAi
IN
pin functions as I/O port)
1 0 : Counts while input on the TAi
IN
pin
is low (Note 1)
1 1 : Counts while input on the TAi
IN
pin
is high (Note 1)
b4 b3
MR2
MR1
MR3 Must be set to “0” in timer mode
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
000
RW
RW
RW
RW
RW
RW
RW
RW
}
Figure 12.1.1.1. Timer Ai Mode Register in Timer Mode
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Item Specification
Count source • External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
Count operation •Up-count or down-count can be selected by external signal or program
•When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divided ratio 1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16
Count start condition Set TAiS bit in the TABSR register to “1” (= start counting)
Count stop condition Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer overflow or underflow
TAiIN pin function I/O port or count source input
TAiOUT pin function I/O port, pulse output, or up/down-count select input
Read from timer Count value can be read by reading TAi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function •Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
•Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
12.1.2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifica-
tions in event counter mode (when not processing two-phase pulse signal). Table 12.1.2.2 lists specifica-
tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Figure 12.1.2.1 shows TAiMR register in event counter mode (when not processing two-phase pulse
signal). Figure 12.1.2.2 shows TA2MR to TA4MR registers in event counter mode (when processing two-
phase pulse signal with the timers A2, A3 and A4).
Table 12.1.2.1. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
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Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
Note 2: Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘00
2
’ (TAi
IN
pin input).
Note 3: Count down when input on TAi
OUT
pin is low or count up when input on that pin is high. The port
direction bit for TAi
OUT
pin must be set to “0” (= input mode).
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
(Note 1)
b1 b0
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin functions as I/O port)
1 : Pulse is output
(TAi
OUT
pin functions as pulse output pin)
Count polarity
select bit (Note 2)
MR2
MR1
MR3 Must be set to “0” in event counter mode
TCK0 Count operation type
select bit
010
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit 0 : UDF register
1 : Input signal to TA
iOUT
pin (Note 3)
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function RW
TCK1 Can be “0” or “1” when not using two-phase pulse signal
processing
TMOD1
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
RW
RW
RW
RW
RW
RW
RW
RW
Figure 12.1.2.1. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
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Item Specification
Count source •Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
Count operation •Up-count or down-count can be selected by two-phase pulse signal
•When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio 1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16
Count start condition Set TAiS bit in the TABSR register to “1” (= start counting)
Count stop condition Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer overflow or underflow
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read by reading timer A2, A3 or A4 register
Write to timer •
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
Select function (Note) •Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN
(j=2,3) pin when input signals on TAjOUT pin is “H”.
•Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.
Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
TAjOUT
Up-
count Up-
count Up-
count Down-
count Down-
count Down-
count
TAjIN
(j=2,3)
TAkOUT
TAkIN
(k=3,4)
Count up all edges
Count up all edges
Count down all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to 0 by Z-phase input.
Notes:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
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Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the TAiP bit in the UDF register to “1” (two-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to ‘00 2’ (TAiIN pin input).
• Set the
p
ort direction bits for TAiIN and TAiOUT to “0”
(
in
p
ut mode
)
.
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
Symbol Address After reset
TA2MR to TA4MR 039816 to 039A16 0016
b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 To use two-phase pulse signal processing, set this bit to “0”.
MR2
MR1
MR3
TCK1
TCK0
010
Bit name Function RW
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Note 1)(Note 2)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
001
RW
RW
RW
RW
RW
RW
RW
RW
To use two-phase pulse signal processing, set this bit to “0”.
To use two-phase pulse signal processing, set this bit to “1”.
To use two-phase pulse signal processing, set this bit to “0”.
Bit symbol
Figure 12.1.2.2. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)
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mm+11 2 3 4 5
TA3
OUT
(A phase)
Count source
TA3
IN
(B phase)
Timer A3
INT2
(Z phase)
(Note)
Input equal to or greater than one clock cycle
of count source
Note: This timing diagram is for the case where the POL bit in the INT2IC register is set to “1” (= rising edge).
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
_______
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase
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Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •Down-count
•
When the counter reaches 0000
16
, it stops counting after reloading a new value
•If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : set value of TAi register 000016 to FFFF16
However, the counter does not work if the divide-by-n value is set to 000016.
Count start condition TA iS b it i n t he TABSR register is set to “1” (start counting) and one of the
following triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit in the ONSF register is set to “1” (= timer starts)
Count stop condition • When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
Interrupt request generation timing
When the counter reaches “000016”
TAiIN pin function I/O port or trigger input
TAiOUT pin function I/O port or pulse output
Read from timer An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Pulse output function
The timer outputs a low when not counting and a high when counting.
Table 12.1.3.1. Specifications in One-shot Timer Mode
12.1.3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the
TAiMR register in one-shot timer mode.
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Figure 12.1.3.1. TAiMR Register in One-shot Timer Mode
Bit name
Timer Ai mode register (i=0 to 4)
Symbol Address After reset
TA0MR to TA4MR 396
16
to 039A
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin functions as I/O port)
1 : Pulse is output
(TAi
OUT
pin functions as a pulse output pin)
MR2
MR1
MR3 Must be set to “0” in one-shot timer mode
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
100
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
Trigger select bit
External trigger select
bit (Note 1)
0 : Falling edge of input signal to TAi
IN
pin (Note 2)
1 : Rising edge of input signal to TAi
IN
pin (Note 2)
Note 1: Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
RW
RW
RW
RW
RW
RW
RW
RW
RW
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12.1.4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows
TAiMR register in pulse width modulation mode. Figures 12.1.4.2 and 12.1.4.3 show examples of how a
16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.
Table 12.1.4.1. Specifications in Pulse Width Modulation Mode
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •D
own-count (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new value at a rising edge of PWM pulse and continues counting
•The timer is not affected by a trigger that occurs during counting
16-bit PWM •High level width n / fj n : set value of TAi register (i=o to 4)
•Cycle time (216-1) / fj fixed fj: count source frequency (f1, f2, f8, f32, fC32)
8-bit PWM
•
High level width n x (m+1) / fj n : set value of TAi register high-order address
•
Cycle time (2
8
-1) x (m+1) / fj m : set value of TAi register low-order address
Count start condition • TAiS bit in theTABSR register is set to “1” (= start counting)
• The TAiS bit is set to "1" and external trigger input from the TAiIN pin
• The TAiS bit is set to "1" and one of the following external triggers occurs
Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
Count stop condition TAiS bit is set to “0” (= stop counting)
Interrupt request generation timing
PWM pulse goes “L”
TAiIN pin function I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
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Figure 12.1.4.1. TAiMR Register in Pulse Width Modulation Mode
Bit name
(FB-10-UM60)
Timer Ai mode register (i= 0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
RW
111
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit (Note 1)
0: Falling edge of input signal to TAi
IN
pin(Note 2)
1: Rising edge of input signal to TAi
IN
pin(Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
0 : Write “1” to TAiS bit in the TASF register
1 : Selected by TAiTGH to TAiTGL bits
Note 1: Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘00
2
’ (TAi
IN
pin
input).
Note 2: The port direction bit for the TAi
IN
pin must be set to “0” (= input mode).
0: Pulse is not output(TAiOUT pin functions as I/O port)
1: Pulse is output(TAiOUT pin functions as a pulse
output pin)
Pulse output funcion
select bit
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Count source (Note1)
Input signal to
TA
iIN
pin
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TA
iOUT
pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Set to “0” upon accepting an interrupt request or by writing in program
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FF
16
; n = 00
16
to FE
16
.
Note 4: This timing diagram is for the case where the TAi register is set to "0202
16
", the TAiTGH and TAiTGL bits in the
ONSF or TRGSR register is set to "00
2
" (TAi
IN
pin input), the MR1 bit in the TAiMR register is set to "0"(falling
edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
1 / f
j
X (m
+ 1) X (2 – 1)
8
1 / f
j
X (m + 1) X n
1 / f
j
X (m + 1)
IR bit in the
TAiIC register
f
j
: Frequency of count source
(f
1
, f
2
, f
8
, f
32
, f
C32
)
i = 0 to 4
Figure 12.1.4.2. Example of 16-bit Pulse Width Modulator Operation
Figure 12.1.4.3. Example of 8-bit Pulse Width Modulator Operation
1 / f
i
X
(2 – 1)
16
Count source
Input signal to
TAiIN pin
PWM pulse output
from TAiOUT pin
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
IR bit in the
TAiIC register
“1”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
i = 0 to 4
Note 1: n = 000016 to FFFE16.
Note 2: This timing diagram is for the case where the TAi register is set to "0003 16", the TAiTGH and TAiTGL bits
in the ONSF or TRGSR register is set to "00 2" (TAiIN pin input), the MR1 bit in the TAiMR register is set
to "1" (rising edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and
TAiTGL bits).
1 / f
j X
n
Set to “0” upon accepting an interrupt request or by writing in program
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Figure 12.2.1. Timer B Block Diagram
Clock source selection
• Event counter
• Timer
• Pulse period measuremnet,
pulse width measurement Reload register
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f1 or f2
f8
f32
TBj overflow (Note)
(j = i – 1, except j = 2 if i = 0)
Can be selected in only
event counter mode
TABSR register
fC32
Polarity switching,
edge pulse
TBiIN
(i = 0 to 2)
Counter reset circuit
Counter
TBi Address TBj
Timer B0 039116
-
039016 Timer B2
Timer B1 039316
-
039216 Timer B0
Timer B2 039516
-
039416 Timer B1
Clock selection
Note: Overflow or underflow.
12.2 Timer B
Note
The M16C/26A(42-pin version) do not include TB2IN pin of Timer B2.
[Precautions when using Timer B2]
• Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the
TB2MR register to “1” when using the Event Count Mode.
• Pulse Period/Pulse Width Measurement Mode
This mode connot be used.
Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the
timer B.
Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to
2) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
• A/D trigger mode: The timer counts only once before it reaches the minimum count "000016". Used in
conjunction with the A/D converter.
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Timer Bi mode register (i=0 to 2)
Symbol Address After reset
TB0MR to TB2MR 039B
16 to 039D16 00XX00002
Bit
name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode or A/D trigger mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation
mode
Count source select bit
Operation mode select bit
(Note 1)
(Note 2)
Note 1: Timer B0.
Note 2: Timer B1, Timer B2.
RW
RW
RW
RW
RW
RW
RW
RO
Function varies with each operation
mode
Figure 12.2.2. TB0MR to TB2MR Registers
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Symbol Address After reset
TABSR 038016 0016
Count start flag
Bit name
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Function
Symbol Address After reset
TB0 039116, 039016 Indeterminate
TB1 039316, 039216 Indeterminate
TB2 039516, 039416 Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Bi register (i=0 to 2)(Note 1)
RW
Measures a pulse period or width
Function
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Note 3: When this mode is used combining delayed trigger mode 0, set the larger value than the
value of the timer B0 register to the timer B1 register.
Divide the count source by n + 1
where n = set value
Timer mode
Event counter
mode
000016 to FFFF16
Divide the count source by n + 1
where n = set value (Note 2) 000016 to FFFF16
Pulse period
modulation mode,
Pulse width
modulation mode
Symbol Address After reset
CPSRF 038116 0XXXXXXX2
Clock prescaler reset flag
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Clock prescaler reset flag
CPSR
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
RW
RW
(b6-b0)
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
Mode Setting range
A/D trigger
mode (Note 3) Divide the count source by n + 1 where
n = set value and cause the timer stop
RW
000016 to FFFF16
Figure 12.2.3. TB0 to TB2 Registers, TABSR Register, CPSRF Register
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Item Specification
Count source f1, f2, f8, f32, fC32
Count operation •Down-count
•When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBi register (i= 0 to 2) 000016 to FFFF16
Count start condition Set TBiS bit(1) to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer underflow
TBiIN pin function I/O port
Read from timer Count value can be read by reading TBi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTES :
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
12.2.1 Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1
shows TBiMR register in timer mode.
Table 12.2.1.1 Specifications in Timer Mode
Timer Bi mode register (i= 0 to 2)
Symbol Address After reset
TB0MR to TB2MR 039B
16
to 039D
16
00XX0000
2
Bit name Function
Bit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
Operation mode select bit 0 0 : Timer mode or A/D trigger mode
b1 b0
TMOD1
TMOD0
MR0 Has no effect in timer mode
Can be set to “0” or “1”
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0 Count source select bit
00
TB0MR register
Must be set to “0” in timer mode
b7 b6
RW
RW
RW
RW
RW
RW
RW
RO
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
Figure 12.2.1.1 TBiMR Register in Timer Mode
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Item Specification
Count source • External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)
Count operation •Down-count
•When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16
Count start condition Set TBiS bit(1) to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer underflow
TBiIN pin function Count source input
Read from timer Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTES :
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode.
Table 12.2.2.1 Specifications in Event Counter Mode
Figure 12.2.2.1 TBiMR Register in Event Counter Mode
Timer Bi mode register (i=0 to 2)
Symbol Address After reset
TB0MR to TB2MR 039B16 to 039D16 00XX00002
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
AA
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Count polarity select
bit (Note 1)
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
b3 b2
Note 1: Effective when the TCK1 bit is set to “0” (input from TBiIN pin). If the TCK1 bit is set to “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Has no effect in event counter mode.
Can be set to “0” or “1”.
Event clock select 0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0)
RW
RW
RW
RW
RW
RW
RW
RO
TB0MR register
Must be set to “0” in timer mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
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Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Up-count
•Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to “000016” to continue counting.
Count start condition Set TBiS (i=0 to 2) bit(3) to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing
• When an effective edge of measurement pulse is input(1)
• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is
set to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no over-
flow) by writing to TBiMR register at the next count timing or later after MR3
bit was set to “1”. At this time, make sure TBiS bit is set to “1” (start count-
ing).
TBiIN pin function Measurement pulse input
Read from timer
Contents of the reload register (measurement result) can be read by reading TBi register(2)
Write to timer Value written to TBi register is written to neither reload register nor counter
Notes:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the
bit 5 to bit 7
in the TABSR register.
12.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse
width measurement mode. Figure 12.2.3.2 shows the operation timing when measuring a pulse period.
Figure 12.2.3.3 shows the operation timing when measuring a pulse width.
Table 12.2.3.1 Specifications in Pulse Period and Pulse Width Measurement Mode
Figure 12.2.3.1
TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Timer Bi mode register (i=0 to 2)
Symbol Address After reset
TB0MR to TB2MR 039B
16
to 039D
16
00XX0000
2
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 0 : Pulse period / pulse width
measurement mode
b1 b0
TMOD1
TMOD0
MR0 Measurement mode
select bit
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
Function
b3 b2
Count source
select bit
Timer Bi overflow
flag ( Note) 0 : Timer did not overflow
1 : Timer has overflowed
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Note: This flag is indeterminate after reset. When the TBiS bit is set to "1" (start counting), the MR3 bit is cleared to “0” (no overflow) by writing to the
TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to “1” in a program. The
TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
RW
RW
RW
RW
RW
RW
RW
RO
TB0MR register
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
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Figure 12.2.3.3 Operation timing when measuring a pulse width
Measurement pulse “H”
Count source
Timing at which counter
reaches “000016”
“1”
“1”
Transfer
(measured value) Transfer
(measured value)
“L”
“0”
“0”
“1”
“0”
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1) (Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
TBiS bit
IR bit in the TBiIC
register
MR3 bit in the TBiMR
register
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “102” (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of
the measurement pulse).
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Set to “0” upon accepting an interrupt request or by
writing in program
i = 0 to 2
Figure 12.2.3.2 Operation timing when measuring a pulse period
Count source
Measurement pulse
TBiS bit
IR bit in the TBiIC
register
Timing at which counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
MR3 bit in theTBiMR
register
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00
2
” (measure the
interval from falling edge to falling edge of the measurement pulse).
(Note 1)(Note 1) (Note 2)
Transfer
(measured value)
“1”
Reload register counter
transfer timing
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Set to “0” upon accepting an interrupt request or by writing in
program
i = 0 to 2
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12.2.4 A/D Trigger Mode
A/D trigger mode is used as conversion start trigger for A/D converter in simultaneous sample sweep
mode of A/D conversion or delayed trigger mode 0. This mode is used as conversion start trigger of A/D
converter. A/D trigger mode is used in Timer B0 and Timer B1. In this mode, the timer is activated only by
one trigger. A/D trigger mode is available only for TB0 and TB1. Figure 12.2.4.1 shows the TBiMR regis-
ter in A/D trigger mode and figure 12.2.4.2 shows the TB2SC register.
Item Specification
Count Source f1, f2, f8, f32, and fC32
Count Operation •Down count
•When the timer underflows, reload register contents are reloaded before
stopping counting
•When a trigger is generated during the count operation, the count is not
affected
Divide Ratio 1/(n+1) n: Setting value of TBi register (i=0,1)
000016-FFFF16
Count Start Condition When the TBiS (i=0,1) bit in the TABSR register is "1"(count started), TBiEN
(i=0,1) bit in TB2SC register is "1", and the following trigger is generated.
(Selection based on TB2SEL bit in the TB2SC register)
• Timer B2 overflow or underflow
• Underflow of Timer B2 interrupt generation frequency counter setting
Count Stop Condition • After the count value is 000016 and reload register contents are reloaded
• Set the TBiS bit to "0"(count stopped)
I
nterrupt Request Timer underflows (1)
Generation Timing
TBiIN Pin Function I/O port
Read From Timer Count value can be read by reading TBi register
Write To Timer (2) • When writing in the TBi register during count stopped.
Value is written to both reload register and counter
• When writing in the TBi register during count.
Value is written to only reload register (Transfered to counter when reloaded next)
NOTES:
1. A/D conversion is started by the timer underflow. For details refer to Section 14. A/D Converter.
2. When using in delayed trigger mode 0, set the larger value than the value of the timer B0 register
to the timer B1 register.
Table 12.2.4.1 A/D Trigger Mode Specifications
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Timer Bi mode register (i= 0 to 1)
Symbol Address After reset
TB0MR to TB1MR 039B
16
to 039C
16
00XX0000
2
Bit name Function
Bit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
AA
A
Operation Mode Select Bit 0 0 : Timer mode or A/D trigger mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in A/D trigger mode
Either "0" or "1" is enabled
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0 Count Source Select Bit
(Note 1)
00
TB0MR register
Set to “0” in A/D trigger mode
b7 b6
RW
RW
RW
RW
RW
RW
RW
RO
TB1MR register
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
When write in A/D trigger mode, set to “0”. When read in A/D
trigger mode, its content is indeterminate.
Note 1: When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
0
), U(P8
1
), V(P7
2
), V(P7
3
), W(P7
4
), W(P7
5
). After forcible cutoff, input "H" to the P8
5
/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If “L” is input to the P8
5
/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to 16.6 Digital Debounce function for SD input.
PWCOM
Symbol Address After reset
TB2SC 039E
16
X0000000
2
Timer B2 Reload Timing
Switch Bit 0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 special mode register (Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
IVPCR1 Three-Phase Output Port
SD Control Bit 1 0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7)
TB2SEL Trigger Select Bit 0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
RW
RW
TB0EN Timer B0 Operation Mode
Select Bit 0 : Other than A/D trigger mode
1 : A/D trigger mode
(Note 5)
RW
TB1EN Timer B1 Operation Mode
Select Bit 0 : Other than A/D trigger mode
1 : A/D trigger mode
(Note 5)
RW
(Note 2)
(Note 3, 4, 7)
(Note 6)
(b6-b5) Reserved bits Must set to "0"
00
Figure 12.2.4.2 TB2SC Register
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Item Specification
Three-phase waveform output pin ___ ___ ___
Six pins (U, U, V, V, W, W)
Forced cutoff input (Note 1) _____
Input “L” to SD pin
Used Timers Timer A4, A1, A2 (used in the one-shot timer mode)
___
Timer A4: U- and U-phase waveform control
___
Timer A1: V- and V-phase waveform control
___
Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
Carrier wave cycle control
Dead timer timer (3 eight-bit timer and shared reload register)
Dead time control
Output waveform Triangular wave modulation, Sawtooth wave modification
Enable to output “H” or “L” for one cycle
Enable to set positive-phase level and negative-phase
level respectively
Carrier wave cycle Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: Setting value of TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-phase PWM output width Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n: Setting value of TA4, TA1 and TA2 register (of TA4,
TA41, TA1, TA11, TA2 and TA21 registers when setting
the INV11 bit to “1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead time Count source x p, or no dead time
p: Setting value of DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Active level Eable to select “H” or “L”
Positive and negative-phase concurrent
Positive and negative-phases concurrent active disable function
Positive and negative-phases concurrent active detect function
Interrupt frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle
basis through 15 times carrier wave cycle-to-cycle basis
12.3 Three-phase Motor Control Timer Function
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the
specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for
three-phase motor control timer function. Also, the related registers are shown on Figure 12.3.2 to Figure
12.3.8.
Table 12.3.1. Three-phase Motor Control Timer Function Specifications
active disable function
Notes: _____
1. When the INV02 bit in the INVC0 register is set to “1” (three-phase motor control timer function), the SD
_____
function of the P85/SD pin is enabled. At this time, the P85 pin cannot be used as a programmable I/O
_____ _____
port. When the SD function is not used, apply “H” to the P85/SD pin. _____
2. When the IVPCR1 bit in the TB2SC register is set to “1” (enable three-phase output forced cutoff by SD
_____
pin input), and “L” is applied to the SD pin, the related pins enter high-impedance state regardless of the
functions which are used. When the IVPCR1 bit is set to “0” (disabled three-phase output forced cutoff
_____ _____
by SD pin input) and “L” is applied to the SD pin, the related pins can be selected as a programmable I/
O port and the setting of the port and port direction registers are enable.
Related pins P72/CLK2/TA1OUT/V/RxD1
_________ _________ ___
P73/CTS2/RTS2/TA1IN/V/TxD1
P74/TA2OUT/W
____
P75/TA2IN/W
P80/TA4OUT/U
___
P81/TA4IN/U
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DRQ
0INV12
1
Trigger
Trigger
Timer B2
(Timer mode)
Signal to be
written to
timer B2
1Timer B2
interrupt request bit
DU1
bit
D
TQQ
Q
U
Three-phase output
shift register
(U phase)
Dead time timer
n = 1 to 255
Trigger
Trigger
Reload register
n = 1 to 255
Trigger
Trigger
U
phase output signal
U
V
V
V
W
W
W phase output
control circuit
DQ
T
DQ
T
W
DQ
T
DQ
T
V
DQ
T
DQ
T
U
W
V
U
Reload
Timer A 1 counter
(One-shot timer mode)
Trigger
TQ
Reload
Timer A 2 counter
(One-shot timer mode)
Trigger
TQ
Reload
Timer A4 counter
(One-shot timer mode)
Trigger
TQ
Transfer trigger
(Note 1)
Timer B2 underflow
DU0
bit
DUB0
bit
TA4 register
TA41
register
TA1
register
TA11
register
TA2
register
TA21
register
Timer Ai(i = 1, 2, 4) start trigger signal
Timer A4 reload control signal
Timer A4
one-shot pulse
DUB1
bit
Dead time timer
n = 1 to 255
Dead time timer
n = 1 to 255
Interrupt occurrence set circuit
ICTB2 register
n = 1 to 15
0
INV13
ICTB2 counter
n = 1 to 15
SD
RESET
INV03
INV14
INV05
INV04
INV00 INV01
INV11
INV11
INV11
INV11
INV06
INV06
INV06
INV07
INV10
1/2
f1 or f2
phase output
control circuit
phase output
control circuit
phase output signal
phase output signal
phase output
signal
phase output signal
phase output signal
Reverse
control
Reverse
control
Reverse
control
Reverse
control
Reverse
control
D
T
D
TQD
T
Reverse
control
IDW
IDV
IDU
D
QT
D
QT
D
QT
b2
b0
b1
Bits 2 through 0 of Position-data-
retain function control register
(address 034E16)
PD8_0
PD8_1
PD7_2
PD7_3
PD7_4
PD7_5
SQ
R
RESET
SD
IVPRC1
Data Bus
Note : If the INV06 bit is set to "0" (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers.
Set to "0" when the TA2S bit is set to "0"
Set to "0" when TA1S bit = "0"
Set to "0" when TA4S bit = "0"
Diagram for switching to P8
0
, P81 and P7
2
- P7
5
is not shown.
Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram
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Three-phase PWM control register 0 (Note 1)
Symbol Address After reset
INVC0 0348
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Effective interrupt output
polarity select bit
INV00
Bit symbol Bit name Description RW
INV01
Effective interrupt output
specification bit
INV02 Mode select bit
INV04 Positive and negative
phases concurrent output
disable bit
INV07 Software trigger select bit
INV06 Modulation mode select
bit
INV05 Positive and negative
phases concurrent output
detect flag
INV03 Output control bit
0: The ICTB2 counter is incremented by
one on the reising edge of the timer A1
reload control signal
1: The ICTB2 counter is incremented by
one on the falling edge of the timer A1
reload control signal
0:
ICTB2 counter incremented by 1 at a
timer B2 underflow
1: Selected by INV00 bit
0: Three-phase motor control timer
function unused
1: Three-phase motor control timer
function
0: Three-phase motor control timer output
disabled
1: Three-phase motor control timer output
enabled
0: Simultaneous active output enabled
1: Simultaneous active output disabled
0: Not detected yet
1: Already detected
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
Setting this bit to “1” generates a transfer
trigger. If the INV06 bit is “1”, a trigger for
the dead time timer is also generated.
The value of this bit when read is “0”.
(Note 9)
(Note 3)
(Note 7)
(Note 2, Note 3)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that INV00 to INV02,
INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.
Note 3: Effective when the INV11 bit is set to “1” (three-phase mode 1). If INV11 is set to “0” (three-phase mode 0), the ICTB2
counter is incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
When setting the INV01 bit to “1”, set the timer A1 count start flag before the first timer B2 underflow.
When the INV00 bit is set to “1”, the first interrupt is generated when the timer B2 underflows n-1 times, if n is the value set
in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 underflow.
Note 4: Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
Note 5: When the INV02 bit is set to “1”(theee-phase control timer functions) and the INV03 is set to "0"(three-phase motor control
timer output disabled), U, U, V, V, W and W pins, including pins shared with other output functions, enter a high-
impedance state.
Note 6: The INV03 bit is set to “0” in the following cases:
• When reset
• When positive and negative go active (INV05="1") simultaneously while INV04 bit is set to “1”
• When set to “0” in a program
• When input on the SD pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when SD input is “L”.)
When both the INV04 and the INV05 bits are set to “1”, the INV03 bit is set to “0”.
Note 7: Can only be set by writing “0” in a program, and cannot be set to “1”.
Note 8: The effects of the INV06 bit are described in the table below.
(Note 4)
RW
RW
RW
RW
RW
RW
RW
RW
(Note 5)
(Note 8)
Item
Mode
Timing at which transferred from IDB0 to
IDB1 registers to three-phase output shift
register
Timing at which dead time timer trigger is
generated when INV16 bit is “0”
INV13 bit
INV06=0
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
the IDB0 to IDB1 registers
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Effective when INV11 is “1” and INV06
is “0”
INV06=1
Sawtooth wave modulation mode
Transferred every transfer trigger
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”
Note 9: If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2
reloaded by a timer B2 underflow).
Note10: Individual pins can be disabled using PFCR register.
(Note 6)
Has no effect
(Note 10)
(Note 5)
Figure 12.3.2. INVC0 Register
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Figure 12.3.3. INVC1 Register
Three-phase PWM control register 1
(Note 1)
Symbol Address After reset
INVC1 0349
16 0016
b7 b6 b5 b4 b3 b2 b1 b0
Timer A1, A2, A4 start
trigger signal select bit
INV10
Bit symbol Bit name Description RW
INV11
Timer A1-1, A2-1, A4-1
control bit
INV12 Dead time timer count
source select bit
INV14 Output polarity control bit
(b7) Reserved bit
INV16 Dead time timer trigger
select bit
INV15 Dead time invalid bit
INV13 Carrier wave detect flag
0: Timer B2 underflow
1: Timer B2 underflow and write to the
TB2 register
0: Three-phase mode 0
1: Three-phase mode 1
0 : f
1 or f2
1 : f1 divided by 2 or f2 divided by 2
0: Timer A1 reload control signal is “0”
1: Timer A1 reload control signal is “1”
0 : Output waveform “L” active
1 : Output waveform “H” active
0: Dead time timer enabled
1: Dead time timer disabled
0: Falling edge of timer A4, A1 or A2
one-shot pulse
1: Rising edge of three-phase output shift
register (U, V or W phase) output
This bit should be set to “0”
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that this
register can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: A start trigger is generated by writing to the TB2 register only while timer B2 stops.
Note 3: The effects of the INV11 bit are described in the table below.
(Note 6)
(Note 5)
RW
RW
RW
RW
RW
RW
RW
RO
(Note 3)
Item
Mode
TA11, TA21, TA41 registers
INV00 bit, INV01 bit
INV13 bit
INV11=0
Three-phase mode 1
Three-phase mode 0
Not used
Has no effect. ICTB2 counted every time
timer B2 underflows regardless of
whether the INV00 to INV01 bits are set.
Has no effect
INV11=1
Used
Effect
Effective when INV11 bit is set to “1”
and INV06 bit is set to “0”
Note 4: If the INV06 bit is set to “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if
the INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).
Note 5: The INV13 bit is effective only when the INV06 bit is set to “0” (triangular wave modulation mode) and the INV1
1 bit is set to “1” (three-phase mode 1).
Note 6: If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge
of three-phase output shift register output)
• The INV15 bit is set to “0” (dead time timer enabled)
• When the INV03 bit is set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U,
V, or W, j: 0 to 1) have always different values (the positive-phase and negative-phase always output
different levels during the period other than dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered
by the falling edge of one-shot pulse).
(Note 4)
0
(Note 2)
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Timer B2 interrupt occurrences frequency set counter
Symbol Address After reset
ICTB2 034D16 X?16
Function
Setting range
b7 b0
If the INV01 bit is “0” (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow.
If the INV01 bit is “1” (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every n'th
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit.
1 to 15
Note : Use MOV instruction to write to this register.
If the INV01 bit is set to “1”, make sure the TB2S bit also is set to “0” (timer B2 count stopped) when writing to this register.
If the INV01 bit is set to “0”, although this register can be written even when the TB2S bit is set to “1” (timer B2 count start),
do not write synchronously with a timer B2 underflow.
RW
WO
(Note)
Nothing is assigned. When write, set to “0”. When read, its content is
indeterminate.
b3
Three-phase output bu
ff
er re
g
ister(i=0,1) (Note)
Symbol Address When reset
IDB0 034A
16
3F
16
IDB1 034B
16
3F
16
RW
RW
RW
RWBit name FunctionBit
DUi
DUBi
DVi
U phase output buffer i
Note: The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The value
written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value
written to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal
of each phase.
(b7-b6)
RW
DVBi
Nothing is assigned. When write, set to "0". When read,
these contents are "0".
Write the output level
0: Active level
1: Inactive level
When read, these bits show the three-phase
output shift register value.
DWi
DWBi
RW
RW
U phase output buffer i
V phase output buffer i
V phase output buffer i
W phase output buffer i
W phase output buffer i
b
7
b5
b
4
b3
b
2b1b0
Dead time timer (Note 1, Note 2)
Symbol Address When reset
DTT 034C
16
??
16
WO
RWFunction Setting range
Note 1: Use MOV instruction to write to this register.
Note 2: Effective when the INV15 bit is set to “0” (dead time timer enable). If the ONV15 bit is set to “1”, the dead time timer
is disabled and has no effect.
1 to 255
b7 b6 b5 b4 b3 b2 b1 b0
Assuming the set value = n, upon a start trigger the timer starts
counting the count souce selected by the INV12 bit and stops
after counting it n times. The positive or negative phase
whichever is going from an inactive to an active level changes
at the same time the dead time timer stops.
Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICCTB2 Register
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Figure 12.3.5.
TA1, TA2, TA4, TA11, TA21 and TA41 Registers
Symbol Address After reset
TA1 0389
16
-0388
16
TA2 038B
16
-038A
16
Indeterminate
TA4 038F
16
-038E
16
Indeterminate
TA11 (Note6,7) 0343
16
-0342
16
Indeterminate
TA21 (Note6,7) 0345
16
-0344
16
Indeterminate
TA41 (Note6,7) 0347
16
-0346
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
RW
Assuming the set value = n, upon a start trigger the timer
starts counting the count source and stops after counting
it n times. The positive and negative phases change at
the same time timer A, A2 or A4 stops.
Function Setting range
Timer Ai, Ai-1 register (i=1, 2, 4) (Note 1, Note 2, Note 3, Note 4, Note 5)
Note 1: The register must be accessed in 16 bit units.
Note 2: When the timer Ai register is set to "0000
16
", the counter does not operate and a timer Ai interrupt does
not occur.
Note 3: Use MOV instruction to write to these registers.
Note 4: If the INV15 bit is "0" (dead time timer enable), the positive or negative phase whichever is going from an
inactive to an active level changes at the same time the dead time timer stops.
Note 5: If the INV11 bit is "0" (three-phase mode 0), the TAi register value is transferred to the reload register by
a timer Ai (i = 1, 2 or 4) start trigger.
If the INV11 bit is "1" (three-phase mode 1), the TAi1 register value is transferred to the reload register
by a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the
next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the
reload register alternately.
Note 6: Do not write to TAi1 registers synchronously with a timer B2 underflow In three-phase mode 1..
.
Note 7: Write to the TAi1 register as follows:
(1) Write a value to the TAi1 register
(2) Wait for one cycle of timer Ai count source.
(3) Write the same value to the TAi1 register again.
WO
0000
16
to FFFF
16
Indeterminate
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Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
0
), U(P8
1
), V(P7
2
), V(P7
3
), W(P7
4
), W(P7
5
). After forcible cutoff, input "H" to the P8
5
/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If “L” is input to the P8
5
/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to 16.6 Digital Debounce function for SD input.
IVPCR1 bit status of U/V/W pins Remarks
P8
5
/NMT/SD pin inputs
"1"
(Three-phase output
forcrible cutoff enable)
"0"
(Three-phase output
forcrible cutoff disable)
H
L
H
L
High impedance
peripheral input/output
or input/output port
peripheral input/output
or input/output port
peripheral input/output
or input/output port
Three-phase output
forcrible cutoff(Note 1)
Note 1: The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to "1" (three-phase
output forcrible cutoff function enable) even when INV03 bit is "0"(three-phase motor control timer output
disalbe)
IVPCR1 bit status of U/V/W pins Remarks
P8
5
/NMT/SD pin inputs
(Note 3)
"1"
(Three-phase output
forcrible cutoff enable)
"0"
(Three-phase output
forcrible cutoff disable)
H
L(Note 1)
H
L(Note 1)
High impedance Three-phase output
forcrible cutoff
Note 1: When "L" is input to the P8
5
/NMI/SD pin, INV03 bit changes in "0" at the same time.
Note 2: The value of the port register and the port direction register becomes effective.
Note 3: When SD function isn't used, set to "0"(Input) in PD8
5
and pullup to "H" in P8
5
/NMI/SD pin from outside.
Input/output port(Note 2)
Three-phase PWM output
Three-phase PWM output
The effect of P8
5
/NMI/SD pin input is below.
1.Case of INV03 = "1"(Three-phase motor control timer output enabled)
2.Case of INV03 = "0"(Three-phase motor control timer output disabled)
PWCOM
Symbol Address After reset
TB2SC 039E
16
X0000000
2
Timer B2 Reload Timing
Switch Bit 0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 special mode register
(Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
IVPCR1 Three-Phase Output Port
SD Control Bit 1 0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7)
TB2SEL Trigger Select Bit 0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
RW
RW
TB0EN Timer B0 Operation Mode
Select Bit 0 : Other than A/D trigger mode
1 : A/D trigger mode
(Note 5)
RW
TB1EN Timer B1 Operation Mode
Select Bit 0 : Other than A/D trigger mode
1 : A/D trigger mode
(Note 5)
RW
(Note 2)
(Note 3, 4, 7)
(Note 6)
(b6-b5) Reserved bits Must set to "0"
00
Figure 12.3.6.
TB2SC Registers
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Figure 12.3.7. TB2 Register, TRGSR Register, and TABSR Register
TA1TGL
Symbol Address After reset
TRGSR 0383
16
00
16
Timer A1 event/trigger
select bit To use the V-phase output control
circuit, set these bits to “01
2
”(TB2
underflow).
Trigger select register
Bit name Function
Bit symbol
b0
To use the W-phase output control
circuit, set these bits to “01
2
”(TB2
underflow).
0 0 :
Input on TA3
IN
is selected (Note 1)
0 1 :
TB2 overflow is selected (Note 2)
1 0 :
TA2 overflow is selected
(Note 2)
1 1 :
TA4 overflow is selected (Note 2)
To use the U-phase output control
circuit, set these bits to “01
2
”(TB2
underflow).
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
RW
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b5 b4
Note 1: Set the corresponding port direction bit to “0” (input mode).
Note 2: Overflow or underflow.
b7 b6 b5 b4 b3 b2 b1
Symbol Address After reset
TABSR 0380
16
00
16
Count start flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Symbol Address After reset
TB2 0395
16
-0394
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
RW
0000
16
to FFFF
16
Function Setting range
Timer B2 register (Note )
Note : The register must be accessed in 16 bit units.
RW
Divide the count source by n + 1 where n = set value.
Timer A1, A2 and A4 are started at every occurrence of
underflow.
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Bit name
Timer Ai mode register
Symbol Address After reset
TA1MR 0397
16
00
16
TA2MR 0398
16
00
16
TA4MR 039A
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit Must set to “10
2
” (one-shot timer mode) for
the three-phase motor control timer function
TMOD1
TMOD0
MR0 Pulse output function
select bit Must set to “0” for the three-phase motor
control timer function
MR2
MR1
MR3 Must set to “0” for the three-phase motor control timer function
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
100
Must set to “1” (selected by event/trigger
select register) for the three-phase motor
control timer function
Trigger select bit
External trigger select
bit
RW
Timer B2 mode register
Symbol Address After reset
TB2MR 039D
16
00XX0000
2
Bit name Function
Bit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
AA
AA
Operation mode select bit Set to “00
2
” (timer mode) for the three-
phase motor control timer function
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0 Count source select bit
0
When write in three-phase motor control timer function, write “0”.
When read, its content is indeterminate.
0
b7 b6
1
0
Has no effect for the three-phase motor
control timer function
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Has no effect for the three-phase motor control timer function.
When write, set to “0”. When read, its content is indeterminate.
Must set to “0” for the three-phase motor control timer function
0
Figure 12.3.8. TA1MR, TA2MR, TA4MR, and TB2MR Registers
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Start trigger signal
for timer A4*
Timer B2
U phase
C
arr
i
er wave
Signal wave
U phase
output signal *
mnn pp
m
U phase
U phase
U phase
INV14 = 0
Timer A4
one-shot pulse*
INV14 = 1
Dead time
Dead time
Transfer to three-phase
output shift register
Rewriting IDB0, IDB1 registers
* Internal signals. See the block diagram of the three-phase motor control timer function.
An example for changing PWM outputs is shown below.
(1)When INV11=1(three-phase mode 1)
· INV01=0, ICTB2=216(timer B2 interrupt is generated at every 2’th
occurrence of a timer B2 underflow), or INV01=1, INV00=1,
ICTB2=116(The timer B2 interrupt is generated on the falling
edge of the timer A1 reload control signal)
· Initial timer value: TA41=m, TA4=m. The TA4 and TA41 registers
are modified every time a timer B2 interrupt occurs. First time,
TA41= n, TA4 = n. Second time, TA41 = p, TA4 = p.
· Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0,
DU1 = 0, DUB1 = 1.The register values are changed to DU0 = 1,
DUB0 = 0, DU1= 1 and DUB1 = 0 the third time a timer B2
interrupt occurs.
(2)When INV11=0(three-phase mode 0)
· INV01=0, ICTB2=116(timer B2 interrupt is generated at every
occurrence of a timer B2 underflow)
· Initial timer value: TA4 = m. The TA4 register is modified each time
a timer B2 interrupt occurs. First time, TA4 = m. Second time, TA4 = n.
Third time, TA4 = n. Fourth time, TA4 = p. Fifth time, TA4 = p.
· Initial values of IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0,
DUB1=1.The register values are changed to DU0 = 1, DUB0 = 0, DU1=
1 and DUB1 = 0 the sixth time a timer B2 interrupt occurs.
TB2S bit in the
TABSR register
INV13
(INV11=1(three-phase
mode 1))
Shown here is a typical waveform for the case where INVC0 = 00XX11XX2 (X = set as suitable for the system) and INVC1 = 010XXXX02.
U phase
output signal *
(“L” active)
(“H” active)
The value written to the TA4 register and TA41 register are transferred on the rising edge of the timer A1 reload signal.
Figure 12.3.9. Triangular Wave Modulation Operation
The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 register to “1”.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to
__ ___ ___
control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated dead-
time timer. Figure 12.3.9 shows the example of triangular modulation waveform, and Figure 12.3.10 shows
the example of sawtooth modulation waveform.
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Timer B2
U phase
Carrier wave
Signal wave
U phase
output signal *
U phase
U phase
output signal *
U phase
U phase
INV14 = 0
Carrier wave: sawtooth waveform
INV14 = 1
Transfer to three-phase
output shift register
Rewriting IDB0, IDB1 registers
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0= 01XX110X2 (X = set as suitable for the
system) and INVC1 = 010XXX002. An example for changing PWM outputs is shown below.
• Initial values of IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1. The register values are
changed to DU0=1, DUB0=0, DU1=1, DUB1=1 a timer B2 interrupt occurs.
Start trigger signal
for timer A4*
Timer A4
one-shot pulse*
Dead time
Dead time
(“H” active)
(“L” active)
Figure 12.3.10. Sawtooth Wave Modulation Operation
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12.3.1 Position-data-retain Function
This function is used to retain the position data synchronously with the three-phase waveform
output.There are three position-data input pins for U, V, and W phases.
A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected
by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address
034E16). This bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge
of each positive phase.
12.3.1.1 Operation of the Position-data-retain Function
Figure 12.3.1.1.1 shows a usage example of the position-data-retain function (U phase) when the
retain trigger is selected as the falling edge of the positive signal.
(1) At the falling edge of the U-phase waveform ouput, the state at pin IDU is transferred to the U-
phase position data retain bit ( bit2 at address 034E16 ).
(2) Until the next falling edge of the Uphase waveform output,the above value is retained.
Transferred
Carrier wave
U-phase waveform output
U-phase waveform output
1 2
Transferred Transferred Transferred
Pin IDU
U-phase position data retain bit
(bit 2 at address 034E
16
)
Note:
Note:
The retain trigger is the falling edge of the positive signal.
Figure 12.3.1.1.1 Usage Example of Position-data-retain Function ( U phase )
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12.3.1.2 Position-data-retain Function Control Register
Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register.
P
osition-data-retain
f
unction control re
g
ister (Note)
Symbol Address When reset
PDRF 034E16 XXXX 00002
RO
RO
RO
RWBit name FunctionBit symbol
PDRW
PDRV
PDRU
W-phase position
data retain bit
Input level at pin IDU is read out.
0: "L" level
1: "H" level
Note: This register is valid only in the three-phase mode.
Retain-trigger
polarity select bit
(b7-b4)
RW
PDRT
V-phase position
data retain bit
Nothing is assigned. When write, set to "0". When read,
contents are indeterminate.
U-phase position
data retain bit
Input level at pin IDV is read out.
0: "L" level
1: "H" level
Input level at pin IDW is read out.
0: "L" level
1: "H" level
0: Rising edge of positive phase
1: Falling edge of positive phase
b
7
b3
b
2b1b0
Figure 12.3.1.2.1. PDRF Register
12.3.1.2.1 W-phase Position Data Retain Bit (PDRW)
This bit is used to retain the input level at pin IDW.
12.3.1.2.2 V-phase Position Data Retain Bit (PDRV)
This bit is used to retain the input level at pin IDV.
12.3.1.2.3 U-phase Position Data Retain Bit (PDRU)
This bit is used to retain the input level at pin IDU.
12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT)
This bit is used to select the trigger polarity to retain the position data.
When this bit is set to "0", the rising edge of each positive phase selected.
When this bit is set to "1", the falling edge of each pocitive phase selected.
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Figure 12.3.2.1. Usage Example of Three-phse/Port output switch function
12.3.2 Three-phase/Port Output Switch Function
When the INVC03 bit in the INVC0 register set to “1”(Timer output enabled for three-phase motor control)
and setting the PFCi (i=0 to 5) in the PFCR register to “0”(I/O port), the three-phase PWM output pin (U,
__ __ ___
U, V, V, W and W) functions as I/O port. Each bit in the PFCi bits (i=0 to 5) is applicable for each one of
three-phase PWM output pins. Figure 12.3.2.1 shows the example of three-phase/port output switch
function. Figure 12.3.2.2 shows the PFCR register and the three-phase protect control register.
Timer B2
U phase
V Phase
W phase
Writing PFCR register(Note)
PFC0 bit : "1"
PFC2 bit : "1"
PFC4 bit : "0"
Functions as port P74
Functions as port P72
Writing PFCR register(Note)
PFC0 bit : "1"
PFC2 bit : "0"
PFC4 bit : "1"
Note : A hazard may be generated at the output signal, depending on the output switch timing. Also, do not generate (short)
be switching to port output during the dead time of three-phase output.
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Figure 12.3.2.2. PFCR Register, and TPRC Register
P
ort
f
unction control re
g
ister (Note)
Symbol Address When reset
PFCR 035816 0011 11112
RW
RW
RW
RWBit name FunctionBit symbol
PFC0
PFC1
PFC2
Port P8
0
output
function select bit
Note: This register is valid only when the INVC03 bit in the INVC0 register is set to "1"(Three-phase motor control
timer output enabled).
Write to this register after setting the TPRC0 bit in the TPRC register to "1" (write enable).
(b7-b6)
RW
PFC3
Nothing is assigned. When write, set to "0". When read,
these contents are "0".
0: Input/Output port P8
0
1: Three-phase PWM output
(U phase output)
PFC4
PFC5
RW
RW
Port P8
1
output
function select bit
Port P7
2
output
function select bit
Port P7
3
output
function select bit
Port P7
4
output
function select bit
Port P7
5
output
function select bit
0: Input/Output port P8
1
1: Three-phase PWM output
(U phase output)
0: Input/Output port P7
2
1: Three-phase PWM output
(V phase output)
0: Input/Output port P7
3
1: Three-phase PWM output
(V phase output)
0: Input/Output port P7
4
1: Three-phase PWM output
(W phase output)
0: Input/Output port P7
5
1: Three-phase PWM output
(W phase output)
b
7
b5
b
4
b3
b
2b1b0
Th
ree-p
h
ase protect contro
l
re
gi
ster
Symbol Address When reset
TPRC 025A
16
00
16
RW
RWBit name FunctionBit symbol
TPRC0
Three-phase
protect control bit
(b7-b1) Nothing is assigned. When write, set to "0". When read,
these contents are "0".
Enable write to PFCR register
0: Write protected
1: Write enabled
b
7
b5
b
4
b3
b
2b1b0
13. Serial I/O
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13. Serial I/O
Note
The M16C/26A (42-pin version) do not use UART0.
Serial I/O is configured with three channels: UART0 to UART2.
13.1. UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 13.1.1 shows the block diagram of UARTi. Figures 13.1.2 and 13.1.3 shows the block diagram of
the UARTi transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
•
Special mode 1 (I2C bus mode)
: UART2
•
Special mode 2
: UART2
•
Special mode 3 (Bus collision detection function, IEBus mode)
: UART2
•
Special mode 4 (SIM mode)
: UART2
Figures 13.1.4 to 13.1.9 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
13. Serial I/O
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Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock source selection
Internal
External
CTS/RTS disabled
CTS/RTS selected
RxD
0
1 / (n
0
+1)
1/16
1/16
1/2
U0BRG
register
CLK
0
CTS
0
/ RTS
0
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
V
CC
RTS
0
CTS
0
TxD
0
(UART0)
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRS=1
CRS=0
CRD=0
CRD=1
RCSP=0
RCSP=1
V
CC
CRD=0
CRD=1
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission control
circuit
Transmit/
receive
unit
CLK
polarity
reversing
circuit CTS/RTS disabled
CTS
0
from UART1
UART reception
Clock synchronous
type
RxD
1
TxD
1
(UART1)
1 / (n
1
+1)
1/16
1/16
1/2
U1BRG
register
CLK
1
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
V
CC
CRD=0
CRD=1
CLKMD0=0
CLKMD1=0 CRS=1
CRS=0
RCSP=0
RCSP=1
CLKMD0=1
CLKMD1=1
Clock source selection
Internal
External
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission
control circuit
Transmit/
receive
unit
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
RTS1
CTS1
Clock output
pin select CTS/RTS disabled
CTS/RTS disabled
CTS/RTS selected
CTS
0
from UART0
CTS
1
/ RTS
1
/
CTS
0
/ CLKS
1
i = 0 to 2
n
i
: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: Bits in the UiMR
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 registers
CLKMD0, CLKMD1, RCSP: Bits in the UCON register
RxD
2
CLK
2
CTS
2
/ RTS
2RTS
2
CTS
2
TxD
2
(UART2)
1 / (n
2
+1)
1/16
1/16
1/2
U2BRG
register
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRS=1
CRS=0
V
CC
CRD=0
CRD=1
Reception
control circuit
Transmission
control circuit
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
RxD polarity
reversing circuit
Internal
External
Clock source selection
TxD
polarity
reversing
circuit
Transmit/
receive
unit
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
Main clock or on-chip oscillator clock
1/2
1/8
1/4
f
1SIO
f
2SIO
f
8SIO
f
32SIO
f
1SIO or
f
2SIO
PCLK1=1
PCLK1=0
SMD2 to SMD0
SMD2 to SMD0
SMD2 to SMD0
Figure 13.1.1. Block diagram of UARTi (i = 0 to 2)
13. Serial I/O
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SP SP
PAR
2SP
1SP
UART
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP: Stop bit
PAR: Parity bit
UARTiÜtransmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
STPS=0
PAR
enabled
PAR
disabled
UART
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Address 03A6
16
Address 03A7
16
Address 03AE
16
Address 03AF
16
Address 03A2
16
Address 03A3
16
Address 03AA
16
Address 03AB
16
Data bus low-order bits
MSB/LSB conversion circuit
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
0
Data bus high-order bits
STPS=1
PRYE=0
PRYE=1
STPS=0
STPS=1
PRYE=0
PRYE=1
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the UiMR register
000
111
SMD2 to SMD0
0
1
SMD2 to SMD0
11
00
Figure 13.1.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
13. Serial I/O
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SP SP
PAR
2SP
1SP
UART
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD2
UARTi transmit register
PAR
disabled
PAR
enabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0UART2transmit
buffer register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART2 receive
buffer register
UARTi receive register
2SP
1SP UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxD2
UART
(8 bits)
UART
(9 bits)
Address 037E
16
Address 037F
16
Address 037A
16
Address 037B
16
Data bus high-order bits
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
0
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP: Stop bit
PAR: Parity bit
STPS=0
STPS=1
PRYE=0
PRYE=1
STPS=0
STPS=1
PRYE=0
PRYE=1
IOPOL=0
IOPOL=1
IOPOL
=0
IOPOL
=1
U2ERE
=0
U2ERE
=1
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the U2MR register
U2ERE : Bit in the U2C1 register
0
1
SMD2 to SMD0
11
00
0
1
SMD2 to SMD0
1
1
00
Figure 13.1.3. Block diagram of UART2 transmit/receive unit
13. Serial I/O
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(b15)
b7 b0
(b8) b7 b0
UARTi transmit buffer register (i=0 to 2)(Note)
Function
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Symbol Address After reset
U0TB 03A3
16
-03A2
16
Indeterminate
U1TB 03AB
16
-03AA
16
Indeterminate
U2TB 037B
16
-037A
16
Indeterminate
R
W
Note: Use MOV instruction to write to this register.
WO
b7
UARTi baud rate generation register (i=0 to 2)(Note 1)
b0
Symbol Address After reset
U0BRG 03A1
16
Indeterminate
U1BRG 03A9
16
Indeterminate
U2BRG 0379
16
Indeterminate
Function
Assuming that set value = n, UiBRG divides the count source
by n + 1 00
16
to FF
1
6
Setting
range
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Use MOV instruction to write to this register.
The transfer clock is shown below when the setting value in the UiBRG register is set as n.
(1) When the CKDIR bit in the UiMR register to “0” (internal clock)
• Clock synchronous serial I/O mode : fj/(2(n+1))
• Clock asynchronous serial I/O (UART) mode : fj/(16(n+1))
(2) When the CKDIR bit in the UiMR register to “1” (external clock)
• Clock synchronous serial I/O mode : f
EXT
• Clock asynchronous serial I/O (UART) mode : f
EXT
/(16(n+1))
R
W
W
O
Note 1: When the SMD2 to SMD0 bits in the UiMR register is set to “0002” (serial I/O disabled) or the RE bit in the UiC1 register is set to “0” (reception
disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits
is set to “0” (no error). Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.) Nothing assignd at the bit 11 in the U0RB and U1RB registers.
When write, set to “0”. When read, its contents is “0”.
(b15)
Symbol Address After reset
U0RB 03A7
16
-03A6
16
Indeterminate
U1RB 03AF
16
-03AE
16
Indeterminate
U2RB 037F
16
-037E
16
Indeterminate
b7 b0
(b8) b7 b0
UARTi receive buffer register (i=0 to 2)
Function
Bit
name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
OER
FER
PER
SUM
Overrun error flag (Note 1)
Framing error flag (Note 1)
Parity error flag (Note 1)
Error sum flag (Note 1)
0 : No overrun error
1 : Overrun error found
Receive data (D
7
to D
0
)
ABT Arbitration lost detecting
flag (Note 2) 0 : Not detected
1 : Detected
R
W
R
W
R
O
R
O
R
O
R
O
R
O
(b7-b0)
(b10-b9)
Receive data (D
8
)R
O
(b8)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Figure 13.1.4. U0TB to U2TB registers, U0RB to U2RB registers, U0BRG to U2BRG registers
13. Serial I/O
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UARTi transmit/receive mode register (i=0, 1)
Symbol Address After reset
U0MR, U1MR 03A016, 03A816 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol RW
CKDIR
SMD1
SMD0 Serial I/O mode select bit
(Note 2)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
(b7)
Parity enable bit
0 : Internal clock
1 : External clock (Note 1)
Stop bit length select bit
Odd/even parity select bit
Reserve bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set value other than the above
b2 b1 b0
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
Write to "0"
Function
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
RW
RW
RW
RW
RW
RW
RW
RW
UART2 transmit/receive mode register
Symbol Address After reset
U2MR 037816 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol RW
CKDIR
SMD1
SMD0 Serial I/O mode select bit
(Note 2)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock (Note 1)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C bus mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
b2 b1 b0
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : No reverse
1 : Reverse
Function
Note 1: Set the corresponding port direction bit for each CLK2 pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxD2 pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL2 and SDA2 pins to “0” (input mode).
RW
RW
RW
RW
RW
RW
RW
RW
(Note 3)
Figure 13.1.5. U0MR to U2MR registers
13. Serial I/O
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Figure 13.1.6. U0C0 to U2C0 registers and UCON register
UARTi transmit/receive control register 0 (i=0 to 2)
Symbol Address After reset
U0C0 to U2C0 03A4
16
, 03AC
16
, 037C
16
00001000
2
b7 b6 b5 b4 b3 b2 b1 b0
Function
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
Data output select bit
0 0 : f
1SIO
or f
2SIO
is selected
0 1 : f
8SIO
is selected
1 0 : f
32SIO
is selected
1 1 : Donotsettothisvalue
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
, P6
4
and P7
3
can be used as I/O ports)
0 : TxDi/SDA2 and SCL2 pins are CMOS output
1 : TxDi/SDA2 and SCL2 pins are N-channel open-drain output
UFORM Transfer format select bit
(Note 2)
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
Bit name
Bit
symbol
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: Effective for clock synchronous serial I/O mode, UART mode transfer data 8 bits long and special mode 2.
Note 3: CTS
1
/RTS
1
can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK
1
output) and the RCSP bit in the
UCON register is set to “0” (CTS
0
/RTS
0
not separated).
Note 4: SDA2 and SCL2 are effective when i = 2.
Note 5: When the SMD2 to SMD0 bits in UiMR regiser are set to “000
2
” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and
SCL2 pins are N-channel open-drain output).
Note 6: When the U1MAP bit in PACR register is “1” (P7
3
to P7
0
), CTS/RTS pin in UART1 is assigned to P7
0
.
RW
RW
RW
RW
RW
RW
RW
RW
RO
(Note 3)
(Note 4)
(Note 5)
(Note 6)
Note 1: When using multiple transfer clock output pins, make sure the following conditions are met:
set the CKDIR bit in the U1MR register to “0” (internal clock)
Note 2: When the U1MAP bit in PACR register is set to “1” (P7
3
to P7
0
), CTS
0
is supplied from the P7
0
pin.
UART transmit/receive control register 2
Symbol Address After reset
UCON 03B0
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol R
W
Function
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit 0 : Continuous receive mode disabled
1 : Continuous receive mode enable
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Output from CLK1 only
1 : Transfer clock output from multiple pins function
selected
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.
U0IRS
U1IRS
U0RRM
U1RRM
UART1 CLK/CLKS
select bit 1 (Note 1)
Effective when the CLKMD1 bit is set to “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
RCSP Separate UART0
CTS/RTS bit 0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS
0
supplied from the P6
4
pin)
R
W
R
W
R
W
R
W
R
W
R
W
R
W
(b7)
(Note 2)
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UARTi transmit/receive control register 1 (i=0, 1)
Symbol Address After reset
U0C1, U1C1 03A5
16
,03AD
16
00000010
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in UiTB register
1 : No data present in UiTB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in UiRB register
1 : Data present in UiRB register
Nothing is assigned.
When write, set “0”. When read, these contents are “0”.
UART2 transmit/receive control register 1
Symbol Address After reset
U2C1 037D
16
00000010
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol Function
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Reception disabled
1 : Reception enabled
U2IRS UART2 transmit interrupt
cause select bit 0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit 0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Data logic select bit 0 : No reverse
1 : Reverse
U2LCH
U2ERE Error signal output
enable bit 0 : Output disabled
1 : Output enabled
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RO
RO
(b7-b4)
0 : Data present in U2TB register
1 : No data present in U2TB register
0 : No data present in U2RB register
1 : Data present in U2RB register
Figure 13.1.7. U0C1 to U2C1 registers, PACR register
Pin assignment control register (Note)
Symbpl Address After reset
PACR 025D
16
00000000
2
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Pin enabling bit
Nothing is assigned. In an attempt
to write to these bits, write “0”.
The value, if read, turns out to
be “0”.
RW
(b6-b3)
001 : 42 pin
100 : 48 pin
All other values are reserved. Do
not use.
PACR0
PACR1
PACR2
RW
RW
Reserved bits
U1MAP UART1 pin remapping bit UART1 pins assigned to
0 : P6
7
to P6
4
1 : P7
3
to P7
0
RW
Note : Make sure the PACR register is written to by the next instruction after setting the PRC2 bit in the PRCR
register to “1” (write enable).
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UART2 special mode register
Symbol Address After reset
U2SMR 0377
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol Function
ABSCS
ACSE
SSS
I
2
C bus mode select bit
Bus busy flag 0 : STOP condition detected
1 : START condition detected (busy)
Bus collision detect
sampling clock select bit
Arbitration lost detecting
flag control bit
0 : Other than I
2
C bus mode
1 : I
2
C bus mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
0 : Not synchronized to R
X
Di
1 : Synchronized to R
X
Di (Note 2)
Set to “0”
Transmit start condition
select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer A0
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to R
X
Di).
(Note1)
Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
(b7)
0
(b3) Reserved bit
Figure 13.1.8. U2SMR register and U2SMR2 register
UART2 special mode register 2
Symbol Address After reset
U2SMR2 0376
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
STAC
SWC2
SDHI
I C bus mode select bit 2
SCL wait output bit 0 : Disabled
1 : Enabled
SDA output stop bit
UART initialization bit
Clock-synchronous bit
Refer to “Table 13.3.4. I
2
C bus Mode Functions”
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS 0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: Transfer clock
1: “L” output
2
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
RW
RW
RW
RW
RW
RW
RW
(b7)
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UART2 special mode register 3
Symbol Address After reset
U2SMR3 0375
16 000X0X0X2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol Function
DL2
SDA digital delay
setup bit
(Note 1, Note 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
b7 b6 b5
0 : Without clock delay
1 : With clock delay
Clock phase set bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Clock output select bit
CKPH
NODC
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I2C bus mode. In other than
I2C bus mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
RW
RW
RW
RW
RW
RW
(b0)
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
(b4)
Figure 13.1.9. U2SMR3 register and U2SMR4 register
UART2 special mode register 4
Symbol Address After reset
U2SMR4 0374
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol RW
Function
ACKC
SCLHI
SWC9
Start condition
generate bit (Note)
Stop condition
generate bit (Note) 0 : Clear
1 : Start
SCL,SDA output
select bit
ACK data bit
Restart condition
generate bit (Note)
0 : Clear
1 : Start
0 : Clear
1 : Start
STAREQ
RSTAREQ
STPREQ
ACKD
0 : Start and stop conditions not output
1 : Start and stop conditions output
SCL output stop
enable bit
ACK data output
enable bit
0 : Disabled
1 : Enabled
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
Note: Set to “0” when each condition is generated.
STSPSEL
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
SCL wait bit 3
RW
RW
RW
RW
RW
RW
RW
RW
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13.1.1. Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1.1.1
lists the specifications of the clock synchronous serial I/O mode. Table 13.1.1.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 13.1.1.1. Clock Synchronous Serial I/O Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • The CKDIR bit in the UiMR(i=0 to 2) register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• The CKDIR bit is set to “1” (external clock ) : Input from CLKi pin
Transmission, reception control
_______ _______ _______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit in the UiC1 register is set to "1" (transmission enabled)
_ The TI bit in the UiC1 register is set to "0" (data present in UiTB register)
_______ _______
_ If CTS function is selected, input on the CTSi pin is “L”
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit in the UiC1 register is set to "1" (reception enabled)
_ The TE bit in the UiC1 register is set to "1" (transmission enabled)
_ The TI bit in the UiC1 register is set to "0" (data present in the UiTB register)
•For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 3) is set to "0" (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
data from the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function • CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic (UART2)
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
• UART1 pin remapping selection
The UART1 pin can be selected from the P67 to P64 or P73 to P70.
Note 1: When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register “0” (transmit data
output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the
high state; if the CKPOL bit in the UiC0 register “1” (transmit data output at the rising edge and the receive data taken in at
the falling edge of the transfer clock), the external clock is in the low state.
Note 2:
If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does not change.
Note 3:
The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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Table 13.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register Bit Function
UiTB
(Note3)
0 to 7 Set transmission data
UiRB
(Note3)
0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate
UiMR
(Note3)
SMD2 to SMD0 Set to “0012”
CKDIR Select the internal clock or external clock
IOPOL(i=2)(Note 4) Set to “0”
UiC0 CLK1 to CLK0 Select the count source for the UiBRG register
CRS _______ _______
Select CTS or RTS to use
TXEPT Transmit register empty flag
CRD _______ _______
Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to “1” to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 1) Select the source of UART2 transmit interrupt
U2RRM (Note 1) Set this bit to “1” to use UART2 continuous receive mode
U2LCH(Note 3) Set this bit to “1” to use UART2 inverted data logic
U2ERE(Note 3) Set to “0”
U2SMR 0 to 7 Set to “0”
U2SMR2 0 to 7 Set to “0”
U2SMR3 0 to 2 Set to “0”
NODC Select clock output mode
4 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set this bit to “1” to use continuous receive mode
CLKMD0 Select the transfer clock output pin when CLKMD1 = 1
CLKMD1 Set this bit to “1” to output UART1 transfer clock from two pins
RCSP
_________
Set this bit to “1” to accept as input the UART0 CTS
0
signal from the P6
4
pin or P7
0
pin
7 Set to “0”
Note 1: Set bit 4 and bit 5 in the U0C1 and U1C1 register are set to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.
Note 2: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
Note 3: Set the bit 6 and bit 7 in the U0C1 and U1C1 register to "0".
Note 4: Set the bit 7 in the U0MR and U1MR register to "0".
i=0 to 2
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Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
13.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese-
lected. Table 13.1.1.4 lists the P64 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 13.1.1.3. Pin Functions(Note 1)
(When Not Select Multiple Transfer Clock Output Pin Function)
Pin name Function Method of selection
TxDi (i = 0 to 2)
(P63, P67, P70)Serial data output
Serial data input
Transfer clock output
Transfer clock input
I/O port
(Outputs dummy data when performing reception only)
RxDi
(P62, P66, P71)
CLKi
(P61, P65, P72)Set the CKDIR bit in the UiMR register to "0"
Set the CKDIR bit in the UiMR register to "1"
Set the PD6_1 bit and PD6_5 bit in the PD6 register, and the PD7_2 bit in the
PD7 register to "0"
Set the PD6_2 bit and PD6_6 bit in the PD6 register, and PD7_1 bit in the PD7
register to "0"(Can be used as an input port when performing transmission only)
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "0"
Set the PD6_0 bit and PD6_4 bit in the PD6 register’ is set to "0", the PD7_3
bit in the PD7 register to "0"
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "1"
Set the CRD bit in the UiC0 register to "1"
CTS input
RTS output
CTSi/RTSi
(P60, P64, P73)
Note 1: When the U1MAP bit in PACR register is “1” (P73 to P70), UART1 pin is assgined to P73 to P70.
Pin function Bit set value
U1C0 register UCON register PD6 register
CRD CRS RCSP CLKMD1 CLKMD0 PD6_4
P6410 0 Input: 0, Output: 1
CTS1000 0
RTS1100
CTS0(Note2) 0
CLKS1
0
0
00 1 0
1(Note 3) 1
Note 1: When the U1MAP bit in PACR register is “1” (P73 to P70), this table lists the P70 functions.
Note 2: In addition to this, set the CRD bit in the U0C0 register to “0” (CT00/RT00 enabled) and the
CRS bit in the U0C0 register to “1” (RTS0 selected).
Note 3: When the CLKMD1 bit is set to "1" and the CLKMD0 bit is set to "0", the following logiclevels are output:
• High if the CLKPOL bit in the U1C0 register is set to "0"
• Low if the CLKPOL bit in the U1C0 register is set to "1"
Table 13.1.1.4. P64 Pin Functions(Note 1)
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D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
TCLK
Stopped pulsing because the TE bit = “0”
Write data to the UiTB register
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
CLKi
TxDi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
“0”
“1”
Stopped pulsing because CTSi = “H”
1 / f
EXT
Write dummy data to UiTB register
UiC1 register
TE bit
UiC1 register
TI bit
CLKi
RxDi
UiC1 register
RI bit
RTSi “H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
UiC1 register
RE bit “0”
“1”
Receive data is taken in
Transferred from UiTB register to UARTi transmit register
Read out from UiRB registerTransferred from UARTi receive register
to UiRB register
SiRIC register
IR bit “0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Transferred from UiTB register to UARTi transmit register
Make sure the following conditions are met when input to the CLKi pin
before receiving data is high:
• TE bit in the UiC0 register is set to "1" (transmit enabled)
• RE bit in the UiC0 register is set to "1" (Receive enabled)
• Write dummy data to the UiTB register
The above timing diagram applies to the case where the register bits are set as follows:
• CKDIR bit in the UiMR register is set to "0"(internal clock)
• CRD bit in the UiC0 register is set to "0" (CTS/RTS enabled), CRS bit to "0" (CTS selected)
• CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer
clock)
• UiIRS bit is set to "0" (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the
UCON register bit 1, and U2IRS bit is the U2C1 register bit 4
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• CKDIR bit in the UiMR register is set to "1" (external clock)
• CRD bit in the UiC0 register is set to "0" (CTS/RTS enabled), CRS bit to "1" (RTS selected)
• CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and
receive data taken in at the rising edge o
f
the trans
f
er clock)
UiC0 register
TXEPT bit
SiTIC register
IR bit
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
(1) Example of transmit timing
(2) Example of receive timing
Figure 13.1.1.1. Typical transmit/receive timings in clock synchronous serial I/O mode
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13.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
•Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial I/O disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to “1” (reception enabled)
•Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (Clock synchronous serial I/O mode)
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless to the TE bit in the UiC1
register.
13.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 13.1.1.2.1
shows the polarity of the transfer clock.
Figure 13.1.1.2.1. Polarity of transfer clock
(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
0
T
X
D
i
R
X
D
i
CLK
i
(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
i
R
X
D
i
CLK
i
Note 1: This applies to the case where the UFORM bit in the UiC0 register is set to "0" (
LSB first) and the UiLCH bit in the UiC1 register is set to "0" (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
(Note 2)
(Note 3)
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13.1.1.3 LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 13.1.1.3.1
shows the transfer format.
Figure 13.1.1.3.1 Transfer format
13.1.1.4 Continuous receive mode
When the UiRRM bit (i = 0 to 2) is set to "1" (continuous receive mode), the TI bit in the UiC1 register
is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM
bit is set to "1", do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM
bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the
U2C1 register.
(1) When the UFORM bit in the UiC0 register "0" (LSB first)
D0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
X
D
i
R
X
D
i
CLK
i
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
X
D
i
R
X
D
i
CLK
i
Note: This applies to the case where the CKPOL bit in the UiC0 register is
set to "0" (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock) and the UiLCH
bit in the UiC1 register "0" (no reverse).
i = 0 to 2
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Figure 13.1.1.4.1. Serial data logic switch timing
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxD
2
(no reverse)
“H”
“L”
“H”
“L”
TxD
2
(reverse)
D0 D1 D2 D3 D4 D5 D6 D7
“H”
“L”
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
Transfer clock
“H”
“L”
(2) When the U2LCH bit in the U2C1 register is set to "1" (reverse)
Note: This applies to the case where the CKPOL bit in the U2C0
register is set to "0" (transmit data output at the falling edge and
the receive data taken in at the rising edge of the transfer clock)
and the UFORM bit is set to "0" (LSB first).
13.1.1.6 Transfer clock output from multiple pins function (UART1)
The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output
pins. (See Figure 13.1.1.6.1) This function is valid when the internal clock is selected for UART1.
Figure 13.1.1.6.1 Transfer Clock Output From Multiple Pins
13.1.1.5 Serial data logic switch function (UART2)
When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register
has its logic reversed before being transmitted. Similarly, the received data has its logic reversed
when read from the U2RB register. Figure 13.1.1.4.1 shows serial data logic.
Microcomputer
T
X
D
1
(P6
7
)
CLKS
1
(P6
4
)
CLK
1
(P6
5
)IN
CLK
IN
CLK
Note 1: This applies to the case where the CKDIR bit in the U1MRregister is set to "0"(internal clock)
and the CLKMD1 bitin the UCON register is set to "1" (transfer clock output from multiple
pins).
Note 2: This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "0"
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "1"
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_______ _______
13.1.1.7 CTS/RTS separate function (UART0)
_______ _______ _______ _______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• The CRD bit in the U0C0 register is set to "0" (enables UART0 CTS/RTS)
_______
• The CRS bit in the U0C0 register is set to "1" (outputs UART0 RTS)
_______ _______
• The CRD bit in the U1C0 register is set to "0" (enables UART1 CTS/RTS)
_______
• The CRS bit in the U1C0 register is set to "0" (inputs UART1 CTS)
_______
• The RCSP bit in the UCON register is set to "1" (inputs CTS0 from the P64 pin)
• The CLKMD1 bit in the UCON register is set to "0" (CLKS1 not used)
_______ _______ _______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
Figure 13.1.1.7.1. CTS/RTS separate function usage
Microcomputer
T
X
D
0
(P6
3
)
R
X
D
0
(P6
2
)IN
OUT
CTS
RTS
CTS
0
(P6
4
)
RTS
0
(P6
0
)
IC
CLK
0
(P6
1
)CLK
Note 1: This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).
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Item Specification
Transfer data format • Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock • The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))
fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16
Transmission, reception control
_______ _______ _______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit in the UiC1 register is set to "1" (transmission enabled)
_ The TI bit in the UiC1 register "0" (data present in UiTB register)
_______ _______
_ If CTS function is selected, input “L” to the CTSi pin
Reception start condition • Before reception can start, the following requirements must be met
_ The RE bit in the UiC1 register is set to "1" (reception enabled)
_ Start bit detection
•For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) is set to "0" (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
data from the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function • LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch (UART2)
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch (UART2)
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
•UART1 pin remapping selection
The UART1 pin can be selected from the P67 to P64 or P73 to P70.
Note 1:
If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does not change.
Note 2:
The U0IRS and U1IRS bits respectively are the bits "0" and "1" in the UCON register; the U2IRS bit is the bit 4 in the U2C1 register.
13.1.2. Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13.1.2.1 lists the specifications of the UART mode.
Interrupt request
generation timing
Table 13.1.2.1. UART Mode Specifications
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Table 13.1.2.2. Registers to Be Used and Settings in UART Mode
Register Bit Function
UiTB 0 to 8 Set transmission data (Note 1)
UiRB 0 to 8 Reception data can be read (Note 1)
OER,FER,PER,SUM
Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
IOPOL(i=2)(Note 4) Select the TxD/RxD input/output polarity
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
CRS _______ _______
Select CTS or RTS to use
TXEPT Transmit register empty flag
CRD _______ _______
Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode
CKPOL Set to “0”
UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select the source of UART2 transmit interrupt
U2RRM (Note 2) Set to “0”
U2LCH (Note 3) Set this bit to “1” to use UART2 inverted data logic
U2ERE (Note 3) Set to “0”
U2SMR 0 to 7 Set to “0”
U2SMR2 0 to 7 Set to “0”
U2SMR3 0 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1 Set to “0”
RCSP
_________
Set this bit to “1” to accept as input the UART0 CTS
0
signal from the P6
4
pin or P7
0
pin
7 Set to “0”
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0
to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the bit 4 to bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: Set the bit 6 to bit 7 in the U0C1 and U1C1 registers to “0”.
Note 4: Set the bit 7 the U0MR and U1MR registers to “0”.
i=0 to 2
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Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the P64
pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected
to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this
pin is in a high-impedance state.)
Table 13.1.2.3. I/O Pin Functions in UART mode(Note 1)
Pin name Function Method of selection
TxDi (i = 0 to 2)
(P6
3
, P6
7
, P7
0
)Serial data output
Serial data input
Input/output port
Transfer clock input
Input/output port
(Outputs "H" when performing reception only)
RxDi
(P6
2
, P6
6
, P7
1
)
CLKi
(P6
1
, P6
5
, P7
2
)Set the CKDIR bit in the UiMR register to "0"
Set the CKDIR bit in the UiMR register to "1"
Set the PD6_1 bit and PD6_5 bit in the PD6 register to "0", PD7_2 bit in the PD7
register to "0"
PD6_2 bit, PD6_6 bit in the PD6 register and the PD7_1 bit in the PD7 register
(Can be used as an input port when performing transmission only)
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "0"
Set the PD6_0 bit and PD6_4 bit in the PD6 register to "0", the PD7_3 bit in the
PD7 register "0"
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "1"
Set the CRD bit in the UiC0 register "1"
CTS input
RTS output
CTSi/RTSi
(P6
0
, P6
4
, P7
3
)
Note 1: When the U1MAP bit in PACR register is set to “1” (P7
3
to P7
0
), UART1 pin is assgined to P7
3
to P7
0
.
Table 13.1.2.4. P64 Pin Functions in UART mode(Note 1)
Pin function Bit set value
U1C0 register UCON register PD6 register
CRD CRS RCSP CLKMD1 PD6_4
P6
4
10 0 Input: 0, Output: 1
CTS
1
0000
RTS
1
10 0
CTS
0
(Note 2) 0
0
0
00 1 0
Note 1: When the U1MAP bit in PACR register is “1” (P7
3
to P7
0
), this table lists the P7
0
functions.
Note 2: In addition to this, set the CRD bit in the U0C0 register to “0” (CTS
0
/RTS
0
enabled) and the CRS
bit in the U0C0 register to “1” (RTS
0
selected).
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Figure 13.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
Start
bit Parity
bit
TxDi
CTSi
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
EXT
fj : frequency of UiBRG count source (f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
)
f
EXT
: frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
“0”
“1”
TxDi
“0”
“1”
“0”
“1”
“0”
“1”
Transfer clock
Tc
“0”
“1”
Tc
Transfer clock
D0D1D2D3D4D5D6D7
ST PD0D1D2D3D4D5D6D7SP ST PSP D0D1
ST
Stop
bit
Start
bit
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
D0D1D2D3D4D5D6D7
ST SP
D8D0D1D2D3D4D5D6D7
ST D8D0D1
ST
SPSP
Stop
bit Stop
bit
“0”
SP
Stopped pulsing
because the TE bit
= “0”
Write data to the UiTB register
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
Transferred from UiTB register to UARTi transmit register
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "1" (parity enabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),
the CRS bit to "0" (CTS selected)
• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Write data to the UiTB register
Transferred from UiTB register to UARTi
transmit register
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
EXT
fj : frequency of UiBRG count source (f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
)
f
EXT
: frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "0" (parity disabled)
• Set the STPS bit in the UiMR register to "1" (2 stop bits)
• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)
• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer
becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 13.1.2.2. Receive Operation
D
0
Start
bit Sampled “L”
UiBRG count
source
RxDi
Transfer clock
RTSi
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
“0”
“1”
Reception triggered when transfer clock
is generated by falling edge of start bit
UiC1 register
RE bit
UiC1 register
RI bit
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Receive data taken in
D
7
D
1
Transferred from UARTi receive
register to UiRB register
The above timing diagram applies to the case where the register bits are set as follows:
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
i = 0 to 2
13.1.2.1. Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 13.1.2.1.1 lists example of bit rate and settings.
Table 13.1.2.1.1 Example of Bit Rates and Settings
Bit Rate Count Source Peripheral Function Clock : 16MHz Peripheral Function Clock : 20MHz
(bps) of BRG
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
1200 f8 103(67h) 1202 129(81h) 1202
2400 f8 51(33h) 2404 64(40h) 2404
4800 f8 25(19h) 4808 32(20h) 4735
9600 f1 103(67h) 9615 129(81h) 9615
14400 f1 68(44h) 14493 86(56h) 14368
19200 f1 51(33h) 19231 64(40h) 19231
28800 f1 34(22h) 28571 42(2Ah) 29070
31250 f1 31(1Fh) 31250 39(27h) 31250
38400 f1 25(19h) 38462 32(20h) 37879
51200
f1
19(13h) 50000 24(18h) 50000
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Figure 13.1.2.3.1. Transfer Format
(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)
(2) When the UFORM bit in the UiC0 register "1" (MSB first)
Note: This applies to the case where the CKPOL bit in the UiC0 register is
set to "0" (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock), the UiLCH bit
in the UiC1 register is set to "0" (no reverse), the STPS bit in the
UiMR register is set to "0" (1 stop bit) and the PRYE bit in the UiMR
register is set to "1" (parity enabled).
D
1
D
2
D
3
D
4
D
5
D
6
SPD0
D
1
D
2
D
3
D
4
D
5
D
6
SPD
0
T
X
D
i
R
X
D
i
CLK
i
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
T
X
D
i
R
X
D
i
CLK
i
ST
ST
D
7
P
D
7
P
SP
SP
ST
ST
P
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
13.1.2.2. Counter Measure for Communication Error
If a communication error occurs while transmitting or receiving in UART mode, follow the procedure
below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in UiMR register “000b” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in UiMR register “001b”, “101b”, “110b”
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiC1
register
13.1.2.3. LSB First/MSB First Select Function
As shown in Figure 14.1.2.3.1, use the UFORM bit in the UiC0 register to select the transfer format.
This function is valid when transfer data is 8 bits long.
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13.1.2.5. TxD and RxD I/O Polarity Inverse Function (UART2)
This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 13.1.2.5.1 shows the
TXD pin output and RXD pin input polarity inverse.
Figure 13.1.2.5.1. TXD and RXD I/O Polarity Inverse
13.1.2.4. Serial Data Logic Switching Function (UART2)
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register.
Figure 13.1.2.4.1 shows serial
data logic.
Figure 13.1.2.4.1. Serial Data Logic Switching
Transfer clock
“H”
“L”
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
TxD
2
(no reverse) “H”
“L”
TxD
2
(reverse)
SPST D3 D4 D5 D6 D7 PD0 D1 D2
“H”
“L”
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)
Transfer clock
“H”
“L”
Note: This applies to the case where the CKPOL bit in the U2C0 register
is set to "0" (transmit data output at the falling edge of the transfer
clock), the UFORM bit in the U2C0 register is set to "0" (LSB first),
the STPS bit in the U2MR register is set to "0" (1 stop bit) and the
PRYE bit in the U2MR register is set to "1" (parity enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)
(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)
Note: This applies to the case where the UFORM bit in the U2C0 register
is set to "0"(LSB first), the STPS bit in the U2MR register is set to "0
" (1 stop bit) and the PRYE bit in the U2MR register is set to "1"(
parity enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
“H”
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TxD
2
(no reverse)
RxD
2
(no reverse)
Transfer clock
TxD
2
(reverse)
RxD
2
(reverse)
“L”
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“L”
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_______ _______
13.1.2.6. CTS/RTS Separate Function (UART0)
_______ _______ _______ _______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• Set the CRD bit in the U0C0 register to "0" (enables UART0 CTS/RTS)
_______
• Set the CRS bit in the U0C0 register to "1"(outputs UART0 RTS)
_______ _______
• Set the CRD bit in the U1C0 register to "0" (enables UART1 CTS/RTS)
_______
• Set the CRS bit in the U1C0 register to "0" (inputs UART1 CTS)
_______
• Set the RCSP bit in the UCON register to "1" (inputs CTS0 from the P64 pin)
• Set the CLKMD1 bit in the UCON register to "0" (CLKS1 not used)
_______ _______ _______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
_______ _______
Figure 13.1.2.6.1. CTS/RTS Separate Function
Microcomputer
TXD0 (P63)
RXD0 (P62)IN
OUT
CTS
RTS
CTS0 (P64)
RTS0 (P60)
IC
Note 1: This applies to the case where U1MAP bit in PACR register
is set to “0” (P67 to P64).
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13.1.3 Special Mode 1 (I2C bus mode)(UART2)
I2C bus mode is provided for use as a simplified I2C bus interface compatible mode. Table 13.1.3.1 lists
the specifications of the I2C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I2C bus
mode and the register values set. Table 13.1.3.4 lists the I2C bus mode fuctions. Figure 13.1.3.1 shows
the block diagram for I2C bus mode. Figure 13.1.3.2 shows SCL2 timing.
As shown in Table 13.1.3.2, the microcomputer is placed in I2C bus mode by setting the SMD2 to SMD0
bits to ‘0102’ and the IICM bit to “1”. Because SDA2 transmit output has a delay circuit attached, SDA
output does not change state until SCL2 goes low and remains stably low.
Table 13.1.3.1. I2C bus Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • During master
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register 0016 to FF16
• During slave
The CKDIR bit is set to “1” (external clock ) : Input from SCL pin
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit in the U2C1 register is set to "1" (reception enabled)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
Select function • Arbitration lost
Timing at which the ABT bit in the U2RB register is updated can be selected
• SDA2 digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value in the U2RB register will be indeterminate. The IR bit in the
S2RIC register does not change
.
Interrupt request
generation timing
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CLK
control
Falling edge
detection
External
clock
Internal clock Start/stop condition detection
interrupt request
Start condition
detection
Stop condition
detection
Reception register
Bus
busy
Transmission
register
Arbitration
Noise
Filter
SDA2
SCL2
UART2
D
TQ
DTQ
D
TQ
NACK
ACK
UART2
UART2
UART2
R
UART2 transmit,
NACK interrupt
request
UART2 receive,
ACK interrupt request,
DMA1 request
IICM=1 and
IICM2=0
S
RQ
ALS
R
SSWC
IICM=1 and
IICM2=0
IICM2=1
IICM2=1
SWC2
SDHI
DMA0, DMA1 request
Noise
Filter
IICM : Bit in the U2SMR
IICM2, SWC, ALS, SWC2, SDHI : Bits in the U2SMR2
STSPSEL, ACKD, ACKC : Bits in the U2SMR4
IICM=0
IICM=1
DMA0
STSPSEL=0
STSPSEL=1
STSPSEL=1
STSPSEL=0
SDASTSP
SCLSTSP
ACKC=1 ACKC=0
Q
Port register
(Note)
I/O port
9th bit falling edge
9th bit
ACKD bit
Delay
circuit
This diagram applies to the case where the SMD2 to SMD0 bits in the the U2MR register is set to "0102" and the IICM bit in the U2SMR
register is set to "1".
Note: If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).
Start and stop condition generation block
Figure 13.1.3.1. I2C bus Mode Block Diagram
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Table 13.1.3.2. Registers to Be Used and Settings in I2C bus Mode (1) (Continued)
Register Bit Function
Master Slave
U2TB 0 to 7 Set transmission data Set transmission data
(Note 1)
U2RB 0 to 7 Reception data can be read Reception data can be read
(Note 1) 8 ACK or NACK is set in this bit ACK or NACK is set in this bit
ABT Arbitration lost detection flag Invalid
OER Overrun error flag Overrun error flag
U2BRG 0 to 7 Set a transfer rate Invalid
U2MR SMD2 to SMD0 Set to ‘0102’Set to ‘0102’
(Note 1) CKDIR Set to “0”Set to “1”
IOPOL Set to “0”Set to “0”
U2C0 CLK1, CLK0 Select the count source for the U2BRG Invalid
register
CRS Invalid because CRD = 1 Invalid because CRD = 1
TXEPT Transmit buffer empty flag Transmit buffer empty flag
CRD Set to “1”Set to “1”
NCH Set to “1”Set to “1”
CKPOL Set to “0”Set to “0”
UFORM Set to “1”Set to “1”
U2C1 TE Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI Transmit buffer empty flag Transmit buffer empty flag
RE Set this bit to “1” to enable reception Set this bit to “1” to enable reception
RI Reception complete flag Reception complete flag
U2IRS Invalid Invalid
U2RRM, Set to “0”Set to “0”
U2LCH, U2ERE
U2SMR IICM Set to “1”Set to “1”
ABC Select the timing at which arbitration-lost Invalid
is detected
BBS Bus busy flag Bus busy flag
3 to 7 Set to “0”Set to “0”
U2SMR2 IICM2
Refer to
Table 13.1.3.4 I2C bus Mode Functions
Refer to
Table 13.1.3.4 I2C bus Mode Functions
CSC Set this bit to “1” to enable clock Set to “0”
synchronization
SWC Set this bit to “1” to have SCL2 output Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th fixed to “L” at the falling edge of the 9th
bit of clock bit of clock
ALS Set this bit to “1” to have SDA2 output Set to “0”
stopped when arbitration-lost is detected
STAC Set to “0”Set this bit to “1” to initialize UART2 at
start condition detection
SWC2 Set this bit to “1” to have SCL2 output Set this bit to “1” to have SCL2 output
forcibly pulled low forcibly pulled low
SDHI Set this bit to “1” to disable SDA2 output Set this bit to “1” to disable SDA 2 output
7 Set to “0”Set to “0”
U2SMR3 0, 2, 4 and NODC Set to “0”Set to “0”
CKPH
Refer to
Table 13.1.3.4 I2C bus Mode Functions
Refer to
Table 13.1.3.4 I2C bus Mode Functions
DL2 to DL0 Set the amount of SDA2 digital delay Set the amount of SDA2 digital delay
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C bus
mode.
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U2SMR4 STAREQ Set this bit to “1” to generate start Set to “0”
condition
RSTAREQ Set this bit to “1” to generate restart Set to “0”
condition
STPREQ Set this bit to “1” to generate stop Set to “0”
condition
STSPSEL Set this bit to “1” to output each condition Set to “0”
ACKD Select ACK or NACK Select ACK or NACK
ACKC Set this bit to “1” to output ACK data Set this bit to “1” to output ACK data
SCLHI Set this bit to “1” to have SCL2 output Set to “0”
stopped when stop condition is detected
SWC9 Set to “0”Set this bit to “1” to set the SCL2 to “L”
hold at the falling edge of the 9th bit of
clock
Register Bit Function
Master Slave
Table 13.1.3.3. Registers to Be Used and Settings in I2C bus Mode (2) (Continued)
Note 1: Not all bits in the register are described above. Set those bits to “0” when writing to the registers in I2C
bus mode.
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Function I2C bus mode (SMD2 to SMD0 = 0102, IICM = 1)
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 0012,
IICM = 0)
Factor of interrupt number
15 (Note 1) (Refer to Fig.
13.1.3.2.)
No acknowledgment
detection (NACK)
Rising edge of SCL2 9th bit
Factor of interrupt number
16 (Note 1) (Refer to Fig.
13.1.3.2.)
Start condition detection or stop condition detection
(Refer to Figure 13.1.3.2.1. STSPSEL Bit Function)
UART2 transmission
output delay
Functions of P70 pin
Noise filter width
Read RxD2 and SCL2 pin
levels
Factor of interrupt number
10 (Note 1) (Refer to Fig.
13.1.3.2.)
Acknowledgment detection
(ACK)
Rising edge of SCL2 9th bit
Initial value of TxD2 and
SDA2 outputs
UART2 transmission
Transmission started or
completed (selected by U2IRS)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TxD2 output
RxD2 input
CLK2 input or output selected
15ns
Possible when the
corresponding port direction bit
= 0
CKPOL = 0 (H)
CKPOL = 1 (L)
Delayed
SDA2 input/output
SCL2 input/output
(Cannot be used in I2C mode)
Initial and end values of
SCL2H
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C bus mode (Note 2)
Timing for transferring data
from the UART reception
shift register to the U2RB
register
IICM2 = 0
(NACK/ACK interrupt) IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 1
(Clock delay) CKPH = 1
(Clock delay)
UART2 transmission
Rising edge of
SCL2 9th bit
UART2 transmission
Falling edge of SCL2
next to the 9th bit
UART2 transmission
Falling edge of SCL2 9th bit
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge) Rising edge of SCL2 9th bit Falling edge of
SCL2 9th bit Falling and rising
edges of SCL2 9th
bit
.
.
DMA1 factor (Refer to Fig.
14.1.3.2.) UART2 reception Acknowledgment detection
(ACK) UART2 reception
Falling edge of SCL2 9th bit
Store received data 1st to 8th bits are stored in
U2RB register bit 0 to bit 7 1st to 8th bits are stored in
U2RB register bit 7 to bit 0 1st to 7th bits are stored in U2RB register
bit 6 to bit 0, with 8th bit stored in U2RB
register bit 8
L
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
Read received data U2RB register status is read
directly as is
CKPH = 0
(No clock delay) CKPH = 0
(No clock delay)
HL
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(Note 3)
Functions of P71 pin
Functions of P72 pin
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to 1 (interrupt requested). (Refer to “Notes on interrupts” in Precautions.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore,
always be sure to clear the IR bit to 0 (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the U2MR register, IICM bit in the U2SMR register,
IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register
Note 2: Set the initial value of SDA2 output while the SMD2 to SMD0 bits in the U2MR register is set to ‘0002’ (serial I/O
disabled).
Note 3: Second data transfer to U2RB register (Rising edge of SCL2 9th bit)
Note 4. First data transfer to U2RB register (Falling edge of SCL2 9th bit)
Table 13.1.3.4. I2C bus Mode Functions
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Figure 13.1.3.2. Transfer to U2RB Register and Interrupt Timing
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
SDA2
SCL2
Receive interrupt
(DMA request) Transmit interrupt
SDA2
SCL2
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to "1" (slave)
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
D6D5D4D3D2D1D8 (ACK or NACK)D7
SDA2
SCL2
D0
ACK interrupt (DMA
request) or NACK interrupt
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
SDA2
SCL2
1st
bit 2nd
bit 3rd
bit 4th
bit 5th
bit 6th
bit 7th
bit 8th
bit 9th
bit
b15
•••
b9 b8 b7 b0
D
8
Contents of the U2RB register
b15
•••
b9 b8 b7 b0
b15
•••
b9 b8 b7 b0
b15
•••
b9 b8 b7 b0 b15
•••
b9 b8 b7 b0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D6D5D4D3D2D1D7D0
ACK interrupt (DMA
request) or NACK interrupt
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D6D5D4D3D2D1D7D0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D6D5D4D3D2D1D7D0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D8 (ACK or NACK)
1st
bit 2nd
bit 3rd
bit 4th
bit 5th
bit 6th
bit 7th
bit 8th
bit 9th
bit
D8 (ACK or NACK)
1st
bit 2nd
bit 3rd
bit 4th
bit 5th
bit 6th
bit 7th
bit 8th
bit 9th
bit
D8 (ACK or NACK)
1st
bit 2nd
bit 3rd
bit 4th
bit 5th
bit 6th
bit 7th
bit 8th
bit 9th
bit
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Receive interrupt
(DMA request) Transmit interrupt
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Contents of the U2RB register
Contents of the U2RB register
Contents of the U2RB register
Contents of the U2RB register
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13.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDA2 pin changes state from high
to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated
when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the BBS bit in the U2SMR register to determine which interrupt source is requesting the
interrupt.
Setup time Hold time
SCL2
SDA2
(Start condition)
SDA2
(Stop condition)
Note: When the PCLK1 bit in the PCLKR register is set to "1", the cycles indicates
the f1SIO's generation frequency cycles; when PCLK1 bit is set to "0", the
cycles indicated the f2SIO's generation frequency cycles.
3 to 6 cycles < setup time (Note)
3 to 6 cycles < hold time (Note)
Figure 13.1.3.1.1. Detection of Start and Stop Condition
13.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to “1” (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the U2SMR4 register to “1” (output).
Make sure that no interrupts or DMA transfers will occur between (1) and (2).
The function of the STSPSEL bit is shown in Table 13.1.3.2.1 and Figure 13.1.3.2.1.
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Table 13.1.3.2.1. STSPSEL Bit Functions
Figure 13.1.3.2.1. STSPSEL Bit Functions
Function
Output of SCL2 and SDA2 pins
Start/stop condition interrupt
request generation timing
STSPSEL = 0
Output transfer clock and data/
Program with a port determines
how the start condition or stop
condition is output
Start/stop condition are de-
tected
STSPSEL = 1
The STAREQ, RSTAREQ and
STPREQ bit determine how the
start condition or stop condition is
output
Start/stop condition generation are
completed
SDA2
Startconditiondetection
interrupt Stopconditiondetection
interrupt
(1)Inslavemode,
CKDIRissetto"1"(externalclock)
SCL2
SDA2
Startconditiondetection
interrupt Stopconditiondetection
interrupt
(2)Inmastermode,
CKDIRissetto"0"(internalclock),CKPHissetto"1"(clockdelayed)
SCL2
SetSTAREQ
to"1"(start) SetSTPREQ
to"1"(start)
STPSELbit 0
STPSELbit
Setto"1"by
aprogram Setto"0"by
aprogram Setto"1"by
aprogram Setto"0"by
aprogram
1st 2nd 3rd 5th 6th 7th 8th 9thbit
1st 2nd 3rd 5th 6th 7th 8th 9thbit
4th
4th
13.1.3.3 Arbitration
Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising
edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to “1” at the
same time unmatching is detected during check, and is cleared to “0” when not detected. In cases
when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to
“1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
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13.1.3.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 13.1.3.2.1.
The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal
SCL2) and an external clock supplied to the SCL2 pin. In cases when the CSC bit is set to “1” (clock
synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high,
the internal SCL2 goes low, at which time the U2BRG register value is reloaded with and starts count-
ing in the low-level interval. If the internal SCL2 changes state from low to high while the SCL2 pin is
low, counting stops, and when the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL2 and SCL2
pin signal. The transfer clock works from a half period before the falling edge of the internal SCL2 1st
bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the U2SMR2 register allows to select whether the SCL2 pin should be fixed to or freed
from low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to “1” (enabled), SCL2 output is turned off (placed in the
high-impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register is set to "1" (0 output) makes it possible to forcibly output
a low-level signal from the SCL2 pin even while sending or receiving data. Clearing the SWC2 bit to “0”
(transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of
outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the
U2SMR3 register is set to "1", the SCL2 pin is fixed to low-level output at the falling edge of the clock
pulse next to the ninth. Setting the SWC9 bit is set to "0" (SCL hold low disabled) frees the SCL2 pin
from low-level output.
13.1.3.5 SDA Output
The data written to the bit 7 to bit 0 (D7 to D0) in the U2TB register is sequentially output beginning with
D7. The ninth bit (D8) is ACK or NACK.
The initial value of SDA2 transmit output can only be set when IICM is set to "1" (I2C Bus mode) and
the SMD2 to SMD0 bits in the the U2MR register are set to ‘0002’ (serial I/O disabled).
The DL2 to DL0 bits in the U2SMR3 register allow to add no delays or a delay of 2 to 8 U2BRG count
source clock cycles to SDA2 output.
Setting the SDHI bit in the U2SMR2 register is set to "1" (SDA output disabled) forcibly places the
SDA2 pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge
of the UART2 transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
13.1.3.6 SDA Input
When the IICM2 bit is set to "0", the 1st to 8th bits (D7 to D0) of received data are stored in the bit 7 to
bit 0 in the U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to "1", the 1st to 7th bits (D7 to D1) of received data are stored in the bit 6 to
bit 0 in the U2RB register and the 8th bit (D0) is stored in the bit 8 in the U2RB register. Even when the
IICM2 bit is set to "1", providing the CKPH bit to "1", the same data as when the IICM2 bit is set to "0"
can be read out by reading the U2RB register after the rising edge of the corresponding clock pulse of
9th bit.
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13.1.3.7 ACK and NACK
If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the
U2SMR4 register is output from the SDA2 pin.
If the IICM2 bit is set to "0", a NACK interrupt request is generated if the SDA2 pin remains high at the
rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin
is low at the rising edge of the 9th bit of transmit clock pulse.
If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
13.1.3.8 Initialization of Transmission/Reception
If a start condition is detected while the STAC bit is set to "1" (UART2 initialization enabled), the serial
I/O operates as described below.
- The transmit shift register is initialized, and the content of the U2TB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UART2 output value does not change state and remains the
same as when a start condition was detected until the first bit of data is output synchronously with
the input clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UART2 transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
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13.1.4 Special Mode 2 (UART2)
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 13.1.4.1 lists the specifications of Special Mode 2. Table 13.1.4.2 lists the registers
used in Special Mode 2 and the register values set. Figure 13.1.4.1 shows communication control ex-
ample for Special Mode 2.
Table 13.1.4.1. Special Mode 2 Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • Master mode
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• Slave mode
The CKDIR bit is set to “1” (external clock selected) : Input from CLK2 pin
Transmit/receive control Controlled by input/output ports
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit in the U2C1 register is set to "1" (reception enabled)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in the U2TB register)
•While transmitting, one of the following conditions can be selected
_ The U2IRS bit in the U2C1 register is set to "0" (transmit buffer empty): when trans
ferring data from the U2TB register to the UART2 transmit register (at start of transmission)
_ The U2IRS bit is set to "1" (transfer completed): when the serial I/O finished sending
data from the UART2 transmit register
• While receiving
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 7th bit of the next data
Select function • Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit in the U2C0 register “1” (transmit data output at the
rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the
low state.
Note 2: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit in the S2RIC register
does not change.
Interrupt request
generation timing
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P1
3
P1
2
P7
0(
TxD
2
)
P7
2(
CLK
2
)
P7
1(
RxD
2
)
P9
3
P7
0(
TxD
2
)
P7
2(
CLK
2
)
P7
1(
RxD
2
)
P9
3
P7
0(
TxD
2
)
P7
2(
CLK
2
)
P7
1(
RxD
2
)
Microcomputer
(Master) Microcomputer
(Slave)
Microcomputer
(Slave)
Figure 13.1.4.1. Serial Bus Communication Control Example (UART2)
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Table 13.1.4.2. Registers to Be Used and Settings in Special Mode 2
Register Bit Function
U2TB
(Note)
0 to 7 Set transmission data
U2RB
(Note)
0 to 7 Reception data can be read
OER Overrun error flag
U2BRG 0 to 7 Set a transfer rate
U2MR
(Note)
SMD2 to SMD0 Set to ‘0012’
CKDIR Set this bit to “0” for master mode or “1” for slave mode
IOPOL Set to “0”
U2C0 CLK1, CLK0 Select the count source for the U2BRG register
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxD2 pin output format
CKPOL Clock phases can be set in combination with the CKPH bit in the U2SMR3
register UFORM Set to “0”
U2C1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS Select UART2 transmit interrupt cause
U2RRM, Set to “0”
U2LCH, U2ERE
U2SMR 0 to 7 Set to “0”
U2SMR2 0 to 7 Set to “0”
U2SMR3 CKPH Clock phases can be set in combination with the CKPOL bit in the U2C0 register
NODC Set to “0”
0, 2, 4 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
Note : Not all bits in the register are described above. Set those bits to “0” when writing to the registers in
Special Mode 2.
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13.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit
in the U2SMR3 register and the CKPOL bit in the U2C0 register.
Make sure the transfer clock polarity and phase are the same for the master and slave to communi-
cate.
13.1.4.1.1 Master (Internal Clock)
Figure 13.1.4.1.1.1 shows the transmission and reception timing in master (internal clock).
13.1.4.1.2 Slave (External Clock)
Figure 13.1.4.1.2.1 shows the transmission and reception timing (CKPH=0) in slave (external clock)
while Figure 13.1.4.1.2.2 shows the transmission and reception timing (CKPH=1) in slave (external
clock).
Data output timing
Data input timing
D0D1D2D3D4D6D7D5
Clock output
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
"H"
"L"
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
"H"
"L"
Figure 13.1.4.1.1.1. Transmission and Reception Timing in Master Mode (Internal Clock)
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Figure 13.1.4.1.2.1. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
Figure 13.1.4.1.2.2. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
Slave control input
Clock input
(CKPOL=0, CKPH=0)
Clock input
(CKPOL=1, CKPH=0)
Data output timing
Data input timing
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
D0D1D2D3D4D6D7D5
Indeterminate
Clock input
(CKPOL=0, CKPH=1)
Clock input
(CKPOL=1, CKPH=1)
Data output timing
Data input timing
"H"
"L"
"H "
"L"
"H "
"L "
"H "
"L"
D0D1D2D3D6D7D4D5
.
Slave control input
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13.1.5 Special Mode 3 (IE Bus mode )(UART2)
In this mode, one bit of IE Bus is approximated with one byte of UART mode waveform.
Table 13.1.5.1 lists the registers used in IE Bus mode and the register values set. Figure 13.1.5.1 shows
the functions of bus collision detect function related bits.
If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt
request is generated.
Table 13.1.5.1. Registers to Be Used and Settings in IE Bus Mode
Register Bit Function
U2TB 0 to 8 Set transmission data
U2RB
(Note)
0 to 8 Reception data can be read
OER,FER,PER,SUM
Error flag
U2BRG 0 to 7 Set a transfer rate
U2MR SMD2 to SMD0 Set to ‘1102’
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Invalid because PRYE=0
PRYE Set to “0”
IOPOL Select the TxD/RxD input/output polarity
U2C0 CLK1, CLK0 Select the count source for the U2BRG register
CRS Invalid because CRD=1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxD2 pin output mode
CKPOL Set to “0”
UFORM Set to “0”
U2C1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS Select the source of UART2 transmit interrupt
U2RRM, Set to “0”
U2LCH, U2ERE
U2SMR 0 to 3, 7 Set to “0”
ABSCS Select the sampling timing at which to detect a bus collision
ACSE Set this bit to “1” to use the auto clear function of transmit enable bit
SSS Select the transmit start condition
U2SMR2 0 to 7 Set to “0”
U2SMR3 0 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
Note : Not all bits in the registers are described above. Set those bits to “0” when writing to the registers in IE
Bus mode.
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(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
Timer A0
(3) The SSS bit in the U2SMR register (Transmit start condition select)
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2
TxD2
CLK2
TxD2
RxD2
TxD2
RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
Input to TA0IN
If ABSCS is set to "1", bus collision is determined when timer
A0 (one-shot timer mode) underflows .
TxD2
RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
Transfer clock
BCNIC register
IR bit (Note)
U2C1 register
TE bit
If ACSE bit is set to "1"
automatically clear when bus collision
occurs), the TE bit is cleared to "0"
(transmission disabled) when
the IR bit in the BCNIC register is
set to "1" (unmatching detected).
If SSS bit is set to "0", the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
(Note 2)
Note 1: The falling edge of RxD2 when the IOPOL is set to "0"; the rising edge of RxD2 when the IOPOL is set to "1".
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where the IOPOL is set to "1" (reversed)
.
Figure 13.1.5.1. Bus Collision Detect Function-Related Bits
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Item Specification
Transfer data format • Direct format
• Inverse format
Transfer clock • The CKDIR bit in the U2MR register is set to “0” (internal clock) : fi/(16(n+1))
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in U2BRG register 0016 to FF16
• The CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))
fEXT: Input from CLK2 pin. n: Setting value in U2BRG register 0016 to FF16
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
Reception start condition • Before reception can start, the following requirements must be met
_ The RE bit in the U2C1 register is set to "1" (reception enabled)
_ Start bit detection
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (the U2IRS bit
is set to "1")
(Note 2) • For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection • Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit in the
S2RIC register does not change.
Note 2: A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1”
(transmission complete) and the U2ERE bit to “1” (error signal output) after reset. Therefore,
when using SIM mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these
bits.
13.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Tables 13.1.6.1 lists the specifications of SIM mode. Table 13.1.6.2 lists the registers used in the SIM
mode and the register values set.
Table 13.1.6.1. SIM Mode Specifications
Interrupt request
generation timing
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Table 13.1.6.2. Registers to Be Used and Settings in SIM Mode
Register Bit Function
U2TB
(Note)
0 to 7 Set transmission data
U2RB
(Note)
0 to 7 Reception data can be read
OER,FER,PER,SUM
Error flag
U2BRG 0 to 7 Set a transfer rate
U2MR SMD2 to SMD0 Set to ‘1012’
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Set this bit to “1” for direct format or “0” for inverse format
PRYE Set to “1”
IOPOL Set to “0”
U2C0 CLK1, CLK0 Select the count source for the U2BRG register
CRS Invalid because CRD=1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Set to “0”
CKPOL Set to “0”
UFORM Set this bit to “0” for direct format or “1” for inverse format
U2C1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS Set to “1”
U2RRM Set to “0”
U2LCH Set this bit to “0” for direct format or “1” for inverse format
U2ERE Set to “1”
U2SMR
(Note)
0 to 3 Set to “0”
U2SMR2 0 to 7 Set to “0”
U2SMR3 0 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
Note: Not all bits in registers are described above. Set those bits to “0” when writing to the registers in SIM
mode.
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Figure 13.1.6.1. Transmit and Receive Timing in SIM Mode
Transfer clock
An “L” level is output from TxD
2
due to
the occurrence of a parity error
Read the U2RB register
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
U2C1 register
TE bit
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
Tc
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
TxD
2
“0”
“1”
“0”
“1”
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
Tc
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
SP
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
SP
SP
TxD
2
RxD
2
pin level
U2C1 register
TI bit
Parity error signal sent
back from receiver
(Note)
U2C0 register
TXEPT bit
S2TIC register
IR bit
Start
bit Parity
bit Stop
bit
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
An “L” level returns due to the
occurrence of a parity error.
The level is
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
The IR bit is set to “1” at the
falling edge of transfer clock
Note : Because TxD
2
and RxD
2
are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.
Note : Because TxD
2
and RxD
2
are connected, this is composite waveform consisting of the TxD
2
output and the parity error signal
sent back from receiver.
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of U2BRG count source (f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
)
f
EXT
: frequency of U2BRG count source (external clock)
n : value set to U2BRG
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of U2BRG count source (f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
)
f
EXT
: frequency of U2BRG count source (external clock)
n : value set to U2BRG
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bitintheU2MR register issetto "0" (1 stop bit)
• PRY bitintheU2MR register issetto"1" (even)
• UFORM bit intheU2C0 register issetto"0" (LSB first)
• U2LCH bit intheU2C1 register issetto"0" (no reverse)
• U2IRSCH bitintheU2C1 register issetto"1"(transmit is completed)
Start
bit Parity
bit Stop
bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Read the U2RB register
(1) Transmission
Transfer clock
U2C1 register
RE bit
RxD
2
pin level
Transmitter's
transmit waveform
(Note)
U2C0 register
RI bit
S2RIC register
IR bit
(1) Reception
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bitintheU2MR register issetto"0"(1 stop bit)
• PRY bit intheU2MR register issetto"1" (even)
• UFORM bit intheU2C0 register issetto"0" (LSB first)
• U2LCH bitintheU2C1 register issetto"0" (no reverse)
• U2IRSCH bit intheU2C1 register issetto"1" (transmit is completed)
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Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Figure 13.1.6.2. SIM Interface Connection
Microcomputer
SIM card
TxD
2
RxD
2
13.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 13.1.6.1.1. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
Figure 13.1.6.1.1. Parity Error Signal Output Timing
ST : Start bit
P : Even Parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
(Note)
Transfer
clock
RxD2
TxD2
U2C1 register
RI bit
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
This timing diagram applies to the case where the direct format is
implemented.
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
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13.1.6.2 Format
• Direct Format
Set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH
bit in the U2C1 register to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 13.1.6.2.1 shows the SIM interface format.
Figure 13.1.6.2.1. SIM Interface Format
P : Even parity
D0 D1 D2 D3 D4 D5 D6 D7 P
Transfer
clcck
TxD
2
TxD
2
D7 D6 D5 D4 D3 D2 D1 D0 P
Transfer
clcck
(1) Direct format
“H”
“L”
“H”
“L”
(2) Inverse format
P : Odd parity
“H”
“L”
“H”
“L”
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Item Performance
A/D Conversion Method Successive approximation (capacitive coupling amplifier)
Analog Input Voltage (Note 1)
0V to AVCC (VCC)
Operating Clock fAD (Note 2)
fAD/divided-by-2 or fAD/divided-by-3 or fAD/divided-by-4 or fAD/divided-by-6
or fAD/divided-by-12 or fAD
Resolution 8-bit or 10-bit (selectable)
Integral Nonlinearity Error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±3LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±5LSB
Operating Modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
Analog Input Pins
(Note 3)
8 pins (AN0 to AN7) + 3 pins (AN30 to AN32) + 1 pins (AN24) (48pin-ver.)
8 pins (AN0 to AN7) + 2 pins (AN30, AN31) (42pin-ver.)
Conversion Speed Per Pin
•Without sample and hold function
8-bit resolution: 49
fAD
cycles
,
10-bit resolution: 59
fAD
cycles
• With sample and hold function
8-bit resolution: 28
fAD
cycles
,
10-bit resolution: 33
fAD
cycles
Table 14.1 A/D Converter Performance
Note 1: Not dependent on use of sample and hold function.
Note 2: Set the fAD frequency to 10 MHz or less.
Without sample-and-hold function, set the fAD frequency to 250kHZ or more.
With the sample and hold function, set the fAD frequency to 1MHZ or more.
14. A/D Converter
Note
Thers is no external connections for port P92 to P93 (AN32, AN24) in the M16C/26A (42-pin version).
Do not use port P92 to P93 (AN32, AN24) for analog input pin in the M16C/26A (42-pin version).
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to
___________
AN7), P90 to P93 (AN30 to AN32, AN24). Similarly, ADTRG input shares the pin with P15. Therefore, when
using these inputs, make sure the corresponding port direction bits are set to “0” (input mode).
When not using the A/D converter, set the VCUT bit to “0” (VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the i bits in the A/D register for ANi, AN3i, and AN2i pins (i = 0 to 7).
Table 14.1 shows the A/D converter performance. Figure 14.1 shows the A/D converter block diagram
and Figures 14.2 to 14.4 show the A/D converter associated with registers.
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Figure 14.1 A/D Converter Block Diagram
=0002
=0012
=0102
=0112
=1002
=1012
=1102
=1112
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
AN
30
AN
31
AN
32
V
ref
V
IN
CH2 to CH0
Decoder
for channel
selection
A/D register 0(16)
Data bus low-order
V
REF
AV
SS
VCUT=0
VCUT=1
Data bus high-order
Port P10 group
Port P9 group
ADGSEL1 to ADGSEL0=012
ADGSEL1 to ADGSEL0=002
AN
24
ADGSEL1 to ADGSEL0=112
f
AD
CKS0=1
CKS0=0
CKS1=1
CKS1=0
1/3
CKS2=0
CKS2=1
1/21/2 ø
AD
A/D conversion rate
selection
(03C1
16
to 03C0
16
)
(03C3
16
to 03C2
16
)
(03C5
16
to 03C4
16
)
(03C7
16
to 03C6
16
)
(03C9
16
to 03C8
16
)
(03CB
16
to 03CA
16
)
(03CD
16
to 03CC
16
)
(03CF
16
to 03CE
16
)
Resistor ladder
Successive conversion register
ADCON0 register
(address 03D616)
ADCON1 register
(address 03D716)
Comparator 0
Addresses
Decoder
for A/D register
A/D register 1(16)
A/D register 2(16)
A/D register 3(16)
A/D register 4(16)
A/D register 5(16)
A/D register 6(16)
A/D register 7(16)
ADCON2 register
(address 03D4
16
)
Port P9 group
=0002
=0012
=0102
=1002
CH2 to CH0
CH2 to CH0
SSE = 1
CH2 to CH0=0012
Comparator 1
ADGSEL1 to ADGSEL0=002
ADGSEL1 to ADGSEL0=012
V
IN1
Note 1: AN32 and AN24 are available for only 48-pin package.
(Note 1)
(Note 1)
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Figure 14.2 ADCON0 to ADCON2 Registers
A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin Select
Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0 0 0 : One-shot mode or Delayed trigger mode 0,1
0 1 : Repeat mode
1 0 : Single sweep mode or
Simultaneous sample sweep mode
1 1 : Repeat sweep mode 0 or Repeat sweep
mode 1
MD0
MD1
Trigger Select Bit 0 : Software trigger
1 : Hardware trigger
TRG
ADST A/D Conversion Start Flag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0 See Table 14.2 A/D Conversion
Frequency Select
CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin Select Bit
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT VREF Connect Bit
(Note2)
A/D Operation Mode
Select Bit 1 0 : Other than repeat sweep mode 1
1 : Repeat sweep mode 1
0 : VREF not connected
1 : VREF connected
b4 b3
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Frequency Select Bit 1
CKS1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Function varies with each operation mode
Function varies with each operation mode
See Table 14.2 A/D Conversion
Frequency Select
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D416 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit 0 : Without sample and hold
1 : With sample and hold
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to “0”
0
A/D Input Group Select Bit 0 0 : Select port P10 group
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Select port P9 group (AN24)
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
RW
TRG1 Trigger Select Bit
See Table 14.2 A/D Conversion
Frequency Select
Function varies with each operation
mode
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A/D trigger control register
(Note 1)(Note 2)
Symbol Address After reset
ADTRGCON 03D2
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
A/D Operation Mode
Select Bit 2 0 : Other than simultaneous sample sweep
mode or delayed trigger mode 0,1
1 : Simultaneous sample sweep mode or
delayed trigger mode 0,1
Bit symbol Bit name Function RW
SSE
A/D Operation Mode
Select Bit 3
HPTRG1
DTE
HPTRG0
RW
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
0 : Other than delayed trigger mode 0,1
1 : Delayed trigger mode 0,1
Note 1: If the ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: Set “00
16
” in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and
repeat sweep mode 1.
AN1 Trigger Select Bit
AN0 Trigger Select Bit Function varies with each operation mode
Function varies with each operation mode
Figure 14.3 ADTRGCON Register
Note : Set the ØAD frequency to 10 MHz or less. The selected ØAD frequency is determined by a combination of
the CKS0 bit in the ADCON0 register, CKS1 bit in the ADCON1 register and the CKS2 bit in the ADCON2 register.
CKS2 CKS1 CKS0 ØAD
000
001
010
100
101
110
111
Divided-by-4 of fAD
Divided-by-2 of fAD
fAD
Divided-by-12 of fAD
011
Divided-by-6 of fAD
Divided-by-3 of fAD
Table 14.2 A/D Conversion Frequency Select
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Figure 14.4 ADSTAT0 Register and AD0 to AD7 Registers
A/D Register i (i=0 to 7) Symbol Address After reset
AD0 03C1
16
to 03C0
16
Indeterminate
AD1 03C3
16
to 03C2
16
Indeterminate
AD2 03C5
16
to 03C4
16
Indeterminate
AD3 03C7
16
to 03C6
16
Indeterminate
AD4 03C9
16
to 03C8
16
Indeterminate
AD5 03CB
16
to 03CA
16
Indeterminate
AD6 03CD
16
to 03CC
16
Indeterminate
AD7 03CF
16
to 03CE
16
Indeterminate
Eight low-order bits of
A/D conversion result
Function
(b15) b7b7 b0 b0
(b8)
When the BITS bit in the ADCON1
register is “1” (10-bit mode)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
When read, its content is
indeterminate
RW
RO
RO
Two high-order bits of
A/D conversion result
When the BITS bit in the ADCON1
register is “0” (8-bit mode)
A/D conversion result
A/D conversion status register 0 (Note 1)
Symbol Address After reset
ADSTAT0 03D316 0016
b7 b6 b5 b4 b3 b2 b1 b0
AN1 Trigger Status Flag 0 : AN1 trigger did not occur during
AN0 conversion
1 : AN1 trigger occured during AN0
conversion
Bit symbol Bit name Function RW
ADERR0
Conversion Termination
Flag
AN0 Conversion Status
Flag
ADSTT0
ADERR1
ADTCSF
RW
RO
RW
RO
RO
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b2)
ADSTRT0 AN0 Conversion
Completion Status Flag
0 : Conversion not terminated
1 : Conversion terminated by
Timer B0 underflow
Delayed Trigger Sweep
Status Flag 0 : Sweep not in progress
1 : Sweep in progress
0 : AN0 conversion not in progress
1 : AN0 conversion in progress
ADSTT1
RW
0 : AN0 conversion not completed
1 : AN0 conversion completed
ADSTRT1 RW
AN1 Conversion Status
Flag 0 : AN1 conversion not in progress
1 : AN1 conversion in progress
AN1 Conversion
Completion Status Flag 0 : AN1 conversion not completed
1 : AN1 conversion completed
Note 1: ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to “1”.
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Figure 14.5 TB2SC Register
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
0
), U(P8
1
), V(P7
2
), V(P7
3
), W(P7
4
), W(P7
5
). After forcible cutoff, input "H" to the P8
5
/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If “L” is input to the P8
5
/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to 16.6 Digital Debounce function for SD input.
PWCOM
Symbol Address After reset
TB2SC 039E
16
X0000000
2
Timer B2 Reload Timing
Switch Bit 0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 special mode register
(Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
IVPCR1 Three-Phase Output Port
SD Control Bit 1 0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7)
TB2SEL Trigger Select Bit 0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
RW
RW
TB0EN Timer B0 Operation Mode
Select Bit 0 : Other than A/D trigger mode
1 : A/D trigger mode (Note 5) RW
TB1EN Timer B1 Operation Mode
Select Bit 0 : Other than A/D trigger mode
1 : A/D trigger mode (Note 5) RW
(Note 2)
(Note 3, 4, 7)
(Note 6)
(b6-b5) Reserved bits Must set to "0"
00
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14.1 Operation Modes
14.1.1 One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table
14.1.1.1 shows the one-shot mode specifications. Figure 14.1.1.1 shows the operation example in one-
shot mode. Figure 14.1.1.2 shows the ADCON0 to ADCON2 registers in one-shot mode.
Table 14.1.1.1 One-shot Mode Specifications
Item Specification
Function The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
a selected pin is once converted to a digital code
A/D Conversion Start
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Condition
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
___________
The ADTRG pin input changes state from “H” to “L” after setting the
ADST bit to “1” (A/D conversion started)
A/D Conversion Stop • A/D conversion completed (If a software trigger is selected, the ADST bit is
Condition set to “0” (A/D conversion halted)).
• Set the ADST bit to “0”
Interrupt Request Generation Timing
A/D conversion completed
Analog Input Pin
Select one pin from AN
0
to AN
7
, AN
30
to AN
32
, AN
24
Readout of A/D Conversion Result
Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Figure 14.1.1.1 Operation Example in One-Shot Mode
•Example when selecting AN2
to an analog input pin
(Ch2 to CH0=0102)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
A/D conversion started
A/D interrupt request generated
A/D pin input voltage
sampling
A/D pin conversion
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A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit (Note 2, 3)
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0 (Note 3)
MD0
MD1 Trigger Select Bit
TRG
ADST A/D Conversion Start
Flag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT VREF Connect Bit (Note 2)
A/D Operation Mode
Select Bit 1
1 : VREF connected
0
0
0 0 : One-shot mode or delayed trigger mode
0,1
b4 b3
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
See Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
0
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D416 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group Select
Bit 0 0 : Select port P10 group (ANi)
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Select port P9 group (AN24)
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
RW
TRG1 Trigger Select Bit 1
b2 b1 b0
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN7
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN30 to AN32 and AN24 can be used in the same way as AN0 to AN7 . Use the ADGSEL1 to ADGSEL0 bits
in the ADCON2 register to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Invalid in one-shot mode
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A/D conversion.
0 : Without sample and hold
1 : With sample and hold
Set to "0" in one-shot mode
See Table 14.2 A/D Conversion
Frequency Select
0
Figure 14.1.1.2 ADCON0 to ADCON2 Registers in One-Shot Mode
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14.1.2 Repeat mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table
14.1.2.1 shows the repeat mode specifications. Figure 14.1.2.1 shows the operation example in repeat
mode. Figure 14.1.2.2 shows the ADCON0 to ADCON2 registers in repeat mode.
Item Specification
Function The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to ADGSEL0
bits in the ADCON2 register select pins. Analog voltage applied to a selected
pin is repeatedly converted to a digital code
A/D Conversion Start
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Condition
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition
Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request Generation Timing
None generated
Analog Input Pin
Select one pin from AN
0
to AN
7
, AN
30
to AN
32
and AN
24
Readout of A/D Conversion Result
Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Table 14.1.2.1 Repeat Mode Specifications
Figure 14.1.2.1 Operation Example in Repeat Mode
•Example when selecting AN2
to an analog input pin
(Ch2 toCH0=0102)
A/D conversion started
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
A/D pin input voltage
sampling
A/D pin conversion
14. A/D Converter
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A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit (Note 2, 3)
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0 (Note 3)
MD0
MD1 Trigger Select Bit
TRG
ADST A/D Conversion Start
Flag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT VREF connect bit (Note 2)
A/D Operation Mode
Select Bit 1
1 : VREF connected
0
0
0 1 : Repeat mode
b4 b3
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
1
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D416 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group Select
Bit 0 0 : Select port P10 group (ANi)
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Select port P9 group (AN24)
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
See Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger Select Bit 1
b2 b1 b0
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN7
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN30 to AN32 and AN24 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in
the ADCON2 register to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Invalid in repeat mode
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A/D conversion.
0 : Without sample and hold
1 : With sample and hold
Set to "0" in repeat mode
0
Figure 14.1.2.2 ADCON0 to ADCON2 Registers in Repeat Mode
14. A/D Converter
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14.1.3 Single Sweep Mode
In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital
code. Table 14.1.3.1 shows the single sweep mode specifications. Figure 14.1.3.1 shows the operation
example in single sweep mode. Figure 14.1.3.2 shows the ADCON0 to ADCON2 registers in single
sweep mode.
Item Specification
Function The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code
A/D Conversion Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition
• A/D conversion completed(When selecting a software trigger, the ADST bit
is set to “0” (A/D conversion halted)).
• Set the ADST bit to “0”
Interrupt Request Generation Timing
A/D conversion completed
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
AN0 to AN7 (8 pins) (Note 1)
Readout of A/D Conversion Result
Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Table 14.1.3.1 Single Sweep Mode Specifications
Note 1: AN30 to AN32 can be used in the same way as AN0 to AN7.
However, all input pins need to belong to the same group.
Figure 14.1.3.1 Operation Example in Single Sweep Mode
•Example when selecting AN
0
to AN
3
to analog input pins (SCAN1 to SCAN0=01
2
)
A/D conversion started
A/D interrupt request generated
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
A/D pin input voltage
sampling
A/D pin conversion
14. A/D Converter
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A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0
MD0
MD1 Trigger Select Bit
TRG
ADST A/D Conversion Start
Flag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit (Note 2)
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT V
REF
Connect Bit
(Note 3)
A/D Operation Mode
Select Bit 1
1 : V
REF
connected
1
0
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
0
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D4
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group
Select Bit 0 0 : Select port P10 group (AN
i
)
0 1 : Select port P9 group (AN
3i
)
1 0 : Do not set
1 1 : Do not set
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Refer to Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger Select Bit 1
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
0 : Software trigger
1 : Hardware trigger (AD
TRG
trigger)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
0 : Without sample and hold
1 : With sample and hold
Set to "0" in single sweep mode
Invalid in single sweep mode
1 0 : Single sweep mode or simultaneous
sample sweep mode
b4 b3
When selecting single sweep mode
0 0 : AN
0
to AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN
30
to AN
32
can be used in the same way as AN
0
to AN
7
. Use the ADGSEL1 to ADGSEL0 bits in the
ADCON2 register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (V
REF
unconnected) to “1” (V
REF
connected), wait for 1 µs or more before
starting A/D conversion.
0
Figure 14.1.3.2 ADCON0 to ADCON2 Registers in Single Sweep Mode
14. A/D Converter
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Item Specification
Function The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is repeatedly converted to a digital code
A/D Conversion Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (Hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition
Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request Generation Timing
None generated
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
AN0 to AN7 (8 pins) (Note 1)
Readout of A/D Conversion Result
Readout one of the AD0 to AD7 registers that corresponds to the selected pin
14.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a
digital code. Table 14.1.4.1 shows the repeat sweep mode 0 specifications. Figure 14.1.4.1 shows the
operation example in repeat sweep mode 0. Figure 14.1.4.2 shows the ADCON0 to ADCON2 registers in
repeat sweep mode 0.
Table 14.1.4.1 Repeat Sweep Mode 0 Specifications
Note 1: AN30 to AN32 can be used in the same way as AN0 to AN7.
However, all input pins need to belong to the same group.
Figure 14.1.4.1 Operation Example in Repeat Sweep Mode 0
•Example when selecting AN
0
to AN
3
to analog input pins (SCAN1 to SCAN0=01
2
)
A/D conversion started
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
A/D pin input voltage
sampling
A/D pin conversion
14. A/D Converter
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A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit (Note 2)
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT VREF Connect Bit (Note 3)
A/D Operation Mode
Select Bit 1
1 : VREF connected
01
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6) Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSET0 bits in the
ADCON2 register to select the desired pin.
Noe 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A/D conversion.
When selecting repeat sweep mode 0
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D416 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group
Select Bit 0 0 : Select port P10 group (ANi)
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Do not set
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Refer to Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger Select Bit 1
0 : Without sample and hold
1 : With sample and hold
Set to "0" in repeat sweep mode 0
0
A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0
MD0
MD1
Trigger Select Bit
TR
G
ADST A/D Conversion Start
Flag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
CKS0
RW
1
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
1
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Invalid in repeat sweep mode 0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
b4 b3
Figure 14.1.4.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 0
14. A/D Converter
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14.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltages applied to the all selected pins are converted to a digital code,
with mainly used in the selected pins. Table 14.1.5.1 shows the repeat sweep mode 1 specifications.
Figure 14.1.5.1 shows the operation example in repeat sweep mode 1. Figure 14.1.5.2 shows the
ADCON0 to ADCON2 registers in repeat sweep mode 1.
Table 14.1.5.1 Repeat Sweep Mode 1 Specifications
Item Specification
Function The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register mainly select pins. Analog voltage
applied to the all selected pins is repeatedly converted to a digital code
Example : When selecting AN0
Analog voltage is converted to a digital code in the following order
AN0 AN1 AN0 AN2 AN0 AN3, and so on.
A/D Conversion Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition
Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request Generation Timing
None generated
Analog Input Pins Mainly Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),
Used in A/D Conversions AN0 to AN3 (4 pins) (Note 1)
Readout of A/D Conversion Result
Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Note 1: AN30 to AN32 can be used in the same way as AN0 to AN7.
However, all input pins need to belong to the same group.
Figure 14.1.5.1 Operation Example in Repeat Sweep Mode 1
•Example when selecting AN
0
to analog input pins (SCAN1 to SCAN0=00
2
)
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
A/D conversion started
A/D pin input voltage
sampling
A/D pin conversion
14. A/D Converter
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A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0
MD0
MD1
Trigger Select Bit
TRG
ADST A/D Conversion Start
Flag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit (Note 2)
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT VREF Connect Bit (Note 3)
A/D Operation Mode
Select Bit 1
1 : VREF connected
1
11
Frequency Select Bit 1
CKS1
1 : Repeat sweep mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
1
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D4h 00h
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group
Select Bit 0 0 : Select port P10 group (ANi)
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Do not set
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Refer to Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger Select Bit 1
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the
ADCON2 register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A/D conversion.
0 : Without sample and hold
1 : With sample and hold
Set to "0" in repeat sweep mode 1
Invalid in repeat sweep mode 1
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
b4 b3
When selecting repeat sweep mode 1
0 0 : AN0 (1 pin)
0 1 : AN0 to AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
b1 b0
0
Figure 14.1.5.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 1
14. A/D Converter
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Item Specification
Function The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code. At this time, the
input voltage of AN0 and AN1 are sampled simultaneously.
A/D Conversion Start Condition
When the TRG bit in the ADCON0 register is "0" (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
When the TRG bit in the ADCON0 register is "1" (hardware trigger)
The trigger is selected by TRG1 and HPTRG0 bits (See Table 14.1.6.2)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
Timer B0, B2 or Timer B2 interrupt generation frequency setting counter
underflow after setting the ADST bit to “1” (A/D conversion started)
A/D Conversion Stop Condition
A/D conversion completed (If selecting software trigger, the ADST bit is
automatically set to "0".
Set the ADST bit to "0" (A/D conversion halted)
Interrupt Generation Timing A/D conversion completed
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or
AN0 to AN7 (8 pins) (Note 1)
Readout of A/D conversion result
Readout one of the AN0 to AN7 registers that corresponds to the selected pin
Note 1: AN30 to AN32 can be used in the same way as AN0 to AN7.
However, all input pins need to belong to the same group.
14.1.6 Simultaneous Sample Sweep Mode
In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by-
one to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously using two
circuits of sample and hold circuit. Table 14.1.6.1 shows the simultaneous sample sweep mode specifica-
tions. Figure 14.1.6.1 shows the operation example in simultaneous sample sweep mode. Figure
14.1.6.2 shows ADCON0 to ADCON2 registers and Figure 14.1.6.3 shows ADTRGCON registers in
simultaneous sample sweep mode. Table 14.1.6.2 shows the trigger select bit setting in simultaneous
sample sweep mode. In simultaneous sample sweep mode, Timer B0 underflow can be selected as a
trigger by combining software trigger, ADTRG trigger, Timer B2 underflow, Timer B2 interrupt generation
frequency setting counter underflow or A/D trigger mode of Timer B.
•Example when selecting AN
0
to
AN3
to analog input pins (SCAN1 to SCAN0=01
2
)
A/D conversion started
A/D interrupt request generated
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
A/D pin input voltage
sampling
A/D pin conversion
Figure 14.1.6.1 Operation Example in Simultaneous Sample Sweep Mode
Table 14.1.6.1 Simultaneous Sample Sweep Mode Specifications
14. A/D Converter
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Figure 14.1.6.2 ADCON0 to ADCON2 Registers for Simultaneous Sample Sweep Mode
A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0
MD0
MD1
Trigger Select Bit
TRG
ADST A/D Conversion Start Fag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit (Note 2)
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT VREF Connect Bit (Note 3)
A/D Operation Mode
Select Bit 1
1 : VREF connected
1
01
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
0
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D416 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group
Select Bit 0 0 : Select port P10 group (ANi)
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Do not set
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Refer to Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger select bit 1
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Refer to Table 14.1.6.2 Trigger Select Bit
Setting in Simultaneous Sample Sweep
Mode
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSET0 bits in the
ADCON2 register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Invalid in simultaneous sample sweep mode
1 0 : Single sweep mode or simultaneous
sample sweep mode
b4 b3
When selecting simultaneous sample sweep
mode
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
1
Refer to Table 14.1.6.2 Trigger Select Bit
Setting in Simultaneous Sample Sweep
Mode
Set to “1” in simultaneous sample
sweep mode
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
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Figure 14.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode
A/D trigger control register (Note 1)
Symbol Address After reset
ADTRGCON 03D2
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
A/D Operation Mode
Select Bit 2
Bit symbol Bit name Function RW
SSE
A/D Operation Mode
Select Bit 3
AN1 Trigger Select Bit
HPTRG1
DTE
HPTRG0
RW
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
AN0 Trigger Select Bit
Note 1: If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
0
0 : Any mode other than delayed trigger
mode 0,1
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
10
Refer to Table 14.1.6.2 Trigger Select
Bit Setting in Simultaneous Sample
Sweep Mode
Set to "0" in simultaneous sample
sweep mode
Table 14.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
TRG HPTRG0TRG1 TRIGGER
0
1
1
1
-
1
0
0
Software trigger
Timer B0 underflow (Note 1)
Timer B2 or Timer B2 interrupt generation frequency
setting counter underflow (Note 2)
AD
TRG
-
-
1
0
Note 1: A count can be started for Timer B2, Timer B2 interrupt generation frequency
setting counter underflow or the INT5 pin falling edge as count start
conditions of Timer B0.
Note 2: Select Timer B2 or Timer B2 interrupt generation frequency setting counter
using the TB2SEL bit in the TB2SC register.
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Item Specification
Function The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits in
the ADCON2 register select pins. Analog voltage applied to the input voltage of the
selected pins are converted one-by-one to the digital code. At this time, Timer B0 under
flow generation starts AN0 pin conversion. Timer B1 underflow generation starts con
version after the AN1 pin. (Note 1)
A/D Conversion Start
AN0 pin conversion start condition
•When Timer B0 underflow is generated if Timer B0 underflow is generated again
before Timer B1 underflow is generated , the conversion is not affected
•When Timer B0 underflow is generated during A/D conversion of pins after the AN1
pin, conversion is halted and the sweep is restarted from AN0 pin
AN1 pin conversion start condition
•When Timer B1 underflow is generated during A/D conversion of the AN0 pin, the
input voltage of the AN1 pin is sampled. The AN1 conversion and the rest of the
sweep start when AN0 conversion is completed.
A/D Conversion Stop
•When single sweep conversion from the AN0 pin is completed
Condition
•Set the ADST bit to "0" (A/D conversion halted)(Note 2)
Interrupt Request A/D conversion completed
Generation Timing
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
AN0 to AN7 (8 pins)(Note 3)
Readout of A/D Conversion Result
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
Note 1: Set the larger value than the value of the timer B0 register to the timer B1 register.
Note 2: Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 0. When write “1”,
unexpected interrupts may be generated.
Note 3: AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same
group.
14.1.7 Delayed Trigger Mode 0
In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a
digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The
Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1
pin is not sampled and converted until the Timer B1 underflow is generated. When the Timer B1 under-
flow is generated, the single sweep conversion is restarted with the AN1 pin. Table 14.1.7.1 shows the
delayed trigger mode 0 specifications. Figure 14.1.7.1 shows the operation example in delayed trigger
mode 0. Figure 14.1.7.2 and Figure 14.1.7.3 show each flag operation in the ADSTAT0 register that
corresponds to the operation example. Figure 14.1.7.4 shows the ADCON0 to ADCON2 registers in
delayed trigger mode 0. Figure 14.1.7.5 shows the ADTRGCON register in delayed trigger mode 0 and
Table 14.1.7.2 shows the trigger select bit setting in delayed trigger mode 0.
Table 14.1.7.1 Delayed Trigger Mode 0 Specifications
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AN
0
AN
1
AN
2
AN
3
Timer B0 underflow
A/D pin input
voltage sampling
A/D pin conversion
AN
0
AN
1
AN
2
AN
3
Timrt B0 underflow
(An interrupt does not affect A/D conversion)
Timer B0 underflow
Timer B1 underflow
Timer B1 underflow
•Example when selecting AN
0
to AN
3
to analog input pins (SCAN1 to SCAN0=01
2
)
•Example 1: When Timer B1 underflow is generated during AN
0
pin conversion
AN
0
AN
1
AN
2
AN
3
Timer B0 underflow
Timer B1 underflow
•Example 2: When Timer B1 underflow is generated after AN
0
pin conversion
AN
0
AN
1
AN
2
AN
3
Timer B0 underflow
(Abort othrt pins conversion)
Timer B0 underflow
Timer B1 under flow
Timer B1 underflow
•Example 3: When Timer B0 underflow is generated during A/D conversion of any pins except AN
0
pin
•Example 4: When Timer B0 underflow is generated again before Timer B1 underflow is generated
after Timer B0 underflow generation
Figure 14.1.7.1 Operation Example in Delayed Trigger Mode 0
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Figure 14.1.7.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation
Example in Delayed Trigger Mode 0 (1)
AN0
AN1
AN2
AN3
Timer B0 underflow
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
AN0
AN1
AN2
AN3
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
A/D pin input
voltage sampling
A/D pin conversion
Do not set to "1" by program
Do not set to "1" by program
Set to "0" by an interrupt request acknowledgement or a program
Set to "0" by an interrupt request acknowledgement or a program
Set to “0" by program
Set to "0" by program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
Timer B0 underflow
Timer B1 underflow
Timer B1 underflow
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
•Example 1: When Timer B1 underflow is generated during AN0 pin conversion
•Example 2: When Timer B1 underflow is generated after AN0 pin conversion
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AN0
AN1
AN2
AN3
Timer B0 underflow
(Abort othrt pins conversion )
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
A/D pin input
voltage sampling
A/D pin conversion
Do not set to "1" by program
Set to "0" by interrupt request acknowledgement or a program
Set to "0" by program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
Timer B0 underflow
Timer B1 underflow
Timer B1 underflow
•Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN0 pin
AN0
AN1
AN2
AN3
Timrt B0 underflow
(An interrupt does not affect A/D conversion)
"1"
"0"
"1"
"0"
"1"
"0"
-
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Do not set to "1" by program
Set to "0" by interrupt request acknowledgement or a program
Set to "0" by program
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
Timer B0 underflow
Timer B1 underflow
•Example 4: After Timer B0 underflow is generated and when Timer B0 underflow is generated again
before Timer B1 underflow is genetaed
Figure 14.1.7.3 Each Flag Operation in ADSTAT0 Register Associated with the Operation
Example in Delayed Trigger Mode 0 (2)
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Figure 14.1.7.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0
A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0
MD0
MD1 Trigger Select Bit Refer to Table 14.1.7.2 Trigger Select Bit
Setting in Delayed Trigger Mode 0
TRG
ADST A/D Conversion Start
Flag (Note 2) 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit (Note 2)
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT V
REF
Connect Bit
(Note 3)
A/D Operation Mode
Select Bit 1
1 : V
REF
connected
01
When selecting delayed trigger sweep mode 0
0
1 1 1 : Set to "111b" in delayed trigger
mode 0
b2 b1 b0
0 0 : One-shot mode or delayed trigger mode
0,1
b4 b3
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: Do not write “1” in delayed trigger mode 0. When write, set to "0".
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN
30
to AN
32
can be used in the same way as AN
0
to AN
7
. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2
register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (V
REF
unconnected) to “1” (V
REF
connected), wait for 1 µs or more before starting
A/D conversion.
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
110
b1 b0
0 0: AN
0
to AN
1
(2 pins)
0 1: AN
0
to AN
3
(4 pins)
1 0: AN
0
to AN
5
(6 pins)
1 1: AN
0
to AN
7
(8 pins)
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: Set to “1” in delayed trigger mode 0.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D4
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit (Note 2) 1 : With sample and hold
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to “0”
0
A/D Input Group
Select Bit 0 0 : Select port P10 group (AN
i
)
0 1 : Select port P9 group (AN
3i
)
1 0 : Do not set
1 1 : Do not set
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Refer to Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger Select Bit 1
1
Refer to Table 14.1.7.2 Trigger Select Bit
Setting in Delayed Trigger Mode 0
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
0
0
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Figure 14.1.7.5 ADTRGCON Register in Delayed Trigger Mode 0
A/D trigger control register (Note 1)
Symbol Address After reset
ADTRGCON 03D216 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Operation Mode
Select Bit 2
Bit symbol Bit name Function RW
SSE
A/D Operation Mode
Select Bit 3
AN1 Trigger Select Bit
HPTRG1
DTE
HPTRG0
RW
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
AN0 Trigger Select Bit
Note 1: If ADTRGCON reigster is rewritten during A/D conversion, the conversion result will be indeterminate.
1
Delayed trigger mode 0, 1
Simultaneous sample sweep mode or
delayed trigger mode 0,1
1
Refer to Table 14.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
Refer to Table 14.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
1
1
Trigger
Timer B0, B1 underflow
TRG
0
HPTRG0
1
TRG1
0
HPTRG1
1
Table 14.1.7.2 Trigger Select Bit Setting in Delayed Trigger Mode 0
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14.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep
conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted
until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,
The single sweep conversion of the pins after the AN1 pin is restarted. Table 14.1.8.1 shows the delayed
trigger mode 1 specifications. Figure 14.1.8.1 shows the operation example of delayed trigger mode 1.
Figure 14.1.8.2 to Figure 14.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 14.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger
mode 1. Figure 14.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2
shows the trigger select bit setting in delayed trigger mode 1.
Table 14.1.8.1 Delayed Trigger Mode 1 Specifications
Item Specification
Function The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltages applied to the selected pins are
converted one-by-one to a digital code. At this time, the ADTRG pin
falling edge starts AN0 pin conversion and the second ADTRG pin falling edge starts
conversion of the pins after AN1 pin
A/D Conversion Start AN0 pin conversion start condition
Condition The ADTRG pin input changes state from “H” to “L” (falling edge)(Note 1)
AN1 pin conversion start condition (Note 2)
The ADTRG pin input changes state from “H” to “L” (falling edge)
•When the second ADTRG pin falling edge is generated during or after A/D
conversion of the AN0 pin, input voltage of AN1 pin is sampled at the time of ADTRG
falling edge. The conversion of AN1 and the rest of the sweep starts when AN0
conversion is completed.
•When the ADTRG pin falling edge is generated again during single sweep conver
sion of pins after the AN1 pin, the conversion is not affected
A/D Conversion Stop
•
A/D conversion completed
Condition •Set the ADST bit to "0" (A/D conversion halted)(Note 3)
Interrupt Request Single sweep conversion completed
Generation Timing
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
AN0 to AN7 (8 pins)(Note 4)
Readout of A/D Conversion Result
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
___________
Note 1: When a thrid ADTRG pin falling edge is generated again during A/D conversion, its trigger is ignored.
___________ ___________
Note 2: The ADTRG pin falling edge is detected synchronized with the operation clock φAD. Therefore, when the ADTRG
___________
pin falling edge is generated in shorter periods than φAD, the second ADTRG pin falling edge may not be
___________
detected. Do not generate the ADTRG pin falling edge in shorter periods than φAD.
Note 3: Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write “1”, unexpected
interrupts may be generated.
Note 4: AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same
group.
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•Example when selecting AN
0
to AN
3
to analog input pins (SCAN1 to SCAN0=01
2
)
A/D pin input
voltage sampling
A/D pin conversion
AN
0
AN
1
AN
2
AN
3
AD
TRG
pin input
•Example 1: When AD
TRG
pin falling edge is generated during AN
0
pin conversion
AN
0
AN
1
AN
2
AN
3
•Example 2: When AD
TRG
pin falling edge is generated again after AN
0
pin conversion
AD
TRG
pin input
•Example 3: When AD
TRG
pin falling edge is generated more than two times after AN
0
pin conversion
AN
0
AN
1
AN
2
AN
3
(invalid)
(valid after single sweep conversion)
AD
TRG
pin input
Figure 14.1.8.1 Operation Example in Delayed Trigger Mode1
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•Example when selecting AN
0
to AN
3
to analog input pins (SCAN1 to SCAN0=01
2
)
A/D pin input
voltage sampling
A/D pin conversion
AN
0
AN
1
AN
2
AN
3
AN
0
AN
1
AN
2
AN
3
•Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion
AD
TRG
pin input
•Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by interrupt request acknowledgement or a program
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Set to "0" by program
Set to "0" by interrupt request acknowledgment or a program
Set to "0" by program
Do not set to "1" by program
Do not set to "1" by program
AD
TRG
pin input
Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (1)
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•Example 3: When ADTRG input falling edge is generated more than two times after AN0 pin conversion
AN0
AN1
AN2
AN3
(invalid)
(valid after single sweep conversion)
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" when interrupt request acknowledgement or a program
Set to "0" by program
Do not set to "1" by program
A/D pin input
voltage sampling
A/D pin conversion
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
ADTRG
pin input
Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (2)
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A/D control register 0 (Note 1)
Symbol Address After reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0
MD0
MD1 Trigger Select Bit Refer to Table 14.1.8.2 Trigger Select Bit
Setting in Delayed Trigger Mode 1
TRG
ADST A/D Conversion Start
Flag (Note 2) 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (Note 1)
Symbol Address After reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit (Note 2)
SCAN0
SCAN1
MD2
BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT V
REF
Connect Bit
(Note 3)
A/D Operation Mode
Select Bit 1
1 : V
REF
connected
01
When selecting delayed trigger mode 1
0
1 1 1 : Set to "111b" in delayed trigger
mode 1
b2 b1 b0
0 0 : One-shot mode or delayed trigger mode
0,1
b4 b3
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: Do not write “1” in delayed trigger mode 1. When write, set to "0".
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN
30
to AN
32
can be used in the same way as AN
0
to AN
7
. Use the ADGSEL1 to ADGSET0 bits in the ADCON2
register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (V
REF
unconnected) to “1” (V
REF
connected), wait for 1 µs or more before starting
A/D conversion.
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
110
b1 b0
0 0: AN
0
to AN
1
(2 pins)
0 1: AN
0
to AN
3
(4 pins)
1 0: AN
0
to AN
5
(6 pins)
1 1: AN
0
to AN
7
(8 pins)
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: Set to “1” in delayed trigger mode 1.
A/D control register 2 (Note 1)
Symbol Address After reset
ADCON2 03D4
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit (Note 2) 1 : With sample and hold
Bit symbol Bit name Function RW
SMP
Reserved Bit Set to
“0”
0
A/D Input Group
Select Bit 0 0 : Select port P10 group (AN
i
)
0 1 : Select port P9 group (AN
3i
)
1 0 : Do not set
1 1 : Do not set
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Refer to Table 14.2 A/D Conversion
Frequency Select
RW
TRG1 Trigger Select Bit 1
1
Refer to Table 14.1.8.2 Trigger Select Bit
Setting in Delayed Trigger Mode 1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
1
0
Figure 14.1.8.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1
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A/D trigger control register (Note 1)
Symbol Address After reset
ADTRGCON 03D216 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Operation Mode
Select Bit 2
Bit symbol Bit name Function RW
SSE
A/D Operation Mode
Select Bit 3
AN1 Trigger Select Bit
HPTRG1
DTE
HPTRG0
RW
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
AN0 Trigger Select Bit
Note 1: If ADTRGCON is rewritten during A/D conversion, the conversion result will be indeterminate.
1
Delayed trigger mode 0, 1
Simultaneous sample sweep mode or
delayed trigger mode 0,1
10
Refer to Table 14.1.8.2 Trigger Select
Bit Setting in Delayed Trigger Mode 1
Refer to Table 14.1.8.2 Trigger Select
Bit Setting in Delayed Trigger Mode 1
0
Figure 14.1.8.5 ADTRGCON Register in Delayed Trigger Mode 1
Trigger
TRG
0
HPTRG0
0
TRG1
1ADTRG
HPTRG1
0
Table 14.1.8.2 Trigger Select Bit Setting in Delayed Trigger Mode 1
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14.2 Resolution Select Function
The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit
precision), the A/D conversion result is stored into bits 0 to 9 in the A/D register i (i=0 to 7). When the BITS
bit is set to “0” (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADi register.
14.3 Sample and Hold
When the SMP bit in the ADCON 2 register is set to “1” (with the sample and hold function), A/D conver-
sion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. The
sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep
mode 0 and repeat sweep mode 1. In these modes, start A/D conversion after selecting whether the
sample and hold circuit is to be used or not. In simultaneous sample sweep mode, delayed trigger mode
0 or delayed trigger mode 1, set to use the Sample and Hold function before starting A/D conversion.
14.4 Power Consumption Reducing Function
When the A/D converter is not used, the VCUT bit in the ADCON1 register isolates the resistor ladder of
the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting
off any current flow into the resistor ladder from the VREF pin.
When using the A/D converter, set the VCUT bit to “1” (VREF connected) before setting the ADST bit in the
ADCON0 register to “1” (A/D conversion started). Do not set the ADST bit and VCUT bit to “1” simulta-
neously, nor set the VCUT bit to “0” (VREF unconnected) during A/D conversion.
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14.5 Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.5.1 has to be
completed within a specified period of time. T (sampling time) as the specified time. Let output imped-
ance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of
the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256
in the 8-bit mode).
VC is generally VC = VIN{1-e c(R0+R) }
And when t = T, VC=VIN- VIN=VIN(1- )
e c(R0+R) =
- T = ln
Hence, R0 = - - R
Figure 14.5.1 shows analog input pin and externalsensor equivalent circuit. When the difference be-
tween VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins. VC changes
from 0 to VIN-(0.1/1024) VIN in timer T. (0.1/1024) means that A/D precision drop due to insufficient
capacitor chage is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is
the value of absolute precision added to 0.1LSB. When f(XIN) = 10MHz, T=0.3µs in the A/D conversion
mode with sample & hold. Output inpedance R0 for sufficiently charging capacitor C within time T is
determined as follows.
T = 0.3µs, R = 7.8kΩ, C = 1.5pF, X = 0.1, and Y = 1024. Hence,
R0 = - - 7.8 X 103 ≅ 13.9 X 103
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D con-
verter turns out of be approximately 13.9kΩ.
Figure 14.5.1 Analog Input Pin and External Sensor Equivalent Circuit
R0R (7.8kΩ)
C (1.5pF)
VIN
VC
Sampling time
Sample-and-hold function enabled:
Sample-and-hold function disabled:
3
fAD
Microcomputer
Sensor equivalent
circuit
2
fAD
1
1T
t
C(R0+R)
1X
Y
X
Y
X
Y
X
Y
T
C•ln X
Y
1.5X10-12•ln 0.1
1024
0.3X10-6
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15. CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses
a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) or CRC-16 (X16 + X15 + X2 + 1) to generate
CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes. The code
is updated in the CRC data register everytime one byte of data is transferred to a CRC input register. The
data register needs to be initialized before use. Generation of CRC code for one byte of data is completed
in two machine cycles.
Figure 15.1 shows the block diagram of the CRC circuit. Figure 15.2 shows the CRC-related registers.
Figure 15.3 shows the calculation example using the CRC_CCITT operation.
15.1. CRC Snoop
The CRC circuit includes the ability to snoop reads and writes to certain SFR addresses. This can be
used to accumulate the CRC value on a stream of data without using extra bandwidth to explicitly write
data into the CRCIN register. For example, it may be useful to snoop the writes to a UART TX buffer ,
or the reads from a UART RX buffer. This can only be used on USB, UART, and SSI registers.
To snoop an SFR address, the target address is written to the CRC snoop Address Register
(CRCSAR). The two most significant bits in this register enable snooping on reads or writes to the target
address. If the target SFR is written to by the CPU or DMA, and the CRC snoop write bit is set (the
CRCSW bit is set to "1"), the CRC will latch the data into the CRCIN register. The new CRC code will be
set in the CRCD register.
Similarly, if the target SFR is read by the CRC or DMA, and the CRC snoop read bit is set (the CRCSR
bit is set to "1"), the CRC will latch the data from the target into the CRCIN register and calculate the
CRC.
The CRC circuit can only calculate CRC codes on data byte at a time. Therefore, if a target SFR is
accessed in a word (16 bit) bus cycle, only the byte of data going to or from the target snooped into
CRCIN, the other byte of the word access is ignored.
Figure 15.1 CRC circuit block diagram
AAAAA
Eight low-order bits
AAAAA
Eight high-order bits
Data bus high-order
Data bus low-order
AAAAAAAAAA
AAAAAAAAAA
AAAAA
AAAAA
CRCD register (16)
CRC input register (8)
AAAAAAAAAA
A
AAAAAAAA
A
AAAAAAAAAA
CRC code generating circuit
x
16
+ x
12
+ x
5
+ 1 OR x
16
+ x
15
+ x
2
+ 1
Address Bus
SnoopB
lock
Snoop
enable
Snoop Address
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
Equal?
(Address 03BD16, 03BC16)
(Address 03BE16)
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Symbol Address After reset
CRCD 03BD
16
to 03BC
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
CRC data register
Function Setting range
0000
16
to FFFF
16
RW
RW
Symbol Address After reset
CRCIN 03BE
16
Indeterminate
b7 b0
CRC input register
Data input
Function
00
16
to FF
16
RW
RW
Setting range
CRC calculation result output
Symbol Address After reset
CRCSAR 03B5
16
to 03B4
16
00XXXXXX XXXXXXXX
16
b7 b0 b7 b0
(b15) (b8)
CRC snoop address register
Symbol Address After reset
CRCMR 03B6
16
0XXXXXX0
2
b7 b0
CRC mode register
CRC mode polynomial
selection bit
Function
0: LSB first
1: MSB first
RW
RW
Bit nameBit symbol
CRC mode selection bit
CRCPS
CRCMS RW
Nothing is assigned.
Write "0" when writing to this bit. The value is indeterminate if read.
0: X
16
+X
12
+X
5
+1 (CRC-CCITT)
1: X
16
+X
15
+X
2
+1 (CRC-16)
CRC mode polynomial
selection bit
Function
0: LSB first
1: MSB first
RW
RW
Bit nameBit symbol
CRC mode selection bit
CRCPS
CRCMS RW
Nothing is assigned. Write "0" when writing to this bit.
The value is indeterminate if read.
0: X
16
+X
12
+X
5
+1 (CRC-CCITT)
1: X
16
+X
15
+X
2
+1 (CRC-16)
CRC mode polynomial
selection bit
Function RW
RW
Bit nameBit symbol
CRCSR RW
Nothing is assigned. Write "0" when writing to this bit.
The value is indeterminate if read.
SFR address to snoop
Function
0: Disabled
1: Enabled
RW
CRCSW
CRCSAR9-0
CRC Snoop on read
enable bit
CRC Snoop on write
enable bit 0: Disabled
1: Enabled RW
(b6-b1)
(b13-b10)
Figure 15.2. CRCD, CRCIN, CRCMR, CRCSAR Register
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Figure 15.3. CRC Calculation
(1) Setting 0000
16
(initial value) b15 b0
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
1000 1000 MSB
Modulo-2 operation is
operation that complies
with the law given below.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
The code resulting from sending 01
16
in LSB first mode is (10000 0000).This the CRC code in the generating polynomial,
(X16 + X12 + X5 + 1), becomes the remainder resulting from dividing(1000 0000)X
16
by ( 1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
(2) Setting 01
16
b0b7
b15 b0
1189
16
2 cycles
After CRC calculation is complete
Thus the CRC code becomes ( 1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 1189
16
in hexadecimal notation. If the CRC operation in MSB first mode is necessary, set the CRC mode
selection bit to "1". CRC data register stores CRC code for MSB first mode.
CRD data register CRCD
[03BD
16
, 03BC
16
]
CRC input register CRCIN
[03BE
16
]
CRD data register CRCD
[03BD
16
, 03BC
16
]
CRC input register CRCIN
[03BE
16
]
(3) Setting 23
16
b0b7
b15 b0
0A41
16
After CRC calculation is complete
CRD data register CRCD
[03BD
16
, 03BC
16
]
98 11
MSB
LSB
LSB
Stores CRC code
Stores CRC code
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16. Programmable I/O Ports
Note
There is no external connections for port P60 to P63, P92 and P93 in the M16C/26A (42-pin version)
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 39 lines P15 to
P17, P6, P7, P8, P90 to P93, P10 for the 48-pin version, or 33 lines P15 to P17, P64 to P67, P7, P8, P90 to
P91, P10 for the 42-pin version. Each port can be set for input or output every line by using a direction
register, and can also be chosen to be or not be pulled high in sets of 4 lines.
Figures 16.1 to 16.4 show the I/O ports. Figure 16.5 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an
output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.
16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
Figure 16.1.1 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register corre-
spond one for one to each port.
16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
Figure 16.2.1 shows the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports
set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 16.3.1 shows the PUR0 to PUR2 registers.
The bits in the PUR0 to PUR2 registers can be used to select whether or not to pull the corresponding port
high in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the
direction bit is set for input mode. ____________
Also, P67 is connected to a pull-up resistor when the CNVSS pin is “H”, and the RESET pin is “L”.
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16.4 Port Control Register
Figure 16.4.1 shows the port control register.
When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port
latch can be read no matter how the PD1 register is set.
16.5 Pin Assignment Control register (PACR)
Figure 16.5.1 shows the PACR. After reset set the PACR2 to PACR0 bit before you input and output it to
each pin. When the PACR register isn’t set up, the input and output function of some of the pins doesn’t
work.
PACR2 to PACR0 bits: control the pins enabled for use.
At reset these bits equal “000”.
When using the 48 pin version of the M16C/26A and the 48 pin version of the M16C/26T set these
bits to “1002”.
When using the 42 pin version of the M16C/26A set these bits to “0012”.
U1MAP: controls the assignment of UART1 pins.
If the U1MAP bit is set to “0” (P67 to P64) the UART1 functions are mapped to P64/CTS1/RTS1,
P65/CLK1, P66/RxD1, and P67/TxD1.
If the U1MAP bit is set to “1” (P73 to P70) the UART1 functions are mapped to P70/CTS1/RTS1,
P71/CLK1, P72/RxD1, and P73/TxD1.
PACR is write protected by PRC2 bit in the PRCR register. PRC2 bit must be set immediately before the
write to PACR.
16.6 Digital Debounce function
Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction. ________ _______ _____
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively. Additionally, a digital debounce function is disabled to the port P17
input and port P85 input. Figure 16.6.1 shows the NDDR register and the P17DDR register.
Filter width : f8 × 1 / (n+1) n: count value set in the NDDR register and P17DDr register
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or
a rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 0016 to FF16 when using the digital debounce
function. Setting to FF16 disables the digital filter. See Figure 16.6.2 for details.
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Figure 16.1. I/O Ports (1)
P9
3
(inside dotted-line included)
Data bus
(Note 1)
Analog input
Pull-up selection
Direction register
Port latch
P6
0
, P6
1
, P6
4
, P6
5
,
P7
3
, P7
5
, P8
1
Note 1: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
P7
4
, P7
6
, P8
0
(inside dotted-line not included)
(inside dotted-line included)
"1"
Output
Data bus
Direction
register
Port latch
Pull-up selection
(Note 1)
Input to respective peripheral functions
P1
5
to P1
6
Data bus
P1
7
(inside dotted-line not included)
(inside dotted-line included)
Direction register
Port latch
Pull-up selection
(Note 1)
Port P1 control register
Input to respective peripheral functions
INT5 Digital
Debounce
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Figure 16.2. I/O Ports (2)
P82 to P84
(Note 1)
P77
(inside dotted-line not included)
P90 to P92
(inside dotted-line included)
Data bus
Pull-up selection
Direction register
Port latch
Data bus
Pull-up selection
Direction register
Port latch
Input to respective peripheral functions
Input to respective peripheral functions
(Note 1)
P70, P71, P72
"1"
Output
Data bus
Direction
register
Port latch
Pull-up selection
(Note 1)
Input to respective peripheral functions
Note 1: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Switching
between
CMOS and
Nch
Analog input
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Figure 16.3. I/O Ports (3)
P6
2
, P6
6
Data bus
Pull-up selection
Direction register
Port latch
Input to respective peripheral functions
(Note 1)
P8
5
P6
3
, P6
7
Output
“1”
Data bus
Pull-up selection
Direction register
Port latch
(Note 1)
Switching between CMOS and Nch
Note 1: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Switching
between
CMOS and Nch
Data bus
Pull-up selection
Direction register
Port latch
NMI Interrupt Input
NMI Enable
Digital Debounce
NMI Enable
SD
(Note 1)
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Figure 16.4. I/O Ports (4)
Data bus
Direction register
Pull-up selection
Port latch
Analog input
Input to respective peripheral functions
P100 to P103
(inside dotted-line
not included)
P104 to P107
(inside dotted-line
included)
(Note 1)
P87
P86
fc
Rf
Rd
Data bus
Direction register
Pull-up selection
Port latch
Direction register
Pull-up selection
Port latch
Data bus (Note)
(Note)
Note: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
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Figure 16.5. I/O Pins
CNV
SS
CNV
SS
signal input
RESET RESET signal input
(Note 1)
(Note 1)
Note 1: symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
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Figure 16.1.1. PD1, PD6, PD7, PD8, PD9, and PD10 Registers
Port Pi direction register (i=6 to 8, and 10) (Note)
Symbol Address After reset
PD6 to PD8 03EE
16
, 03EF
16
, 03F2
16
00
16
PD10 03F6
16
00
16
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PDi_0 Port Pi
0
direction bit
PDi_1 Port Pi
1
direction bit
PDi_2 Port Pi
2
direction bit
PDi_3 Port Pi
3
direction bit
PDi_4 Port Pi
4
direction bit
PDi_5 Port Pi
5
direction bit
PDi_6 Port Pi
6
direction bit
PDi_7 Port Pi
7
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 6 to 8, and 10)
Note: Ports must be enabled using the PACR
In 48 pin version set PACR2, PACR1, PACR0 to "1002"
In 42 pin version set PACR2, PACR1, PACR0 to "0012"
RW
RW
RW
RW
RW
RW
RW
RW
Port P1 direction register (Note 1)
Symbol Address After reset
PD1
03E316 00
16
Bit
name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
PD1_5 Port P1
5
direction bit
RW
PD1_6 Port P1
6
direction bit
RW
PD1_7 Port P1
7
direction bit
RW
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b4-b0)
Note 1: Ports must be enabled using the PACR
In 48 pin version set PACR2, PACR1, PACR0 to "1002"
In 42 pin version set PACR2, PACR1, PACR0 to "0012"
Port P9 direction register (Note 1,2)
Symbol Address After reset
PD9
03F316 XXXX0000
2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
PD9_0 Port P9
0
direction bit
PD9_1 Port P9
1
direction bit
PD9_2 Port P9
2
direction bit
PD9_3 Port P9
3
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
RW
RW
RW
RW
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(B7-b4)
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR
register's PRC2 bit to "1"(write enabled).
Note 2: Ports must be enabled using the PACR
In 48 pin version set PACR2, PACR1, PACR0 to "1002"
In 42 pin version set PACR2, PACR1, PACR0 to "0012"
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Symbol Address After reset
P6 to P8 03EC16, 03ED16, 03F016 Indeterminate
P10 03F416 Indeterminate
Port Pi register (i=6 to 8 and 10) (Note1)
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
bit
Pi_1 Port Pi
1
bit
Pi_2 Port Pi
2
bit
Pi_3 Port Pi
3
bit
Pi_4 Port Pi
4
bit
Pi_5 Port Pi
5
bit
Pi_6 Port Pi
6
bit
Pi_7 Port Pi
7
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level (Note 1)
(i = 6 to 8 and 10)
RW
RW
RW
RW
RW
RW
RW
RW
Note1: Ports must be enabled using the PACR
In 48 pin version set PACR2, PACR1, PACR0 to "1002"
In 42 pin version set PACR2, PACR1, PACR0 to "0012"
Port P1 register
(Note1)
Symbol Address After reset
P1 03E116 Indeterminate
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
P1_5 Port P15 bit
P1_6 Port P16 bit
P1_7 Port P17 bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level
RW
RW
RW
RW
Note1: Ports must be enabled using the PACR
In 48 pin version set PACR2, PACR1, PACR0 to "1002"
In 42 pin version set PACR2, PACR1, PACR0 to "0012"
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b4-b0)
Port P9 register
(Note1)
Symbol Address After reset
P9 03F116 Indeterminate
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
P9_0 Port P90 bit
P9_1 Port P91 bit
P9_2 Port P92 bit
P9_3 Port P93 bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level
RW
RW
RW
RW
RW
Note1: Ports must be enabled using the PACR
In 48 pin version set PACR2, PACR1, PACR0 to "1002"
In 42 pin version set PACR2, PACR1, PACR0 to "0012"
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b7-b4)
Figure 16.2.1. P1, P6, P7, P8, P9, and P10 Registers
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Pull-up control register 0
Symbol Address After reset
PUR0 03FC
16 0016
Bit name Function Bit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PU03 P1
5
to P1
7
pull-up 0 : Not pulled high
1 : Pulled high (Note)
RW
Note : The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-up control register 2
Symbol Address After reset
PUR2 03FE
16 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
PU20 P8
0
to P8
3
pull-up
PU21 P8
4
to P8
7
pull-up
PU22 P9
0
to P9
3
pull-up
PU24 P10
0
to P10
3
pull-up
PU25 P10
4
to P10
7
pull-up
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
0 : Not pulled high
1 : Pulled high (Note)
RW
RW
RW
RW
RW
RW
(b7-b6)
Note : The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b2-b0)
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b7-b4)
Pull-up control register 1
Symbol Address After reset(Note 5)
PUR1 03FD16 000000002
Bit name Function Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
PU14 P6
0
to P6
3
pull-up
PU15 P6
4
to P6
7
pull-up
PU16 P7
0
to P7
3
pull-up
PU17 P7
4
to P7
7
pull-up
0 : Not pulled high
1 : Pulled high (Note)
Note : The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
RW
RW
RW
RW
RW
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b3-b0)
0 : Not pulled high
1 : Pulled high (Note)
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b3)
Figure 16.3.1. PUR0 to PUR2 Registers
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Figure 16.4.1. PCR Register
Port control register
Symbpl Address After reset
PCR 03FF16 00
16
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
PCR0 Port P1 control bit
Nothing is assigned.
In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
RW
(b7-b1)
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17
pins are read. When set for
output, the port latch is read.
1: The port latch is read
regardless of whether the port
is set for input or output.
Figure 16.5.1. PACR Register
Pin assignment control register (Note)
Symbpl Address After reset
PACR 025D
16
00000000
2
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Pin enabling bit
Nothing is assigned. In an attempt
to write to these bits, write “0”.
The value, if read, turns out to
be “0”.
RW
(b6-b3)
001 : 42 pin
100 : 48 pin
All other values are reserved. Do
not use.
PACR0
PACR1
PACR2
RW
RW
Reserved bits
U1MAP UART1 pin remapping bit UART1 pins assigned to
0 : P6
7
to P6
4
1 : P7
3
to P7
0
RW
Note : Make sure the PACR register is written to by the next instruction after setting the PRC2 bit in the PRCR
re
g
ister to “1” (write enable).
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Figure 16.6.1. NDDR and P17DDR Registers
NMI digital debounce register (Note)
Symbol Address After reset
NDDR 033E
16
FF
16
RW
b7 b0
Function RW
Note 1 : If the microcomputer is to be moved out of stop mode by NMI interrupt, make sure NDDR register is
set to “FF
16
” (the digital debounce filter is disabled) before entering stop mode.
Note 2 : Make sure the PACR register is written to by the next instruction after setting the PRC2 bit in the
PRCR register to "1" (write enable).
Setting range
00
16
~FF
16
Assuming that set value =n,
for n = 0 to FEh, NMI / SD pulse whose width is greater than
(V1/8) / ( n + 1) will be input.
For n = FFh, the digital debounce filter is disabled.
All signals are input.
P1
7
digital debounce register
Symbol Address After reset
P17DDR 033F
16
FF
16
RW
b7 b0
Function RW
Setting range
00
16
~FF
16
Assuming that set value =n,
for n = 0 to FEh, INPC1
7
/INT5 pulse whose width is greater
than (V1/8) / ( n + 1) will be input.
For n = FFh, the digital debounce filter is disabled.
All signals are input.
Note : If the microcomputer is to be moved out of stop mode by INT5 interrupt, make sure P17DDR register is
set to “FF
16
” (the digital debounce filter is disabled) before entering stop mode.
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Figure 16.6.2. Functioning of Digital Debounce Filter
f8
P85 / P17
Data Bus
1. (Condition after reset). Reload = FF, Port In = signal Out continuosly.
2. Reload = 03. At edge of Port In != Signal Out, Counter gets Reload Value and
stats counting down.
3. Port In = Signal Out, counting stops.
4. At edge of Port In != Signal Out, Counter gets Reload Value and starts counting.
5. Counter underflows, stops, and Port In is driven to Signal Out.
6. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.
7. Counter underflows, stops, and Port In is driven to Signal Out.
8. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.
9. FF is written to Reload Value. Counter is stopped and loaded with FF.
Port In = Signal Out continuously.
Clock
Port In
Reload Value
(write)
Digital Debounce Filter
Signal Out
Count Value
(read)
To NMI and SD / INT5 and INPC17
Data Bus
f8
Reload Value
Port In
Signal Out
Count Value
Reload Value
(continued)
Port In
(continued)
Signal Out
(continued)
Count Value
(continued)
FF 03
FF 03 02 01 03 02 01 00 FF
03 FF
03 02 01 00
FF FF 03 02 FF
1 2 345
6789
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Pin name Connection
Ports P1, P6 to P10
X
OUT
(Note 3)
AV
SS
, V
REF
AV
CC
After setting for input mode, connect every pin to V
SS
via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 1, Note 2, Note 4)
Open
Connect to V
CC
Connect to V
SS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input
mode until it is switched to output mode in a program after reset. For this reason, the voltage level
on the pin becomes indeterminate, causing the power supply current to increase while the port
remains in input mode.
Futhermore, by considering a possibility that the contents of the direction registers could be
changed by noise or noise-induced runaway, it is recommended that the contents of the
directionregisters be periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
Note 3: With external clock or V
CC
input to X
IN
pin.
Note 4: When using the 48pin version, set PACR2, PACR1, PACR0 to "1002".
When using the 42pin version, set PACR2, PACR1, PACR0 to "0012".
Note 5: When the main clock oscillation circuit is not used, set the CM05 bit in the CM0 register to “0”
(main clock stops) to reduce power consumption.
Connect via resistor to V
CC
(pull-up) (Note 5)
Xin
Table 16.1. Unassigned Pin Handling in Single-chip Mode
Figure 16.7. Unassigned Pins Handling
(Input mode)
·
·
·
(Input mode)
(Output mode)
XOUT
AVCC
AVSS
VREF
Microcomputer
VCC
VSS
In single-chip mode
Open
Open
·
·
·
Note : when using the 48pin version, set PACR2, PACR1, PACR0 to "1002".
when using the 42pin version, set PACR2, PACR1, PACR0 to "0012".
(Note)
Port P1, P6 to P10
XIN
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Table 17.1. Flash Memory Version Specifications
Item
Flash memory operating mode
Erase block
Program method
Erase method
Program, erase control method
Protect method
Number of commands
Program/Erase
Endurance(Note1)
ROM code protection
Specification
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
See Figure 17.2.1 to17.2.3 Flash Memory Block Diagram
In units of word
Block erase
Program and erase controlled by software command
All user blocks are write protected by bit FMR16.
In addition, the block 0 and block 1 are write protected by bit FMR02.
5 commands
100 times (U3, U5) 1,000 times (U7, U9)
100 times (U3, U5) 10,000 times (U7, U9)
Parallel I/O and standard serial I/O modes are supported.
Data Retention 20 years (Topr=55°C)
Block 0 to 3 (program area)
Block A and B (data are) (Note2)
Note 1: Program and erase endurance definition
Program and erase endurance are the erase endurance of each block. If the program and erase endurance are
n times (n=100,1,000,10,000), each block can be erased n times. For example, if a 2-Kbyte block A is erased
after writing 1 word data 1024 times, each to different addresses, this is counted as one program and erasure.
However, data cannot be written to the same address more than once without erasing the block. (Rewrite
disabled)
Note 2: To use the limited number of erasure efficiently, write to unused address within the block instead of rewrite.
Erase block only after all possible address are used. For example, an 8-word program can be written 128 times
before erase is necessary. Maintaining an equal number of erasure between Block A and B will also improve
efficiency. We recommend keeping track of the number of times erasure is used.
17. Flash Memory Version
17.1 Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally con-
tains flash memory.
In the flash memory version, the flash memory can perform in three rewrite mode : CPU rewrite mode,
standard serial I/O mode and parallel I/O mode.
Table 17.1 shows the flash memory version specifications. (Refer to “Table 1.1 Performance outline of
M16C/26A group (48-pin device)" for the items not listed in Table 17.1. or “Table 1.2 Performance Outline
of M16C/26A group (42-pin device)”).
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Table 17.2. Flash Memory Rewrite Modes Overview
Flash memory CPU rewrite mode Standard serial I/O mode Parallel I/O mode
rewrite mode
Function
Area which User ROM area User ROM area User ROM area
can be rewritten
Operation Single chip mode Boot mode Parallel I/O mode
mode
ROM None Serial programmer Parallel programmer
programmer
The user ROM area is rewrit-
ten when the CPU executes
software command
EW0 mode:
Rewrite in area other than
flash memory
EW1 mode:
Rewrite in flash memory
The user ROM area is rewrit-
ten using a dedicated serial
programmer.
Standard serial I/O mode 1:
Clock synchronous serial
I/O
Standard serial I/O mode 2:
UART
The user ROM area is rewrit-
ten using a dedicated paral-
lel programmer
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17.2 Memory Map
The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 17.2.1 to
17.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer
operation program in single-chip mode and a separate 2-Kbyte space as the block A and B.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite,
standard serial input/output, and parallel input/output modes. However, if block 0 and 1 are rewritten in
CPU rewrite mode, setting the FMR02 bit in the FMR0 register to “1” (block 0, 1 rewrite enabled) and the
FMR16 bit in the FMR1 register to “1”(blocks 0 to 3 rewrite enabled) enable rewriting. Also, if blocks 2 to 3
are rewritten in CPU rewrite mode, setting the FMR16 bit in the FMR1 register to “1” (blocks 0 to 3 rewrite
enabled) enables writing. Setting the PM10 bit in the PM1 register to “1”(data area access enabled) for
block A and B enables to use.
The boot ROM area is reserved area. This boot ROM area has a standard serial I/O mode control program
stored in it when shipped from the factory. Do not rewrite the boot ROM area.
00FFFF16
Block B :2K bytes (Note 2)
00F00016
4K bytes (Note 4)
0FF00016
0FFFFF16 Boot ROM area
0FE00016
0FC00016
0FDFFF16
0F800016 Block 2 : 16K bytes
0FBFFF16
0F7FFF16
0F000016
0FFFFF16
User ROM area
Block A :2K bytes (Note 2)
Block 2 : 16K bytes (Note 5)
Block 3 : 32K bytes (Note 5)
Block 1 : 8K bytes (Note 3)
Block 0 : 8K bytes (Note 3)
00F7FF16
00F80016
Note 1: To specify a block, use the maximum even address in the block.
Note 2: Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
Note 3: Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
Note 4: The boot ROM area is reserved. Do not access.
Note 5: Blocks 2 and 3 are enabled for programs and erases when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
Figure 17.2.1. Flash Memory Block Diagram (ROM capacity 64K byte)
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00FFFF16
Block B :2K bytes (Note 2)
00F00016
4K bytes (Note 4)
0FF00016
0FFFFF16 Boot ROM area
0FE00016
0FC00016
0FDFFF16
0F800016
0FBFFF16
0F7FFF16
0F400016
0FFFFF16
User ROM area
Block 2 : 16K bytes (Note 5)
Block A :2K bytes (Note 2)
Block 1 : 8K bytes (Note 3)
Block 0 : 8K bytes (Note 3)
Block 3 : 16K bytes (Note 5)
00F7FF16
00F80016
Note 1: To specify a block, use the maximum even address in the block.
Note 2: Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
Note 3: Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
Note 4: The boot ROM area is reserved. Do not access.
Note 5: Blocks 2 and 3 are enabled for programs and erases when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
Figure 17.2.2. Flash Memory Block Diagram (ROM capacity 48K byte)
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00FFFF16
Block B :2K bytes (Note 2)
00F00016
4K bytes (Note 4)
0FF00016
0FFFFF16 Boot ROM area
0FE00016
0FC00016
0FDFFF16
0FA00016
0FBFFF16
0FFFFF16
User ROM area
Block A :2K bytes (Note 2)
Block 2 : 8K bytes (Note 5)
Block 1 : 8K bytes (Note 3)
Block 0 : 8K bytes (Note 3)
00F7FF16
00F80016
Note 1: To specify a block, use the maximum even address in the block.
Note 2: Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
Note 3: Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
Note 4: The boot ROM area is reserved. Do not access.
Note 5: Blocks 2 is enabled for programs and erases when the FMR16
bit in the FMR1 register is set to "1". (CPU rewrite mode only)
Figure 17.2.3. Flash Memory Block Diagram (ROM capacity 24K byte)
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17.3 Functions To Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code
check function for standard input/output mode to prevent the flash memory from reading or rewriting.
17.3.1 ROM Code Protect Function
The ROM code protect function prevents the flash memory from reading and rewriting in parallel input/
output mode. Figure 17.3.1.1 shows the ROMCP register. The ROMCP register is located in the user
ROM area. The ROMCP1 bit consists of two bits. The ROM code protect function is enabled and reading
and rewriting flash memory is disabled when setting either or both of two ROMCP1 bits to “0” other than
the ROMCR bit is ‘002’. However, when setting the ROMCR bit to ‘002’, the flash memory can be read or
rewritten. Once the ROM code protect function is enabled, the ROMCR bits can not be changed in paral-
lel input/output mode. Therefore, use the standard serial input/output or other modes to rewrite the flash
memory.
17.3.2 ID Code Check Function
Use the ID code check function in standard serial input/output mode. Unless the flash memory is blank,
the ID codes sent from the programmer and the seven bytes ID codes written in the flash memory are
compared to see if they match. If the ID codes do not match, the commands sent from the programmer
are not acknowledged. The ID code consists of 8-bit data, starting with the first byte, into addresses,
0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. The flash memory
has a program with the ID code set in these addresses.
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Figure 17.3.1.1. ROMCP Address
Figure 17.3.2.1. Address for ID Code Stored
Symbol Address Factory Setting
ROMCP 0FFFFF
16
FF
16
(Note 4)
ROM code protect control address
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
00: Disables protect
01:
10:
11:
00:
01:
10:
11: Disables protect
ROM code protect reset
bit (Note 2, Note 4)
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
ROMCR
ROMCP1
b5 b4
b7 b6
11
Reserved bit Set this bit to “1”
Reserved bit Set this bit to “1”
Reserved bit Set this bit to “1”
Reserved bit Set this bit to “1”
Enables ROMCP1 bit
}
Enables protect
}
Note 1: When the ROMCR bits are set to other than ‘00
2
’ and the ROMCP1 bits are set to other than
‘11
2
’ (ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: When the ROMCR bits are set to ‘00
2
’, the ROM code protect level 1 is reset. Because the
ROMCR bits can not be modified in parallel input/output mode, modify in standard serial input/
output mode.
Note 3: The ROMCP1 bits are valid when the ROMCR bits are ‘01
2
’, ‘10
2
’ or ‘11
2
’.
Note 4: This bit can not be set to “1” once it is set to “0”. The ROMCP address is set to ‘FF
16
’ when a
block, including the ROMCP address, is erased.
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset vector
Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
DBC vector
NMI vector
0FFFFF
16
to 0FFFFC
16
0FFFFB
16
to 0FFFF8
16
0FFFF7
16
to 0FFFF4
16
0FFFF3
16
to 0FFFF0
16
0FFFEF
16
to 0FFFEC
16
0FFFEB
16
to 0FFFE8
16
0FFFE7
16
to 0FFFE4
16
0FFFE3
16
to 0FFFE0
16
0FFFDF
16
to 0FFFDC
16
4 bytes
Address
ROMCP
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Item EW0 mode EW1 mode (Note 2)
Operation mode Single chip mode Single chip mode
Area where User ROM area User ROM area
rewrite control
program can be placed
Area where The rewrite control program must be The rewrite control program can be
rewrite control transferred to any area other than executed in the user ROM area
program can be the flash memory (e.g., RAM) before
executed being executed
Area which can be User ROM area User ROM area
rewritten However, this excludes blocks
with the rewrite control program
Software command None • Program, block erase command
Restrictions Cannot be executed in a block having
the rewrite control program
• Read status register command
Can not be used
Mode after programming Read Status Register mode Read Array mode
or erasing
CPU state during auto- Operation Hold state (I/O ports retain the state
write and auto-erase before the command is executed
(Note 1)
Flash memory status • Read the FMR00, FMR06 and Read the FMR0 register's FMR00,
detection(Note 2) FMR07 bits in the FMR0 register by FMR06, and FMR07 bits in a program
a program
• Execute the read status register
command and read the SR7, SR5
and SR4 bits
Condition for transferring
Set the FMR40 and FMR41 bits in The FMR40 bit in the FMR4 register
to erase-suspend (Note 3)
the FMR4 register to "1" by program. is set to "1" and the interrupt request of
17.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without using a ROM programmer, etc. Verify the Program and the Block Erase commands are executed
only on blocks in the user ROM area.
For interrupts requested during an erasing operation in CPU rewrite mode, the M16C/26A flash module
offers an erase-suspend function which the erasing operation to be suspended, and access made available
to the flash. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode.
Table 17.4.1 shows the differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes. 1 wait is
required for the CPU erase-write control.
Table 17.4.1. EW0 Mode and EW1 Mode
Note 1: Do not generate a DMA transfer.
Note 2: Block 1 and 0 are enabled to rewrite by setting the FMR02 bit in the FMR0 register to "1" and
setting the FMR16 bit in the FMR1 register to "1". Block 2 to 3 are enabled to rewrite by setting
the FMR16 bit in the FMR1 register to "1".
Note 3: The time, until entering erase suspend and reading flash is enabled, is maximum td (SR-ES)
after satisfying the conditions.
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17.4.1 EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by
setting the FMR11 bit in the FMR1 register to “0”.
When setting the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control pro-
gramming and erasing. The FMR0 register or the status register indicates whether a programming or
erasing operations is completed.
When entering the erase-suspend during the auto-erasing, set the FMR40 bit to “1” (erase-suspend
enabled) and the FMR41 bit to “1” (suspend request). And wait for td(SR-ES). After verifying the FMR46
bit is set to “1” (auto-erase stop), access to the user ROM area. When setting the FMR41 bit to “0” (erase
restart), auto-erasing is restarted.
17.4.2 EW1 Mode
EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (set to “1” after first
writing “0”). The FMR0 register indicates whether or not a programming or an erasing operation is com-
pleted. Do not execute the software commands of read status register in EW1 mode.
When an erase/program operation is initiated the CPU halts all program execution until the operation is
completed or erase-suspend is requested.
When enabling an erase suspend function, set the FMR40 bit to “1” (erase suspend enabled) and ex-
ecute block erase commands. Also, preliminarily set an interrupt to enter the erase-suspend to an inter-
rupt enabled status. After td(SR-ES) from an interrupt request and entering erase suspend, an interrupt
can be acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically set to “1” (suspend request) and
an auto-erasing is halted. If an auto-erasing is not completed (the FMR00 bit is “0”) after an interrupt
process completed, set the FMR41 bit to “0” (erase restart) and execute block erase commands again.
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17.5 Register Description
Figure 17.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 17.5.2
shows the flash memory control register 4.
17.5.1 Flash memory control register 0 (FMR0)
•FMR 00 Bit
This bit indicates the operation status of the flash memory. The bit is “0” during programming, erasing,
or erase-suspend mode; otherwise, the bit is “1”.
•FMR01 Bit
The microcomputer enables to acknowledge commands by setting the FMR01 bit to “1” (CPU rewrite
mode). To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by only
writing “0”.
•FMR02 Bit
The combined setting of the FMR02 bit and the FMR16 bit enable to program and erase in the user
ROM area. See Table 17.5.2.1 for setting details. To set this bit to “1”, it is necessary to set to “1” after
first setting to “0”. Set this bit to “0” by only writing “0”. This bit is enabled only when the FMR01 bit is
“1” (CPU rewrite mode enable).
•FMSTP Bit
This bit resets the flash memory control circuits and minimizes power consumption in the flash
memory. Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit
by a program in a space other than the flash memory.
Set the FMSTP bit to “1” if one of the following occurs:
•A flash memory access error occurs during erasing or programming in EW0 mode (FMR00 bit does not
switch back to “1” (ready)).
•Low-power consumption mode or on-chip oscillator low-power consumption mode is entered.
Figure 17.5.1.3 shows a flow chart illustrating how to start and stop the flash memory before and after
entering low power mode. Follow the procedure on this flow chart.
When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or
wait mode, the flash memory is turned back on. The FMR0 register does not need to be set.
•FMR06 Bit
This is a read-only bit indicating an auto-program operation status. This bit is set to “1” when a pro-
gram error occurs; otherwise, it is set to “0”. For details, refer to 17.8.4 Full Status Check.
•FMR07 Bit
This is a read-only bit indicating an auto-erase operation status. The bit is set to “1” when an erase
error occurs; otherwise, it is set to “0”. For details, refer to 17.8.4 Full Status Check.
Figure 17.5.1.1 shows a EW0 mode set/reset flowchart, figure 17.5.1.2 shows a EW1 mode set/reset
flowchart.
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17.5.2 Flash memory control register 1 (FMR1)
•FMR11 Bit
EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the
FMR01 bit is “1”.
•FMR16 Bit
The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user
ROM area. To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by
only writing “0”. This bit is enabled only when the FMR01 bit is “1”.
•FMR17 Bit
If FMR17 bit is “1” (with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the
access to block A and block B. Regardless of the content of the FMR17 bit, access to other block and
the internal RAM is determined by PM17 bit setting.
Set this bit to “1” (with wait state) when rewriting more than 100 times (Option).
Table 17.5.2.1. Protection using FMR16 and FMR02
FMR16 FMR02 Block A, Block B Block 0, Block 1 other user block
0 0 write enabled write disabled write disabled
0 1 write enabled write disabled write disabled
1 0 write enabled write disabled write enabled
1 1 write enabled write enabled write enabled
17.5.3 Flash memory control register 4 (FMR4)
•FMR40 Bit
The erase-suspend function is enabled by setting the FMR40 bit is set to “1” (enabled).
•FMR41 Bit
When setting the FMR41 bit to “1” in a program during auto-erasing in EW0 mode the flash module
enters erase suspend mode. In EW1 mode, the FMR41 bit is automatically set to “1” (suspend re-
quest) when an interrupt request of an enabled interrupt is generated, the FMR41 bit is automatically
set to “1” (suspend request) and when an auto-erasing operation is restarted, set the FMR41 bit to “0”
(erase restart).
•FMR46 Bit
The FMR46 bit is set to “0” during auto-erasing execution and set to “1” during erase-suspend mode.
Do not access to flash memory while this bit is “0”.
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Note 1: When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an
interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the
P8
5
/NMI/SD pin is “H” when selecting the NMI function. Set by program in a space other than the
flash memory in EW0 mode. Set this bit to read alley mode and “0”
Note 2: Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not
generate an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.
Note 3: Set this bit by a program in a space other than the flash memory.
Note 4: This bit is set to “0” by executing the clear status command.
Note 5: This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to
“1” when the FMR01 bit is set to “0”. However, the flash memory does not enter low-power
consumption status and it is not initialized.
Flash memory control register 0
Symbol Address After reset
FMR0 01B7
16
00000001
2
b7 b6 b5 b4 b3 b2 b1 b0
FMR00
Bit symbol Bit name Function RW
0: Busy (during writing or erasing)
1: Ready
CPU rewrite mode select bit
(Note1) 0: Disables CPU rewrite mode
(Disables software command)
1: Enables CPU rewrite mode
(Enables software commands)
FMR01
Block 0, 1 rewrite enable bit
(Note 2) Set write protection for user ROM area
(see Table 17.5.2.1)
Flash memory stop bit
(Note 3, 5)
FMR02
FMSTP
0
RY/BY status flag
Reserved bit Set to “0”
0: Terminated normally
1: Terminated in error
Program status flagFMR06
0: Terminated normally
1: Terminated in error
Erase status flagFMR07
RW
RW
RW
RW
RO
RO
RO
(b5-b4)
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
0
(Note 4)
(Note 4)
Flash memory control register 1
Symbol Address After reset
FMR1 01B5
16
000XXX0X
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function
EW1 mode select bit (Note1) 0: EW0 mode
1: EW1 mode
FMR11
Block A, B access wait bit (
Note 3)
Reserved bit When read, its content is indeterminate
Reserved bit Set to “0”
Nothing is assigned. When write, set to “0”.
When read, its contect is indeterminate.
RW
RO
RW
RW
RW
(b0)
(b4)
Reserved bit
(b3-b2) RO
Note 1: Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA
transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P85/NMI/SD pin is “H”
when the NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are
both set to “0”
Note 2: Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA
transfer after setting to “0”.
Note 3: When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1”
(with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the
block A and B. Regardless of the content of the FMR17 bit, access to other block and the internal
RAM is determined be PM17 bit setting.
(b5)
FMR16 RW
Block 0 to 3 rewrite enable
bit (Note2)
FMR17
Set write protection for user ROM area
(see Table 17.5.2.1)
0: Disable
1: Enable
0: PM17 enabled
1: With wait state (1 wait)
When read, its content is indeterminate
Figure 17.5.1. FMR0 and FMR1 register
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Flash memory control register 4
Symbol Address After reset
FMR4 01B3
16
01000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol Bit name Function
Erase suspend
request bit (Note 2) 0: Erase restart
1: Suspend request
FMR41
0
Reserved bit Set to “0”
Erase suspend function
enable bit (Note 1) 0: Disabled
1: Enabled
Reserved bit Set to “0”
00
RW
RW
RW
RO
RW
FMR40
(b5-b2)
(b7)
RO
Note 1: When setting this bit to “1”, set to “1” immediately after setting it first to “0”. Do not generate an
interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set by a program in a
space other than the flash memory in EW0 mode.
Note 2: This bit is valid only when the erase-suspend enable bit (FMR40) is “1”. Writing is enabled only
between executing an erase command and completing erase (this bit is set to “1” other than the
above duration). This bit can be set to “0” or “1” by a program in EW0 mode. In EW1 mode, this bit
is automatically set to “1” when the FMR40 bit is “1” and a maskable interrupt is generated during
erasing. Do not write to “1” by a program (writing “0” is enabled).
FMR46
00
Erase status 0: During auto-erase operation
1: Auto-erase stop
(erase suspend mode)
Figure 17.5.2. FMR4 register
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Execute the Read Array command (Note 3)
Single-chip mode
Set CM0, CM1, and PM1 registers (Note 1) Execute software commands
Jump to the rewrite control program transfered to an
internal RAM area (in the following steps, use the
rewrite control program internal RAM area)
Transfer a rewrite control program to internal RAM
area
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Set the FMR01 bit to “1” after writing “0” (
CPU rewrite mode enabled) (Note 2)
EW0 mode operation procedure
Rewrite control program
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16 bits in the
CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
Note 2: Set the FMR01 bit to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA transfer
between setting the bit to “0” and setting it to “1”. Set the FMR01 bit in a space other than the internal flash
memory. Also, set only when the P8
5
/NMI/SD pin is “H” at the time of the NMI function selected.
Note 3: Disables the CPU rewrite mode after executing the read array command.
Figure 17.5.1.1. Setting and Resetting of EW0 Mode
Single-chip mode (Note 1)
Set CM0, CM1, and PM1 registers (Note 2)
Set the FMR01 bit to “1” (CPU rewrite mode
enabled) after writing “0”
Set the FMR11 bit to “1” (EW1 mode) after writing
“0” (Note 3)
Program in ROM
EW1 mode operation procedure
Execute software commands
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
Note 1: In EW1 mode, do not set boot mode.
Note 2: Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16
bits. in the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
Note 3: Set the FMR01 bits to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA
transfer between setting the bit to “0” and setting the bit to “1”. Set the FMR01 bit in a space other
than the internal flash memory. Set only when the P85/NMI/SD pin is “H” at the time of the NMI
function selected.
Figure 17.5.1.2. Setting and Resetting of EW1 Mode
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Figure 17.5.1.3. Processing Before and After Low Power Dissipation Mode
Start main clock
oscillation
Transfer a low power internal consumption mode
program to RAM area
Switch the clock source of CPU clock.
Turn main clock off. (Note 2)
Jump to the low power consumption mode
program transferred to internal RAM area.
(In the following steps, use the low-power
consumption mode program or internal RAM area)
Wait until the flash memory circuit stabilizes (t
PS
)
(Note 3)
Set the FMSTP bit to “0” (flash memory operation)
Set the FMSTP bit to “1” (flash memory stopped.
Low power consumption state)(Note 1)
Process of low power consumption mode or
on-chip oscillator low power consumption mode
switch the clock source of the CPU clock (Note 2)
Low power consumption
mode program
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
Set the FMR01 bit to “1” after setting “0” (
CPU rewrite mode enabled)
Jump to a desired address in the flash memory
wait until oscillation stabilizes
Note 1: Set the FMRSTP bit to “1” after setting the FMR01 bit to “1”(CPU rewrite mode).
Note 2: Wait until the clock stabilizes to switch the clock source of the CPU clock to the main clock or the sub clock.
Note 3: Add a t
PS
wait time by a program. Do not access the flash memory during this wait time.
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17.6 Precautions in CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
17.6.1 Operation Speed
When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode),
select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16
bits in the CM1 register. Also, when selecting f3(ROC) of a on-chip oscillator as a CPU clock source,
before entering CPU rewrite mode (EW0 or EW1 mode), the ROCR3 to ROCR2 bits in the ROCR
register set the CPU clock division rate to “divide-by-4” or “divide-by-8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
17.6.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the
flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK in-
struction
17.6.3 Interrupts
EW0 Mode
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the
RAM area.
_______
• The NMI and watchdog timer interrupts can be used since the FMR0 and FMR1 registers are
forcibly reset when either interrupt is generated. However, the jump addresses for each interrupt
service routines to the fixed vector table are set and interrupt programs are required. Flash
memory rewrite operation is halted when the NMI or watchdog timer interrupt is generated. Set the
FMR01 bit to “1” and execute the rewrite and erase program again after exiting the interrupt rou-
tine.
• The address match interrupt can not be used since the CPU tries to read data in the flash memory.
EW1 Mode
• Do not acknowledge any interrupts with vectors in the relocatable vector table or the address
match interrupt during the auto-program or erase-suspend function.
17.6.4 How to Access
To set the FMR01, FMR02, FMR11 or FMR16 bit to “1”, write “1” after first setting the bit to “0”. Do not
generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction
_______
to set it to “1”. When the NMI function is selected, set the bit while an “H” signal is applied to the P85/
_______ _____
NMI/SD pin.
17.6.5 Writing in the User ROM Space
17.6.5.1 EW0 Mode
• If the supply voltage drops while rewriting the block where the rewrite control program is stored,
the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit-
ten. If this error occurs, rewrite the user ROM area in standard serial I/O mode or parallel I/O
mode.
17.6.5.2 EW1 Mode
• Do not rewrite the block where the rewrite control program is stored.
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17.6.6 DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”.
(the auto-programming or auto-erasing duration ).
17.6.7 Writing Command and Data
Write the command code and data to even addresses in the user ROM area.
17.6.8 Wait Mode
When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the
WAIT instruction.
17.6.9 Stop Mode
When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable the DMA
transfer before setting the CM10 bit to “1” (stop mode).
17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consump-
tion Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands.
• Program
• Block erase
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17.7 Software Commands
Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing
a command code, 8 high-order bits (D15–D8) are ignored.
Table 17.7.1. Software Commands
17.7.1 Read Array Command (FF16)
This command reads the flash memory.
By writing command code ‘xxFF16’ in the first bus cycle, read array mode is entered. Content of a
specified address can be read in 16-bit unit after the next bus cycle. The microcomputer remains in
read array mode until an another command is written. Therefore, contents of multiple addresses can
be read consecutively.
17.7.2 Read Status Register Command (7016)
This command reads the status register.
By writing command code ‘xx7016’ in the first bus cycle, the status register can be read in the second
bus cycle (Refer to 17.8 Status Register). Read an even address in the user ROM area. Do not
execute this command in EW1 mode.
Command
Program
Clear status register
Read array
Read status register
First bus cycle Second bus cycle
Block erase
Write
Write
Write
Write
Write
Mode
Read
Write
Write
Mode
X
WA
BA
Address
SRD
WD
xxD016
Data
(D15 to D0)
xxFF16
xx7016
xx5016
xx4016
xx2016
Data
(D15 to D0)
X
X
X
WA
X
Address
SRD: Status register data (D7 to D0)
WA : Write address (However,even address)
WD : Write data (16 bits)
BA : Highest-order block address (However,even address)
X : Any even address in the user ROM area
xx : 8 high-order bits of command code (ignored)
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Start
Program
completed
YES
NO
Note 1: Write the command code and data at even address.
Note 2: Refer to "Figure 17.8.4.1. Full Status Check and
Handling Procedure for Each Error"
Write command code ‘xx40
16
’ to
the write address (Note 1)
Write data to the write address
(Note 1)
FMR00=1?
Full status check
(Note 2)
Figure 17.7.4.1. Flow Chart of Program Command
17.7.3 Clear Status Register Command (5016)
This command clears the status register to “0”.
By writing ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4
to SR5 bits in the status register are set to “0”.
17.7.4 Program Command (4016)
The program command writes 2-byte data to the flash memory. By writing ‘xx4016’ in the first bus cycle
and data to the write address specified in the second bus cycle, the auto-programming/erasing (data
prorgramming and verify) start. Set the address value specified in the first bus cycle to same and even
address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register
indicates whether an auto-programming operation has been completed. The FMR00 bit is set to “0”
during the auto-programming and “1” when the auto-programming operation is completed. After the
auto-programming operation is completed, the FMR06 bit in the FMR0 register indicates whether or
not the auto-programming operation has been completed as expected. (Refer to 17.8.4 Full Status
Check). Also, each block disables writing (Refer to “Table 17.5.2.1”). Do not write additions to the
address which is already programmed. When commands other than a program command are ex-
ecuted immediately after a program command, set the same address as the write address specified in
the second bus cycle of the program command, to the specified address value in the first bus cycle of
the following command. In EW1 mode, do not execute this command on the blocks where the rewrite
control program is allocated. In EW0 mode, the microcomputer enters read status register mode as
soon as the auto-programming operation starts and the status register can be read. The SR7 bit in the
status register is set to “0” as soon as the auto-programming operation starts. This bit is set to “1”
when the auto-programming operation is completed. The microcomputer remains in read status regis-
ter mode until the read array command is written. After completion of the auto-programming operation,
the status register indicates whether or not the auto-programming operation has been completed as
expected.
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Note 1: Write the command code and data at even address.
Note 2: Refer to "Figure 17.8.4.1. Full Status Check and Handling Porcedure
for Each Error".
Note 3: Execute the clear status register command and block erase
command at least 3 times until an erase error is not generated when
an erase error is generated.
Write ‘xxD0
16
’ to the highest-order
block address (Note 1)
Start
Block erase completed
YES
NO
Write command code ‘xx20
16
’
(Note 1)
FMR00=1?
Full status check
(Note 2,3)
Figure 17.7.5.1. Flow Chart of Block Erase Command (when not using erase suspend function)
17.7.5 Block Erase
By writing ‘xx2016’ in the first bus cycle and ‘xxD016’ in the second bus cycle to the highest-order (even
addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit
in the FMR0 register indicates whether the auto-programming operation has been completed. The
FMR00 bit is set to “0” during the auto-erasing operation and “1” when the auto-erasing operation is
completed. When using the erase-suspend function in EW0 mode, the FMR46 bit in the FMR4 register
indicates whether a flash memory has entered erase-suspend mode. The FMR46 bit is set to “0”
during auto-erasing operation and “1” when the auto-erasing operation is completed (entering erase-
suspend). After the completion of an auto-erasing operation, the FMR07 bit in the FMR0 register
indicates whether or not the auto erasing-operation has been completed as expected. (Refer to 17.8.4
Full Status Check). Also, each block disables erasing. (Refer to “Table 17.5.2.1”). Figure 17.7.5.1
shows a flow chart of the block erase command programming when not using the erase-suspend
function. Figure 17.7.5.2 shows a flow chart of the block erase command programming when using an
erase-suspend function. In EW1 mode, do not execute this command on the block where the rewrite
control program is allocated. In EW0 mode, the microcomputer enters read status register mode as
soon as the auto-erasing operation starts and the status register can be read. The SR7 bit in the status
register is set to “0” as soon as the auto-erasing operation starts. This bit is set to “1” when the auto-
erasing operation is completed. The microcomputer remains in read status register mode until the
read array command is written. Also excute the clear status register command and block erase com-
mand at least 3 times until an erase error is not generated when an erase error is generated.
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Note 1: Write the command code and data to even address.
Note 2: Execute the clear status register command and block erase
command at least 3 times until an erase error is not generated when
an erase error is generated.
Note 3: In EW0 mode, allocate an interrupt vector table of an interrupt, to be
used, to a RAM area
Note 4: Refer to "Figure 17.8.4.1. Full Status Check and Handling Porcedure
for Each Error".
Start
Block erase completed
Write the command code ‘xx2016’
(Note 1)
Write ‘xxD016’ to the highest-order
block address (Note 1)
YES
NO
FMR00=1?
Full status check
(Note 2,4)
FMR40=1
Interrupt service routine
(Note 3)
FMR41=1
YES
NO
FMR46=1?
Access Flash Memory
Return
(Interrupt service routine end)
FMR41=0
(EW0 mode)
(EW1 mode)
Start
Block erase completed
Write the command code ‘xx2016’
(Note 1)
Write ‘xxD016’ to the highest-order
block address (Note 1)
YES
NO
FMR00=1?
Full status check
(Note 2,4)
FMR40=1
FMR41=0
Interrupt service routine
(Note 3)
Access Flash Memory
Return
(Interrupt service routine end)
Figure 17.7.5.2. Block Erase Command (at use erase suspend)
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Bits in the
SRD register
SR4 (D
4
)
SR5 (D
5
)
SR7 (D
7
)
SR6 (D
6
)
Status name Contents
SR1 (D
1
)
SR2 (D
2
)
SR3 (D
3
)
SR0 (D
0
)
Program status
Erase status
Sequence status
Reserved
Reserved
Reserved
Reserved
"1"
Ready
Terminated by error
Terminated by error
-
-
-
-
-
"0"
Busy
Completed normally
Completed normally
-
-
-
-
-
Reserved
Bits in the
FMR0
register
FMR00
FMR07
FMR06
Value
after
reset
1
0
0
Table 17.8.1. Status Register
17.8 Status Register
The status register indicates the operating status of the flash memory and whether an erasing or a pro-
gramming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0
register indicate the status of the status register.
Table 17.8.1 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the read status register
command
(2) When a given even address in the user ROM area is read after executing the program or block
erase command but before executing the read a rray command.
17.8.1 Sequence Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. This bit is set to “0” (busy)
during an auto-programming and auto-erasing and “1” (ready) as soon as these operations are com-
pleted. This bit indicates “0” (busy) in erase-suspend mode.
17.8.2 Erase Status (SR5 and FMR07 Bits)
Refer to 17.8.4 Full Status Check.
17.8.3 Program Status (SR4 and FMR06 Bits)
Refer to 17.8.4 Full Status Check.
• D7 to D0: Indicates the data bus which is read out when executing the read status register command.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is 1, the program, and block erase command are not
acknowledged.
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17.8.4 Full Status Check
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur-
rence of each specific error. Therefore, execution results can be verified by checking these status bits
(full status check). Table 17.8.4.1 shows errors and the status of FMR0 register. Figure 17.8.4.1
shows a flow chart of the full status check and handling procedure for each error.
Table 17.8.4.1. Errors and FMR0 Register Status
FMR00 register
(SRD register)
status Error Error occurrence condition
FMR07 FMR06
(SR5) (SR4)
1 1 Command • When any commands are not written correctly
sequence error • A value other than ‘xxD016’ or ‘xxFF16’ is written in the second
bus cycle of the block erase command (Note 1)
• When the block erase command is executed on protected blocks
• When the program command is executed on protected blocks
1 0 Erase error • When the block erase command is executed on unprotected
blocks but the blocks are not automatically erased correctly
0 1 Program error • When the program command is executed on unprotected blocks
but the blocks are not automatically programmed correctly.
Note 1: The flash memory enters read array mode by writing command code ‘xxFF16’ in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
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Full status check
FMR06 =1
and
FMR07=1?
NO
Command
sequence error
YES
FMR07=
0?
YES
Erase error
NO
(1) Execute the clear status register command and set
the status flag to “0” whether the command is
entered.
(2) Reexecute the command after checking that it is
entered correctly or the program command or the
block erase command is not executed for the
blocks which are protected.
(1) Execute the clear status register command and set
the erase status flag to “0”.
(2) Reexecute the block erase command.
(3) Execute (1) and (2) at least 3 times until an erase
error is not generated.
Note 4: If the FMR06 or FMR07 bits is “1”, any of the Program or Block Erase command can not
be aknowledged. Execute the clear status register command before executing those
commands.
FMR06=
0?
YES
Program error
NO
Full status check completed
Note 1: If the error still occurs, the block can not be
used.
(1) Execute the clear status register command and set
the program status flag to “0”.
(2) Reexecute the Program command.
Note 2: If the error still occurs, the block can not be
used.
[During programming]
Figure 17.8.4.1. Full Status Check and Handling Procedure for Each Error
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17.9 Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer which is applicable for the M16C/26A group. For more
information about serial programmers, contact the manufacturer of your serial programmer. For details on
how to use the serial programmer, refer to the user’s manual included with your serial programmer.
Table 17.9.1 shows pin functions (flash memory standard serial input/output mode). Figures 17.9.1 and
17.9.2 show pin connections for standard serial input/output mode.
17.9.1 ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to 17.3 Functions To Prevent Flash Memory from Rewriting.)
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Pin Description
V
CC
,V
SS
Apply the voltage guaranteed for Program and Erase to Vcc pin and 0
V to Vss pin.
CNV
SS
Connect to Vcc pin.
RESET
X
IN
Connect a ceramic resonator or crystal oscillator between X
IN
and
X
OUT
pins. To input an externally generated clock, input it to X
IN
pin
and open X
OUT
pin.
X
OUT
AV
CC
, AV
SS
V
REF
Connect AVss to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for AD from this pin.
P1
5
, P1
7
Input "H" or "L" level signal or open.
P6
0
to P6
3
Input "H" or "L" level signal or open.
P6
4
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitor signal output pin for boot program
operation check
P6
5
P6
6
Serial data input pin
P6
7
Serial data output pin
P7
0
to P7
7
Input "H" or "L" level signal or open.
P8
0
to P8
4
,
P8
7
Input "H" or "L" level signal or open.
P9
0
to P9
3
,Input "H" or "L" level signal or open.
P10
0
to P10
7
Input "H" or "L" level signal or open.
Name
Power input
CNV
SS
Reset input
Clock input
Clock output
Analog power supply input
Reference voltage input
Input port P1
Input port P6
BUSY output
SCLK input
RxD input
TxD output
Input port P7
Input port P8
Input port P9
Input port P10
I/O
I
I
I
O
I
I
I
O
I
I
O
I
I
I
I
P8
5
RP input I Connect this pin to Vss while RESET is low. (Note 2)
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
Reset input pin. While RESET pin is "L" level, wait for td(ROC).
(Note 1)
P8
6
CE input I Connect this pin to Vcc while RESET is low. (Note 2)
P1
6
P1
6
input Connect this pin to Vcc while RESET is low. (Note 2)
I
Table 17.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode)
Note 1: When using standard serial input/output mode 1, to input “H” to the TxD pin is necessary while the
___________
RESET pin is “L”. Therefore, connect this pin to VCC via a resistor. Adjust the pull-up resistor value
on a system not to affect a data transfer after reset, because this pin changes to a data-output pin
Note 2: Set following either or both
_____
•Connect the CE pin to VCC.
_____
•Connect the RP pin to VSS and the P16 pin to VCC.
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Figure 17.9.1. Pin Connections for Serial I/O Mode (1)
M16C/26A Group
(Flash memory version)
31
32
33
34
35
36
37
38
39
40
41
42
12
11
10
9
8
7
6
5
4
3
2
1
16
15
14
13
27
28
29
30
BUSY SCLK
RxD TxD
Vcc
Vss
RESET
Connect
oscillator
circuit
Mode setup method
Signal
CNVss
Reset
Value
Vcc
Vss to Vcc
Package: 42P2R
CE
Note
RP
Note
17
21
20
19
18
26
22
23
24
25
Note: Set following either or both in serial I/O mode while the RESET pin is held L .
⋅ Connect the CE pin to VCC.
⋅ Connect the RP pin to VSS and the P16 pin to VCC.
P1
6
Note
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Figure 17.9.2. Pin Connections for Serial I/O Mode (2)
M16C/26A Group
(Flash memory version)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
Mode setup method
Signal
CNVss
Reset
Value
Vcc
Vss to Vcc
Package: 48P6Q-A
BUSY SCLK
RxD TxD
Connect
oscillator
circuit
Vcc
Vss
RESET
CE
Note
RP
Note
P1
6
Note
Note: Set following either or both in serial I/O mode while the RESET pin is held L .
⋅ Connect the CE pin to V
CC
.
⋅ Connect the RP pin to V
SS
and the P16 pin to V
CC
.
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17.9.2 Example of Circuit Application in Standard Serial I/O Mode
Figure 17.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure
17.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's
manual for a serial writer to handle pins controlled by the serial writer.
Figure 17.9.2.1. Circuit Application in Standard Serial I/O Mode 1
SCLK input
BUSY output
TxD output
RxD input
BUSY
SCLK
TXD
CNVss
P86(CE)
RESET
RxD
Reset input
User reset
singnal
Microcomputer
(1) Controlling pins and external circuits vary with the serial programmer. For more
information, refer to the user's manual included with the serial programmer.
(2) In this example, a selector controls the input voltage applied to CNVss to switch
between single-chip mode and standard serial I/O mode.
(3) In standard serial input/output mode 1, if the user reset signal becomes “L” while
the microcomputer is communicating with the serial programmer, break the
connection between the user reset signal and the RESET pin using a jumper
switch.
P85(RP)
(Note 1)
(Note 1)
Note 1. Set following either or both
• Connect the CE pin to VCC
• Connect the RP pin to VSS and the P16 pin to VCC
P16
(Note 1)
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Monitor output
RxD input
TxD output
BUSY
SCLK
TxD
CNVss
P8
6
(CE)
RxD
Microcomputer
(1) In this example, a selector controls the input voltage applied to CNVss to switch
between single-chip mode and standard serial I/O mode.
P8
5
(RP)
(Note 1)
(Note 1)
Note 1. Set following either or both
• Connect the CE pin to V
CC
• Connect the RP pin to V
SS
and the P1
6
pin to V
CC
P1
6
(Note 1)
Figure 17.9.2.2. Circuit Application in Standard Serial I/o Mode 2
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17.10 Parallel I/O Mode
In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is appli-
cable for the M16C/26A group. For more information about the parallel programmer, contact your parallel
programmer manufacturer. For details on how to use the parallel programmer, refer to the user’s manual of
the parallel programmer.
17.10.1 ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read or rewritten. (Refer to 17.3
Function to Prevent Flash Memory from Rewriting.)
18. Electrical Characteristics (M16C/26A)
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18. Electrical Characteristics
Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor
for electrical characteristics of V-ver.
18.1. Normal version
Table 18.1. Absolute Maximum Ratings
O
p
e
r
a
t
i
n
g
a
m
b
i
e
n
t
t
e
m
p
e
r
a
t
u
r
e
P
a
r
a
m
e
t
e
rU
n
i
t
I
n
p
u
t
v
o
l
t
a
g
e
Analog supply voltage
S
u
p
p
l
y
v
o
l
t
a
g
e
O
u
t
p
u
t
v
o
l
t
a
g
e
V
O
-
0
.
3
t
o
V
C
C
+
0
.
3
-
0
.
3
t
o
V
C
C
+
0
.
3
P
d
P
o
w
e
r
d
i
s
s
i
p
a
t
i
o
n
Storage temperature
R
a
t
e
d
v
a
l
u
e
V
V
V
C
o
n
d
i
t
i
o
n
V
I
AV
CC
V
C
C
T
stg
T
o
p
r
S
y
m
b
o
l
m
W
V
P
1
5
t
o
P
1
7
,
P
6
0
t
o
P
6
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
3
,
P
1
0
0
t
o
P
1
0
7
,
X
I
N
,
V
R
E
F
,
R
E
S
E
T
,
C
N
V
S
S
V
C
C
=
A
V
C
C
V
CC
=AV
CC
-0.3 to 6.5
-0.3 to 6.5
-65 to 15 0
3
0
0
-
2
0
t
o
8
5
/
-
4
0
t
o
8
5
-40 C
Topr
85 C
C
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
P8
0
to P8
7
, P9
0
to P9
3
, P10
0
to P10
7
,
X
OUT
When the Microcomputer is Operating
F
l
a
s
h
P
r
o
g
r
a
m
E
r
a
s
e0
t
o
6
0
<
=<
=
Program Area
(Block 0 to Block 3)
P
r
o
g
r
a
m
A
r
e
a
(
B
l
o
c
k
A
,
B
l
o
c
k
B
)
C
C
C
-20 to 85 / -40 to 85
18. Electrical Characteristics (M16C/26A)
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Table 18.2.
Recommended Operating Conditions (Note 1)
2.7 5.5
Typ. Max. UnitParameter
V
CC
Supply voltage
Symbol Min. Standard
Analog supply voltage V
CC
AVcc V
V0
0
Analog supply voltage
Supply voltage
V
IH
I
OH (avg)
HIGH average
output current
mA
mA
Vss
AVss
0.7V
CC
V
V
V
V
CC
0.3V
CC
0
LOW input
voltage
I
OH (peak)
HIGH peak output
current
HIGH input
voltage
-5.0
-10.0
LOW peak output
current 10.0
5.0
mA
f
(X
IN
)Main clock input oscillation frequency
(Note 3)
LOW average
output current
I
OL (peak)
mA
I
OL (avg)
V
V
IL
33 X V
CC
-80
V
CC
=3.0 to 5.5V
V
CC
=2.7 to 3.0V 0
0MHz
MHz
20
f
(X
CIN
) Sub-clock oscillation frequency kHz
50
32.768
Note 1: Referenced to VCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage are followed.
Note 4: The total IOL(peak) for all ports must be 80mA max. The total IOH(peak) for all ports must be -80mA max.
f
1
(ROC) On-chip oscillation frequency 1 MHz1
f
(PLL) PLL clock oscillation frequency (Note 3) V
CC
=3.0 to 5.5V
V
CC
=2.7 to 3.0V
10
10
MHz
MHz
f
(BCLK) CPU operation clock 0MHz
20
T
SU
(PLL) PLL frequency synthesizer stabilization wait time V
CC
=5.0V
V
CC
=3.0V 50
20 ms
ms
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
f
2
(ROC) On-chip oscillation frequency 2
f
3
(ROC) On-chip oscillation frequency 3 MHz2MHz16
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
,
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
,
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
33 X V
CC
-80
20
0.5
1
8
2
4
26
X
IN
, RESET, CNV
SS
V
IH
HIGH input
voltage
LOW input
voltage
V
IL
X
IN
, RESET, CNV
SS
0.8V
CC
VV
CC
V
0.2V
CC
0
Main clock input oscillation frequency
20.0
0.0
f(X
IN
) operating maximum
frequency
[MH
Z
]
V
CC
[V] (main clock: no division) 5.53.0
10.0
2.7
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
33.3 x V
CC
-80MH
Z
PLL clock oscillation frequency
0.0
f(PLL) operating maximum
frequency
[MH
Z
]
V
CC
[V] (PLL clock oscillation) 5.5
10.0
2.7
AAAAAAA
AAAAAAA
AAAAAAA
3.0
33.3 x V
CC
-80MH
Z
20.0
18. Electrical Characteristics (M16C/26A)
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Table 18.3. A /D Conversion Characteristics (Note 1)
Standard
Min. Typ. Max.
–
INL
Resolution
Integral non-
linearity
error
Bits
V
REF
=V
CC
10
Symbol Parameter Measuring condition Unit
LSB
±3
LSB
V
REF
=V
CC
=3.3V, 5V
8 bit ±2
R
LADDER
t
CONV
Ladder resistance
Conversion time(10bit),
Sample & hold function available
Reference voltage
Analog input voltage
kΩ
µs
V
V
IA
V
REF
V
0
2.0
10
V
CC
V
REF
40
3.3
Conversion time(8bit),
Sample & hold function available µs
2.8
t
CONV
V
REF
=V
CC
V
REF
=V
CC
=5V, ø
AD
=10MHz
V
REF
=V
CC
=5V, ø
AD
=10MHz
DNL Differential non- linearity error
Offset error
Gain error
–
–
LSB
LSB
LSB
±1
±3
±3
10 bit LSB
±5
LSB±3
LSB
V
REF
=V
CC
=3.3V, 5V
8 bit ±2 LSB
±5
–
Absolute
accuracy
V
REF
=V
CC
=3.3V
V
REF
=V
CC
=5V
10 bit V
REF
=V
CC
=3.3V
V
REF
=V
CC
=5V
Note 1: Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC is less than 4.2V,
and make ØAD frequency equal to or lower than fAD/2.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 2. A case
with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 2.
Note 4: In a case with sample & hold function, the sampling time is 3ØAD. In a case without sample & hold function, the sampling
time is 2ØAD.
18. Electrical Characteristics (M16C/26A)
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Table 18.4.
Flash Memory Version Electrical Characteristic (Note 1): Program Area for U3 and U5, Data Area for U7 and U9
Word program time (Vcc=5.0V, Topr=25°C)
Block erase time 75
0.2
600
9µs
s
Parameter Standard
Min. Typ.
(Note 2) Max Unit
Symbol
–
–
0.4 9 s
0.7 9s
1.2 9s
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
–Erase/Write cycle (Note 3) cycle
td(SR-ES)
–
Time delay from Suspend Request until Erase Suspend
Data retention time (Note 5)
ms
year
8
20
Word program time (Vcc=5.0V, Topr=25°C)
Block erase time(Vcc=5.0V, Topr=25°C) 100 µs
Parameter Standard
Min. Typ.
(Note 2) Max Unit
Symbol
–
–
0.3 s
(2Kbyte block)
–Erase/Write cycle (Note 3, 8, 9) 10000 (Note 4, 10) cycle
td(SR-ES) Time delay from Suspend Request until Erase Suspend ms8
t
PS
Flash Memory Circuit Stabilization Wait Time µs
15
–Data retention time (Note 5) year
20
t
PS
Flash Memory Circuit Stabilization Wait Time µs
15
100/1000 (Note 4, 11)
Table 18.5.
Flash Memory Version Electrical Characteristics (Note 6): Data Area for U7 and U9 (Note 7)
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
Note 1: When not otherwise specified, Vcc = 2.7 to5.5V; Topr = 0 to 60 °C.
Note 2: VCC = 5V; Topr = 25 °C.
Note 3: Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000, 10,000),
each block can be erased n times. For example, if a 2Kbytes block A is erased after writing 1 word data 1,024 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited)
Note 4: Maximum number of E/W cycles for which opration is guaranteed.
Note 5: Topr = 55°C.
Note 6: When not otherwise specified, Vcc = 2.7 to 5.5V; Topr = -20 to 85°C / -40 to 85°C (Option).
Note 7: Table18.5 applies for Block A or B E/W cycles > 1000. Otherwise, use Table 18.4.
Note 8: To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to unused word addresses within the
block
instead of rewrite. Erase block only after all possible addresses are used. For example, an 8-word program can be written 256 times maximum before erase
becomes necessary. Maintaining an equal number of erasure between block A and block B will also improve efficiency. It is important to track the total number
of times erasure is used.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error
disappears.
Note 10: When Block A or B E/W cycles exceed 100, select one wait state per block access. When FMR17 is set to "1", one wait state is inserted per access to Block A
or B - regardless of the value of PM17. Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless of
the setting of FMR17.
Note 11: The program area and the data area for U3 and U5 are 100 E/W cycles; the program area for U7 and U9 is 1,000 E/W cycles.
Note 12: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
18. Electrical Characteristics (M16C/26A)
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Table 18.6.
Voltage Detection Circuit Electrical Characteristics (Note 1, Note 3
)
Table 18.7.
Power Supply Circuit Timing Characteristics
Symbol Standard
Typ. Unit
Measuring condition Min. Max.
Parameter
Vdet4 Voltage down detection voltage (Note 1) V
V
CC
=1.7 to 5.5V
Note 1: Vdet4 > Vdet3
Note 2: Vdet3s is the min voltage at which "hardware reset 2" is maintained.
Note 3: The voltage detection circuit is designed to use when VCC is set to 5V.
Note 4: When reset level detection voltage is 2.7V or below, operating with f(BCLK) 10MHz is guaranteed if the supply voltage is over the reset
level detection voltage excluding A/D conversion accuracy, serial I/O and flash memory program and erase.
3.2
Vdet3 Reset level detection voltage (Notes 1, Note 3) V
V
Symbol Standard
Typ. Unit
Measuring condition Min. Max.
Parameter
2
V
CC
=2.7 to 5.5V
Note 1: When V
CC
= 5V
150
6 (Note 1)
td(R-S) STOP release time
20
20
td(S-R) Hardware reset 2 release wait time
µs
ms
Vdet3s Low voltage reset retention voltage (Note 2)
Vdet3r Low voltage reset release voltage V
td(P-R) Time for internal power supply stabilization during powering-on
td(E-A) Ｖoltage detection circuit operation start time
ms
V
CC
=2.7 to 5.5V
V
CC
=Vdet3r to 5.5V
td(W-S) Low power dissipation mode wait mode release time 150 µs
3.8 4.45
td(ROC) Time for internal on-chip oscillator stabilization during powering-on 40
2.3 2.8 3.4
1.7
2.35 2.9 3.5
µs
µs
<
=
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
CPU clock
t
d(R-S)
(a)
(b) t
d(W-S)
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
t
d(S-R)
Vdet3r
V
CC
CPU clock
VC26, VC27
t
d(E-A)
Stop Operate
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
td(S-R)
Voltage Down Detection
Reset (Hardware Reset 2)
Release Wait Time
td(E-A)
Voltage Detection Circuit
Operation Start Time
Voltage Detection Circuit
ROC
RESET
VCC
td(ROC)td(P-R)
td(ROC)
Time for Internal On-chip
Oscillator Stabilization During
Powering-On
18. Electrical Characteristics (M16C/26A)
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Table 18.8.
Electrical Characteristics (Note 1
)
Symbol
V
OH
V
OH
HIGH output voltage
V
OH
V
OL
LOW output
voltage
LOW output
voltage
V
OL
V
OL
HIGH output
voltage
HIGH output
voltage
Standard
Typ. Unit
Measuring condition
V
V
V
X
OUT
V2.0
0.45 V
V
X
OUT
2.0
2.0
Min. Max.
Parameter
I
OH
=-1mA
I
OH
=-0.5mA
I
OL
=1mA
I
OL
=0.5mA
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
HIGH output voltage X
COUT
With no load applied
With no load applied 2.5
1.6 V
Hysteresis
Hysteresis
HIGH input
current
I
IH
LOW input
current
I
IL
V
RAM
RAM retention voltage
V
T+-
V
T-
V
T+-
V
T-
CLK
0
to CLK
2
,TA2
OUT
to TA4
OUT
,0.2 1.0 V
0.2 2.5 V
5.0 µA
µA
At stop mode 2.0 V
RESET
TA0
IN
to TA4
IN
, TB0
IN
to TB2
IN
,
AD
TRG
, CTS
0
to CTS
2
,
V
I
=5V
V
I
=0V -5.0
R
fXIN
R
fXCIN
Feedback resistance X
IN
Feedback resistance X
CIN
15
1.5 MΩ
MΩ
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7,
X
IN
, RESET, CNVss
R
PULLUP
Pull-up
resistance 50 kΩ
INT
0
to INT
5
, NMI,
V
X
COUT
0
0
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
V
I
=0V 30 170
KI
0
to KI
3
, RxD
0
to RxD
2
,
V
CC
-2.0
V
CC
-2.0
Note 1: Re
f
erenced to VCC 4 2 to 5 5V VSS 0V at Topr 20 to 85
°
C/ 40to85
°
C
f
(BCLK) 20MHz unless otherwise speci
f
ied
I
OH
=-5mA
I
OH
=-200µA
V
CC
-2.0
V
CC
-0.3
V
CC
V
CC
V
CC
V
CC
I
OL
=5mA
I
OL
=200µA
LOW output voltage
LOW output voltage
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7,
X
IN
, RESET, CNVss
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
Hysteresis
V
T+-
V
T-
0.2 0.8 V
X
IN
VCC = 5V
Note 1:
Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -20 to 85
°
C / -40 to 85
°
C, f(BCLK)=20MHz unless otherwise specified.
18. Electrical Characteristics (M16C/26A)
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VCC = 5V
Table 18.9.
Electrical Characteristics (2) (Note 1
)
S
y
m
b
o
lStandard
T
y
p
.U
n
i
t
Measuring condition M
i
n
.M
a
x
.
P
a
r
a
m
e
t
e
r
I
C
C
P
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
(
V
C
C
=
4
.
0
t
o
5
.
5
V
)
T
h
e
o
u
t
p
u
t
p
i
n
s
a
r
e
o
p
e
n
a
n
d
o
t
h
e
r
p
i
n
s
a
r
e
V
S
S
M
a
i
n
c
l
o
c
k
,
n
o
d
i
v
i
s
i
o
nmA1
6
f(BCLK)=20MHz,
F
l
a
s
h
m
e
m
o
r
y
mA
F
l
a
s
h
m
e
m
o
r
y
P
r
o
g
r
a
mV
CC
=5.0V
f(BCLK)=10MHz,
mA
F
l
a
s
h
m
e
m
o
r
y
E
r
a
s
eV
CC
=5.0V
f(BCLK)=10MHz,
T
opr
=25°C3µ
A
Stop mode,
f
(
B
C
L
K
)=3
2
k
H
z
,
Wait mode (Note 2),
Oscilla tion ca pa c ity High µ
A
0
.
8
µ
A
M
a
s
k
R
O
M
o
r
F
l
a
s
h
m
e
m
o
r
y
Note 1: Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(X
IN
)=20MHz unless otherwise specified.
Note 2: With one timer operated using f
C32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Note 5: With one timer operated.
mA
f(BCLK)=1MHz, Wait mode(Note 5) µA
Low power dissipation mode,
RAM(Note 3)
f
(
B
C
L
K
)
=
3
2
k
H
zµA
Low power dissipation mode,
Flash memory(Note 3)
f(BCLK)=32kHz, µA
F
l
a
s
h
m
e
m
o
r
y
On-chip oscillation, f2(ROC),
f(BCLK)=32kHz,
Wait mode(Note 2),
Oscilla tion ca pa c ity Low
I
d
e
t
4V
o
l
t
a
g
e
d
o
w
n
d
e
t
e
c
t
i
o
n
d
i
s
s
i
p
a
t
i
o
n
c
u
r
r
e
n
t
(
N
o
t
e
4
)
µA
I
d
e
t
3R
e
s
e
t
a
r
e
a
d
e
t
e
c
t
i
o
n
d
i
s
s
i
p
a
t
i
o
n
c
u
r
r
e
n
t
(
N
o
t
e
4
)
µA
On-chip oscillation
f2 (ROC) selected, f(B CLK) =1MH z
1
9
1
1
1
1
2
2
5
4
5
0
5
0
1
0
3
0
.
74
8
1.2
M
a
i
n
c
l
o
c
k
,
n
o
d
i
v
i
s
i
o
n
f(BCLK)=20MHz,
M
as
k
ROM
On-chip oscillation
f2 (ROC) s elected, f(B CLK)=1MH z
mA1
2
mA
1
7
1
.
5
Low power dissipation mode,
ROM(Note 3)
f(BCLK)=32kHz, µA
2
5
M
as
k
ROM
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
i
o
n
f2
(
R
O
C
)
s
e
l
e
c
t
e
d
,
f
(
B
C
L
K
)
=
1
M
H
z
i
n
w
a
i
t
m
o
d
e
(
N
o
t
e
5
)µ
A
3
0
18. Electrical Characteristics (M16C/26A)
page 263
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VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Table 18.10. External Clock Input (XIN input)
Max.
External clock rise time ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
50
20
20 9
9
18. Electrical Characteristics (M16C/26A)
page 264
823fo5002,51.raM00.1.veR 0010-2020B90JER
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VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Table 18.12. Timer A Input (Gating Input in Timer Mode)
Table 18.13. Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 18.14. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 18.15. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Table 18.11. Timer A Input (Counter Input in Event Counter Mode)
Table 18.16. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
ns
TAiIN input LOW pulse width
tw(TAL)
Min. ns
ns
Unit
TAiIN input HIGH pulse width
tw(TAH)
ParameterSymbol
tc(TA) TAiIN input cycle time
40
100
40
Standard
Max.
Min. ns
ns
ns
Unit
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
tc(TA)
tw(TAH)
tw(TAL)
Symbol Parameter
400
200
200
Standard
Max.
Min. ns
ns
ns
Unit
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
tc(TA)
tw(TAH)
tw(TAL)
Symbol Parameter
200
100
100
Standard
Max.
Min. ns
ns
Unit
tw(TAH)
tw(TAL)
Symbol Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width 100
100
Standard
Max.
Min. ns
ns
ns
Unit
ns
ns
Symbol Parameter
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
2000
1000
1000
400
400
Standard
Max.
Min. ns
ns
ns
Unit
Symbol Parameter
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
800
200
200
18. Electrical Characteristics (M16C/26A)
page 265
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Table 18.17. Timer B Input (Counter Input in Event Counter Mode)
Table 18.18. Timer B Input (Pulse Period Measurement Mode)
Table 18.19. Timer B Input (Pulse Width Measurement Mode)
Table 18.20. A/D Trigger Input
Table 18.21. Serial I/O
_______
Table 18.22. External Interrupt INTi Input
VCC = 5V
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
ns
ns
ns
tc(TB)
tw(TBH)
tw(TBL)
ParameterSymbol Unit
tc(TB)
tw(TBL)
tw(TBH)
ns
ns
ns
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
TBiIN input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
tc(TB)
tw(TBH)
Symbol Parameter Unit
tw(TBL) ns
TBiIN input HIGH pulse width
TBiIN input cycle time
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(TB)
Symbol Parameter Unit
tw(TBL) ns
tw(TBH) TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(AD)
tw(ADL)
Symbol Parameter Unit
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
Standard
Max.
Min. ns
ns
tw(INH)
tw(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
tc(CK)
tw(CKH)
tw(CKL)
ParameterSymbol Unit
td(C-Q)
tsu(D-C)
th(C-Q) TxDi hold time
RxDi input setup time
TxDi output delay time
th(C-D) RxDi input hold time
100
40
40
80
80
200
400
200
200
400
200
200
1000
125
250
250
200
100
100
0
70
90
80
18. Electrical Characteristics (M16C/26A)
page 266
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
TAiIN input
TAiOUT input
During event counter mode
TBiIN input
ADTRG input
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
h(TIN-UP)
t
su(UP-TIN)
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
TAiIN input
Two-phase pulse input in event counter mode
t
c(TA)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
XIN input
t
w(H)
t
w(L)
t
r
t
f
t
c
Figure 18.1. Timing Diagram (1)
18. Electrical Characteristics (M16C/26A)
page 267
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
Figure 18.2. Timing Diagram (2)
t
su(D–C)
CLKi
TxDi
RxDi
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
INTi input
18. Electrical Characteristics (M16C/26A)
page 268
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Table 18.23. Electrical Characteristics (
Note 1)
S
y
m
b
o
l
V
O
H
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
H
V
O
L
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
L
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
S
t
a
n
d
a
r
d
T
y
p
.Unit
Measuring condition
V
V
X
OUT
V
V
X
O
U
T
0
.
5
0
.
5
M
i
n
.M
a
x
.
V
CC
-0.5
P
a
r
a
m
e
t
e
r
I
O
H
=-1
m
A
I
O
H
=-0
.
1
m
A
I
O
H
=-5
0
µ
A
I
O
L
=
1
m
A
I
O
L
=
0
.
1
m
A
I
O
L
=
5
0
µ
A
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
X
C
O
U
T
With no load applied
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d2.5
1.6 V
H
y
s
t
e
r
e
s
i
s
H
y
s
t
e
r
e
s
i
s
H
I
G
H
i
n
p
u
t
c
u
r
r
e
n
t
I
IH
L
O
W
i
n
p
u
t
c
u
r
r
e
n
t
I
I
L
V
RAM
R
A
M
r
e
t
e
n
t
i
o
n
v
o
l
t
a
g
e
V
T
+
-
V
T
-
V
T
+
-
V
T
-
0
.
8V
1
.
8V
4.0 µA
µA
A
t
s
t
o
p
m
o
d
e2
.
0V
R
E
S
E
T
X
I
N
,
R
E
S
E
T
,
C
N
V
s
sV
I
=
3
V
V
I
=
0
V-4
.
0
R
fXIN
R
f
X
C
I
N
Feedback res istance X
IN
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
eX
C
I
N
2
5
3.0 MΩ
MΩ
R
P
U
L
L
U
P
Pull-up
resistance 1
0
0kΩ
V
X
C
O
U
T
0
0
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
V
I
=
0
V5
05
0
0
C
L
K
0
t
o
C
L
K
2
,
T
A
2
O
U
T
t
o
T
A
4
O
U
T
,
T
A
0
I
N
t
o
T
A
4
I
N
,
T
B
0
I
N
t
o
T
B
2
I
N
,
A
D
T
R
G
,
C
T
S
0
t
o
C
T
S
2
,
I
N
T
0
t
o
I
N
T
5
,
N
M
I
,
KI
0
to KI
3
, RxD
0
to RxD
2
X
IN
, RESET, CNVss
V
CC
-0.5
V
CC
-0.5
N
o
t
e
1
:
R
e
f
e
r
e
n
c
e
d
t
o
V
C
C
=
2
.
7
t
o
3
.
6
V
,
V
S
S
=
0
V
a
t
T
o
p
r
=
-
2
0
t
o
8
5
°
C
/
-
4
0
t
o
8
5
°
C
,
f
(
B
C
L
K
)
=
1
0
M
H
z
u
n
l
e
s
s
o
t
h
e
r
w
i
s
e
s
p
e
c
i
f
i
e
d
.
V
CC
V
CC
V
CC
0
.
5
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P
1
5
t
o
P
1
7
,
P
6
0
t
o
P
6
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
3
,
P
1
0
0
t
o
P
1
0
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
H
y
s
t
e
r
e
s
i
sV
T
+
-
V
T
-
0.
8V
X
I
N
18. Electrical Characteristics (M16C/26A)
page 269
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Table 18.24. Electrical Characteristics (2) (
Note 1)
VCC = 3V
Symbol Standard
Typ. Unit
Measuring condition Min. Max.
Parameter
The output pins are open and
other pins are VSS
Main clock, no division mA
f(BCLK)=10MHz, 12
Flash memory
ICC Power supply current
(VCC=2.7 to 3.6V)
Topr=25°C3µA
Stop mode,
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
µA
0.7
µA
Mask ROMor
Flash memory
Note 1: Referenced to VCC=2.7 to 3.6V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2: With one timer operated using fC32.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Note 5: With one timer o
p
erated.
f(BCLK)=1MHz, Wait mode µA
Low power dissipation mode,
RAM(Note 3)
f(BCLK)=32kHz, µA
Low power dissipation mode,
Flash memory(Note 3)
f(BCLK)=32kHz, µA
Flash memory
On-chip oscillation, f2(ROC)
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity Low
Idet4 Voltage down detection dissipation current (Note 4) µA
0.6
Idet3 Reset level detection dissipation current (Note 4) µA
7
Vcc=3.0V mA
Flash memory f(BCLK)=10MHz,
Program
Vcc=3.0V mA
Flash memory f(BCLK)=10MHz,
Erase
14
5
10
11
25
450
45
10
3
Main clock, no division mA
f(BCLK)=10MHz, 10
Mask ROM 7
Mask ROM Low power dissipation mode,
ROM(Note 3)
f(BCLK)=32kHz, µA
25
1
On-chip oscillation,
f2(ROC) selected, f(BCLK)=1MHz mA
On-chip oscillation,
f2(ROC) selected, f(BCLK)=1MHz 1
On-chip oscillation,
f2(ROC) selected, f(BCLK)=1MHz
in wait mode (Note 5) µA
25
mA
18. Electrical Characteristics (M16C/26A)
page 270
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Timing Requirements
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Table 18.25. External Clock Input (XIN input)
Max.
External clock rise time ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
100
40
40 18
18
18. Electrical Characteristics (M16C/26A)
page 271
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Timing Requirements
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Table 18.26. Timer A Input (Counter Input in Event Counter Mode)
Table 18.27. Timer A Input (Gating Input in Timer Mode)
Table 18.28. Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 18.29. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 18.30. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Table 18.31. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
ns
TAi
IN
input LOW pulse width
t
w(TAL)
Min. ns
ns
Unit
TAi
IN
input HIGH pulse width
t
w(TAH)
ParameterSymbol
t
c(TA)
TAi
IN
input cycle time
60
150
60
Standard
Max.
Min. ns
ns
ns
Unit
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
600
300
300
Standard
Max.
Min. ns
ns
ns
Unit
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
300
150
150
Standard
Max.
Min. ns
ns
Unit
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width 150
150
Standard
Max.Min. ns
ns
ns
Unit
ns
ns
Symbol Parameter
TAi
OUT
input cycle time
TAi
OUT
input HIGH pulse width
TAi
OUT
input LOW pulse width
TAi
OUT
input setup time
TAi
OUT
input hold time
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-T
IN
)
t
h(T
IN-
UP)
3000
1500
1500
600
600
Standard
Max.
Min. µs
ns
ns
Unit
Symbol Parameter
TAi
IN
input cycle time
TAi
OUT
input setup time
TAi
IN
input setup time
t
c(TA)
t
su(TA
IN
-TA
OUT
)
t
su(TA
OUT
-TA
IN
)
2
500
500
18. Electrical Characteristics (M16C/26A)
page 272
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Table 18.32. Timer B Input (Counter Input in Event Counter Mode)
Table 18.33. Timer B Input (Pulse Period Measurement Mode)
Table 18.34. Timer B Input (Pulse Width Measurement Mode)
Table 18.35. A/D Trigger Input
Table 18.36. Serial I/O
_______
Table 18.37. External Interrupt INTi Input
Timing Requirements
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBi
IN
input cycle time (counted on one edge)
TBi
IN
input HIGH pulse width (counted on one edge)
TBi
IN
input LOW pulse width (counted on one edge)
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
ParameterSymbol Unit
t
c(TB)
t
w(TBL)
t
w(TBH)
ns
ns
ns
TBi
IN
input HIGH pulse width (counted on both edges)
TBi
IN
input LOW pulse width (counted on both edges)
TBi
IN
input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
t
c(TB)
t
w(TBH)
Symbol Parameter Unit
t
w(TBL)
ns
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(TB)
Symbol Parameter Unit
t
w(TBL)
ns
t
w(TBH)
TBi
IN
input cycle time
TBi
IN
input HIGH pulse width
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(AD)
t
w(ADL)
Symbol Parameter Unit
AD
TRG
input cycle time (trigger able minimum)
AD
TRG
input LOW pulse width
Standard
Max.
Min. ns
ns
t
w(INH)
t
w(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
t
c(CK)
t
w(CKH)
t
w(CKL)
ParameterSymbol Unit
t
d(C-Q)
t
su(D-C)
t
h(C-Q)
TxDi hold time
RxDi input setup time
TxDi output delay time
t
h(C-D)
RxDi input hold time
150
60
60
120
120
300
600
300
300
600
300
300
1500
200
380
380
300
150
150
0
100
90
160
18. Electrical Characteristics (M16C/26A)
page 273
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Figure 18.3. Timing Diagram (1)
TAiIN input
TAiOUT input
During Event Counter Mode
TBiIN input
ADTRG input
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
h(TIN-UP)
t
su(UP-TIN)
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
TAiIN input
Two-Phase Pulse Input in Event Counter Mode
t
c(TA)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
XIN input
t
w(H)
t
w(L)
t
r
t
f
t
c
18. Electrical Characteristics (M16C/26A)
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VCC = 3V
Figure 18.4. Timing Diagram (2)
t
su(D–C)
CLKi
TxDi
RxDi
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
INTi input
18. Electrical Characteristics (M16C/26T)
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18.2. T version
Table 18.38. Absolute Maximum Ratings
Oper at ing ambi ent
temperature
Parameter Unit
Input
voltage
Analog supply voltage
Supply voltage
Output
voltage
V
O
-0 .3 to V
CC
+0.3
-0 .3 to V
CC
+0.3
P
d
Pow er dissipation
Storage tem perature
Rated value
V
V
V
Condition
V
I
AV
CC
V
CC
T
stg
T
opr
Symbol
mW
V
P1
5
to P 1
7
, P 6
0
to P 6
7
, P 7
0
to P 7
7
,
P8
0
to P 8
7
, P 9
0
to P 9
3
, P 1 0
0
to P 1 0
7
,
X
IN
, V
REF
, RESET, C NV
SS
V
CC
=AV
CC
V
CC
=AV
CC
-0 .3 to 6 .5
-0 .3 to 6 .5
-65 to 150
300
-40 to 85 C
-4 0 C T o p r 8 5 C
C
P1
5
to P 1
7
, P 6
0
to P 6
7
, P 7
0
to P 7
7
,
P8
0
to P 8
7
, P 9
0
to P 9
3
, P 1 0
0
to P 1 0
7
,
X
OUT
W hen the Microcomputer is Operating
Flash Program
Erase C0 to 60
Program area
(Block 0 to Block 3)
Data area
(Block A, Block B) -40 to 85 C
<
=<
=
18. Electrical Characteristics (M16C/26T)
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Table 18.39.
Recommended Operating Conditions (Note 1)
3.0 5.5
Typ. Max. UnitParameter
V
CC
Supply voltage
Symbol Min. Standard
Analog supply voltage V
CC
AVcc V
V0
0
Analog supply voltage
Supply voltage
V
IH
I
OH (avg)
HIGH average
output current
mA
mA
Vss
AVss
0.7V
CC
V
V
V
V
CC
0.3V
CC
0LOW input voltage
I
OH (peak)
HIGH peak output
current
HIGH input voltage
-5.0
-10.0
LOW peak output
current 10.0
5.0
mA
f
(X
IN
)Main clock input oscillation frequency (Note 3)
LOW average
output current
I
OL (peak)
mA
I
OL (avg)
V
V
IL
0MHz
20
f
(X
CIN
) Sub-clock oscillation frequency kHz
50
32.768
Note 1: Referenced to V
CC
= 3.0 to 5.5V at Topr = -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
Note 4: The total IOL(peak) for all ports must be 80mA max. The total IOH(peak) for all ports must be -80mA max.
f
1
(ROC) On-chip oscillation frequency 1 MHz1
f
(PLL) PLL clock oscillation frequency (Note 3) 10 MHz
20
f
(BCLK) CPU operation clock 0MHz
20
T
SU
(PLL) PLL frequency synthesizer stabilization wait time V
CC
=5.0V
V
CC
=3.0V 50
20 ms
ms
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
f
2
(ROC) On-chip oscillation frequency 2
f
3
(ROC) On-chip oscillation frequency 3 MHz2MHz16
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
0.5 2
14
826
X
IN
, RESET, CNV
SS
X
IN
, RESET, CNV
SS
V
IH
HIGH input voltage
LOW input voltageV
IL
0.8V
CC
VV
CC
V
0.2V
CC
0
Main clock input oscillation frequency
20.0
0.0
f(X
IN
) operating maximum
frequency
[MH
Z
]
VCC[V] (main clock: no division) 5.53.0
10.0
2.7
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
20MHZ
PLL clock oscillation frequency
20.0
0.0
f(PLL) operating maximum
frequency
[MH
Z
]
VCC[V] (PLL clock oscillation) 5.5
10.0
AAAAA
AAAAA
AAAAA
3.0
20MHZ
18. Electrical Characteristics (M16C/26T)
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Table 18.40. A/D Conversion Characteristics (Note 1)
Standard
Min. Typ. Max.
–
INL
Resolution
Integral non-
linearity
error
Bits
V
REF
=V
CC
10
Symbol Parameter Measuring condition Unit
LSB±3
LSB
VREF =VCC=3.3V, 5V
8 bit ±2
RLADDER
tCONV
Ladder resistance
Conversion time(10bit),
Sample & hold function available
Reference voltage
Analog input voltage
kΩ
µs
V
VIA
VREF
V
0
2.0
10
VCC
VREF
40
3.3
Conversion time(8bit),
Sample & hold function available 2.8
tCONV
VREF =VCC
V
REF
=VCC=5V, ø
AD
=10MHz
V
REF
=V
CC
=5V, ø
AD
=10MHz
DNL Differential non- linearity error
Offset error
Gain error
–
–
LSB
LSB
LSB
±1
±3
±3
Note 1: Referenced to V
CC
=AV
CC
=V
REF
=3.3 to 5.5V, V
SS
=AV
SS
=0V at Topr = -40 to 85 °C unless otherwise specified.
Note 2: AD operation clock frequency (Ø
AD
frequency) must be 10 MHz or less. And divide the f
AD
if V
CC
is less than 4.2V,
and make Ø
AD
frequency equal to or lower than f
AD
/2.
Note 3: A case without sample & hold function turn Ø
AD
frequency into 250 kHz or more in addition to a limit of Note 2.
A case with sample & hold function turn Ø
AD
frequency into 1MHz or more in addition to a limit of Note 2.
Note 4: A case with sample & hold function the sampling time is 3/Ø
AD
.
A case without sam
p
le & hold function the sam
p
lin
g
time is 2/Ø
AD
.
10 bit LSB
±5
LSB±3
LSB
VREF =VCC=3.3V, 5V
8 bit ±2 LSB
±5
–
Absolute
accuracy
VREF =VCC=3.3V
VREF =VCC=5V
10 bit VREF =VCC=3.3V
VREF =VCC=5V
18. Electrical Characteristics (M16C/26T)
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Table 18.41. Flash Memory Version Electrical Characteristics (Note 1) for 100 E/W cycle products / 1,000 E/W cycle products
Note 1: When not otherwise specified, Vcc = 3.0 to5.5V; Topr = 0 to 60 °C.
Note 2: Vcc = 5V; Topr = 25 °C.
Note 3: Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, 10,000), each block can be erased n times.
For example, if a 2Kbytes block A is erased after writing 1 word data 1,024 times, each to a different address, this
counts as one program and erase endurance. Data cannot be written to the same address more than once
without erasing the block. (Rewrite prohibited)
Note 4: Maximum number of E/W cycles for which opration is guaranteed.
Note 5: Topr = 55°C.
Note 6: When not otherwise specified, Vcc = 3.0 to 5.5V; Topr = -40 to 85°C.
Note 7: This is a standard when program or erase endurance exceeds over 1,000 times.
Word program time or block erase time up to 1,000 times is the same as program area.
Note 8: To reduce the number of program and erase endurance when working with systems requiring numerous rewrites,
write to unused word adresses within the block instead of rewrite. Erase block only after all prossible addresses
are used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block B will also improve efficiency. It is improtant
to track the total number of times erasure is used.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase
command at least three times until erase error disappears.
Note 10: When Block A or B E/W cycles exceed 1,000 (Option), select one wait state per block access. When bit 7 in
Flash memory control register 1(FMR17 in address 01B5
16
) is set to "1", one wait state is inserted per access to
Block A or B - regardless of the value of PM17. Wait state insertion during access to all other blocks, as well as to
internal RAM, is controlled by PM17 - regardless of the setting of FMR17.
Note 11: Customers desiring Erase/Write cycle information should contact their Renesas technical support representative.
Note 12: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
W
o
r
d
p
r
o
g
r
a
m
t
i
m
e
(
V
c
c
=
5
.
0
V
,
T
o
p
r
=
2
5
°
C
)
Block erase time 7
5
0.2 60
0
9µ
s
s
P
a
r
a
m
e
t
e
rS
t
a
n
d
a
r
d
Min. T
y
p
.
(
N
o
t
e
2
)
M
a
xUnit
S
y
m
b
o
l
–
–
0
.
49s
0
.
79s
1
.
29s
2Kbyte block
8K
b
y
t
e
b
l
o
c
k
1
6K
b
y
t
e
b
l
o
c
k
3
2
K
b
y
t
e
b
l
o
c
k
–
E
r
a
s
e
/
W
r
i
t
e
c
y
c
l
e
(
N
o
t
e
3
)1
0
0
/
1
,
0
0
0
(
N
o
t
e
4
,
1
1
)cycle
t
d
(
S
R
-
E
S
)
–
T
i
m
e
d
e
l
a
y
f
r
o
m
S
u
s
p
e
n
d
R
e
q
u
e
s
t
u
n
t
i
l
E
r
a
s
e
S
u
s
p
e
n
d
Data retention time (Note 5)
m
s
y
e
a
r
8
20
W
o
r
d
p
r
o
g
r
a
m
t
i
m
e
(
V
c
c
=
5
.
0
V
,
T
o
p
r
=
2
5
°
C
)
B
l
o
c
k
e
r
a
s
e
t
i
m
e
(
V
c
c
=
5
.
0
V
,
T
o
p
r
=
2
5
°
C
)1
0
0µ
s
Parameter S
t
a
n
d
a
r
d
Min. T
y
p
.
(
N
o
t
e
2
)
M
a
xUnit
Symbol
–
–
0.3 s
(2Kbyte block)
–
Erase/Write cycle (Note 3, 8, 9) 10,000
(Note 4,10)
cycle
t
P
S
F
l
a
s
h
M
e
m
o
r
y
C
i
r
c
u
i
t
S
t
a
b
i
l
i
z
a
t
i
o
n
W
a
i
t
T
i
m
eµ
s1
5
t
d
(
S
R
-
E
S
)
T
i
m
e
d
e
l
a
y
f
r
o
m
S
u
s
p
e
n
d
R
e
q
u
e
s
t
u
n
t
i
l
E
r
a
s
e
S
u
s
p
e
n
dm
s8
t
PS
Flash Memory Circuit Stabilization Wait Time µs
15
–
D
a
t
a
r
e
t
e
n
t
i
o
n
t
i
m
e
(
N
o
t
e
5
)y
e
a
r
20
Table 18.42. Flash Memory Version Electrical Characteristics (Note 6) for 10,000 E/W cycle products
[Block A and Block B (Note 7)]
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
18. Electrical Characteristics (M16C/26T)
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Table 18.43.
Power Supply Circuit Timing Characteristics
Symbol Standard
Typ. Unit
Measuring condition Min. Max.
Parameter
2
V
CC
=3.0 to 5.5V 150
td(R-S) STOP release time
ms
td(P-R) Time for internal power supply stabilization during powering-on
td(W-S) Low power dissipation mode wait mode release time (Note 2) 150 µs
td(ROC) Time for internal on-chip oscillator stabilization during powering-on 40
µs
µs
CPU clock
t
d(R-S)
(a)
(b) t
d(W-S)
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
ROC
RESET
VCC
td(P-R) td(ROC)
td(ROC)
Time for Internal On-chip
OscillatorStabilization During
Powering-On
18. Electrical Characteristics (M16C/26T)
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VCC = 5V
Table 18.44.
Electrical Characteristics (Note 1
)
Symbol
V
OH
V
OH
HIGH output voltage
V
OH
V
OL
LOW output
voltage
LOW output
voltage
V
OL
V
OL
HIGH output
voltage
HIGH output
voltage
Standard
Typ. Unit
Measuring condition
V
V
V
X
OUT
V2.0
0.45 V
V
X
OUT
2.0
2.0
Min. Max.
Parameter
I
OH
=-1mA
I
OH
=-0.5mA
I
OL
=1mA
I
OL
=0.5mA
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
HIGH output voltage X
COUT
With no load applied
With no load applied 2.5
1.6 V
Hysteresis
Hysteresis
HIGH input
current
I
IH
LOW input
current
I
IL
V
RAM
RAM retention voltage
V
T+-
V
T-
V
T+-
V
T-
CLK
0
to CLK
2
,TA2
OUT
to TA4
OUT
,0.2 1.0 V
0.2 2.5 V
5.0 µA
µA
At stop mode 2.0 V
RESET
TA0
IN
to TA4
IN
, TB0
IN
to TB2
IN
,
AD
TRG
, CTS
0
to CTS
2
,
V
I
=5V
V
I
=0V -5.0
R
fXIN
R
fXCIN
Feedback resistance X
IN
Feedback resistance X
CIN
15
1.5 MΩ
MΩ
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7,
X
IN
, RESET, CNVss
R
PULLUP
Pull-up
resistance 50 kΩ
INT
0
to INT
5
, NMI,
V
X
COUT
0
0
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
V
I
=0V 30 170
KI
0
to KI
3
, RxD
0
to RxD
2
V
CC
-2.0
V
CC
-2.0
Note 1: Re
f
erencedtoV
CC
=42to55V V
SS
=0VatTopr= 40to85
°
C
f
(BCLK)=20MHz unless otherwise speci
f
ied
I
OH
=-5mA
I
OH
=-200µA
V
CC
-2.0
V
CC
-0.3
V
CC
V
CC
V
CC
V
CC
I
OL
=5mA
I
OL
=200µA
LOW output voltage
LOW output voltage
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7
P1
5
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
3
,
P10
0
to P10
7,
X
IN
, RESET, CNVss
Hysteresis
V
T+-
V
T-
X
IN
0.2 0.8 V
Note 1: Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
18. Electrical Characteristics (M16C/26T)
page 281
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
Table 18.45.
Electrical Characteristics (2) (Note 1
)
S
y
m
b
o
lStandard
Typ. U
n
i
t
Measuring condition Min. Max.
P
a
r
a
m
e
t
e
r
IC
CP
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
(
VC
C=
4
.
0
t
o
5
.
5
V
)
The output pins are open and
other pins are VSS mA1
6
f(BCLK)=20MHz,
Main clock, no division
F
l
a
s
h
m
e
m
o
r
y
mA
F
l
a
s
h
m
e
m
o
r
y
P
r
o
g
r
a
mVCC=5.0V
f(BCLK)=10MHz,
mA
F
l
a
s
h
m
e
m
o
r
y
E
r
a
s
eVCC=5.0V
f(BCLK)=10MHz,
Topr=25
°
C3µ
A
S
t
o
p
m
o
d
e
,
f
(
B
C
L
K
)=3
2
k
H
z
,
Wait mode (Note 2),
Oscilla tion ca pa c ity High µ
A
0
.
8
µ
A
Note 1: Referenced to V
CC
=4.2 to 5.5V, V
SS
=0V at Topr = -40 to 85 °C, f(X
IN
)=20MHz unless otherwise specified.
Note 2: With one timer operated using f
C32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: With one timer operated.
mA
µA
Low power dissipation mode,
RAM(Note 3)
f
(
B
C
L
K
)
=
3
2
k
H
zµA
Low power dissipation mode,
Flash memory(Note 3)
f(BCLK)=32kHz, µA
Fl
as
h
memo ry
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
i
o
n
,
f2
(
R
O
C
)
s
e
l
e
c
t
e
d
,
f
(
B
C
K
)
=
1
M
H
z
,
W
a
i
t
m
o
d
e
(
N
o
t
e
4
)
f(BCLK)=32kHz,
Wait mode(Note 2),
Oscilla tion ca pa c ity Low
On-chip oscillation
f2(ROC) selected, f(BCK)=1MHz
19
1
11
1
2
25
4
5
0
5
0
1
0
3
18. Electrical Characteristics (M16C/26T)
page 282
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)
Table 18.46. External Clock Input (XIN input)
Max.
External clock rise time ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
50
20
20 9
9
18. Electrical Characteristics (M16C/26T)
page 283
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)
Table 18.48. Timer A Input (Gating Input in Timer Mode)
Table 18.49. Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 18.50. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 18.51. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Table 18.47. Timer A Input (Counter Input in Event Counter Mode)
Table 18.52. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
ns
TAiIN input LOW pulse width
tw(TAL)
Min. ns
ns
Unit
TAiIN input HIGH pulse width
tw(TAH)
ParameterSymbol
tc(TA) TAiIN input cycle time
40
100
40
Standard
Max.
Min. ns
ns
ns
Unit
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
tc(TA)
tw(TAH)
tw(TAL)
Symbol Parameter
400
200
200
Standard
Max.
Min. ns
ns
ns
Unit
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
tc(TA)
tw(TAH)
tw(TAL)
Symbol Parameter
200
100
100
Standard
Max.
Min. ns
ns
Unit
tw(TAH)
tw(TAL)
Symbol Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width 100
100
Standard
Max.
Min. ns
ns
ns
Unit
ns
ns
Symbol Parameter
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
2000
1000
1000
400
400
Standard
Max.
Min. ns
ns
ns
Unit
Symbol Parameter
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
800
200
200
18. Electrical Characteristics (M16C/26T)
page 284
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)
Table 18.53. Timer B Input (Counter Input in Event Counter Mode)
Table 18.54. Timer B Input (Pulse Period Measurement Mode)
Table 18.55. Timer B Input (Pulse Width Measurement Mode)
Table 18.56. A/D Trigger Input
Table 18.57. Serial I/O
_______
Table 18.58. External Interrupt INTi Input
VCC = 5V
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBi
IN
input cycle time (counted on one edge)
TBi
IN
input HIGH pulse width (counted on one edge)
TBi
IN
input LOW pulse width (counted on one edge)
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
ParameterSymbol Unit
t
c(TB)
t
w(TBL)
t
w(TBH)
ns
ns
ns
TBi
IN
input HIGH pulse width (counted on both edges)
TBi
IN
input LOW pulse width (counted on both edges)
TBi
IN
input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
t
c(TB)
t
w(TBH)
Symbol Parameter Unit
t
w(TBL)
ns
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(TB)
Symbol Parameter Unit
t
w(TBL)
ns
t
w(TBH)
TBi
IN
input cycle time
TBi
IN
input HIGH pulse width
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(AD)
t
w(ADL)
Symbol Parameter Unit
AD
TRG
input cycle time (trigger able minimum)
AD
TRG
input LOW pulse width
Standard
Max.
Min. ns
ns
t
w(INH)
t
w(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
t
c(CK)
t
w(CKH)
t
w(CKL)
ParameterSymbol Unit
t
d(C-Q)
t
su(D-C)
t
h(C-Q)
TxDi hold time
RxDi input setup time
TxDi output delay time
t
h(C-D)
RxDi input hold time
100
40
40
80
80
200
400
200
200
400
200
200
1000
125
250
250
200
100
100
0
70
90
80
18. Electrical Characteristics (M16C/26T)
page 285
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
TAiIN input
TAiOUT input
During event counter mode
TBiIN input
ADTRG input
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
h(TIN-UP)
t
su(UP-TIN)
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
TAiIN input
Two-phase pulse input in event counter mode
t
c(TA)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
XIN input
t
w(H)
t
w(L)
t
r
t
f
t
c
Figure 18.5. Timing Diagram (1)
18. Electrical Characteristics (M16C/26T)
page 286
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 5V
Figure 18.6. Timing Diagram (2)
tsu(D–C)
CLKi
TxDi
RxDi
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C–Q) th(C–D)
th(C–Q)
INTi input
18. Electrical Characteristics (M16C/26T)
page 287
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Table 18.59. Electrical Characteristics (
Note)
S
y
m
b
o
l
VO
H
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
VO
H
VO
LL
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
VO
L
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
Standard
Typ. U
n
i
t
Measuring condition
V
V
XO
U
T
V
V
XO
U
T0.5
0.5
M
i
n
.M
a
x
.
VC
C-0
.
5
P
a
r
a
m
e
t
e
r
IOH=-1mA
IOH=-0.1mA
IOH=-50µA
IOL=1mA
IOL=0.1mA
IOL=50µA
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
H
I
G
H
P
O
W
E
R
LOWPOWER
XC
O
U
TWith no load applied
With no load applied 2.5
1
.
6V
H
y
s
t
e
r
e
s
i
s
H
y
s
t
e
r
e
s
i
s
H
I
G
H
i
n
p
u
t
c
u
r
r
e
n
t
II
H
L
O
W
i
n
p
u
t
c
u
r
r
e
n
t
IIL
VRAM RAM retention voltage
VT
+
-VT
-
VT
+
-VT
-
0.8 V
1
.
8V
4.0 µA
µ
A
At stop mode 2.0 V
R
E
S
E
T
XIN, RESET, CNVss VI=3V
VI=0V -4
.
0
RfXIN
RfXCIN
Feedback res istance XIN
Feedback res istance XCIN 25
3.0 MΩ
MΩ
RP
U
L
L
U
PPull-up
resistance 1
0
0kΩ
V
XC
O
U
T0
0
With no load applied
With no load applied
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
VI=0V 5
05
0
0
C
L
K0
t
o
C
L
K2,
T
A
2O
U
T
t
o
T
A
4O
U
T,
T
A
0I
N
t
o
T
A
4I
N,
T
B
0I
N
t
o
T
B
2I
N,
A
DT
R
G,
C
T
S0
t
o
C
T
S2,
I
N
T0
t
o
I
N
T5,
N
M
I
,
K
I0
t
o
K
I3,
R
x
D0
t
o
R
x
D2
XI
N,
R
E
S
E
T
,
C
N
V
s
s
VC
C-0
.
5
VC
C-0
.
5
Note 1 : Referenced to VCC=3.0 to 3.3V, VSS=0V at Topr = -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
VC
C
VC
C
VC
C
0.5
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
P
15
t
o
P
17,
P
60
t
o
P
67,
P
70
t
o
P
77,
P
80
t
o
P
87,
P
90
t
o
P
93,
P
1
00
t
o
P
1
07
P
15
t
o
P
17,
P
60
t
o
P
67,
P
70
t
o
P
77,
P
80
t
o
P
87,
P
90
t
o
P
93,
P
1
00
t
o
P
1
07
P15 to P17, P 60 to P67, P70 to P77, P80 to P87, P90 to P93,
P100 to P107
P15 to P17, P 60 to P67, P70 to P77, P80 to P87, P90 to P93,
P100 to P107
P15 to P17, P 60 to P67, P70 to P77, P80 to P87, P90 to P93,
P100 to P107
HysteresisVT+-VT- 0.8 V
XI
N
18. Electrical Characteristics (M16C/26T)
page 288
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Table 18.60. Electrical Characteristics (2) (
Note 1)
VCC = 3V
S
y
m
b
o
lS
t
a
n
d
a
r
d
T
y
p
.Unit
M
e
a
s
u
r
i
n
g
c
o
n
d
i
t
i
o
nM
i
n
.Max.
P
a
r
a
m
e
t
e
r
Th
e
o
u
t
p
u
t
p
i
n
s
a
r
e
o
p
e
n
a
n
d
o
t
h
e
r
p
i
n
s
a
r
e
VS
SMain clock, no division m
A
f
(
B
C
L
K
)
=
1
0
M
H
z
,
1
2
F
l
a
s
h
m
e
m
o
r
y
IC
CP
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
(
VC
C=
3
.
0
t
o
3
.
6
V
)
Topr=25°C3µA
Stop mode,
f(BCLK)=32kHz,
W
a
i
t
m
o
d
e
(
N
o
t
e
2
)
,
O
s
c
i
l
l
a
t
i
o
n
c
a
p
a
c
i
t
y
H
i
g
h
µ
A
0
.
7
µ
A
N
o
t
e
1
:
R
e
f
e
r
e
n
c
e
d
t
o
VC
C=
3
.
0
t
o
3
.
3
V
,
VS
S=
0
V
a
t
T
o
p
r
=
-
4
0
t
o
8
5
°
C
,
f
(
B
C
L
K
)
=
2
0
M
H
z
u
n
l
e
s
s
o
t
h
e
r
w
i
s
e
s
p
e
c
i
f
i
e
d
.
N
o
t
e
2
:
W
i
t
h
o
n
e
t
i
m
e
r
o
p
e
r
a
t
e
d
u
s
i
n
g
fC
3
2.
N
o
t
e
3
:
T
h
i
s
i
n
d
i
c
a
t
e
s
t
h
e
m
e
m
o
r
y
i
n
w
h
i
c
h
t
h
e
p
r
o
g
r
a
m
t
o
b
e
e
x
e
c
u
t
e
d
e
x
i
s
t
s
.
N
o
t
e
4
:
W
i
t
h
o
n
e
t
i
m
e
r
o
p
e
r
a
t
e
d
.
µ
A
Low power dissipation mode,
RAM(Note 3)
f
(
B
C
L
K
)
=
3
2
k
H
z
,
µA
L
o
w
p
o
w
e
r
d
i
s
s
i
p
a
t
i
o
n
m
o
d
e
,
F
l
a
s
h
m
e
m
o
r
y
(
N
o
t
e
3
)
f(BCLK)=32kHz, µ
A
F
l
a
s
h
m
e
m
o
r
y
On-chip oscillation, f2(ROC) selected,
f(BCK)=1MHz,Wait mode (Note 4)
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscilla tion ca pa c ity Low
7
V
c
c=
3
.
0
Vm
A
Fl
as
h
memo ry f(BCLK)=10MHz,
P
rogram
V
c
c=
3
.
0
Vm
A
Fl
as
h
memo ry f(BCLK)=10MHz,
E
rase
1
0
1
1
25
4
5
0
4
5
1
0
3
1
On-chip oscillation,
f2(ROC) selected, f(BCK)=1MHz m
A
18. Electrical Characteristics (M16C/26T)
page 289
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Timing Requirements
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)
Table 18.61. External Clock Input (XIN input)
Max.
External clock rise time
ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
100
40
40 18
18
VCC = 3V
18. Electrical Characteristics (M16C/26T)
page 290
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Timing Requirements
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)
Table 18.62. Timer A Input (Counter Input in Event Counter Mode)
Table 18.63. Timer A Input (Gating Input in Timer Mode)
Table 18.64. Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 18.65. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 18.66. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Table 18.67. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Max.
ns
TAi
IN
input LOW pulse width
t
w(TAL)
Min. ns
ns
Unit
TAi
IN
input HIGH pulse width
t
w(TAH)
ParameterSymbol
t
c(TA)
TAi
IN
input cycle time
60
150
60
Standard
Max.
Min. ns
ns
ns
Unit
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
600
300
300
Standard
Max.
Min. ns
ns
ns
Unit
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
300
150
150
Standard
Max.
Min. ns
ns
Unit
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width 150
150
Standard
Max.Min. ns
ns
ns
Unit
ns
ns
Symbol Parameter
TAi
OUT
input cycle time
TAi
OUT
input HIGH pulse width
TAi
OUT
input LOW pulse width
TAi
OUT
input setup time
TAi
OUT
input hold time
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-TIN)
t
h(TIN-UP)
3000
1500
1500
600
600
Standard
Max.
Min. µs
ns
ns
Unit
Symbol Parameter
TAi
IN
input cycle time
TAi
OUT
input setup time
TAi
IN
input setup time
t
c(TA)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
2
500
500
18. Electrical Characteristics (M16C/26T)
page 291
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
VCC = 3V
Table 18.68. Timer B Input (Counter Input in Event Counter Mode)
Table 18.69. Timer B Input (Pulse Period Measurement Mode)
Table 18.70. Timer B Input (Pulse Width Measurement Mode)
Table 18.71. A/D Trigger Input
Table 18.72. Serial I/O
_______
Table 18.73. External Interrupt INTi Input
Timing Requirements
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
ns
ns
ns
tc(TB)
tw(TBH)
tw(TBL)
ParameterSymbol Unit
tc(TB)
tw(TBL)
tw(TBH)
ns
ns
ns
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
TBiIN input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
tc(TB)
tw(TBH)
Symbol Parameter Unit
tw(TBL) ns
TBiIN input HIGH pulse width
TBiIN input cycle time
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(TB)
Symbol Parameter Unit
tw(TBL) ns
tw(TBH) TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(AD)
tw(ADL)
Symbol Parameter Unit
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
Standard
Max.
Min. ns
ns
tw(INH)
tw(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
tc(CK)
tw(CKH)
tw(CKL)
ParameterSymbol Unit
td(C-Q)
tsu(D-C)
th(C-Q) TxDi hold time
RxDi input setup time
TxDi output delay time
th(C-D) RxDi input hold time
150
60
60
120
120
300
600
300
300
600
300
300
1500
200
380
380
300
150
150
0
100
90
160
18. Electrical Characteristics (M16C/26T)
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VCC = 3V
Figure 18.7. Timing Diagram (1)
TAiIN input
TAiOUT input
During Event Counter Mode
TBiIN input
ADTRG input
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
h(TIN-UP)
t
su(UP-TIN)
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
TAiIN input
Two-Phase Pulse Input in Event Counter Mode
t
c(TA)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
XIN input
t
w(H)
t
w(L)
t
r
t
f
t
c
18. Electrical Characteristics (M16C/26T)
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Figure 18.8. Timing Diagram (2)
t
su(D–C)
CLKi
TxDi
RxDi
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
INTi input
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19. Usage Precaution
19.1 SFR
19.1.1 Precaution for 48 pin version
Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR
register to "1002".
19.1.2 Precaution for 42 pin version
Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR
register to "0012".
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19.2 PLL Frequency Synthesizer
Stabilize supply voltage so that the standard of the power supply ripple is met.
10
Typ. Max. Unit
Parameter
f(ripple) Power supply ripple allowable frequency(VCC)
Symbol Min. Standard
kHz
Power supply ripple allowabled amplitude
voltage
Power supply ripple rising/falling gradient
(VCC=5V)
(VCC=3V)
(VCC=5V)
(VCC=3V)
Vp-p(ripple)
VCC(|∆V/∆T|)
0.5
0.3
0.3
0.3
V
V/ms
V/ms
V
Vp-p(ripple)
f(ripple)
VCC
f
(ripple)
Power supply ripple allowable frequency
(V
CC
)
V
p-p(ripple)
Power supply ripple allowable amplitude
voltage
Figure 19.1 Timing of Voltage Fluctuation
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19.3 Power Control
1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator.
2. Set the MR0 bit in the TAiMR register(i=0 to 4) to “0”(pulse is not output) to use the timer A to exit stop
mode.
3. When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any
instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the
DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT
instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue reads
ahead the instructions following WAIT, and depending on timing, some of these may execute before the
microcomputer enters wait mode.
Program example when entering wait mode
Program Example: JMP.B L1 ; Insert JMP.B instruction before WAIT instruction
L1: FSET I ;
WAIT ; Enter wait mode
NOP ; More than 4 NOP instructions
NOP
NOP
NOP
4. When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which
sets the CM10 bit in the CM1 register to “1”, and then insert at least 4 NOP instructions. When entering
stop mode, the instruction queue reads ahead the instructions following the instruction which sets the
CM10 bit to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop
mode or before the interrupt routine for returning from stop mode.
Program example when entering stop mode
Program Example: FSET I
BSET CM10 ; Enter stop mode
JMP.B L1 ; Insert JMP.B instruction
L1: NOP ; More than 4 NOP instructions
NOP
NOP
NOP
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5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the
main clock.
Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub
clock.
6. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A dash current may flow through the input ports in high impedance
state, if the input is floating. When entering wait mode or stop mode, set non-used ports to input and
stabilize the potential.
(b) A/D converter
When A/D conversion is not performed, set the VCUT bit in the ADCON1 register to “0” (no VREF
connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after
setting the VCUT bit to “1” (VREF connection).
(c) Stopping peripheral functions
Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not stop
peripheral function clocks in wait mode), before changing wait mode.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
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19.4 Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.
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19.5 Interrupts
19.5.1 Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
19.5.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘000016’
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
_______
19.5.3 The NMI Interrupt
_______ _______
1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting to “1” the PM24
bit in the PM2 register. Once enabled, it stays enabled until a reset is applied.
_______
2. The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the
_______
P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
_______ _______
3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This
_______
is because while input on the NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
_______ _______
4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because
_______
when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current
consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-
ated thereafter. _______ _______
5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must
each be 2 CPU clock cycles + 300 ns or more.
_______
6. When using the NMI interrupt for exiting stop mode, set the NDDR register to “FF16” (disable digital
debounce filter) before entering stop mode.
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19.5.4 Changing the Interrupt Generation Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not
requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 19.2 shows the procedure for changing the interrupt generate factor.
Figure 19.2. Procedure for Changing the Interrupt Generate Factor
Changing the interrupt source
Disable interrupts (Note 2, Note 3)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (Note 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Enable interrupts (Note 2, Note 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to Section 1.5.6, “Rewrite the Interrupt Control Register” for details about the
instructions to use and the notes to be taken for instruction execution.
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______
19.5.5 INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
_______ _______
input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
3. When using the INT5 interrupt for exiting stop mode, set the P17DDR register to “FF16” (disable digital
debounce filter) before entering stop mode.
19.5.6 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewritten, due to the internal bus and the instruction queue buffer timing.
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19.5.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
Example 1:Using the NOP instruction to keep the program waiting until
the interrupt control register is modified
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00
16
”.
NOP ;
NOP
FSET I ; Enable interrupts.
The number of NOP instruction is 2.
Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00
16”.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “00
16
”.
POPC FLG ; Enable interrupts.
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19.6 DMAC
19.6.1 Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously(*1).
Step 2: Make sure that the DMAi is in an initial state(*2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Notes:
*1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to
“0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be
written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
*2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.
(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If
the read value is a value in the middle of transfer, the DMAi is not in an initial state.
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19.7 Timer
19.7.1 Timer A
19.7.1.1 Timer A (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the TAi register is read at the same time the counter is reloaded, the read value
is always “FFFF16”. If the TAi register is read after setting a value in it, but before the counter starts
counting, the read value is the one that has been set in the register.
_____
3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
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19.7.1.2 Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the
ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”
(count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits and
the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether
after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the TAi register is read at the same time the counter is reloaded, the read value
is always “FFFF16” when the timer counter underflows and “000016” when the timer counter over-
flows. If the TAi register is read after setting a value in it, but before the counter starts counting, the
read value is the one that has been set in the register.
_____
3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
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19.7.1.3 Timer A (One-shot Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
2. When setting TAiS bit to “0” (count stop), the following occur:
• The counter stops counting and the content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).
3. Output in one-shot timer mode synchronizes with a count source internally generated. When the
external trigger has been selected, a maximun delay of one cycle of the count source occurs be-
tween the trigger input to TAiIN pin and output in one-shot timer mode.
4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
•Change the operation mode from timer mode to one-shot timer mode.
• Change the operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.
5. When a trigger occurs while the timer is counting, the counter reloads the reload register value, and
continues counting after a second trigger is generated and the counter is decremented once. To
generate a trigger while counting, space more than one cycle of the timer count source from the first
trigger and generate again.
6. When selecting the external trigger for the count start conditions in timer A one-shot timer mode, do
generate an external trigger 300ns before the count value of timer A is set to “000016”. The one-shot
timer does not continue counting and may stop.
_____
7. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
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19.7.1.4 Timer A (Pulse Width Modulation Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
•Change an operation mode from timer mode to PWM mode.
•Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
_____
4. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
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19.7.2 Timer B
19.7.2.1 Timer B (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count
starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. The counter value can be read out at any time by reading the TBi register. However, if this register
is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi
register is read after setting a value in it but before the counter starts counting, the read value is the
one that has been set in the register.
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19.7.2.2 Timer B (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count
starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. The counter value can be read out at any time by reading the TBi register. However, if this register
is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi
register is read after setting a value in it but before the counter starts counting, the read value is the
one that has been set in the register.
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19.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2)
register before setting the TBiS bit in the TABSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit is set to “1” (count starts), be sure to set the TM0D0, TM0D1, MR0, MR1, TCK0
and TCK1 bits to the same value as previously written and the MR2 bit to "0".
2. The IR bit in the TBiIC register (i=0 to 2) goes to “1” (interrupt request), when an effective edge of
a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be
determined by use of the MR3 bit in the TBiMR register within the interrupt routine.
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
5. Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
6. When the count is started and the first effective edge is input, an indeterminate value is transferred
to the reload register. At this time, timer Bi interrupt request is not generated.
7. The value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and
timer Bi interrupt request may be generated between the count start and an effective edge input.
8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
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19.8 Serial I/O (Clock-synchronous Serial I/O)
19.8.1 Transmission/reception _______ ________
1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready, which informs the transmission side that the
________
reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if
________ ________
the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmit and receive
_______
data with consistent timing. With the internal clock, the RTS function has no effect.
_____
2. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____ _________
(three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the U1MAP
bit in PACR register is “1”) and CLK2 pins go to a high-impedance state.
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19.8.2 Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register
is set to “0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the
transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register is set to “1”
(transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer
clock), the external clock is in the low state.
• The TE bit in the UiC1 register is set to “1” (transmission enabled)
• The TI bit in the UiC1 register is set to “0” (data present in UiTB register)
_______ _______
• If CTS function is selected, input on the CTSi pin is “L”
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19.8.3 Reception
1. In operating the clock-synchronous serial I/O, operating the transmitter generates a clock for the re-
ceiver shift register. Fix settings for transmission even when using the device only for reception. Dummy
data is output to the outside from the TxDi pin when receiving data.
2. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission
enabled) and write dummy data to the UiTB register, and the clock for the receiver shift register will
thereby be generated. When an external clock is selected, set the TE bit to "1" and write dummy data to
the UiTB register, and the clock for the receiver shift register will be generated when the external clock
is fed to the CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the RE bit in the UiC1 register (i = 0 to 2) is set to “1” (data present in the UiRB register),
an overrun error occurs and the OER bit in the UiRB register is set to “1” (overrun error occurred). In this
case, because the content of the UiRB register is indeterminate, a corrective measure must be taken by
programs on the transmit and receive sides so that the valid data before the overrun error occurred will
be retransmitted. Note that when an overrun error occurred, the IR bit in the SiRIC register does not
change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
5. When an external clock is selected, make sure the external clock is in high state if the CKPOL bit is set
to “0”, and in low state if the CKPOL bit is set to “1” before the following conditions are met:
• Set the RE bit in the UiC1 register to “1” (reception enabled)
• Set the TE bit in the UiC1 register to “1” (transmission enabled)
• Set the TI bit in the UiC1 register to “0” (data present in the UiTB register)
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19.9 Serial I/O (UART Mode)
19.9.1 Special Mode 1 (I2C bus Mode)
When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0”
and wait for more than half cycle of the transfer clock before setting each condition generate bit
(STAREQ, RSTAREQ and STPREQ) from “0” to “1”.
19.9.2 Special Mode 2 _______ _____
If a low-level signal is applied to the P85/NMI/SD pin when the IVPCR1 bit in the TB2SC register is set to
_____
"1" (three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the U1MAP
bit in PACR register is “1”) and CLK2 pins go to a high-impedance state.
19.9.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmission
complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be
sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
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19.10 A/D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref
connected), start A/D conversion after waiting 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7),AN24,AN3i(i=0 to 2)) each and
the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 19.4 is an
example connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the TGR bit in ADCON0 register is set to "1" (external trigger), make sure the port
___________
direction bit for the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A/D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
7. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Figure 19.3. Use of capacitors to reduce noise
Microcomputer
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
VCC
VSS
AVCC
AVSS
VREF
ANi
C4
C1 C2
C3
ANi: ANi(i=0 to 7), AN24, and AN3i (i=0 to 2)
VCC VCC
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8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/
D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i.
This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
• When operating in one-shot mode, single-sweep mode, simultaneous sample sweep mode, delayed
trigger mode 0 or delayed trigger mode 1
Check to see that A/D conversion is completed before reading the target A/D register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0
register to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The
contents of A/D register i irrelevant to A/D conversion may also become indeterminate. If while A/D
conversion is underway the ADST bit is cleared to “0” in a program, ignore the values of all A/D register
i.
10.When setting the ADST bit in the ADCON register to "0" to terminate a conversion forcefully by the
program in single sweep conversion mode, A/D delayed trigger mode 0 and A/D delayed trigger mode
1 during A/D conversion operation, the A/D interrupt request may be generated. If this causes a prob-
lem, set the ADST bit to "0" after the interrupt is disabled.
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19.11 Programmable I/O Ports _____
1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to
a high-impedance state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.
3. When the INV03 bit in the INVC0 register is "1"(three-phase motor control timer output enabled), an "L"
_______ _____
input on the P85/NMI/SD pin, has the following effect:
•When the IVPCR1 bit in the TB2SC register is set to “1” (three-phase output forcible cutoff by input
_____ __ __ ___
on the SD pin enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state._____
•When the IVPCR1 bit is set to “0” (three-phase output forcible cutoff by input on SD pin
__ __ ___
disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.
Therefore, the P85 pin can not be used as programmable I/O port when the INV03 bit is set to "1".
_____ _______ _____
When the SD function isn't used, set PD85 to “0” (Input) and pull the P85/NMI/SD pin to “H” externally.
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19.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise
tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,
etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests con-
ducted in the flash memory version.
19.13 Mask ROM Version
19.13.1 Internal ROM area
When using the masked ROM version, write nothing to internal ROM area.
19.13.2 Reserve bit
The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”.
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19.14 Flash Memory Version
19.14.1 Functions to Inhibit Rewriting Flash Memory
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
and 0FFFFB16. If wrong data is written to these addresses, the flash memory cannot be read or written in
standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”.
19.14.2 Stop mode
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1”(stop
mode) after setting the FMR01 bit to “0”(CPU rewrite mode disabled) and disabling the DMA transfer.
19.14.3 Wait mode
When the microcomputer enters wait mode, excute the WAIT instruction after setting the FMR01 bit to
“0”(CPU rewrite mode disabled).
19.14.4
Low power dissipation mode, on-chip oscillator low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
19.14.5 Writing command and data
Write the command code and data at even addresses.
19.14.6 Program Command
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.
19.14.7 Operation speed
When CPU clock source is main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10
MHz or less for BCLK using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1
register. Also, when CPU clock is f3(ROC) on-chip oscillator clock, before entering CPU rewrite mode
(EW0 or EW1 mode), set the ROCR3 to ROCR2 bits in the ROCR register to “divied by 4” or “divide by 8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
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19.14.8 Instructions prohibited in EW0 Mode
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
19.14.9 Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used, providing that its vector
is transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table. _______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
19.14.10 How to access
To set the FMR01, FMR02, FMR11 or FMR16 bit to “1”, set the subject bit to “1” immediately after setting
to “0”. Do not generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the
_______
instruction to set the bit to “1”. Set the bit while either the PM24 bit in the PM2 register is set to “0” (NMI
_______ _______
disable) or the PM24 bit is set to “1” (NMI funciton) and a high-level (“H”) signal is applied to the NMI pin.
19.14.11 Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
19.14.12 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register is set
to "0" (during the auto program or auto erase period).
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19.14.13 Regarding Programming/Erasure Times and Execution Time
As the number of programming/erasure times increases, so does the execution time for software com-
mands (Program, and Block Erase). _______
The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog
timer interrupt. If a software command is aborted by such reset or interrupt, the affected block must be
erased before reexecuting the aborted command.
19.14.14 Definition of Programming/Erasure Times
"Number of programs and erasure" refers to the number of erasure per block.
If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times.
For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different
address, this is counted as one program and erasure. However, data cannot be written to the same
adrress more than once without erasing the block. (Rewrite prohibited)
19.14.15
Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (U7, U9)
When Block A or B E/W cycles exceed 100, select one wait state per block access. When FMR17 is set
to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state
insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless
of the setting of FMR17.
To use the limited number of erasure efficiently, write to unused address within the block instead of
rewite. Erase block only after all possible address are used. For example, an 8-word program can be
written 128 times before erase becomes necessary.
Maintaining an equal number of erasure between Block A and B will also improve efficiency.
We recommend keeping track of the number of times erasure is used.
19.14.16 Boot Mode
An indeterminate value is sometimes output in the I/O port until the internal power supply becomes stable
_____________
when "H" is applied to the CNVSS pin and "L" is applied to the RESET pin.
When setting the CNVSS pin to "H", the following procedure is required:
____________
(1) Apply an "L" signal to the RESET pin and the CNVSS pin.
(2) Bring VCC to more than 2.7V, and wait at least 2msec.
(Internal power supply stable waiting time)
(3) Apply an "H" signal to the CNVSS pin.
____________
(4) Apply an "H" signal to the RESET pin.
When the CNVSS pin is “H” and RESET pin is “L”, P67 pin is connected to the pull-up resister.
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19.15 Noise
Connect a bypass capacitor (approximately 0.1µF) across the VCC and VSS pins using the shortest and
thicker possible wiring. Figure 19.4 shows the bypass capacitor connection.
M16C/26A Group
(M16C/26A, M16C/26T)
Bypass Capacitor
Connecting PatternConnecting Pattern
VSS VCC
Figure 19.4 Bypass Capacitor Connection
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19.16 Instruction for a Device Use
When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic
discharge period.
Appendix 1. Package Dimensions
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Appendix 1. Package Dimensions
LQFP48-P-77-0.50 –
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
48P6Q-A
Plastic 48pin 7✕7mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
1.0 ––
M
D
7.4 ––
M
E
7.4
8°0°0.1
1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4
01.7
e
e
E
H
E
1
48 37
24
25
36
12
13
H
D
D
MD
ME
A
F
y
b2
I2
Recommended Mount Pad
A
1
A
2
L
1
L
Detail F
Lp
A3
c
Lp 0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
e
b
x
M
Recommended
SSOP42-P-450-0.80 Weight(g)
––
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy+42 Alloy
42P2R-E Plastic 42pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.250
.050
.130.317.28–
.6311.30–
–
–
.271
–
–
.02.30.150.517.48.80.9311.50.7651
–
.4311–
.42
–
–
.40.20.717.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
eb
2
e
1
I
2
Recommended Mount Pad
–
–
Z
1
0.75
––
0.9
z
Recommended
42 22
21
1
H
E
E
ey
F
A
A
2
A
1
L
1
L
c
Detail F
G
b
D
Detail G
z
Z
1
Appendix 2. Functional Difference
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Appendix 2. Functional Difference
Appendix 2.1 Differences between M16C/26A and M16C/26T
Item M16C/26A M16C/26T
Main Clock during Oscillating Stoped
and after Reset (Default value “0” while and after the (Default value “1” while and after the
CM05 bit is reset.) CM05 bit is reset.)
Voltage Detection Available Not available
Circuit (VCR1 register, VCR2 register, (reserve register)
(Function of 001916, D4INT register)
001A16, 001F16)
Cold Start/Warm Start
Available Not available
Detection Function WDC5 bit in theWDC register
Package 48P6Q, 42P2R 48P6Q
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not built
in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
Appendix 2. Functional Difference
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Appendix 2.2 Differences between M16C/26A and M16C/26
Item M16C/26A M16C/26
Clock Generation 4 circuits (Main clock oscillation circuit, 3 circuits (Main clock oscillation circuit,
Circuit Sub clock oscillation circuit, Sub clock oscillation circuit,
on-chip oscillator, on-chip oscillator)
PLL frequency synthesizer)
System Clock On-chip oscillator Main clock
Source After Reset (Initial value "1" of CM21 bit) (Initial value "0" of CM21 bit)
(Initial value of the CM21
bit in the CM2 register)
On-chip Oscillator Clock
Selectable (8MHz/1MHz/500KHz) Fixed (1MHz)
PACR2 to PACR0 in Necessary to set after reset No PACR register
the PACR register 48pin:"1002", 42pin:"0012"
IFSR20 bit in the Necessary to set to "1" after reset No IFSR2A register
IFSR2A register
External Interrupt ________
8 causes (INT2 added) 7 causes
13 pin
(48-pin version)
________
P84/INT2/ZP IVCC
Function
P70, P71N-ch open drain output and CMOS N-ch open drain output
output are selectable by S/W
A/D Input Pin 12 channels 8 channels
(48-pin version)
A/D operation Mode 8 modes (single, repeat, single sweep, 5 modes (single, repeat, single sweep,
repeat sweep mode 0, repeat sweep repeat sweep mode 0, repeat sweep
mode 1, simultaneous sampling, mode 1)
delayed trigger mode 0, delayed
trigger mode 1)
1 shunt current measurement function
is available
Timer B Operation 5 modes (timer, event counter, pulse 4 modes (timer, event counter, pulse
Mode periods measurement, pulse width periods measurement, pulse width
measurment, A/D trigger) measurment)
1 shunt current measurement function
is available
CRC Calculation Available (compatible to CRC-CCITT Not available
and CRC-16 methods)
Three-phase motor •Waveform output/Switching port output •Waveform output/Switching port output
Control by software is enabled by software is disabled
•Position data retention function •No position data retention function
Digital Debounce _______ _____
This function is in the NMI/SD pin and Not available
Function ________
INT5 pin
3 pin
(48-pin version)
P90/CLKOUT/TB0IN/AN30P90/TB0IN
function (CLKOUT: f1, f8, f32, and fC output)
UART1 Compatible Switching to P64 to P67 or P70 to P73P64 to P67
pin is enabled
Flash Memory Protection to blocks 0, 1 by FMR02 bit Protection to blocks 0,1 by FMR02 bit
Protect Function Protection to the blocks 0 to 3 by
FMR16 bit
Package 48P6Q, 42P2R 48P6Q
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not built
in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
Register Index
page 327
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
Register Index
A
AD0 to AD7 179
ADCON0 to ADCON2 177, 182, 184, 186, 188, 190, 192
ADSTAT0 179
ADTRGCON 178, 193, 199, 205
AIER 73
C
CM0 34
CM1 35
CM2 36
CPSRF 91,105
CRCD 209
CRCIN 209
CRCMR 209
CRCSAR 209
D
D4INT 26
DAR0 81
DAR1 81
DM0CON 80
DM0SL 79
DM1CON 80
DM1SL 80
DTT 116
F
FMR0 236
FMR1 236
FMR4 237
I
ICCTB2 116
ICTB2 117
IDB 116
IDB0 116
IFSR 62,70
IFSR2A 62
Interrupt Control 61
INVC0 114
INVC1 115
N
NDDR and P17DDR 222
O
ONSF 91
P
P0 to P13 219
PACR 134,221
PCLKR 37
PCR 221
PD0 to PD13 218
PDRF 124
PFCR 126
PLC0 38
PM0 31
PM1 31
PM2 37
PRCR 54
PUR0 to PUR2 220
R
RMAD0 73
RMAD1 73
ROCR 35
ROMCP 231
S
SAR0 81
SAR1 81
T
TA0 to TA4 90
TA0MR to TA4MR 89
TA11 117
TA1MR 120
TA2 117
TA21 117
TA2MR 120
TA2MR to TA4MR 96
TA4 117
TA41 117
TA4MR 120
Register Index
page 328
823fo5002,51.raM00.1.veR 0010-2020B90JER
)T62/C61M,A62/C61M(puorGA62/C61M
TABSR 90,105,119
TAiMR 94,101
TB0 to TB5 105
TB0MR to TB5MR 104
TB2 119
TB2MR 120
TB2SC 118, 180
TCR0 81
TCR1 81
Timer Ai Mode 92
TPRC 126
TRGSR 91, 119
U
U0BRG to U2BRG 131
U0C0 to U2C0 133
U0C1 to U2C1 134
U0MR to U2MR 132
U0RB to U2RB 131
U0TB to U2TB 131
U2SMR 135
U2SMR2 135
U2SMR3 136
U2SMR4 136
UCON 133
UDF 90
V
VCR1 26
VCR2 26
W
WDC 75
WDTS 75
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-1
0.51 Feb/ 01/ 04 2 Note 2 in Table 1.1 is revised.
3 Note 2 in Table 1.2 is revised.
10 Table 1.6 is revised.
39 The section “7.3 Ring Oscillator Clock” is revised.
58 The section “9.3 Interrupt Control” is revised.
60 Figure 9.3.2 is added. IFSR2A register is revised.
68 ______
The section “9.6 INT Interrupt” is revised.
IFSR2A register in Figure 9.6.1 is deleted.
69 _______
The section “9.7 NMI Interrupt” is revised.
72 The section “10. Watchdog Timer” is revised.
81 Table 11.2.2 is revised.
100 The section “12.2 Timer B” is revised. Figure 12.2.2 is revised.
102 Figure 12.2.2.1 is revised.
107 Figure 12.2.4.2 is revised.
114 Figure 12.3.6 is revised.
122 The section “13. Serial I/O” is revised.
124 Figure 13.1.2 is revised.
149 Table 13.1.3.3 is revised.
161 Table 13.1.5.1 is revised.
168
to
201 The chapter 14 is revised.
202 The section 15 is revised.
205 The section “16. Programmable I/O port” is revised.
206 The section “16.6 Digital Debounce function” is revised.
216 Figure 16.6.1 is revised.
222 Table 17.4 and Note 5, 7 are revised.
241 Table 17.41 and Note 5, 7 are revised.
260 Table 17.78 and Note 5, 7 are revised.
271 The section 18.2 is revised.
277 Note 2 in Table 18.4.1 is revised.
297 Figure 18.9.3 is revised.
302 The chapter 20 is revised.
0.51A
Mar/09/04 120 Figure 12.3.1.2.1 and the section 12.3.1.2.4 are partly revised.
0.70 April/08/04 1 The section “1. Overview” is partly revised.
2,3 Table 1.1 and 1.2 are partly revised.
6 The section “1.4 Product List” is partly revised.
8,9 Figure 1.3 to 1.5 are partly revised.
11 Table 1.7 is partly revised.
14 The Chapter ”3. Memory” is partly revised. Note 2 in Figure 3.1 is added.
15 The Chapter “4. Special Function Register” is partly revised.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-2
24 The section “5.5 Voltage Detection Curcuit” is partly revised.
Figure 5.5.1 and 5.5.2 are partly revised.
25 VCR1 register and VCR2 register in Figure 5.5.3 are partly revised.
26 Figure 5.5.4 is partly revised.
27 The section “5.5.1 Voltage Detection Interrupt” is partly revised.
28 Figure 5.5.1.1.2.1 is partly revised.
29 Figure 6.2 is partly revised.
32 Figure 7.2 is partly revised.
33 Figure 7.3 is partly revised.
34 Figure 7.5 is partly revised.
35 Processer mode register 2 in Figure 7.6 is partly revised.
37 The section “7.1 Main Clock” is partly revised.
40 Figure 7.4.1 is partly revised.
41 The section “7.5 CPU Clock and Peripheral Function Clock” and “7.5.2 Peripheral
Function Clock” are partly revised.
49 The section “7.7 System Clock Protective Function” and “7.8 Oscillation Stop and
Re-oscillation Detect Function” are partly revised.
60 IFSR2A register in Figure 9.3.2 is partly revised.
62 The section “9.4 Interrupt Sequence” is partly revised.
63 The section “9.4.1 Interrupt Response Time” and Figure 9.4.1.1 are partly revised.
89 Table 12.1.1.1 is partly revised.
97 Table 12.1.4.1 is partly revised.
100 Setction 12.2. Timer B” is partly revised.
101 The Timer Bi register in Figure 12.2.3 is partly revised.
106 The section “12.2.4 A-D trigger mode” and table 12.2.4.1 are partly revised.
107 Figure 12.2.4.1 and 12.2.4.2 are partly revised.
110 Figure 12.3.2 is partly revised.
112 “ Timer B2 interrupt occurrences frequency set counter” in Figure 12.3.4 is partly
revised.
114 Figure 12.3.6 is partly revised.
117 Figure 12.3.9 PFCR register and TPRC register is deleted.
121 The section “13.3.2 Three-phase/Port Output Switch Function”, Figure “12.3.2.1
Usage Example of Three-phse/Port output switch function” and Figure “12.3.2.2
PFCR register and TPRC register” are added.
130 “UART 2 special mode register 2” in Figure 13.1.8 is partly revised.
131 “UART 2 special mode register 3” in Figure 13.1.9 is partly revised.
134 Table 13.1.1.2 is partly revised.
141 Table 13.1.2.2 is partly revised.
149 Figure 13.1.3.1 is partly revised.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-3
169 Table 14.1 is partly revised.
172 Figure 14.4 is partly revised.
173 Figure 14.5 is partly revised.
178 The section “14.1.3. Single Sweep Mode” is partly revised.
184 The section “14.1.6 Simultaneous Sample sweep Mode” is partly revised.
187 The section “14.1.7 Delayed Trigger Mode 0” and Table 15.1.7.1 are partly revised.
188 Figure 14.1.7.1 is revised.
189, 190 Figure 14.1.7.2 and 14.1.7.3 are revised
191 Figure 14.1.7.3 is deleted.
192 Figure 14.1.7.6 is partly revised.
193 The section “14.1.8 Delayed Trigger Mode 1” and Table 15.1.8.1 are partly revised.
195, 196 Figure 14.1.8.2 and 14.1.8.3 are partly revised.
200 Figure 14.5.1 is partly revised.
202 The chapter “15. CRC Calculation Circuit” is partly revised.
204 Figure 15.3 is partly revised.
205 The chapter “16. Programmable I/O Ports” is partly revised.
206 The section “16.5 Pin Assignment Control register(PACR)” is partly revised.
214 “Pull-up control register 2” in Figure 16.3.1 is partly revised.
222 Table 17.4 and 17.5 are revised partly revised. Note 6 and 10 are partly revised.
223 Note 3 in Table 17.6 is added.
241 Table 17.41 and 17.42 are revised partly revised. Note 10 is partly revised.
242 Note 3 in Table 17.43 is added.
257
to
268 The section “17.3 V version” is deleted.
269 Table 18.1 is partly revised.
270
to
227 Setction “18.2. Memory Map” and Figure18.2.3 and 18.2.4 are revised.
280 “•FMR17 Bit” in the section 18.5.2 is partly revised.
269
to
300 Chapter “18. Flash memory Version” is revised.
302 Capter “20 Difference between M16C/26A and M16C/27” is partly revised.
1.00 Mar/15/05 All pages Word standardized (on-chip oscillator, A/D)
1 “M16C/26T” in “1. Overview” is added.
2,3 Table 1.1 and Table 1.2 are revised.
6 “1.4 Product List” and Table 1.3 to 1.5 are revised.
7 “ROM/RAM capacity” and “Product code” in Figure 1.3 are partly revised.
Table 1.6 is added.
8 “Figure 1.4 Marking Diagram” is added.
9, 10 The 24 and 25 pin in Figure 1.5 and the 27 and 28 pin in Figure 1.6 are revised.
11 “Power supply input” in Talbe 1.6 is revised. “I/O port P6” and “Î/O port P7” are
partly revised.
12 “I/O prot P9” is partly revised.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-4
15 “3. Memoty” is partly revised. The size of internal ROM in Figure 3.1 is revised.
16 to 21 “4. Special Function Register” is change from “?” to “X”.
16
Register name of D4INT register is revised. Note 2 and 3 in Table 4.1 are revised.
19 The after reset of IDB0 and ICB1 register are revised.
21 The after reset of ADTRGCON and PD9 are revised.
22 “5.1.2 Hardware Reset 2” is added “Note”, and partly revised.
23 “5.4 Oscillation Stop Detection Reset” is partly revised.
25 “5.5 Voltage Detection Circuit” is added “Note”, and partly revised. Figure 5.5.1 is
revised. Figure “WDC register” is deleted.
26 The VC25 bit in “VCR2 register” in Figure 5.5.2 is deleted.
27 Figure 5.5.3 is revised.
28 to 30 “5.5.1 Voltage Down Detection Interrupt”, “5.5.2 Limitations on Exiting Stop Mode”
and “5.5.3 Limitations Exiting Wait Mode” are revised.
31 Figure 6.2 is partly revised.
32 “Oscillator status after reset” in Table 7.1 is partly revised.
33 Figure 7.1 is partly revised.
34 The after reset value of “CM0 register” is revised.
35 The bit 7 to 4 in Figure 7.4 is revised.
37 Note 2 and note 4 in PM2 register is revised.
39 7 line in “7.1 Main Clock” is added.
41 “7.3 On-chip Oscillator Clock” is revised.
42 Figure 7.4.1 is partly revised.
45 “7.6.1.6 On-chip Oscillator Mode” is partly revised.
46 Table 7.6.2.3.1 is added.
48 Figure 7.6.1 is partly revised.
49 Notes in Figure 7.6.1.1 is revised.
54
Note in “8. Protection” is added. “NDDR register” in “8. Protection” and Figure 8.1 is added.
55 Note in “9. Interrupt” is added.
58 Note 2 in Table 9.2.1.1 is added.
64 Note 2 in Figure 9.4.1 is added.
68 “Watchdog Timer” in Figure 9.5.1 is added.
74 “10. Watchdog Timer” is partly revised. Figure 10.1 is partly revised.
75 Note 3 of WDC register in Figure 10.2 is added.
76 “10.2 Cold start/Warm start” is added.
77 Note in “11. DMAC” is added.
83 Figure 11.1.1 is partly revised.
87 Note in “12. Timers” is added.
91 TRGSR register in Figure 12.1.4 is revised.
94 “Normal processing operation” in Table 12.1.2.2 is partly revised.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-5
100 “Count Start Condition” in Table 12.1.4.1 is patly revised.
112 “Notes” of Table 12.3.1 is revised.
113 Figure 12.3.1 is partly revised.
114 The function of INV00 bit and note 1,3, 5, 6 in Figure 12.3.2 are partly revised.
115 The function in INV13 bit is revised. Note 2 is added.
116 Reset value of “Three-Phase Output Buffer Register” in Figure 12.3.4 is revised.
117 Note 6 in Figure 12.3.5 is revised.
120 Figure 12.3.9 is partly revised.
125 Note in Figure 12.3.2.1 is added.
127 Note in “13. Serial I/O” is added. “13.1 UARTi(i=0 to 2)” is partly revised.
128
to
130 Figure 13.1.1 to Figure 13.1.3 are partly revised.
131 Note 2 in UiRB register and note 1 in UiBRG register are revised.
132 Function of SMD2 to SMD0 bits and Note 3 in U2MR register are revised.
133 Note 5 and 6 in UiC0 register are added. Note 2 in UCON register is added.
134 PACR register is added in Figure 13.1.7.
137 “Transfer clock” in Table 13.1.1.1 is partly revised.
“UART 1 pin remapping selection” in Select function is added.
138 Function of RCSP bit in Table 13.1.1.2 is partly revised.
139
“RxDi” in Table 13.1.1.3 is partly revised. Note 1 in Table 13.1.1.3 and Table 13.1.1.4 are added.
140 The comment of fEXT in Figure 13.1.1.1 is added.
141 “13.1.1.1 Counter Measure for Communication Error Occurs” is added.
143 Note 2 in Figure 13.1.1.6.1 is added.
144 Note 1 in Figure 13.1.1.7.1 is added.
145 “Transfer clock” in Table 13.1.2.1 is partly revised.
“UART 1 pin remapping selection” in Select function is added.
146 Function of RCSP bit in Table 13.1.2.2 is partly revised.
147
“RxDi” in Table 13.1.2.3 is partly revised. Note 1 in Table 13.1.2.3 and Table 13.1.2.4 are added.
149,150
“13.1.2.1 Bit Rates” and “13.1.2.2 Counter Measure for Communication Error Occurs” is added.
152 Note 1 in Figure 13.1.2.6.1 is added.
153 “Transfer clock” in Table 13.1.3.1 is partly revised.
163 “Transfer clock” in Table 13.1.4.1 is partly revised.
165 “UFORM” in Table 13.1.4.2 is revised.
169 Figure 13.1.5.1 is partly revised.
170 “Transfer clock” in Table 13.1.6.1 is partly revised.
175
Note in “14. A/D Converter” is added.“Integral Nonlinearity Error” in Table 14.1 is partly revised.
206 “14.2 Sample and Hold” is partly revised.
206, 207 “14.5 Analog Input Pin and External Sensor Equivalent Circuit Example” and
“14.6 Precautions of Using A/D Converter” are deleted. “14.5 Output Impedance
of Sensor under A/D Conversion” is added.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-6
209 “After reset” of CRCSAR register in Figure 15.2 is revised.
211 Note in “16. Programmable I/O Ports” is added.
211 “16.3 Pull-up Control Register 0 to Pull-up Control Register 2” is added P67.
212 “16.5 Pin Assignment Cotrol register” is added “M16C/26T”. PRC2 bit is revised.
“16.6 Digital Debounce function” is partly revised. (INPC17 is added.)
214 P77, P90 to P92 in Figure 16.2 is partly revised.
218 The after reset of PD9 register in Figure 16.1.1 is revised.
221 Note 1 in Figure 16.5.1 is revised.
222 Note in NDDR register and P17DDR register is added.
224 Note 5 in Table 16.1 is added.
225
to
293 “Flash Memory Version” and “Electrical Characteristics” are exchanged.
225 “Erase block” and “Progream/Erase Endurance” in Table 17.1 are revised.
227 “17.2 Memory Map” is partly revised.
232 “17.4 CPU Rewrite Mode” is partly revised. Note2 in Table 17.4.1 is partly revised.
234 “17.5.1 Flash memory control register 0” is partly revised.
236 The after reset of FMR0 register and Note 3 of FMR1 register in Figure 17.5.1 is revised.
239 Figure 17.5.1.3 is partly revised.
240 The FMR16 bit in “17.6.4 How to Access” is added.
241 “17.6.9 Stop Mode” is partly revised.
244 “17.7.6 Block Erase” is partly revised.
250 Table 17.9.1 and note 2 is partly revised.
251, 252 Figure 17.9.1 and Figure 17.9.2 are partly revised.
253, 254 Figure 17.9.2.1 and Figure 17.9.2.2 are partly revised.
256 The condition of “Pd” in Table 18.1 is revised. Flash Program Erase of “Topr” is added.
257 Table 18.2 is modified.
258 Measuring condition in Table 18.3 is partly revised.
259 Table 18.4 and Table 18.5 are added “tPS” and “td(SR-ES)”. Note 3 and Note 8 are revised.
260 Table 18.6, Table 18.7 and “Power Supply Circuit Timing Diagram” are modified.
261 The “hysteresis XIN” in Table 18.8 is added.
262 Table 18.9 is revised.
266 “XIN input” in Figure 18.1 is added.
268 The “hysteresis XIN” in Table 18.23 is added. Note 1 is partly revised.
269 Table 18.24 is revised.
273 “XIN input” in Figure 18.3 is added.
275 The condition of “Pd” in Table 18.38 is revised. Flash Program Erase of “Topr” is added.
276 Table 18.39 is partly revised.
277 “Tolerance Level Impedance” in Table 18.40 is added.
278 Table 18.41 and Table 18.42 are added “tPS” and “td(SR-ES)”. Note 3 and 8 are revised.
279 Table 18.43 and “Power Supply Circuit Timing Diagram” are revised.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-7
280 The “hysteresis XIN” in Table 18.44 is added. Note 1 is partly revised.
281 Table 18.45 is revised.
285 “XIN input” in Figure 18.5 is added.
287 The “hysteresis XIN” in Table 18.59 is added. Note 1 is partly revised.
288 Table 18.60 is revised.
292 “XIN input” in Figure 18.7 is added.
294
to
323 Chapter “19. Usage precaution” is added.
296 The title of Figure 19.2 is partly revised.
297, 298 Ths subsection 3, 4, 5 and 6(a) are revised.
300 _______
The subsection 1 in “19.6.3 The NMI interrupt” is partly revised.
301 The title of “19.6.4” is partly revised.
302 The last 2 lines in “19.6.6 Rewrite the Interrupt Control Register” is partly revised.
305, 306 The subsection 2 in “19.8.1.1 Timer A (Timer Mode)” and “19.8.1.2 Timer A (Event
Counter Mode)” are revised.
307 “19.8.1.3 Timer A (One-shot Timer Mode)” is partly revised.
309, 310 The subsection 2 in “19.8.2.1 Timer B (Timer Mode)” and “19.8.2.2 Timer B (Event
Counter Mode)” are revised.
311 The subsection 6 and 7 in “19.8.2.3 Timer B (
Pulse Period/pulse Width Measurement Mode
)”
are partly revised.
312 The subsection 1 in “19.9.1 Transmission/reception” is partly revised.
314 The subsection 1, 2 and 5 in “19.9.3 Reception” is partly revised.
316, 317 The subsection 2 and 10 in “19.11 A/D Converter” are partly revised.
318 The subsection 3 in “19.12 Programmalbe I/O Ports” is partly revised.
319 “19.13 Electric Characteristic Differences Between Mask ROM and Flash Memory
Version Microcomputers” and “19.14.2 Reserve bit” are partly revised.
320 “19.15.1 Function to Inhibit Rewriting Flash Memory” is partly revised.
321 The title of “19.15.8” is revised. “19.15.10 How to access” is revised.
322
“19.15.13 Regarding Programming/Erasure Times and Execution Time”, “19.15.14
Definition of Programming/Erasure Times” and “19.15.16 Boot Mode” are partly revised.
325 “Appendix 2.1 Differences between M16C/26A and M16C/26T” is added.
275 “Operating ambient temperature” in Table 18.38 is revised.
276, 277 Table 18.39 and 18.40 are partly revised.
278 Table 18.41 and 18.42 are partly revised.
279 Figure of timing is revised.
281 Table 18.45 is partly revised.
284 Table 18.57 is partly revised.
287, 288 Table 18.59 and 18.60 are partly revised.
REVISION HISTORY M16C/26A Hardware Manual
Rev. Date Description
Page Summary
C-8
288 Tabl 18.60 is revised.
294 Table 18.72 is partly revised.
296 The max values of “Power supply ripple rising/falling gradient” are revised.
M16C/26A Group(M16C/26A,M16C/26T) Hardware Manual
Publication Data : Rev.0.51 Feb 01, 2004
Rev.1.00 Mar 15, 2005
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
M16C/26A Group (M16C/26A,M16C/26T)
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
