Document No. 70-0099-02 │www.psemi.com
Page 1 of 7
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
8-lead CS OIC
RFC
RF1 RF2
CMOS
Control
Driver
CTRL
The PE9354 SPDT High Power UltraCMOS™ RF Switch is
designed to cover a broad range of applications from near DC
to 3000 MHz. This single-supply reflective switch integrates on-
board CMOS control logic driven by a simple, single-pin CMOS
and TTL compatible control input. Using a nominal +3-volt
power supply, a typical input 1 dB compression point of +31
dBm can be achieved. The PE9354 also exhibits input-output
isol ati o n of bet ter th an 30 dB at 200 0 MHz and is offered in a
small 8-lead ceramic SOIC package.
The PE9354 is optimized for commercial space applications.
Single Event Latch up (SEL) is physically impossible and
Single Event Upset (SEU) is better than 10-9 erro rs per bit/day.
Fabricated in Peregrine’s UltraCMOS™ technology, the
PE9354 offers excellent RF performance and intrinsic radiation
tolerance.
Pro duct Specificat ion
SPDT High Power
UltraCMOS™ RF Switch
Rad hard for Space Applications
Product Description
Figure 1. Functional Schematic Diagram Figure 2. Package Type
Features
• Single 3-volt power supply
• Low insertion loss: 0.55 dB at 2000 MHz
• High isolation of 30 dB at 2000 MHz
• Typical input 1 dB compression point of
+31 dBm
• 100 Krad total dose
• Single-pin CMOS or TTL logic control
• Low cost
Table 1. A/C Electrical Specifications -55 °C to +125 °C, VDD = 3 .0 V (ZS = Z L = 50 Ω)
Parameter Conditions Minimum Typical Maximum Units
Operation Frequency1 DC 3000 M Hz
Ins ert ion Los s 2000 MH z 0.5 5 0.8 0 dB
Isolation – RFC to RF1/RF2 2000 MHz 28 32 dB
Isolati on – R F1 t o RF2 2000 MH z 24 28 dB
Return Los s 2 2000 MHz 22 dB
Inp ut 1 dB C o mpres s i o n 2000 MH z 28 31 dB m
Note: 1. Device linearity will begi n to degrade below 10 MHz.
Note: 2. Return loss not measured in production due to equipment limitations
PE9354
Product Specification
PE9354
Page 2 of 7
©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions
Table 2 . Pin Descriptions
Table 3. Absolute Maximum Ratings
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For fle xibility to
support systems that have 5-volt control logic
drivers, the cont rol logic input h as be en designed
to handle a 5-volt logic HIGH signal. (A minimal
curre nt will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
Latc h-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Figure 3. Pin Configuration
Electrostatic Discharge (ESD) Precautions
When handlin g this U l traCM OS ™ device, observe
the sa me precautions that you would use with
other ES D-sensiti ve dev ices . Althou gh this dev ice
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
PE9354
1
2
3
4
8
7
6
5
V
DD
CTRL
GND
RFC
RF1
GND
GND
RF2
Pin
No. Pin
Name Description
1 VDD Nominal +3V supply connection.
2 CTRL
CMOS or TTL logic level:
High = RFC to RF 1 signal path
Low = RFC to RF2 signal path
3 GND
Ground connection. Traces should be
physically short and connected to
gro un d pl ane for bes t per form anc e.
4 RFC Common RF por t for sw itch.1
5 RF2 RF2 port.1
6 GND
Ground Connection. Traces should be
physically short and connected to
gro un d pl ane for bes t per form anc e.
7 GND
Ground Connection. Traces should be
physically short and connected to
gro un d pl ane for bes t per form anc e.
8 RF1 RF1 port.1
Note 1: All RF pins must be DC blocked with an external series
capacitor or held at 0 VDC.
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input
except for the CTRL input -0.3 VDD+
0.3 V
VCTRL Voltage on CTRL input 5.0 V
TST Storage temperature range -65 150 °C
TOP Operating temperature
range -55 125 °C
PIN Input po wer ( 5 0 Ω) 32 dBm
VESD ESD volt age (Human Body
Model) 200 V
Total Dose Total Cumu lative Ex pos u re
to Ioni zing Radiation 100k Rads
(Si)
Table 4. DC Electrical Specifications Table 5. Control Logic Truth Table
Parameter Min Typ Max Units
VDD Power Supply
Voltage 2.7 3.0 3.3 V
Inp ut Le ak a ge -1 1 µA
IDD Power Supply
Current
(VDD = 3V, VCNTL = 3V) 28 100 µA
Control Voltage High 0.7xVDD V
Control Voltage Low 0.3xVDD V
Control Voltage Signal Path
CTRL = CMOS or TTL High RFC to RF1
CTRL = CMOS or TTL Low RFC to RF2
Abso lute Ma ximum Ratings are those values
listed in the above table. Exceeding these values
may caus e permanent devi ce da m age.
Functional operation should be restricted to the
limits in the DC Electrical Specifications tab le.
Exposure to abso lute maximum ratings fo r
exten de d perio ds may affect device reliabilit y.
Product Specification
PE9354
Page 3 of 7
Document No. 70-0099-02 │www.psemi.com ©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ -55 °C to 125 °C
Figure 4. Insertion Loss – RFC to RF1 Figure 5. Input 1dB Compression Point
Figure 6. Insertion Loss – RFC to RF2 Figure 7. Isolation – RFC to RF1
Product Specification
PE9354
Page 4 of 7
©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions
Typical Performance Data @ -55 °C to 125 °C
Figure 8. Isolation – RFC to RF2 Fig ure 9. Iso lation – RF1 /R F2 to RF2/RF1
Figure 10. Return Loss – RFC Figure 11. Return Loss – RF1, RF2
Product Specification
PE9354
Page 5 of 7
Document No. 70-0099-02 │www.psemi.com ©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit Information
Ev aluation Kit
The SP DT S witch Evaluation Kit board was designed to
ease customer ev aluation of the PE9354 SPDT switch.
The RF com m on por t is c onnec ted through a 50 Ω
transmission line to the top lef t SM A connector, J1.
Port 1 and Port 2 are connect ed through 50 Ω
transmission lines to t he top t wo SMA connect ors on
the ri ght side of the boar d, J2 and J3. A through
transmission line connects S MA connec tors J4 and J5.
This transm is sion line can be used to est imate the loss
of t he P CB over the envir onm ental condit ions being
evaluated.
The boar d is c ons tructed of a two metal lay er FR4
mater i al with a total thic k nes s of 0. 031” . The bot tom
layer pr ov ides gr ound for t he RF transm is s ion lines .
The t ransmiss i on lines wer e des igned us ing a c oplanar
waveguide with ground plane m odel us ing a trace width
of 0. 030”, trace gaps of 0. 007”, dielectric thicknes s of
0.028”, met al thick nes s of 0.0014” and εr of 4.4.
J6 provides a means f or cont r olling DC and digital
inputs to the dev ic e. Starting from the lower lef t pin,
the sec ond pin to the right ( J 2-3) is connected to t he
device CNTL input. The fourt h pin to the right (J2-7) is
connected to t he dev ic e VDD input. A decoupling
capacitor (100 pF ) is prov ided on both CTRL and VDD
traces. It is the respons ibility of the cus tomer to
determine proper supply decoupling for their design
application. Removing these com ponents f r om the
evaluation board has not been s hown to degrade RF
performance.
The gr ound plane has been r em ov ed from beneath the
device for perf or m ance issues. It was found that
insertion loss dips ( s uck-out s ) were ex per ienc ed due to
the capac itive ef fect of the metal pack age s itt ing
insulated by t he solder-mask on the ground plane. All Figure 13. Evaluation Board Schematic
Figure 12. Evaluation Board Layouts
Peregrine specifi cati on 102/0129
data specified and shown on this dat as heet was taken
using this evaluation board c onfigurat ion. For optimal
performance, the package may be solder ed dir ec tly to
the ground plane, but the reliabilit y is s ues as s oc iated
with t his mounting must be addr essed by the customer .
Product Specification
PE9354
Page 6 of 7
©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions
8-lead CS OIC
Figure 14. Package Drawing
Table 6. Ordering Information
TOP VIEW
.050 T YP
.015 T YP
.150 T YP
.380 / .410
.210 / .250
.180 SQ MAX Pin 1
SIDE VIEW .070 Max
ALL DIMENSIONS ARE IN INCHES
.005 T yp
Or der Code Part Marking Description Package Shipping Method
9354-01 PE9354 ES Engineering Samples 8-lead Ceramic SOIC 50 units / Tray
9354-11 PE9354 Flight Units 8-lead Ceramic SOIC 50 units / Tray
9354-00 PE9354-EK PE9354 Evaluation Kit Evaluation Kit 1 / Box
Product Specification
PE9354
Page 7 of 7
Document No. 70-0099-02 │www.psemi.com ©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
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Data Sheet Identification
Advance Information
The product is in a formative or design st age. The data
sheet cont ains design target specificat ions f or product
development. Specifications and feat ures may change in
any manner without notice.
Preliminary Specification
The data sheet cont ains preliminar y data. Additional data
may be added at a later date. Peregrine reserves t he right
to change specifications at any tim e without notice in order
to supply t he best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Peregrine will notify
cust omers of the intended changes by issuing a DCN
(Document Change Notice).
The information in t his data sheet is believed t o be reliable.
Howeve r, Peregrine assume s no liabilit y for the use of this
information. Use shall be entir ely at the user’s own risk.
No patent r ight s or licenses t o any circuits described in this
data sheet are implied or granted t o any third party.
Peregrine’s products are not designed or int ended for use in
devices or systems int ended for sur gical implant, or in other
applications intended t o support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situat ion in which personal injury or death m ight occur.
Peregr ine assum e s no liability for damages, including
consequential or incidental dam ages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi ar e registered t r ademarks
and UltraCMOS and HaRP are trademarks of Per egrine
Semiconductor Corp.
South As ia Pa cific
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
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