Data Sheet
1.0 Introduction
1.1
Overview The VRC5 074 S
y
s te m Contro l ler is a sof twa re -c on fi
g
urable chip that directl
y
connects
the VR5000 CPU to SDRAM memor
y
, a PCI Bus, and a Loca l Bus, without exter nal
lo
g
ic or buffer in
g
. From the CPU’ s viewpoint, the contr oller act s as a memor
y
control-
ler, DMA control ler, PCI-Bus host br id
g
e, and Local- Bus host brid
g
e. From th e view-
point of PCI a
g
ents, the contr oller act s as master and tar
g
et on the PCI Bus. The
controller also has one serial port and fo ur tim ers.
1.2
Features
CPU Interface
• Conn ects directly to a 250 MHz VR5000 CPU.
• 100 MHz CPU bus.
• Peak block-transfer throughput of 800 Mbytes/sec, maximum sustained
throughput of 640 Mbytes/sec.
• 16 x 8-byte (128-byte) CPU-to-controller FIFO.
• Little-endian or big-endian byte order on CPU interface.
• Sup ports secondary cache.
• 15 interrupt sources, individually enabled and assigned to one of the CPU’s
seven interrupt inputs.
• Sup port s all CPU bus-cycle types (but the only write type is pipelined write) .
Parity generat ion and checking on CPU data cycles.
• Mode data at reset provi ded by a serial EEPROM or by the controller.
•3.3V I/O.
Memory Interf ace
• 100 MHz memory bus.
• Maximum sustained throughput of 800 Mbytes/sec.
• Sup port s three physical loads per data bit: two SDRAM physical banks and
one other (e.g., EPROM, Flash, or buffers bridging to a secondary memory
bus).
• Sup port s four types of SDRAM with two to four on- chip virt ual banks: 256M b
four-bank, 64Mb four-bank, 64Mb two-bank, 16Mb two-bank.
• On-chip bank-interl eaving buffers.
• Programmable address ranges for each memory bank.
• Memory may maintain multiple open SDRAM pages.
• Parity or ECC generat ion and checking of memor y data cycles wit h 64+8 bits
of SDRAM and no performance degradation.
VRC5074 System Controller
June 1998
• Read/write buffers:
- 8-dword (64-b yte) CPU W rite FIFO.
- 8-dword (64-byte) PCI Write FIF O .
• On-chip refresh generation.
•3.3V I/O.
PCI Bus
• Full compliance with
PCI Local Bus Specification, Revision 2.1
.
• Four possible conf igurations:
- 66 MHz, 64-bit bus (maximum sustained bandwi dth 533 Mbytes/sec)
- 66 MHz, 32-bit bus (maximum sustained bandwi dth 267 Mbytes/sec)
- 33 MHz, 64-bit bus (maximum sustained bandwi dth 267 Mbytes/sec)
- 33 MHz, 32-bit bus (maximum sustained bandwi dth 133 Mbytes/sec)
• PCI-Master support, allowing the CPU, DMA, and Local-Bus masters to
access targets on the PCI Bus via two prog ram mable PCI Address Windows.
• PCI-Target support, allowing PCI-Bus masters to access to all controller
resources.
- Eleven pro gramm able Base Address Register (BAR) windows.
- All read s are delayed transactions.
- Up to four si mu ltaneous delayed transactions.
• Master and target r ead/write bur sts up to 2 Mbytes in le ngth.
• Master and target read/write buffers:
- 32-entry x 8-byte (256-byte) PCI Outp ut FIFO.
- 32-entry x 8-byte (256-byte) PCI Input FIFO.
- 4-entry x 8-by te (32-byte) CPU Delayed Read Completion (DRC) Buffer.
- 4-entry x 8-by te (32-byte) DMA Delayed Read Compl eti on (DRC) Buffer.
• Optional PCI Central Resource functions:
- Buff ered PCI clock to 5 oth er PCI devices.
- PCI clock can be external or derived from CPU clock.
- Arbitration for the controll er and 5 other PCI devices.
- CPU interrupt control for 5 PCI devices.
• Full PCI Configuration Space.
• 64-bit addressing suppor t for master and ta rget using Dual Addr ess Cycle
(DAC).
• Locked cycle (exclusive access) support as master and target.
• Parity generation and checking on address and data cycles.
• Compliant with both 3.3V and 5V PCI signaling.
Local Bus
• 25 MHz or 50 MHz bus (0. 25 or 0.50 of system clock).
• Programmable chip-selects for 7 devi ces plus Boot ROM.
- Each chip-select supports up to 4GB address space.
- Devices may alternatively be located on the memory bus.
- Chip-se lect signal s m ay alt ernatively be used for DMA or UART control, or
as general-purpose I/O signal s.
• Sup port for bu rst cycles on the Local Bus.
• Support for Local-Bus master control of the Local Bus, using 68000 or Intel
arbitration protocols.
• Programmable con trol-si gnal relat ionships and timing:
- Timing can be fixed or use external Ready signal.
- 12-bit ti m er for externa l Ready signal.
• 3.3V outputs, 5V- tol erant inputs
DMA
• Two DMA channel s.
• Block transfers to or from any physical address.
• Tran sfers initiated by the CPU, a PCI-Bus ma ster, or a Local -Bus master.
• Peak block-transfer throughput of 800 Mbytes/sec, maximum sustained
throughput of 640 Mbytes/sec.
• 32 x 8-byte (256-byte) DMA FIFO.
• Two set s of DMA c ontrol registers. One set can be programm ed wh il e the
other performs a transfer.
• Chained transfers—when one transfer completes, anot her program med
transfer aut om aticall y begins.
• Sup port s bidirect ional, unal igned transfers.
• Optional hardwar e handshake si gnals (REQ#, ACK#, EOT#) if certain chi p-
selects are not used.
Serial Port (UART)
• Compatible with National Semiconductor’s PC16550D UART.
• Receiver and trans mitter each have a 16-byte FIFO.
• 5, 6, 7, or 8 bits per character.
• Eve n, odd, or no parity- bit generation and detecti on.
• 1, 1.5, or 2 sto p-bit generation.
• Bau d-rate generator divi sion of input clock by 1 to (216 -1).
• Prioritized interrupt controls.
• DSR and DTR control signals.
• Optio nal hardwar e controls (CT S#, RT S#, DCD#, XIN#) if certain chi p-sel ects
are not used.
Timers
• 16-bi t SDRAM ref resh timer.
• 24-bi t CPU-b us read timer.
• 32-bit general -purpose ti m er.
• 32-bit watchdog timer.
• All timers are cascada ble.
Multi-Controller Support
Contents
1.0 Introduction .....................................................................................................................1
1.1 Overview ...........................................................................................................................1
1.2 Features............................................................................................................................ 1
2.0 Internal and S
y
stem Architecture................................................................................ 11
2.1 Internal Architecture........................................................................................................11
2.2 System-Design Options ..................................................................................................13
2.3 Terminology.....................................................................................................................19
2. 4 R e fe r e n ce D oc u m e n t s ... ..... .. .... ... .... ......... .. .... ... .... .. ..... .. .... .. ..... ......... .. .... ... .... .. ..... .. .... ..19
3.0 Si
g
nal Summa r
y
............................................................................................................ 21
4.0 Re
g
ister and Resource Summar
y
................................................................................ 31
4.1 Register Summary .......................................................................................................... 31
4.2 Resource-Accessibility Summary....................................................................................34
4.3 Address Space Summary ...............................................................................................3 6
5.0 CPU/S
y
stem Interface and Re
g
isters .......................................................................... 37
5.1 CPU and System Configuration and Monitoring .............................................................37
5. 2 C PU Int er f a ce......... .. .... .. ..... .. .... ... .... .. ..... ........ ... .... .. ..... .. .... .. ..... ......... .. .... ... .... .. ..... .. ......37
5.2.1 Signal Connect ions to CPU.. . .. .. .... .. . .. .. .... .. . .. .. .. .... ......... ........... ......... .. . .. .. .... .. . .. .. .... .37
5.2.2 CPU-Interface Data Path...........................................................................................38
5.2.3 SysAd Flow Control...................................................................................................39
5.2.4 Parity Checking and Generation ...............................................................................40
5.2.5 CPU Reads .. ........... .. . .. .... .. ........... .. . .. .... .. ........... .. . .. .... .. ........... . .. .. .... .. . .. .... .. ........... .4 0
5.2.5.1 Read Requests that Hit the Secondary Cache ....................................................40
5.2.5.2 Non-Matching Read Add ress.... . .. .... .... . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... ...40
5.2.5.3 Branches to Unaligned Addresses......................................................................41
5. 2 .6 En d ia n Co n fig ura tio n... .. .... .. ..... .. .... ... .... .. ..... ........ ... .... .. ..... .. .... ... .... ......... .. .... ... .... .. .. 41
5.3 Multi-Controller Configurations........................................................................................ 41
5.3.1 Distinguishing Between Multiple Controllers .............................................................41
5.3.2 The Ma in Controller................................................................................................... 42
5.3.3 Programming.............................................................................................................42
5.3.4 CntrValid#, WrRdy # and MCW rRdy# ....... ........... .. . .. .. .... .. . .. .. .... ......... .. . .. .. .... .. . .. .. .... .43
5.3.5 Access Targeting.......................................................................................................4 4
5.4 Physical Device Address Registers (PDARs) .................................................................45
5.4.1 Initialization State of PDARs .....................................................................................45
5. 4 .2 PD AR Fie ld s..... .. .... .. ..... .. .... ... .... ......... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... .. ..... .. .... .. 46
5.4.3 PDAR Address Decodin g Example........................................................................... 49
5.5 CPU Interface Registers ................................................................................................. 50
5.5.1 CPU Status Register (CPUSTAT)..............................................................................50
5. 5 .2 In t e rr u p t Co n trol R e gist e r (I N TCTR L) .......... .. .... .. ..... ......... .. .... ... .... .. ..... .. .... ......... .. .. 52
5.5.3 Interrupt Status Register 0 (INTSTAT0).....................................................................55
5.5.4 Interrupt Status 1/CPU Interrupt Enable Register (INTSTAT1) .................................55
5.5.5 Interrupt Clear Register (INTCLR)............................................................................. 56
5.5.6 PCI Interrupt Control Register (INTPPES)................................................................ 57
5.6 T imer Registers...............................................................................................................58
5.6.1 SDRAM Refresh Control Register (T0CTRL)............................................................ 58
5.6.2 SDRAM Refresh Counter Register (T0CNTR)..........................................................59
5.6.3 CPU-Bus Read T ime-Out Control Register (T1CTRL).............................................. 59
5.6.4 CPU- Bus Rea d T ime-Out Counter Register (T 1CNT R). .. ....... .. . .. .. .. .. .. . .. .. .. .. .. ....... .. .60
5.6.5 Gener al-Purpose T im e r Cont rol Regi st er (T2CT RL)......... .. .. .. ........... .. . .. .. .... .. . .. .. .... .60
5.6.6 Gener al-Purpose T im e r Count er Regi ster (T2CNT R)....... .... .. ........... .. . .. .. .. .... ......... .6 1
5.6.7 Watchdog Tim er Control Regist er (T3CT RL).... .... ......... ........... ......... .. . .. .. .... .. . .. .. .... .61
5.6.8 Watchdog Tim er Counter Register (T 3CNT R) ...... . .. .. .... .. . .. .. .... ......... .. . .. .. .... .. . .. .. .... .62
6.0 Main-M emory Interface and Registers ... .... ............. ............................... . .. .... .... ..........6 3
6.1 Memor y Configu ration and M onitoring....... .... .. . .. .... .... ............................... . .. .... .. ............6 3
6.2 Physical Loads...... .. .... .... ...................... . .. .. .... ............. . .. .... .. ................................. . .. .. ..... 63
6.3 Write FIFOs.....................................................................................................................6 4
6.4 Boot - ROM and External-Device Address i ng...... .. .. .... ......... ......... ........... .. . .. .. .... .. . .. .. .... .64
6.4.1 Memory- Bus Addressing Of Boot ROM and External Devices ........ .. .......................65
6.4.2 Boot-Memory Timing.................................................................................................65
6.5 SDRAM Main Memory .................................................................................................... 67
6.5.1 Bank-Interleaving ......................................................................................................67
6.5.2 SDRAM Chip Initialization.........................................................................................68
6.5.3 Direct Connections, SIMMs, and DIMMs ..................................................................68
6.5.4 Address-Multiplexing Modes.....................................................................................68
6.5.5 Performance.............................................................................................................. 69
6.5.6 Memory Timing..........................................................................................................71
6.5.7 Memory Refresh........................................................................................................71
6. 5 .8 Er r o r C he c king ....... ......... .. ..... .. .... .. ..... .. .... ......... .. ..... .. .... ... .... .. ..... .. .... ......... .. ..... .. ....72
6.5.9 Memory Sharing in Multi-Controller Configurations...................................................7 2
6. 6 Memo ry - In terf a ce Re g i s te r s.... .. ..... .. .... ... .... ......... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... .. .. 72
6.6.1 Memory Control Register (MEMCTRL) ..................................................................... 72
6.6.2 Memory Access T iming Register (ACSTIME) ...........................................................74
6.6.3 Memory Check Error Status Register (CHKERR).....................................................74
7.0 PCI -Bus Interface and Registers ....... ......... .. . .. .. .... .. . .. .. .... .. . .. .. .. ........... .. . .. .. .... .. . .. .. .. ...78
7.1 PCI-Bus Configuration and Monitoring............................................................................ 78
7.2 Read and Wr i te Buffers........ .... ........................ . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... ...79
7.3 PCI Command s Suppor ted......... .. .... .... ......... ........... .. . .. .... .. ........... ......... ........... .. . .. .... .. .8 0
7.4 PCI Master Transactions (Controller-to-PCI) ..................................................................81
7.4.1 PCI Address Window Registers ................................................................................81
7.4.2 PCI Address Decoding Example............................................................................... 81
7. 4 .3 PC I- Maste r Write s......... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... .. ..... .. ..... .. .... ......... .. ..... .. .... .. 82
7.4.3.1 Combining ...........................................................................................................82
7.4.3.2 Byte-Merging....................................................................................................... 82
7.4.4 PCI-Master Reads.....................................................................................................83
7.4.4.1 Retried Reads .....................................................................................................83
7.4.4.2 Prefetching on PCI-Master Reads......... .... .... ............. . .. .... ........................ . .. .... ...83
7.4.5 PCI-Ma ster Parity Detection...................................................................................... 84
7.4.6 PCI I/O Space Cycles................................................................................................85
7.5 PCI Target T ransactions (PCI-to-Controller) ...................................................................85
7.5.1 PCI Loop-Back Accesses..........................................................................................85
7.5.2 PCI-Target Writes......................................................................................................86
7.5.3 PCI -Tar get Reads.. .. .. . .. .. .... .. . .. .. .... .. . .. .. .... .. . .. .. .. .... ......... ........... ......... .. . .. .. .... .. . .. .. .... .86
7.5.4 PCI-Target Parity Detection....................................................................................... 87
7.6 64-Bit PCI Bus.................................................................................................................87
7.7 Dual Address Cycle (DAC) Suppo rt....... .. .... .. ........... .. . .. .. .... .. . .. .. .. ........... .. . .. .. .... .. . .. .. .. ...88
7.8 PCI Cent ral Resour ce Suppor t.... .... .. .... ......... .. . .. .. .... .. . .. .. .... .. . .. .. .... ......... .. . .. .. .... .. . .. .. .... .88
7.8.1 Central Resource Functions...................................................................................... 88
7.8.2 Central Resource Terminology..................................................................................89
7.8.3 External Arbitration....................................................................................................89
7.9 PCI Clocking ...................................................................................................................90
7.10 PCI Locked Cycles..........................................................................................................91
7.11 PCI-Bus Registers...........................................................................................................91
7.11.1 PCI Control Register (PCICTRL)............................................................................... 91
7. 11 .2 PC I Ar b i t e r Re g i s te r (PCIAR B). .. .... ... .... .. ..... ........ ... .... .. ..... .. .... ... .... ......... .. .... ... .... .. .. 98
7.11.3 P CI Master (Initiator) Regi st ers 0 and 1 (PCI I NITn)......... ......... ......... ........... .. . .. .. .. .10 1
7. 11 .4 PC I Er r o r R e gist e r (P C IERR). .... .. ..... .. .... .. ..... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... ..103
7.12 PCI Configuration Space Cycles...................................................................................103
7.12.1 As PCI-Bus Master and Target................................................................................104
7.12.2 Co nfigur ation Me chanisms........ .... ............. . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... .104
7.12.3 Generating ID SEL Input s ........ .... .... . .. .... .... . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... .105
7.13 PCI Configuration Space Registers ..............................................................................105
7.13.1 PCI Vendor ID Register (VID). .................................................................................107
7.13.2 PCI Device ID Register (DID)..................................................................................107
7.13.3 PCI Command Regist er (PCICMD).... .. .... .. . .. .. .... .. . .. .. .. .... ......... . .. .. .... .. . .. .. .. .... ........107
7.13.4 PCI Status Register (PCISTS) ................................................................................108
7.13.5 PCI Revision ID Register (REVID) .......................................................................... 109
7.13.6 PCI Class Code Regist er (CLASS)........ .. ......... .... ......... ........... ......... .. . .. .. .... .. . .. .. ... 110
7.13.7 PCI Cache-Line Size Register (CLSIZ)................................................................... 110
7. 1 3.8 PC I L a te n cy Tim e r R e gi ster (M LTIM)........... ........ ... .... .. ..... .. .... ... .... ......... .. .... ... .... .. 110
7.13.9 PCI Header Type Register (HTYPE)....................................................................... 110
7.13.10 PCI Base Address Registers (BARn)...................................................................... 110
7.13.11 PCI Sub-System Vendor ID (SSVID). .......................................................................111
7.13.12 PCI Sub-System ID (SSID) ......................................................................................111
7.13.13 PCI Interrupt Line Register (INTLIN)....................................................................... 112
7. 1 3.14 PC I In terr u p t Pin Regi ster (I N T PI N) .. .. .... .. ..... .. .... ... .... .. ..... ......... .. .... .. ..... .. .... ... .... .. 112
8.0 Lo cal-Bu s Interface and Reg isters. ........................................................................... 113
8.1 Local-Bus Configuration and Monitoring. ...................................................................... 113
8.2 Device Chip-Select Configuration ................................................................................. 114
8.3 Local-Bus Master Transactions (Controller-to-Local Bus)............................................. 116
8.3.1 Timing...................................................................................................................... 116
8.3.2 Dword vs. Block Requests ...... .... .... . .. .... .... . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... . 117
8.3.2.1 Dword Requests................................................................................................ 117
8.3.2.2 Block Requests .......... .... . .. .... .... . .. .... .... . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... . 117
8.4 Arbitration for Local-Bus Control................................................................................... 118
8.4.1 Signal Redefinition for Local-Bus Masters .............................................................. 119
8.4.2 Local-Bus Target T ransactions (Local Bus-to-Controller)........................................ 119
8.5 Local Bus vs. 64-bit PCI Bus.........................................................................................120
8. 6 L o c a l -B u s R e giste rs....... ... .... .. ..... .. .... ......... .. ..... .. .... .. ..... .. .... ... .... ......... .. ..... .. .... .. ..... .. .. 120
8.6.1 Local Bus Configuration Register (LCNFG)............................................................121
8.6.2 Local Bus Chip-Select T iming Registers (LCSTn)................................................... 122
8.6.3 Device Chip-Select Function Register (DCSFN)..................................................... 125
8.6.4 Device Chip-Selects as I/O Bits Register (DCSIO) ................................................. 128
8.6.5 Local Boot Chip-Select Timing Register (BCST)..................................................... 129
9. 0 D MA Contro lle r a nd Re g i s te r s.... .. .... ... .... .. ..... ........ ... .... .. ..... .. .... ... .... ......... .. .... ... .... .. 130
9.1 DMA Configuration and Monitoring............................................................................... 130
9.2 DMA Tran sfer Mechani sm................................ . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... .13 0
9.2.1 Configur ation and Enabling............. . .. .... .... . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... .13 0
9.2.2 Operation.................................................................................................................131
9.2.3 Completion .............................................................................................................. 131
9. 3 D a ta Aligne r .. ......... .. .... .. ..... .. .... ... .... ......... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... .. ..... .. ....131
9.4 DM A Hardw are Handshaking...... .... .. .... ......... ......... .... ......... ........... ......... .. . .. .. .... .. . .. .. ...132
9.4.1 External DM A Reques ts........ .. .. .... .. . .. .. .... .. . .. .. .. .... ......... ........... ......... .. . .. .. .... .. . .. .. ...133
9. 4 .2 En d O f Tr a n sf e r........... .. .... .. ..... .. .... ......... .. ..... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... ..133
9.5 DMA Registers.............................................................................................................. 133
9.5.1 DMA Control Registers 0 and 1 (DMACTRLn)......... .. .. .... ......... . .. .. .... .. . .. .. .. .... ........13 3
9.5.2 DMA Source Address Register 0 and 1 (DMASRCAn)........................................... 136
9.5.3 DMA Destination Address Register 0 and 1 (DMADESAn) .....................................136
10.0 Serial Port and Registers ........................................................................................... 137
10.1 Ser ial- Por t Confi gurat io n and Monitorin g. .. .... ............. . .. .... .... . .. .... ........................ . .. .... .13 7
10.2 Additional UART Signals...............................................................................................137
10.3 UART Clocking.............................................................................................................. 138
10.4 Serial-Port Registers.....................................................................................................139
10.4.1 UART Receiver Data Buffer Register (UARTRBR) .................................................139
10.4.2 UART T ransmitter Data Holding Register (UARTTHR)...........................................139
10.4.3 UART Interrupt Enable Register (UARTIER)...........................................................139
10.4.4 UART Divisor Latch LSB Register (UARTDLL).......................................................140
10.4.5 UART Divisor Latch MSB Register (UARTDLM)..................................................... 140
10.4.6 UART Interrupt ID Register (UARTIIR).................................................................... 140
10.4.7 UART FIFO Control Register (UARTFCR).............................................................. 141
10.4.8 UART Line Control Register (UARTLCR)................................................................142
10.4.9 UART Modem Control Register (UARTMCR).........................................................143
10.4.10 UART Line Status Register (UARTLSR).................................................................144
10.4.11 UART Modem Status Register (UARTMSR)...........................................................144
10 . 4.12 U ART Sc ra tch R egi s ter (UARTSC R ) .... ......... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... ..145
11.0 Interrupts ..................................................................................................................... 147
12.0 Reset and Initialization............................................................................................... 149
12.1 Types of Reset..............................................................................................................149
12.2 Pow er-Up and Cold Reset Confi gurat io n Signal s................ ......... ........... .. . .. .. .... .. . .. .. ...150
12.3 PCI Reset Sequenc i ng..... .... .. .... ......... .. . .. .. .... .. . .. .. .... .. . .. .. .. .... ......... . .. .. .... .. . .. .. .... .. . .. .. .. .15 1
12 . 4 C PU an d Co nt roll e r Ini t i a l izatio n .......... ......... .. ..... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... ..151
12.4.1 Reset Signal Control ...............................................................................................151
12.4.2 Initial i zati on Sequenc e . .... .... . .. .. .... ............. . .. .... .. ............. . .. .... ............. . .. .. .... ..........15 2
12.4.2.1 Connecting the Serial Mode EEPROM .............................................................152
12.4.2.2 Initialization Data...............................................................................................153
12.4.3 In-Circuit Programm ing of the Serial Mode EEPROM....... .. .... ........................ . .. .... .15 4
13.0 Endian-Mode Software Issues ...................................................................................156
13.1 Overview ....................................................................................................................... 156
13.2 Endian Modes........... .... ............. . .. .... .... . .. .... .... . .. .... .... . .. .... .... . .. .... ........................ . .. .... .15 6
13 . 3 L A N C o ntro ll e r Ex a mp l e. ......... ......... .. ..... .. .... .. ..... .. .... ... .... ......... .. ..... .. .... .. ..... .. .... .........158
13.3.1 DMA Accesses from Ethernet FIFO........................................................................ 158
13 . 3.2 Wor d Ac cess e s to I/O R e gist e rs ....... .. .... .. ..... .. .... ... .... .. ..... ......... .. .... .. ..... .. .... ... .... .. 1 58
13.3.3 Byte or Halfword Accesse s to I/O Registers ...........................................................159
13.4 GUI Controller Example ................................................................................................ 160
13 . 4.1 Wor d Ac cess e s to I/O R e gist e rs ....... .. .... .. ..... .. .... ... .... .. ..... ......... .. .... .. ..... .. .... ... .... .. 1 60
13.4.2 Byte or Halfword Accesse s to I/O Registers ...........................................................161
13.4.3 Accesses to RDRAM...............................................................................................161
14.0 Timing Diagrams.........................................................................................................162
14.1 CPU Accesses to Local Memory...................................................................................162
14.2 PCI-Bus Accesses ........................................................................................................173
14 . 3 L o c a l -B u s Ac cess e s... .. ..... .. .... .. ..... .. .... ......... .. ..... .. .... ... .... .. ..... ......... .. .... .. ..... .. .... ... .... ..181
15.0 Testing.......................................................................................................................... 190
16.0 Electrical Specifications.............................................................................................191
16.1 Terminology...................................................................................................................191
16.2 Absolute Maximum Ratings .......................................................................................... 192
16.3 Reco mmended Operat ing Range . .... .... . .. .... .... . .. .... .... . .. .... .... . .. .... ............. . .. .... .... . .. .... .19 2
16.4 DC Characteristics........................................................................................................193
16.5 AC Specifications.......................................................................................................... 194
16.5.1 Clock Timing............................................................................................................ 194
16.5.2 CPU, Memory, Local Bus and Interrupt Signals......................................................194
16 . 5.3 PC I- Bus In te r face. ......... .. .... ... .... ......... .. .... ... .... .. ..... .. .... ......... .. ..... .. .... ... .... .. ..... .. ....197
17.0 Pinout...........................................................................................................................198
18.0 Package........................................................................................................................210
Appendix A Revision 2 Errata.........................................................................................................213
A.1 Serial Configuration Stream.......................................................................................... 213
A.2 PCI-Bus Interface..........................................................................................................213
A.2.1 Revision ID.............................................................................................................. 213
A.2.2 PCI Timing Problems............................................................................................... 213
A.2.3 PCI Loopback Reads ..............................................................................................213
A .2 . 4 PCI L O C K#.... ... .... .. ..... .. .... .. ..... .. .... ... .... ......... .. .... ... .... .. ..... .. .... ... .... ......... .. .... ... .... .. 2 13
A.2.5 PCI Address Parity Error.........................................................................................21 3
A.2.6 PCI Target Prefetch May Cause OUTFIFO Overrun............................................... 214
A.3 Secondary Cache in Multi-Controller Configuration......................................................214
A.4 UART External Clock ....................................................................................................215
Appendix B Index.............................................................................................................................217
2.0 Internal and System Architectu re
2.1
Internal Architecture There are three master s internal to the contr oller tha t can
g
enerate acces ses:
CPU
PCI Bus
DMA (which generates accesses on behalf of the CPU, PCI-Bus m asters, or
Local-Bus maste rs)
There are four targets internal to the controller that can respond to an access:
Memory (SDRAM and oth er devi ces on the memory bus )
PCI Bus
Local Bus
Controller’s Internal Registers (Table 8 on page 31)
There are independent, point-to-point buses, 64-bits wide in each direction, that con-
nect all possible master-target pairs (except loop-back pairs):
CPU-to-Memory
CPU-to-PCI Bus
CPU-to-Local Bus
CPU-to-Controller’s Internal Registers
DMA-to-Memory
DMA-to-PCI Bus
DMA-to-Local Bus
DMA-to-Cont roller’s Internal Regist ers
PCI Bus-to-M emory
PCI Bus-to-Local Bus
PCI Bus-to-C ontroll er’s Internal Registers
Figure 1 shows these internal buses. If only one master accesses a given target, no
resource con tention occurs, so that accesses by al l masters can p roceed simulta-
neousl y to t hei r separ ate t arg ets. When multi ple m asters attempt to ac cess a given ta r-
get, the controller arbitrates as follows:
When th e Contr oller’s Internal Regist ers are targeted by multiple masters simulta-
neously, the arbitratio n is ver y fast, because the registers run so quickly. The longest
delay any master is likely to see is only a few clocks.
The Memory target also responds very fast when targeted by multiple masters simul-
taneously. It attempts to service all requests in t he m ost effi cient m anner, for example
by givi ng priority to requests for a page that is curr ently open. SDRAM h as such high
bandwid th that it is unlikel y for any one master t o be held off for more than a few cloc ks.
The PCI-Bus target has an arbiter for responding to simultaneous accesses by the
CPU and DMA. The arbit er i s controll ed by programmabl e fi elds that govern the dura-
tion of consecutive accesses by the se ma sters.
The Loca l-Bus tar get, li ke t he PCI-Bus t arget, has a programm able arbiter that governs
the duration of consecutive accesses by the CPU, DMA and PCI masters.
Figure 1: VRC5074 Int ernal Architecture
2.2
System-Design
Options
Several si
g
nals are samp led at reset (Section 12.0) to determine the properti es of the
controller’ s operation in a s
y
stem , in cludin
g
:
Endian Mode:
The CPU interface can operate in either little-endian or bi
g
-endian
mode. However, the memor
y
, PCI- Bus, and Local-Bus interfaces alwa
y
s operate
in little-endian mode.
PCI-Bus and Local-Bus Width:
The control ler can support either a 64-bi t PCI Bus
and no Local Bus, or a 32-bit PCI Bus and a 32-bi t Local Bus.
PCI Central Resource Functions:
The controller can operate either as the PCI
Central Resource or it can oper ate in a PCI Stand-Al one M ode (i .e., not t he
Central Resource).
Multi-Controller Configurations:
When multiple controllers are used in a s
y
stem ,
each has its own ID and address s pace, and one controller i s the Main Controll er.
Fi
g
ure 2 throu
g
h Fi
g
ure 7 show examples of how the control ler can be use d in s
y
stem
desi
g
ns.
Figure 2: Single-Cont roller, 32-Bit PCI-Bus Confi guration
Fi
g
ure 2 shows a s
y
stem in which the controller supports two ph
y
sical banks of
SDRAM memor
y
, a 32-bit Local Bus with Boot ROM and two other devices , and a 32-
bit PCI Bus. If t he CPU and con troller shown he re are t he main CPU and the main PCI
controller in the s
y
stem, the control ler can perf orm all (or an
y
) of the PCI Central
Resourc e functi ons for other PCI dev ices, and the CPU can run the PCI Confi
g
urati on
Space c
y
cles for all PCI devic es in the s
y
stem .
If the VR5000 CPU has a secondar y cache, the controll er monitors cache hits. An
optional Serial EEPROM provides mode data to the CPU at reset. If the EEPROM is
not used, the contr oller itself can confi gure the CPU with a default mode sequence.
Figure 3: Single-Controll er, 64-Bit PCI-Bus Confi guration With Memory-Bus Buffer
Figure 3 shows a system in which the controller supports the maximum of three phys-
ical loa ds on the memory bus—two physi cal banks of SDRAM memory plus one r ow of
tran sceiver s, whi ch in turn suppor t add iti onal de vi ces. Si gna ls t hat wer e u sed in Figur e
2 for a the 32-bit Local Bus a re conf igured here to be the high addr ess and data bits for
a 64-bit PCI Bus.
Only t he address and data signals to no n-SDRAM loads on the memory bus need t o be
buffered. The chip-selects for t hese devices need not be buffer ed, becaus e each of
these bits supports only a single load.
Figure 4: Single-Cont roller, 64-Bit PCI-Bus Confi guration
Figure 4 is simil ar to Figure 3, but shows a system in which the contr oller support s
more than the maxi mum of th ree phys ica l lo ads on the memor y bus. If mor e than thr ee
loads are placed on the memor y bus, the bus will slow down. Such configurations
require eit her a CPU SysClock slower than 100 MHz or b uffering on the mem ory bus,
as is done i n Figur e 3.
Figure 5: Intell igent PCI Peripher al Configuration (St and-Alone Mode)
Figur e 5 shows a system in which a VRC50 74 cont rol ler is an intell igent peripheral to a
Main CPU and its associated PCI host bridge. The VRC5074 contro ll er is on a PCI
board with direc t connection to its own VR5000 CPU, supportin g one or two physical
banks of SDRAM on t he memory bus plus up to eight other devices on the Loca l Bus.
The daughter board connects to the mai n system controller over a 32-bit PCI Bus.
Accesses via the Main Controll e r to its resources can proceed sim ultaneously with
accesses via the VRC5074 controller to i ts resources, except when two PCI Bus mas-
ters attempt to access the same resource simultaneously via the shared PCI Bus.
In such a system, the main system cont roller would typically act as th e PCI Ce ntral
Resourc e, and the main system CPU woul d run the PCI Configurati on Space cycles for
all PCI devices in the system. This is called a
stand-alone
configurati on because the
VRC5074 controller does not per form the PCI Central Resource functions.
Figure 6: PCI Peripheral Configuration With No CPU (Stand-Al one Mod e)
Figure 6 shows a system in whic h the controller is placed on a PCI daugh ter board
without i ts own CPU. As in Figure 5, the con tr oller supports one or tw o physical ban ks
of SDRAM on the memor y bus plus up to eight ot her devices on the Loc al Bus. The
daughter board connects to the mai n system controller over a 32-bit PCI Bus.
Here aga in, the mai n system controll er acts as the PCI Central Resour ce, and the ma in
syst em CPU runs th e PCI Configur ation Space cycles for al l PCI devices in the syst em.
This is also called a
stand-alone
configu ration, because the VRC5074 controller does
not provide the PCI Central Resource functions.
Figure 7: Multi-Cont roller Confi guration W it h Dual PCI Buses
Figur e 7 shows a system i n which one VR5000 CPU is attached directly t o two VRC5074
controllers. In this example, one controller is config ured to support a 32-bit PCI Bus
whil e the other contr oller supports a second, separate, 64 -bit PCI Bus. Either cont roller
can support one or two physi cal banks of SDRAM, and the controller supporti ng the
32-bit PCI Bus can have up to seven other devices on its Local Bus. A simi lar multi-
configuration could be used to att ach one or more VRC5074 controllers and one or
more ASICs to a single CPU.
If the VR5000 CPU is the main system CPU, it would run t he PCI Configurati on Space
cycl es for all PCI devi ces in the syst em, and each of the two VRC5074 controll ers would
provide PCI Central Resource functions for its assoc iat ed PCI Bus.
2.3
Terminology
# as a suffi x on a si
g
nal name means active-Low. Si
g
nals wi thout this suffix are
active-Hi
g
h.
0x
means a hexade cimal number.
assert
means to drive a si
g
nal to its active stat e (active- Low or act ive-H i
g
h).
b
means bit, or a binar
number.
B
means b
y
te.
controller
means the VRC5074 S
y
stem Controller.
dword
or
doubleword
means 8 b
y
tes. This definition i s MIPS-c om patible and
differs from the
PCI Local Bus Spec if ication
, where a dword is 4 b
y
tes.
external agent
means an
y
lo
g
ic devi ce directl
y
connected to the CPU that
supports CPU requests.
external device
means an
y
lo
g
ic device, ot her t han the CPU, that is conne cted to
t h e con t r o l l er.
flushed
is not used, because it is an am bi
g
uous term (it means either write-back
or discar d ).
h
means a hexadecimal nibble.
Local Bus
means the controlle r’s Loc al Bus, not the PCI Local Bus.
Main Contro ll er
means the controller directl
y
connected to t he main CPU in a
s
y
stem. Onl
y
the Main Controller should run PCI Confi
g
urati on Space c
y
cles.
Mb
means me
g
abit.
MB
means me
g
ab
y
te.
memory
(unless otherwise modified) means memor
y
attached to the controller.
module
means a set of chips, as in a SIMM or DIMM.
n
means an inte
er.
negate
means to drive a si
g
nal to its inactive state. See
assert
, above.
PCI Stand-Alone Mode
means the controll er’s operatin
g
mo de w h en i t i s not
providin
g
the PCI Central Resource functions for the s
y
stem.
qword
or
quadword
means 16 b
y
tes. Thi s definit ion is MIPS-compatible and
differs from the
PCI Local Bus Spec if ication
, where a qword is 8 b
y
tes.
SDRAM
means s
y
nchronous DRAM.
word
means 4 b
y
tes. This definition is MIPS-compatible and differs from the
PCI
Local Bus Specifica tion
, where a
word
is 2 b
y
tes.
2.4
Reference
Documents
Th e fo ll o w in
g
docume nts form a part of this data sheet.
Vr5000 Microprocessor User ’s Manual, Revision 1.1
(NEC E lectronics , Inc.,
Document No. U11323EU1V0UM00).
Vr5000 Bus Interf ace User’s Manual, Revi sion 1.1
(NEC Electronics, Inc.,
Document No. U11322EU1V0UM00).
CB-C9 Multipl ying Asynch rono us PLL (APLL) Data Sheet, Preliminar y, November
1996
(NEC Elect ronics, In c.).
CB-C9 ASIC Famil y 0.35 Micron Standard Cell Sp ecification V ersion 1.1a Analog
PLL for Clock Skew Control - AAPLNIL, Preliminary
(NEC Electronics, Inc.).
CB-C8VX/VM ASIC Family 0.5 mic ron Standard Cell User’s Manu al, Mega
Function NY16550L UART, Preliminary, 4 October 1996
(NEC Elect ronics, In c.).
DDB-V
RC
5074 Singl e Board Computer Specif ication
(NEC Electronics, Inc.).
PCI Local Bus Specification, Revision 2.1
(Peri pheral Compone nt Interconnect
Special Interest Group).
3.0 Signal Summary
The cont roller has 35 0 sig nals, 124 power or grou nd pins, and 26 no-c onnects or blank
pins, for a t otal of 500 pi ns. Table 1 t hrough Table 6 summari ze si gnal funct ions. An “#”
suffix on a signal name means active-Low. The pinouts are shown in Section 17.0 on
page 197.
Table 1: CPU-Bus Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
Pulldown
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
BigEndian I/O No HiZ 0 25 3 Endian Mo de. Thi s s ignal is no rmall y an in put,
jus t as it is to the CPU. It sp ec ifies the endi an
mod e of t h e C PU inter face (bi g-en dia n = Hig h,
little-endian = Low). The input from this signal
is ORed with th e Endian Bit (EB) of the Seri al
Mode EEPROM sequence to specify the
CPU ’s endian mode (S ec tion 12.4.2) .
As an output, this signal is the chip-select for
the Serial Mode EEPROM (Section 12.4.1).
The signal is also an output during the wiggl e-
mode test (Section 15.0).
CntrValid# I/O No HiZ external
pullup 100 50 6 Controller Output Valid. Output from the
con troller indicating valid infor m atio n on
SysAD bus, except tha t it is an input in mul ti-
con troller configur ation s (Section 5.3.4) . The
sig nal connects to the ValidI n# s ignal on the
CPU .
CntrVccOk ONo Low 0 50 6 Con t roller Vc c O K. Output fr om the control ler
initial iz ation logic, indi c ating that the CPU can
read the initialization (mode) bits. CntrVccOk is
held low by VccOk until the controller
initial iz ation logic has r ead th e S er ial Mode
EEPROM (Section 12.4.2).
ColdReset# ONo Low 0 50 6 Col d Reset . Asserted w hen VccOk is negated
or on a so ft ware cold res et (Section 5.5.1).
Negated synchronously wit h S y s Clock, 64K
clocks after CntrVccOk is asserted.
CPUValid# INo HiZ CPU Output Valid. Input from the CPU
indicating valid information on SysAD bus. This
sig nal connects to the ValidO ut# si gnal on t he
CPU.
Int#[5:0] O No HiZ exter nal
pullup 100 50 6 Maskable Interrupts. Co ntroll er interrupts to
CPU.
MCWrRdy# O No High 50 50 6 Multi-Controller Write Ready. Output from
con troller indica ting w hen it c an acc ept a CPU
wri te . Th e signal is used onl y in multi- contro ller
con figurations ( S ec tio n 5.3.4) .
ModeClock IYes Mode Clock. SysClock divi ded by 256.
Provided by the C PU (Section 12.4.2).
ModeOut O Yes High 6 Mod e Data. Serial boot-mo de data for CP U
initial iz ation. The data is generated by the
con tro ller, or it is g enerated f rom a Seria l Mode
EEPROM and monitored and corrected by the
controller (Section 12.4). This signal connects
to th e M odeIn si gnal on t he CP U.
NMI# O No HiZ external
pullup 100 50 6 Non-Maskable Interrupt. Controller non-
maskable interrupt to CPU.
PROM_CLK O Yes Low 5 50 6 PROM Clock. O utpu t cloc k t o the Serial Mode
EEPROM (Section 12.4.2).
PROM_SD I/O Yes HiZ external
pullup 5506PROM Seri al Data. The contro ller dr iv es
addr ess and co mmand s ou t and re ceiv es CPU
seri al boot- mode da ta in on this signal , which is
connected to the Seri al Mode EEPROM
(Sectio n 12.4.2). The signal m us t b e pulle d up
if the Serial Mode EEPROM is not
implemented.
Reset# ONo Low 0 50 6 Reset. Asserted when VccOk is negated or on
pro gr am m ed warm r es et. Negated eith er 64
clocks after ColdReset# is negated for power-
up and cold resets, or 64 clocks after bei ng
asserted due to a warm reset (Section 5.5.1).
ScDOE# O No HiZ external
pulldown 50 50 6 Secon dary - Cache Dat a Out pu t E nable . T he
controller negates ScDOE# duri ng cache
misse s, wh en t he con trolle r i s p rov iding d ata t o
the CPU, and asserts ScDO E # to indicat e th at
it will s upply t he last dword of a r ead response
in the next clock.
ScMatch INo Se condary-Cache Match. Hit/miss indication
from secondary cache fo r current request.
Valid two clocks a fter the address is driven.
ScWord[1:0] I/O No 50 50 6 Secondary-Cache Word. Double wor d offset
within the s ec ondary cac he line.
SysAD[63:0] I/O No HiZ 100 50 6 System Ad dres s and Dat a. System
multiplexed address/data bus. The controller
uses the SysAD[63:0] bits and the
SysCmd[2:0] bits to intern ally generate byte
enables, per Ta ble 4.14 of the
VR5000 Bus
Int er face User’s M anual
.
SysADC[7:0] I/O No HiZ 100 50 6 System Ad dres s and Dat a Check. System
address/data check bus (one even-parity bit
per SysAD byte).
SysClock INo System Cl ock. The c ontrol ler has an intern al
phase-locked loop (PLL) attached to SysClock.
SysCmd[8:0] I/O No HiZ 100 50 6 System Co mman d. The command and o r
data-type for the cu rrent bus cycle.
VccOk IYes Vc c OK. Input from external analog circuit
indic ati ng that power to the CP U an d co nt roll er
has been above 3.135 volt s for more t han 10 0
mil lis econds. The as s ertion of this signal
begins the initialization s equen c e.
WrRdy# I/O No High 50 50 6 Write Ready. Ou tput from the con troller
indic ati ng when it c an ac c ept a CP U wr ite,
except that it is an input in m ulti - c ontrol ler
con figurations ( S ec tio n 5.3.4) .
Table 1: CPU-Bus Signals (continued)
Signal I/O 5V
Tolerant Reset
Value Pullup/
Pulldown
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
Table 2: Memory-Bus Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
BootCS# O Yes High 5 50 6 Boot Memory Chip-S elect. The devi c e
corresponding to thi s ch ip- s elect may be
located either on the Local Bus or the Memory
Bus, as specified in the MEM/LOC bit of the
BOOTCS Physical Device Add ress Register
(PDARs, Section 5.4). This signal is also listed
in Table 4.
DQM O No High 0 50 12 Data Qual ifie r M ask. SDRAM chip data I/O
qualifi er m as k .
MAbank0[14:0] O No Low 100 50 12 Memory Address, Bank 0. Mul tiple x ed r ow/
column address for memory bank 0 (even
bank).
MAbank1[14:0] O No Low 100 50 12 Memory Address, Bank 1. Mul tiple x ed r ow/
column address for memory bank 1 (odd
bank).
MCAS#[1:0] O No High 100 50 12 Mem ory Column Address S t robes. These
signals are for physical banks 1 and 0,
respect iv ely, an d ar e logically disti nc t.
MDC[7:0] I/O No HiZ 100 50 6 Memory Data Check. Even-parity or ECC
syndrome bits for M D[63:0].
MCS#[1:0] O No High 100 50 12 Memory Chip-Selects. These signals are for
phy s ic al banks 1 and 0, re s pec tive ly , and are
logic ally disti nc t.
MD[63:0] I/O No HiZ 100 50 6 Memory Data.
MRAS#[1:0] O No High 100 50 12 Mem ory Row Addres s S t robes. These
signals are for physical banks 1 and 0,
respect iv ely, an d ar e logically disti nc t.
MRDY# IYes Memory Ready. Access-ready timing for non-
SDRAM memory (such as Fla sh). The timing
associated with such de vices can,
alternatively, be specified in the Memory
Access Timing Register (ACSTIME), as
des c r ibed in Sec tio n 6.6.2.
MWE#[1:0] O Yes High 100 50 12 Memory Write-Enables. T hese signa ls are for
phy s ic al banks 1 and 0, re s pec tive ly , and are
logic ally disti nc t.
Table 3: PCI-Bus Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
ACK64# I/O Sa m e as LOC_C LK in Table 4. PCI Acknowledge 64-Bit Transfer. Asserted
by the c ontrolle r when it is ready to dr iv e data
as a tar get. This signal is car r ied on the
LOC_CLK pin when P CI64# is as s er ted.
C/BE#[3:0] I/O Yes 33 or 66 50 12 PCI Command and Byte-Enables. During th e
addr es s phase of a tra ns ac tion, the si gnals
carry the bus command. During the data phase,
they carry byte-enables for the data on
PCI_AD[31:0].
C/BE#[7:4] I/O Sam e as LOC_A[ 3:0] in T able 4. PCI Comma nd and Byte- E nables (64 -bit).
These signals are c ar r ied on the LOC_A[4:0]
pins when PCI64# is a s s er ted.
DEVSEL# I/O Yes exter nal
pullup 10 12 P CI Device Sel ect. Asserted by the controller
to indicat e that it is the targ et of the cur r ent
acce ss. Samp led by the control ler to determi ne
whet her any d evice is responding to the cu rrent
access.
FRAME# I/O Ye s ext ernal
pullup 10 12 PCI Cycle Frame. Asserted by the controller as
mast er to ind ic ate the durat ion of an ac c es s .
Sampled by the controller to determine the
duration of an access.
GNT#[4:0] I/O Yes 2 12 PCI Bus Gran t . Asserted by the controller as
PCI Central Resource (PCICR # asserted) to
indic ate that a req ues ting dev ice m ay c ontrol
the PCI Bus. In Stand-Alone Mode, (PCICR#
negated and GNT#[4:1] ar e unused inputs )
GNT #[0] is sa m pled by the contr oller to
determine if it has been granted its request on
REQ#[0] for control of the PCI Bus.
IDSEL IYes PCI Initialization Device Select. Sel ects the
con troller as the target for Co nfigur ation Read
and Write transaction s . During Central
Resource operation (PCICR# asserted), IDSEL
outp uts may b e provided b y resi stively couplin g
to PCI _AD[31 :1 6] si gnals. See sectio n 3.7.4. of
the PCI Local Bus Spec ifi c ation, Revision 2. 1.
INTA# I/O Ye s ext er nal
pullup 012
PCI Interrupt A. I NTA# is an output if PCI CR#
is n egated. INTA# is n ever d riven Hi gh (pseudo
open- drain). See Section 5.5.2 and S ec tion
5.5.3 for interrupt prioritization and enabling.
INTB# I Yes external
pullup PCI Interrupt B. See Section 5.5.2 and Sect ion
5.5.3 for interrupt prioritization and enabling.
INTC# I Yes external
pullup PCI Interrupt C. See Section 5.5.2 and Sect ion
5.5.3 for interrupt prioritization and enabling.
INTD# I Yes external
pullup PCI Interrupt D. See Section 5.5.2 and Sect ion
5.5.3 for interrupt prioritization and enabling.
INTE# I Yes external
pullup Au xiliary Interrupt. See Section 5.5.2 and
Sect ion 5. 5.3 for interrupt prioritiz ati on and
enabling.
IRDY# I/O Ye s ext er nal
pullup 10 12 PCI Initiator Ready. Asserted by t he controller
as mas ter to indic ate that i t is dri ving vali d data
on a wr ite, or that it is pr epared to accept dat a
on a re ad. Sampled by t he c ontro ller in
conjunction with TRDY#.
LOCK# I/O Yes external
pullup 10 12 P CI Exclusive Acces s . Indicates an atomic
operation that may take multiple bus
transactions to complete.
M66EN IYes PCI 66 MHz Enable . Enables 66 MHz
oper atio n of the PC I Bus . When M66EN is
asserted, all devices on the PCI Bus must run
at 66 MHz .
PCI_AD[31:0] I/O Yes 33 or 66 12 PCI Multiplexed Address and Data.
PCI_AD[63:32] S ame as LOC_AD[31: 0] in Table 4. PCI Multiplexed Address and Data (64-bit). If
PCI64# is as s er ted, bits 63 :32 of the PCI Bus
are carried on the LOC_AD [31:0] pins.
PAR I/O Yes 33 or 66 12 PCI Parity. The even-parity bi t f or
PCI_A D[3 1:0] and C/ B E #[3:0].
PAR64 I/O Same as LOC_A[ 4] in Table 4. PCI Parity (64-bit ) . The ev en- parit y bit for
PCI_AD[63:32] and C/BE#[7:4]. Only valid
when P CI64 # is as s er ted .
PCI64# IYes PCI 64- Bit. Wh en P CI64 # is as s er ted , 64-bit
PCI- B us operation is enabled and Loc al Bus
oper atio n is di sabl ed. ( Sect ion 7.6 and Se cti on
8.5). In this case:
• the LOC_AD[31:0] pins ca rry the
PCI_A D[6 3:32] signals.
• the LOC_A[3:0] pins carry the C/BE#[7:4]
signals.
• the LOC_ A [4] pin car r ies the PAR64 signal.
• the LOC_ A LE pin car r ies the REQ64#
signal.
• the LOC_ CLK pin carr ies the ACK64#
sig nal.
PCI64 # is a s tat ic sign al a nd must be va lid and
unc hanging during and after re s et.
PCICR# IYes PCI Ce ntral Reso ur ce. I dentifi es the co ntroller
as the P CI Cen tral Resource ( S ec tio n 7.8). If
PCICR# is asserted:
• PCLK[4:0] are all outputs.
• REQ #[4:0] are al l input s .
• GNT#[4:0] are all outputs.
• INTA# is an input.
• PCI RS T# is an output .
• The c ontrolle r co nfigur es 64- bit PC I
oper atio n with its RE Q64# output.
• The controller generates P CI Conf igurat ion
Space cycles.
PCICR# is a st atic sig nal and must be valid and
unc hanging during and after reset. See Sect ion
7.8 f or detai ls .
PCIRST# I/O Yes 0 12 PCI Reset. PC IRST# is an input, ex c ept that it
is an out put if PCIC R# is asserted. See Se ction
12.3 for details on PCIRST# during reset.
Table 3: PCI-Bus Signals (con ti nued)
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
PCLK[4:0] I/O Yes 133 12 PCI Clock. The maximum frequency can b e 66
MHz. When PCI CR# is nega te d, PCLK [0] is a n
input and PC LK [4:1] a r e floated. When
PCICR # i s ass er ted, PCLK[ 4:0] ar e all out puts.
The cont r oller alwa y s us es P CLK[ 0] as it s P CI-
Bus clock.
PCLKIN IYes PCI Clock Input . External input for PCLK[4:0].
PERR# I/O Yes external
pullup 012PCI Parity Error. Reports even-parity da ta
errors across the PCI_AD[31 :0], C/BE#[3:0]
and P AR sign als, o r acros s the PC I_ AD[63:32 ],
C/BE #[7:4], and PA R64 signals.
REQ#[4:0] I/O Yes 5 12 PCI Bus Request. Sam pled by the con troller
as PCI Central Res ourc e to determine if a P CI
device wis hes to con trol the PCI Bus. In Stan d-
Alone Mode, the controller asserts REQ#[0] to
req ues t control of the PCI Bus , and RE Q#[4: 1]
are unused in puts. Co mpare t he description of
GNT#[4:0].
REQ64# I/O Same as LOC_ALE in Table 4. PCI 64-Bit Request. Asserted by the controller
when it is ready to drive dat a as a m as ter. This
signal is carried on the LOC_ALE pin when
PCI64# is asserted.
SERR# I/O Yes external
pullup 012PCI S yst em Error . Repor ts even- parit y
address errors on PCI_AD[31 :0], C/BE#[3:0]
and PAR, or on PCI_AD[63:32], C/BE#[7:4] or
PAR64; data errors on the Special Cycle
command; or any othe r catastrophic system
error. SERR# is never dr iv en High (pseudo
open-drain).
STOP# I/O Ye s ext er nal
pullup 10 12 PCI Stop. Asserted by the control ler as target
to requ est that a t ransf er be st op ped. Sam pled
by the c ontrolle r in c onjunct ion wit h TRDY#
TRDY# I/O Ye s ext er nal
pullup 10 12 P CI Target Re ady. Asserted by th e controller
as tar get to indicat e that it is driv ing valid data
on a re ad, or that it is prepare d to accept data
on a write. Sampled by the controller in
conjunction with IRDY#.
Table 3: PCI-Bus Signals (con ti nued)
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
Table 4: Local-Bus Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
BootCS# O Same as BootCS # in Table 2. Boo t Me mory Chip-Se lect. The device
corresponding to thi s ch ip- s elect may be
located ei ther o n the Local Bu s or the Memory
Bus, as specified in the MEM/LOC bit of the
BOOTCS Physical Device Add ress Register
(PDAR), Section 5.4.
DCS#[8:2] I/O Yes HiZ 10 50 6 Device Ch ip-Selec ts (or other fu nctions). The
devices corresponding to the se chip-selects
may be located e ither on the Local Bus o r the
Memory Bu s, as specified in the MEM/LOC bi t
of th e corresponding Physical D evice Address
Register (PDAR), Section 5.4.
After res et, soft war e can c onfig ur e the
DCS #[8:2] signa ls as follo ws :
• DCS#[2] = UART_RTS# (active-low
output) or general-purpose I/O.
• DC S #[3] = UART_CT S # ( ac tive-low in put)
or ge ner al-purpos e I/O.
• DC S #[4] = UA RT_DCD# (act iv e- low input)
or ge ner al-purpos e I/O.
• DCS#[5] = UART_XIN (clock input) or
general-purpose I/O.
• DCS#[6] = DMA _A CK # (ac t iv e- low output)
or ge ner al-purpos e I/O.
• DCS#[7] = DMA_REQ# (active-low input)
or ge ner al-purpos e I/O.
• DCS#[8] = DMA_EOT# (active-low input)
or ge ner al-purpos e I/O.
See the following s ecti ons for det ails:
• Additional UART Signals, Section 10.2.
• DMA Hardware Handshaking, Section 9. 4.
• De v ic e Chip-S elect Function Registe r
(DC S FN), Section 8.6.3.
• De v ic e Chip-S elects as I/O Bits Register
(DCSIO), Section 8.6.4.
LOC_A[4:0] I/O Yes Low 66 50 12 Local - Bus Byte - E nables and Low - Address
Bits (or other functions). During the f irst clock
of a Local-Bus cycle , LOC_A[3:0] carry active-
low by te-enables ( in effec t, BE#[3:0] for the
Loc al B us ) . During the rem ainder of a non-
block bus cycle, LOC_A[4:0] carry t he f ive lo w-
address bits (the same bits that were carried
on L OC_AD[4:0] bit s when LO C_A LE was
active).
The f unc tio n of the LOC_A[4:0] si gnals
changes whe n a Local-Bus master takes
control of the Local Bus (See Section 8.4.1).
If PCI64# is asserted :
• LOC_A[3:0] = PCI -Bus C/BE#[7:4].
• LOC_A[4] = PCI -Bus PAR64.
See Section 8.5 for detai ls .
LOC_AD[31:0] I/O Yes HiZ 66 50 12 Loc al-Bu s Address and Data (or other
functions). Local 32-bit mul tiple x ed address /
data bus.
If PCI64# is asserted :
• LOC_AD[31:0] = PCI-Bus PCI_AD[63 :32].
See Section 8.5 for detai ls .
LOC_ALE I/O Yes Low 66 50 12 Local-Bus Address Latch Enable (or other
function). Asserted in the same clock as the
access.
If PCI64# is asserted :
• LOC_ALE = PCI-Bus REQ64# .
See Section 8.5 for detai ls .
LOC_BG#
or
HLDA
O Yes High 5 50 6 Local-Bus Grant (or othe r function). Indicates
that the cont r oller has relinquished the Local
Bus t o a r equesting master on the Local Bus.
This s ignal becomes HLDA in Intel bus-
arb itrat ion mode ( S ec tion 8.6.1) .
LOC_BGACK# IYes Local-Bus Grant Acknowledge. Indi ca te s
that an Local-Bus ma ster has taken control of
the Local Bus .
LOC_BR#
or
HOLD
I Yes ex ternal
pullup L ocal-Bus Request (or ot her function) .
Asserted by a Local-Bus master to request
control of the L ocal Bus. This signal becomes
HOLD in Intel bus-arbitration mode (Section
8.6. 1) . LOC_B R# may r equire an external
pullup, depending on the application.
LOC_CLK O Yes High 100 50 12 Loc al-Bus Clock ( or other func tio n) .
Generat ed by c ontroller . T he frequency is
SysClock divided by 4 or by 2.
If PCI64# is asserted :
• LOC_CLK = PCI-Bus ACK6 4# .
See Section 8.5 for detai ls .
LOC_FR# I/O Yes High 10 50 6 Local- Bus Frame. Indicates that a Local Bus
cycle is taking place.
LOC_RD# I/O Yes High 10 50 6 Local - Bus Re ad. Used fo r Local Bus devices
that im plem ent sepa rat e re ad an d w rit e c ontrol
signals.
LOC_RDY# I/O Yes High e xter nal
pullup 10 50 6 Local-Bu s Ready. Acknowledge signal for
devices on the L ocal Bus that do not re spond
in a fixed amount of t im e, as specifi ed in the
Loc al B us Chip-S elect Timing Register s
(LCSTn), Section 8.6.2. L OC_RDY# may
req uir e an external pullup, de pendin g on the
application.
LOC_WR# I/O Yes High 10 50 6 Local-Bus Write or Read. Us ed as Writ e,
along wit h LOC_RD#, for dev ic es that
imp lem ent se par ate re ad and writ e c ontrol
sig nals. Used as W r ite/Read# for devic es tha t
imp lem ent a si ngle write/read control si gnal.
Table 4: Local-Bus Signals (continued)
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
Table 5: DMA Hardware-Handshake Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
DMA_ACK# O Same as DS C#[6 ] T able 4. DMA Acknowledge. Used by t he control ler to
ac k nowledge a DMA t r ans fer request from an
external device. If DMA_ACK# is used,
however , DMA_REQ# must als o b e us ed.
This signal can be implemented by software,
after rese t, as a n alternative to DSC #[6] signal.
Se e S ec tion 9.4 for de tails.
DMA_REQ# I Same as DS C#[7 ] T able 4. DMA Request. Used by an ext er nal device t o
request a DMA transfer.
This signal can be implemented by software,
after rese t, as a n alternative to DSC #[7] signal.
Se e S ec tion 9.4 for de tails.
DMA_EOT# I Sam e as DS C#[8] T able 4. DMA End of Tran sf er. Used by an exte r nal
dev ic e to ab or t a DMA transfe r , but only if the
DM A so ur c e is doing the handshaking.
This signal can be implemented by software,
after rese t, as a n alternative to DSC #[8] signal.
Se e S ec tion 9.4 for de tails.
Table 6: Serial-Port (UART) Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
UART_CTS# I Same as DS C#[3] T able 4. Seri al-P ort Cl ear To Se nd. Th is sig nal can b e
implemented by software, after reset, as an
alt ernati ve to DS C#[3] si gnal. S ee Sect ion 10.2
for deta ils .
UART_DCD# I Same as DS C#[4] T able 4. Serial-Port Data Carrier Detect. This signal
ca n be im plement ed by s oftware, after reset,
as a n altern ative t o DS C#[4] signal. See
Section 10.2 for details.
UART_DSR# I Yes HiZ Serial-Port Data Set Ready.
UART_DTR# I/O Yes HiZ internal
pulldown
(50K ohm)
1506Se ri al-P ort Dat a T e rmi nal Ready. Thi s s ignal
is s am pled dur ing r ese t (Sectio n 12. 4) in order
to set the c ontrol ler ’s ID number in a mult i-
controller configuration (Section 5.3).
UART_RTS# O Same as DS C#[2 ] T able 4. Seri al-Por t Rea d To Send. This sign al ca n be
implemented by software, after reset, as an
alt ernati ve to DS C#[2] si gnal. S ee Sect ion 10.2
for deta ils .
UART_RxDRDY# I Yes HiZ Serial-Port Receive Data.
UART_TxDRDY# I/O Yes HiZ internal
pulldown
(50K ohm)
1506Serial-Port Transmit Data. This signal is
sampled d uring reset (Section 12.4) in order to
set the controller’s ID number in a multi-
controller configuration (Section 5.3).
UART_XIN I Same as DS C#[5] T able 4. Seri al-Port External Crystal In put. This
signal can be implemented by software, after
re set, as an alt erna tive to DSC#[ 5] sign al. See
Section 10.2 for details.
Table 7: Utility Signals
Signal I/O 5V
Tolerant Reset
Value Pullup/
down
Toggle
Rate
(MHz)
AC
Load
(pF)
DC
Drive
(mA) Description
SMC INo Scan Mode Control. Se lects test type . Low for
normal operation.
TEST# IYes Test-Mode Enable . Enables tes t mode. High
for norm al operat ion.
TEST_SEL IYes Te st S elect. S elects test type. Low for normal
operation.
4.0 Register and Reso urce Summar y
4.1
Re
g
ister Summar
y
Table 8 summarizes the c ontroller’s internal re
g
ister set. This listin
g
is or
g
anized b
y
th e
base-addre ss offset, shown in the left-most column of the table. The base addres s for
the re
g
ister set is specified b
y
the INTCS Ph
y
sical Device Address Re
g
ister (S ection
5.4). Detailed descriptions of each re
g
ister are
g
iven in the sections listed in the ri
g
ht-
most
Reference
column of the table.
The PCI- r e lat e d r e
g
isters are shown in two separate blocks in Table 8. The main PCI-
Bus Re
g
iste rs be
g
in at offset 0x00E0, and the PCI Confi
g
urati on Space Re
g
isters
be
g
in at offset 0x0200. The PCI Confi
g
urati on Space Re
g
ister s can actuall
y
be
accessed via two different methods, as described in Section 7.13.
If
y
ou confi
g
ure the cont roller’ s CPU in terface to oper ate in Bi
g
-Endi an mode (Sect ion
5.2.6), see Section 13.0 for the implications of accessin
g
re
g
ist ers in this mode.
Table 8: Register Summary
Offs et Fr om
Base aRegister Name Acronym Size
(bytes) CPU-Bus
R/W Reset Va lu e Ref eren ce
Physical Device Address Registers (PDAR s)—
See Sectio n 5.4 on pa ge 45
0x0000 SDRAM Bank 0 SDRAM0 8 R/W 0x0 0000 00D0 Section 5.4 on page 45
0x0008 SDRAM Bank 1 SDRAM1 8 R/W 0x0 0000 00D0 Section 5.4 on page 45
0x 0010 Devi c e Chip-S elect 2 DCS 2 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x 0018 Devi c e Chip-S elect 3 DCS 3 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x 0020 Devi c e Chip-S elect 4 DCS 4 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x 0028 Devi c e Chip-S elect 5 DCS 5 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x 0030 Devi c e Chip-S elect 6 DCS 6 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x 0038 Devi c e Chip-S elect 7 DCS 7 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x 0040 Devi c e Chip-S elect 8 DCS 8 8 R/W 0x0 0000 0000 Se c tion 5.4 on page 45
0x0048
reserved
— 8 R 0x 0 0000 0000 —
0x0050
reserved
— 8 R 0x 0 0000 0000 —
0x0058
reserved
— 8 R 0x 0 0000 0000 —
0x 0060 PCI Ad dr es s Wind ow 0 PCIW0 8 R/W 0x0 00 00 00C0 Sec tion 5.4 on page 45
0x 0068 PCI Ad dr es s Wind ow 1 PCIW1 8 R/W 0x0 00 00 00C0 Sec tion 5.4 on page 45
0x0070 Controller Internal
Regis ters and Devices INTCS 8 R/W 0x0 1Fh0 00EF bSection 5.4 on page 45
0x0078 Boot ROM Chip-Select BOOTCS 8 R/W 0x0 1FC0 002F cSection 5.4 on page 45
CPU Interface Registers—
See Sectio n 5.5 on pa ge 50
0x 0080 CPU St atus CPU S TAT 8 R/W 0x0000 0000 0000 0N00 Se c tion 5.5.1 on p age 50
0x 0088 Interrupt Control INTCTRL 8 R /W 0X88 88 8888 8888 8888 Se c tion 5.5.2 on p age 52
0x 0090 Interrupt S tatus 0 INT S TAT0 8 R 0x0000 00 00 0000 0000 Se c tion 5.5.3 on p age 55
0x0098 Interr upt St atus 1 an d CPU
Interrupt E nable INT S TAT1 8 R/W 0x0001 0000 0000 0000 Se c tion 5.5.4 on p age 55
0x 00A 0 Interrupt Clear INT CLR 8 R/W 0x0000 0000 0000 00 00 Section 5.5. 5 on page 56
0x00A8 PCI Interrupt Control INTPPES 8 R/W 0x0000 00 00 0000 0000 Section 5.5.6 on p age 57
0x00B0
reserved
— 8 R 0x 0000 0000 00 00 0000 —
0x00B8
See PCI - B us Registers, below
Me mory-I nterface Re gi st ers—
See Sect ion 6.6 on page 72
0x00C0 Memory Control MEMCTRL 8 R/W 0x0000 00 00 0000 0080 Section 6.6.1 on p age 72
0x00C8 Memory Access Timing ACSTIME 8 R/W 0x0000 0000 0000 001F Section 6.6.2 on page 7 4
0x00D0 Memory Check Error Status CHKERR 8 R 0x0000 0000 0000 0000 Section 6.6.3 on page 74
0x00D8
reserved
— 8 R 0x 0000 0000 00 00 0000 —
PCI-Bus Re g isters—
See Section 7.11 on page 91
0x00E0 PCI Control PCICTRL 8 R/W 0X6000 0000 8000 0000 Section 7.11.1 on page 91
0x 00E 8 PCI Arbiter PCIA RB 8 R/W 0x0050 0011 11 00 003F S ection 7.11.2 on page 98
0x 00F0 PCI Maste r (Initi ator) 0 PCIINIT0 8 R/W 0x0000 0000 0000 8406 Sec tion 7.11.3 on page 101
0x 00F8 PCI Maste r (Initi ator) 1 PCIINIT1 8 R/W 0x0000 0000 0000 8406 Sec tion 7.11.3 on page 101
0x00B8 dPCI Error PCIERR 8 R/W 0x00 00 0000 0000 0000 Section 7.11.4 o n page 103
See also the PCI Co nfigu r ation Sp ac e Registers, star ting at offse t 0x0200 , below
Lo cal-Bu s Registers—
See Sect ion 8.6 on page 120
0x 0100 Loca l B us Confi gur ati on LCNFG 8 R/W 0x0 0000 0000 Se c tion 8.6.1 on p age 121
0x0108
reserved
— 8 R 0x 0 0000 0000 —
0x 0110 Loca l B us Chip-S elect Timing 2 LCS T2 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x 0118 Loca l B us Chip-S elect Timing 3 LCS T3 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x 0120 Loca l B us Chip-S elect Timing 4 LCS T4 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x 0128 Loca l B us Chip-S elect Timing 5 LCS T5 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x 0130 Loca l B us Chip-S elect Timing 6 LCS T6 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x 0138 Loca l B us Chip-S elect Timing 7 LCS T7 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x 0140 Loca l B us Chip-S elect Timing 8 LCS T8 8 R/W 0x0 0000 0000 Se c tion 8.6. 2 on page 122
0x0148
reserved
— 8 R 0x 0 0000 0000 —
0x0150 Device Chip-Select Muxing and
Output Enables DCSFN 8 R /W 0x0 0000 0000 Secti on 8.6.3 on page 1 25
0x 0158 Devi c e Chip-S elect s As I /O B its DCSIO 8 R/W 0x0 0000 0000 Se c tion 8.6. 4 on page 128
0x0160
reserved
— 8 R 0x 0 0000 0000 —
0x0168
reserved
— 8 R 0x 0 0000 0000 —
0x0170
reserved
— 8 R 0x 0 0000 0000 —
0x0178 Local Boot Chip-Select Timing BCST 8 R/W 0x0 003F 8E3F Section 8.6.5 on page 129
DM A Regist ers—
See Section 9.5 on page 133
0x0180 DMA Control 0 DMACTRL0 8 R/W 0x0000 0000 0000 0000 Section 9.5.1 on page 133
0x0188 DMA Source Address 0 DMASRCA0 8 R/W 0x0000 0000 0000 0000 Section 9. 5.2 on page 136
0x0190 DMA Destin ation Address 0 DMADESA0 8 R/W 0x0000 0000 0000 0000 Section 9. 5.3 on page 136
0x0198 DMA Control 1 DMACTRL1 8 R/W 0x0000 0000 0000 0000 Section 9.5.1 on page 133
0x01A0 DMA Source Address 1 DMASR CA1 8 R/W 0x0000 0000 0000 0000 Section 9.5.2 on page 136
0x01A8 DMA Destination Address 1 DMADESA1 8 R/W 0x0000 0000 0000 00 00 Section 9.5.3 on page 136
0x01B0
reserved
— 8 R 0x 0000 0000 00 00 0000 —
0x01B8
reserved
— 8 R 0x 0000 0000 00 00 0000 —
Timer Registers—
See Section 5.6 on page 58
0x01C0 SDRAM Refresh Control T0CTRL 8 R/W 0x0000 0001 0000 0186 Section 5.6.1 on page 58
0x01C8 SDRAM Refresh Counter T0CNTR 8 R/W 0x0000 0000 0000 0000 Section 5.6.2 on page 59
0x01D0 CPU-Bus Read Time-Out Control T1CTRL 8 R/W 0x0000 0000 0000 0000 Section 5.6.3 on page 59
0x01D8 CPU-Bus Rea d Time-Out
Counter T1CNTR 8 R/W 0x0000 0000 0000 0000 Section 5.6.4 on page 60
0x 01E 0 Gener al-Pur pose Timer Contr ol T2CTRL 8 R/W 0x0000 0000 0000 0000 Se c tion 5.6.5 on page 60
0x 01E 8 Gener al-Pur pose Timer Counter T2CNTR 8 R/W 0x0000 0000 00 00 0000 Section 5.6.6 on p age 61
Table 8: Register Summary (continued)
Offs et Fr om
Base aRegister Name Acronym Size
(bytes) CPU-Bus
R/W Reset Va lu e Ref eren ce
0x01F0 W atchdog Timer Control T3CTRL 8 R/W 0x0000 0000 0000 0000 Section 5.6.7 on page 61
0x01F8 W atchdog Timer Counter T3CNTR 8 R/W 0x0000 0000 0000 0000 Section 5.6.8 on page 62
PCI Configuration Space Registers—
See Section 7.13 on page 105
0x0200 ePCI Vendor ID VID 2 R 0x1033 Section 7.13.1 on page 107
0x0202 ePCI Device ID DID 2 R 0x005A Section 7.13.2 on page 107
0x0204 ePCI Command PCICMD 2 R/W 0x0000 or
0x0006 fSection 7.13.3 on page 107
0x0206 eP CI Status PCIS TS 2 R/W 0x02A 0 Se c tion 7.13.4 on page 108
0x 0208 ePCI Revis ion I D REVI D 1 R 0x01 Se c tion 7.13.5 on page 109
0x 0209 ePCI Class Code CLASS 3 R 0x06 0000 Section 7.13.6 on page 110
0x020C ePCI Cache Line Size CLSIZ 1 R/W 0x00 Section 7.13.7 on page 110
0x020D eP CI Latenc y Timer MLTIM 1 R /W 0x00 Section 7.13 .8 on page 110
0x 020E ePCI Header Type HTYP E 1 R 0x00 Se c tion 7.13.9 on page 110
0x 020F eBIST
unimplemented
1 R 0x00 —
0x0210 ePCI Base Address Register
Control BA RC 8 R/W 0x0000 00 00 0000 00 04 Se c tion 7.13.10 on page
110
0x 0218 ePCI Bas e A ddr ess Registe r 0 BA R0 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0220 ePCI Bas e A ddr ess Registe r 1 BA R1 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0228 ePCI C ardbus CIS Pointer
unimplemented
4 R 0x00 00 0000 —
0x 022C ePCI Su b-System Vendor ID SSVID 2 R/W
depends on vario us
conditions
Se c tion 7.13.1 1 on page
111
0x 022E ePCI Sub-System ID SSID 2 R/W
depends on vario us
conditions
Se c tion 7.13.1 2 on page
111
0x 0230 eExpa nsion ROM Base Address
unimplemented
4 R 0x00 00 0000 —
0x 0234 e
reserved
—6R0x00 —
0x023C ePCI Interrupt Line INT LIN 1 R/W 0xFF Se c tion 7.13.1 3 on page
112
0x 023D ePCI Inter r upt Pi n INTPIN 1 R 0x01 Section 7.13.14 on page
112
0x 023E ePCI Min_Gnt
unimplemented
1 R 0x00 —
0x023F ePCI Max_Lat
unimplemented
1 R 0x00 —
0x0240 ePCI Ba s e A ddr ess Register 2 BAR2 8 R/W 0x0000 0000 00 00 0000 Section 7.13.10 on page
110
0x 0248 ePCI Bas e A ddr ess Registe r 3 BA R3 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0250 ePCI Bas e A ddr ess Registe r 4 BA R4 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0258 ePCI Bas e A ddr ess Registe r 5 BA R5 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0260 ePCI Bas e A ddr ess Registe r 6 BA R6 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0268 ePCI Bas e A ddr ess Registe r 7 BA R7 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0270 ePCI Bas e A ddr ess Registe r 8 BA R8 8 R/W 0x0000 0000 0000 00 00 Sec tion 7.13.10 on page
110
0x 0278 ePCI Ba se Address Register
BOOT BARB 8 R/W 0x00 00 0000 0000 00 04 Sec tion 7.13.10 on page
110
Table 8: Register Summary (cont inued)
Offs et Fr om
Base aRegister Name Acronym Size
(bytes) CPU-Bus
R/W Reset Va lu e Ref eren ce
4.2
Resource-
Accessibility
Summary
Table 9 summarizes the acc e ssibilit
y
of contr oller resources to the CPU and DMA
lo
g
ic.
0x0280:
0x02FF
reserved
—128R0x00 —
Serial-Port Registers—
See Section 10.4 on page 139
0x 0300 UART Rec eiver Data Bu ff er UARTRBR 1 R 0x0000 0000 0000 00 x x Section 10 .4.1 on page 139
0x0300 UART Transmitter Data Holding UARTTHR 1 W 0x0000 0000 0000 00xx Section 10.4.2 on page 139
0x 0308 UART Inter r upt Enable UAR TI E R 1 R/W 0x00 00 0000 00 00 0000 Section 10 .4.3 on page 139
0x0300 UART Divisor Latch LSB UARTDLL 1 R/W 0x0000 0000 0000 00xx Section 10.4.4 on page 140
0x 0308 UART Div isor Latch MSB UARTDLM 1 R/W 0x0000 0000 00 00 00xx Section 10.4.5 on page 140
0x 0310 UART Inter r upt ID UAR TI IR 1 R 0x0000 0000 0000 0001 Se c tion 10 .4.6 on page 140
0x 0310 UART FI FO Control UAR TF CR 1 W 0x0000 00 00 0000 0000 Se c tion 10 .4.7 on page 141
0x 0318 UART Line Contro l UARTL CR 1 R/W 0x0000 0000 0000 00 00 Sec tion 10 .4.8 on page 142
0x0320 UART Modem Control UARTMCR 1 R/W 0x0000 0000 0000 0000 Section 10.4.9 on page 143
0x 0328 UART Line Status UARTLSR 1 R /W 0x0000 0000 0000 0060 Se c tion 10 .4.10 on page
144
0x 0330 UART M odem Status UARTMSR 1 R/W 0x0000 0000 0000 0000 Se c tion 10 .4.11 on page
144
0x0338 UART Scratch UARTSCR 2 R/W 0x0000 00 00 0000 00xx Section 10.4.12 on page
145
a. At r eset, the base address for the regist er set of a singl e controller, or t he Main Contr oller in a multi-contro ller c onfig ura-
tion, is 0 x 0 1FA0 0000 . For the base addr ess of ot her cont roll ers in a mul ti-controller configuration, see Section 5.3.
b. The “h” nibble in this reset value change s in multi -controller configurations (Sect ion 5.3).
c. The BOOTCS reset value depends on the size of the PCI bus, s ize of boot ROM, and other conditions. See Section
5.4.2 and Section 5.3.
d. This is a non-consecutive address.
e. These are the controller’s in tern al addr esses for accessing the PCI Configuration Spa c e Registers. To obtain these
addresses, a value of 0x0200 has been added to the off s et of t he Configuration S pace Registers s hown in Table 26 on
page 105. There are two paths for accessing each of these registers. See Section 7.13.
f. PCICMD resets to 0x0000 when PCICR# is negate d, or to 0x0006 when PCICR # is asserted.
Table 8: Register Summary (cont inued)
Offs et Fr om
Base aRegister Name Acronym Size
(bytes) CPU-Bus
R/W Reset Va lu e Ref eren ce
Table 9: System Resources Accessible to t he CPU and DMA
Targe t s Acc ess ible Throu gh Co ntr oller Accessible
By CPU Accessible
By DMA Reference
Boot ROM Ye s Yes Sec tio n 6.4 on page 64
SDRAM M em ory Ye s Yes Sec tio n 6.5 on page 67
PCI Memory Space a
a. Via PCI Address Windows (see Section 5.4) with controller as PCI master.
Ye s Yes Sec tio n 7.4 on page 81
PCI I/O space aYes Yes Sectio n 7.4.6 on page 85
PCI Config ur ation Registers aYes Yes Section 7.12 on page 103
External (DCS[8:2]) Devices b
b. Any devic e s elected by a DCS[8:2] signal. Such devi ces can reside on the Memory or
Local Bus.
Ye s Yes Sec tio n 8.6.3 on page 12 5
Controller’s Internal Registers cYes Yes Tabl e 8 on page 31
Table 10 summarizes the accessibility of controller resources to PCI-Bus masters.
Table 11 summar izes the accessibili ty of controller resource s to Local-Bus ma sters.
c. Includes Physical Device Addre ss Register s (PDARs), System and CPU control r egis-
ters, Memory-B us control registe rs, PCI-Bus control registers an d PCI configuration reg-
isters, Local -B us cont rol registers , DMA control registers, UART control registers, Timer
control registers
Table 10: System Resources Accessi ble to PCI-Bus Masters
Targe t s Acc ess ible Throu gh Co ntr oller Accessi ble By PC I-Bu s
Masters Reference
Boot ROM Yes Sect ion 6.4 on page 64
SDRAM M em ory Yes Sect ion 6.5 on page 67
PCI I/O space No
PCI Config ur ation S pac e No a
a. A PCI-Bus mast er cann ot access non-controller PC I Configuration S pace via the con-
trolle r, but it can access the controlle r’s ow n inter nal PCI configuration r egist ers either
directly (see Table 8 on page 31) or when the PCI Central Resource asserts the appropri-
ate IDSEL signal.
Sect ion 7.1 2 on page 103
External (DCS[8:2]) Devices b
b. Any devic e s elected by a DCS[8:2] signal. Such devi ces can reside on the Memory or
Local Bus.
Yes Sect ion 8.6 .3 on pag e 125
Controller’s Internal Registers c
c. Includes Physical Device Address Registers (PDARs), System and CPU contro l regis-
ters, Memory-B us control registers, PCI-Bus control registers an d PCI configuration reg-
isters, Local -Bus cont rol registers , DMA control registers, UART control registers, Timer
control registers
Yes Table 8 on page 31
Table 11: System Resources Accessible to Local-Bus Masters
Targe t s Acc ess ible Throu gh Co ntr oller Accessible By Local-
Bus Masters a
a. A ccesses by Local-Bus masters are implemented by the controller ’s DMA logic, as
desc ribed in Secti on 8.4. 2.
Reference
Boot ROM Yes b
b. Device must be on the Memory Bus.
Section 6.4 on page 64
SDRAM M em ory Yes Sect ion 6.5 on page 67
PCI Memory Space c
c. Via PCI Address Windows (see Section 5.4) with controller as PCI master.
Yes Sect ion 7.4 on page 81
PCI I/O space cYes Section 7.4.6 on pag e 85
PCI Config ur ation S pac e cYes Sec tion 7.12 on pa ge 103
External (DCS[8:2]) Devices d
d. Any devic e s elected by a DCS[8:2] signal. Such devi ces can reside on the Memory or
Local Bus.
Yes bSection 8.6.3 on page 125
Controller’s Internal Registers e
e. In cludes Physical Device Address Registers (PDARs), System and CPU control regis-
ters, Memory-B us control registe rs, PCI-Bus control registers an d PCI configuration reg-
isters, Local -B us cont rol registers , DMA control registers, UART control registers, Timer
control registers
Yes Table 8 on page 31
4.3
Address Space
Summary
Fi
g
ure 8 summari zes the acces sib ilit
y
of addre ss space s support ed b
y
the controller’ s
Ph
y
sical Dev ice Address Re
g
ist ers (PDARs) , which are described fu ll
y
in Secti on 5.4.
Figure 8: Access Supported By Physic al Device Address Regist ers (PDARs)
5.0 CPU/Sys tem Interface and Register s
The co ntroller can inter face directly to a VR5000 CPU, in full compliance with t he
V
R
5000 Bus Interface User’s Man ual, Revis ion 1.1
. The controller can operate with or
without dire ct connection to a VR5000 CPU. When it operat es without di rect connec-
tio n, a nother CPU in t he system would co nfigure the controller , a s shown in Figure 6 on
page 17.
The CPU interface operates at a maximum frequenc y of 100 MHz and supports a pe ak
block -tran sfer thr oughput of 800 MB/sec and a maxi mum sustained t hroughput of 640
Mbyt es/sec .
Through the controller, the CPU can gain access to mem ory, the PCI Bus, the Local
Bus, and t he contro ller’ s internal regist ers (Table 8). All CPU bus-cycl e types and dat a
sizes supported by the VR5000 SysAD bus are supported by the contr oller, except
that —du e to t he pipelined nature of the controlle r’s CPU interface— th e Pip elined Write
Mode is the onl y non-block write mode supported.
Section 12.4.2 on page 152 describes the CPU initialization procedures, the CPU
operating modes imposed by the con tr oller. Multi- controll er configurations (Section
5.3) allow either multip le VRC5074 contr oll ers or a single VRC5074 cont roller and oth er
external agents to resid e on the CPU interface. Fig ure 7 on page 18 shows an exam-
ple. Such system desi gns must p ay special att ention to loading issues on the CPU b us.
5.1
CPU and S
y
stem
Confi
g
uration and
Monitorin
g
Software confi gures and monitors the CPU interface and the cont roller’s general sys-
tem functions by usi ng the following registers:
CPU and Controller Initialization, Section 12.4 on page 151.
Physical Device Address Registers (PDARs), Section 5.4 on page 45.
CPU Interface Registers, Sectio n 5.5 on page 50.
Timer Registers, Section 5.6 on page 58.
5.2
CPU Interface
5.2.1
Signal Connections t o
CPU
Table 12 summar ize the signal connections between the CPU and the controll er.
Table 12: CPU-Controller Signal Connections
CP U Controller Signal
Signal R/W R/W Signal
BigEndian I I/O BigEndian
ColdReset# I O ColdReset#
ExtR qs t# I (tied Hi gh) —
Int#[5:0] I O Int#[5:0]
JTCK I a—
JTDI I a—
JTDO O a—
5.2.2
CPU-Interface Data
Path
The controlle r sam ples addresses and data from the CPU on the r isi n
g
ed
g
e of
S
y
sClock. On the controller side of the CPU interf ace, a 16 x 8-b
y
te ( 128-b
y
te) CPU-to-
controller FIFO (the
CPU-Interf ace FIFO)
buffers S
y
sAd infor ma ti on. The FIFO can
hold 16 dwords of S
y
sAd items (address or data) and is surrounded b
y
two pipel ine
sta
g
es. On the CPU side of the inter face, eve r
y
si
g
nal is buffered throu
g
h a row of re
g
-
isters.
If t he CPU issues a memor
y
read while the controller’s CPU-Interface FIFO is empt
y
,
the re quest b
y
passes t he FIFO and is loaded dire ctl
y
int o a row of re
g
isters. If the FIFO
or controller-side re
g
ister row is not empt
y
, addresses do not b
y
pass the FIFO. If the
CPU interface is idle, a read request b
y
passes both the FIFO and the controller-side
re
g
ister row , savin
g
a minimum of one c loc k compared to th e non-idle c ase. The CPU’s
RdRd
y
input si
g
nal is not driven b
y
the contr oller and shoul d be tied Low. Since the
JTTMS# I a—
ModeClock O I ModeClock
ModeIn I O ModeOut
NMI# I O NMI#
RdRdy # I ( tied Low) —
Releas e# O a—
Reset# I O Reset#
ScCWE#[1:0] O a—
ScDCE#[1:0] O a—
ScDOE# I O ScDOE#
ScLine[15:0] I/O a—
ScMatch I I ScMatch
ScCLR# O a—
ScTCE# I/O a—
ScTDE# O a—
ScTOE# O a—
ScValid# I/O a—
ScWord[1:0] I/O I/O ScWord[1:0]
SysAD[63:0] I/O I/O SysAD[63:0]
SysADC[7:0] I/O I/O SysADC[7:0]
SysClock I I SysClock
SysCmd[8:0] I/O I/O SysCmd[8:0]
SysCmdP I/O a—
ValidIn# I I/O CntrValid#
ValidOut# O I CPUValid#
VccOk I O CntrVccOk
WrRdy# I I/O WrRdy# b
a. The controller does not connect to this signal.
b. In multi-controller confi gurations, all external a gents’ MCWrRdy# signals must be ORed
together and regi stered in an external device. Th e output o f this device must then be
wir ed to the CPU’s WrRdy# input and to the controller s’ WrRdy# inputs.
Table 12: CPU-Controller Signal Connections (conti nued)
CP U Controller Signal
Signal R/W R/W Signal
controller support s only a single pending read, the read is implicitly st all ed until th e
read data is returned.
For CPU reads, the controller drives response data from the targe t onto the SysAd bus
and asserts the CntrValid# signal. For block reads, t he controll er negates ScDOE#
aft er it h as bee n determi ned that the secon dary cache (i f impl ement ed) has mis sed on
the request. ScDOE# remains negated until the third of four dwords is returned to the
CPU. Since t he re-assertion of ScDOE# indicates that the control ler will dri ve the last
dword in the next cycle, the third dword is held back and ScDOE# remains negated
unti l t he fo urth dword is driv en by the respondi ng re source. This additional clock for the
third and fourth dwords is necessary due to the unpr edictable timing rel ationshi p
between the thir d and fourth dwords. T he ti ming for ScDOE# is the same in a multi-
controller config urat ion as it is in a singl e-controller configuration.
Data for CPU writ es alwa ys goes through the CPU-Int erf ace FIFO before being loa ded
into the controller -si de register row. The controll er requests th e appropriate resource
when the address and cycle-type i nformation are loaded int o the register row. Whe n
the asso ciated resource i s available, the address and data at the output of the FIFO is
clocked into th e targeted resource and the FIF O adv ances.
5.2.3
SysAd Flow Control The CPU may be stal led if i t requests access to a target th at is not rea dy. This occurs
when the outstanding requests have filled the controller ’s CPU-Interface FIFO. The
controller monitors the stat us of th e FIFO and stalls th e CPU if it needs to prevent a
FIFO ov erfl ow. Stall ing occ urs ei ther impli citl y or e xplic itly. The CPU is impl icitl y sta lled
if a rea d resource is unavailabl e; the contro ll er does not proceed until i t rec eives the
requested data for the pending read cycle. The cont rol ler always leaves room in t he
FIFO for a read request, so that rea ds are never expli citly stalled.
The CPU is explicitly stalled when the buffer contains six items of SysAd information
(addr ess or data); in t his case, the controll er negates W rRdy#. Although the FIFO can
hold a maximum o f 16 items of SysAd information, the a cti on of stalli ng the CPU m ust
begin early, due to the pi pelined natur e of both the contr oller and the CPU interface.
For example, the following case is one in which the FIFO will fill up. When WrRdy# is
negate d, the CPU m ay iss ue two mo re reque sts (a n on-b lock writ e fo llowed b y a block
writ e) before it i s stalled on the third r equest. These t wo additional requests represent
seven more items in the FIFO. Including two items in the controller’ s pipeli ne, the to tal
in the FIFO by the time the CPU stall s is 15 items. This leaves one place in the FIFO
for t he CPU to issue a r ead re quest. At this poi nt, the CPU is stal le d. I f th e thi rd r equest
issued foll owing the negati on of W rRdy# is a write request, that request is expl icitly
stalled. I f th e third request is a rea d, however, that request goes int o the last plac e in
the buffer and the CPU i s implicitly stalled.
If the FI FO begins to empty, or if the above wor st-case scenar io does not occur , i.e. the
FIFO does not contain 15 i tems when the CPU is stall ed, the controller reasserts and
negate s Wr Rdy# based on the FIFO dept h and the pen din g stal led wri te r eques t. If t he
stalled request is a non-block write request, the controller reasserts WrRdy# for one
clock when the FIFO contai ns less than 13 it em s. Similar ly, if the stalled request is a
block writ e request, the controller reasserts Wr Rdy# for one clock once t he buf fer con-
tains less than 10 items. If the FIFO empties to fi ve items , the controller asserts
Wr R dy# unti l the FIFO fi lls back up to six or more i tem s.
If the CPU i s stal led i mplici tly on a read r equest, th e contr oller reass erts W rRdy# when
the FIF O empties to fi ve items. The FIFO always empt ies befor e the com pletion of t he
read request.
5.2.4
Parity Checking and
Generation
By default, when the DISPC and DISCPUPC bits are cleared in the CPU Status Reg-
ist er (CPUSTAT, Section 5. 5.1), the cont roller checks even pari ty during CPU writes
and generates even parity during CPU reads. The SysAd bus is only checked during
data tr ansfers, not address transf ers. Write parity is checked when the information is in
the controll er’ s CPU-in terface regi ster row. Read parity i s generated when the dat a is
dri ven fr om the resource t o the CPU inte rface, after by te swapping (i f nec essary). If the
CPCEEN bit is set in the Interrupt Control Register (INTCTRL, Section 5.5. 2) an i nter-
rupt is generat ed when a CPU read or wri te parity er ror is detected.
When r eturning bad dat a t o t he CPU during a block read (cache-l ine fi ll) , the con troller
sets bit Sy sCmd[5] and bad parit y on SysADC[7:0 ] for
each
data wor d of t he bl ock th at
is bad . However, the VR5000 CPU onl y looks at comman d bit 5 of the
first
data wor d in
a block. Thus, if the dat a error is in a word of the bl ock other than the first word, the
CPU will onl y noti ce the er ror when t he data i s fetch ed from th e CPU’s ca che, in which
case a cache except ion (not a bus-er ror exception) is gener ated.
5.2.5
CPU Reads The CPU’s RdRdy# input should be tied Low (asserted). Reads are self-throttling,
because only one outstanding read is generat ed by the CPU and supported by the
co ntrol ler.
5.2.5.1
Read Requests t hat Hi t
the Secondary Cache
A block read issued by the CPU may be a request that was spec ula ti vely issu ed to both
the cont rol ler and the secondary cache. If the sec ondary c ache hits on the request, the
controller ’s CPU interface and (potentially) the targeted resource must abort the
request. The controller does thi s by monitoring ScM atch, which is an inpu t t o both the
CPU and the controller. When ScMatch is asserted two clocks after the address is
issued, the controller aborts the re ad from the target ed resource (i f the request has
made it through the FI FO) and removes the request from the FIFO.
5.2.5.2
Non-Matchi ng Read
Address
When a read request is issued by the CPU, but the address does not match any of
those program med into the controller’s Physi cal Device Address Registers (Section
5.4), the controller res ponds to the CPU by drivi ng all 0s on the SysAd bus. The
TMODE bits in the CPU Status Register (CPUSTAT, Section 5.5) determine whether
good or bad parity will be generated f or this respons e. An opt ional, programmable
interrupt may be gene rat ed when this condit ion occurs, as specifi ed by the CNTDEN
bit in the Interrupt Status Register 0 (INTSTAT0, Section 5.5.2).
For multi-controller configu rations (Section 5.3 ), if no devic e responds to the read
request after a programmable time-out interval has elapsed, as specified in the CPU-
Bus Read Time- O ut Cont rol Register (T1CTRL, Section 5.6.3) , the Main Control ler
responds by drivi ng all 0s on the SysAd bus. As in sin gle-contr oller conf igurati ons,
good or bad parity may be generated for this response, and an interrupt may be gen-
erated when the condit ion occurs.
5.2.5.3
Branches to Unali
g
ned
Addresses
The controller implements a hardware fix for the VR5000 CPU bu
g
that pr events the
CPU from correctl
y
handlin
g
a doubleword fetch due to a branch to an unali
g
ned
address.
The controlle r uses the S
y
sAD[63:0] bits and the S
y
sCmd[2:0] bits to internall
y
g
ener-
ate b
y
te enables, per Table 4.14 of the
V r5000 Bus Interface User’s Manual
. For a 4-
b
y
te read to an address that is not doubleword- ali
g
ned, the cont roller correctl
y
g
ener-
ates t he b
y
te enabl es and retu rns the prop er data to t he CPU, on the p rope r b
y
te lane s.
5.2.6
Endian Configuration The controller’s CPU interface supports either bi
g
- or litt le-endian b
y
te orderin
g
. How-
ever, all of the controll er’s lo
g
ic, except the CPU interface, operates solel
y
in little-
endian mode. To implement a bi
g
-endian CPU interface, do either of the followin
g
:
Set the Bi
g
Endian (BE) bit in th e CPU’s Confi
g
Re
g
iste r durin
g
the CPU and
controller ini ti alizati on sequence ( Section 12.4), or
Tie the contr oller’s and the CPU’ s Bi
g
Endian si
g
nal Hi
g
h.
If ei ther or both of these conditions occur, the controlle r will swap incomin
g
and out
g
o-
in
g
b
y
tes on the S
y
sAd bus so that t he CPU can operate i n bi
g
-endi an mode whi le the
controller operates in little-endian mode. The software implications of this, and some
related PCI-device examples, are described in Section 13.0.
5.3
Multi-Controller
Confi
g
urations
The controller can support multiple ext ernal a
g
e n ts, incl u din
g
mu lti p le V RC5074 con-
trollers. Fi
g
ure 7 on pa
g
e 18 illustrates such a s
y
stem desi
g
n. This is called
multi-con-
trol ler mode
, or a
multi-controller configuration
. The lo
g
ic for this support handles
functions such as which controller initializes the CPU, which controller responds to
Boot ROM accesses, separation of the default re
g
ist er address space of each cont rol -
ler, compensa tion for external l
y
combinin
g
the i ndividua l W rRd
y
# si
g
nals, and handlin
g
bus c
y
cles that are not responded to.
5.3.1
Disti nguishing
Be t w e en Mu ltiple
Controllers
In a sin
g
le-controller confi
g
urati on, the base addr ess of the controller’s internal confi
g
-
uration re
g
ist ers is 0x1FA0_0000 after reset. In a multi-controller confi
g
uration, th e
UAR T_DTR# and UART_TxDRDY# si
g
nals are sampled at reset to i dentif
y
each con-
trol ler a nd assi
g
n separ ate address sp aces f or their inter nal re
g
ister s. The sampled ID
deter mines the b ase address of each contr oller’ s re
g
ist er set . An I D of 00 i dent ifies t he
Main Cont ro ller
, as sho wn in Table 13 . Software c an read thi s ID in the MAINCTRL field
of the CPU Status Re
g
ister (C P U S TAT), S e ction 5.5.1.
Table 13: Reset Confi guration Signal s for Multi-Con troller Conf igurations
Sign al Samp led at Re set
Controll er
I D Numb er
Base Address
Of Controller’ s
Internal Regis t ers
After Res et
(PDAR = IN TCS)
Base Address
Of Boot ROM After
Reset
(PDAR = BOOTCS)
UART_DTR# UART_TxDRDY#
0000
(Main Controller) 0x0 1FA0_000 0 a0x 0 1FC 0 0000
UAR T_DTR# and UART _TxDRDY# hav e 50k-ohm p ulldowns inter nally. Thus, in a sin-
gle-controller configuration, no connection to these signals is necessary.
5.3.2
The Main Control ler The Main Controller is responsible for any activity that is not performed by any other
contr olle r . At boot t ime, t he Main Cont roll er perf orms the CPU’s initiali zati on sequence
(Section 12.4) by dri ving the clock, address, and command to the Seri al Mode
EEPROM (if present), reading i n the configur ati on informati on (if Serial Mode
EEPROM is present) or provid ing the defaul t (if Serial Mode EEPROM is not present ),
correcting any illegal cases, and sending initialization information to the CPU. Other
contr oller(s) in the syst em moni to r the initialization sequen ce in order to obtai n the con-
figurati on inf ormation that is relevant to them. After initi alizat ion, the Main Contr oller
responds to Boot ROM fetches.
The concepts of Main Controller and PCI Cent ral Re source (Secti on 7.8) are unre-
lat ed. The contr olle r can be a Main Contro ller for a gi ven CPU, but that CPU might not
be the Main CPU in the syst em , and th e Main Contr oller for that CPU, or any other
CPU in t he system, might not provide the PCI C entral Re source for the system.
5.3.3
Programming All contr ollers i n a multi -control ler confi guration must have their TMO DE bits pro-
gramm ed in their CPU Stat us Register (CPUST AT), Se ction 5.5.1 , as soon as possible
aft er th e s ystem boo ts. These bit s indi cat e to the cont roll er t hat t his i s a mult i-co ntrol ler
configuration and how the Main Controller should handl e read requests that are not
responded to. The bit s must be program med before read requests are issued to
devices other th an the Main Controller.
If t he TMODE bits are not programmed before read requests are issued to devi ces
other than the Main Controller, the controller behaves as though in single-controller
confi gurat ion. A read to another control ler cause s a no-target decode in the Main Con-
trol ler. The Mai n Controll er responds immedi ately with al l zeros. There is, then, a high
li keliho od that either this data wi ll be taken as the response for t he read r equest or t hat
the tr ue response and the Main Cont roller’s no-target re sponse will collide, causing
bus contention.
In a multi -control ler confi guration, the Main Contr oller waits for the CPU-Bus Read
Time- O ut Cont rol Regist er (T1CTRL), Secti on 5.6.3 and Secti on 5.6.4, to term inate
before responding to the request with al l zeros. The time-out count er must ha ve been
ini tializ ed for this feat ure to work. This give s the targeted control ler time t o respond to
the read request.
0 1 01 0x0 1F80_0000
disabled
1 0 10 0x0 1F60_0000
disabled
1 1 11 0x0 1F40_0000
disabled
a. This i s the base addr ess for all single-controller configurati ons, and for the Main Control-
ler in a mult i-controller configuration.
Table 13: Reset Confi guration Signal s for Multi-Con troller Conf igurations
Sign al Samp led at Re set
Controll er
I D Numb er
Base Address
Of Controller’ s
Internal Regis t ers
After Res et
(PDAR = IN TCS)
Base Address
Of Boot ROM After
Reset
(PDAR = BOOTCS)
UART_DTR# UART_TxDRDY#
When out standing read requests are responded to, the Main Cont rol ler automaticall y
resets the CPU-Bus Read T ime-Out Counter. Read requests in any of the cont rol ler
pipel ines are discarded when a response is provi ded to the CPU. This is possible
because the CPU has only one read outstanding at any time, so if a read response
occurs, a read in the pipeline is by definition not destined for this controller. If a write
request does not decode in the contr oller, t he write data is disr egarded regardless of
whether the system impl em ents a single- or multi-control ler configurati on.
5.3.4
CntrValid#, WrRdy#
and MCWrRdy#
In a multi-controller configuration, the bidirectional CntrValid# signal is shared by all
contr ollers. On a CPU access , al l con tr ollers decod e the acce ss but only one contr oller
(the
active controller)
decodes the add ress as being for it . The active controller dri ves
CntrValid# and all other contr oll ers take it as an input, so that they can keep track of
what is happening on the CPU bus.
Wr Rdy# is an input in a multi-cont roller conf igurati on, as opposed to an outp ut in sin-
gle-controller confi gurations. Due to the speed of the CPU’ s bus interf ace, all of the
MCWrRdy# outputs from all controlle rs must be external ly ORed and registered (on
SysC lock) t o generate WrRdy# to the CPU and all contr oller s. Figur e 9 shows the con-
necti ons .
Figure 9: Multi-Controller Signal Connections
If t he CPU is writing to mem ory attached t o one of the controllers, that cont rol ler will
negate its MCWrRdy# output while the other controllers will assert their MCWrRdy#
output s. The OR gate wil l then caus e WrRdy# to the CPU an d all other controll ers to be
negated, thus indicating that further writes are being held off.
Programming the TMODE bits to indicat e a multi -controller configuration causes the
controller to compensate for the ext ernal combination of al l ext ernal agents’ WrRdy#
signals. The controller expects this extra clock delay when monitoring the WrRdy#
input in a multi -controller conf igurati on, and it adjusts the CPU-Inter face FIFO water
mar ks accordi ngly.
DQ
CPUController
Controller
Controller
WrRdy#
MCWrRdy#
MCWrRdy#
MCWrRdy#
WrRdy#
WrRdy#
WrRdy#
CntrValid#
CntrValid#
CntrValid#
ValidIn#
SysClock
5.3.5
Access Targeti ng In a multi-controller confi
g
uration in whic h one or more VRC5074 controllers, and pos-
sibl
y
other devices, sha re a comm on CPU bus , each VRC5074 cont rol ler watches al l
activit
y
on the shared bus to determine which accesses are int ended for it. If that
VRC5074 controller deter mines that the cur rent access is not intend ed for it, tha t con-
trol ler flus hes wri tes after the CPU-Interface FIFO (Section 5.2.2) and drops rea ds
either when it sees another device’s answer or after it s own read tim e-out.
5.4
Physical Device
Address Registers
(PDARs)
The bottom 36 bits (bits 35:0) of the CPU’s S
y
sAD bus are the val id ph
y
sical address
bits. These are deco ded b
y
the controller accor din
g
to masks in the controller’s 13
Ph
y
sical Device Address Re
g
isters (PDARs). Fi
g
ure 8 on pa
g
e 36 shows how the
PDARs facili tate accesses b
y
various bus masters to various bus tar
g
ets.
Table 14 summari zes the c haracteri stics of the PDARs. The text that follows speci fi es
the contents of each PDAR.
5.4.1
Init ial ization State of
PDARs
Afte r the Serial Mode EEPROM initi alizes t he CPU at reset (Secti on 12.0), the PDARs
turn off all ph
y
sical address space exc ept t he chip-selects for the cont rol ler’s int ernal
re
g
ist er space (INTCS) and the Boot ROM (BOOTCS). The PDARs ar e located at the
Table 14: Physical Device Address Registers (PDARs)
Regist er Symbol Off set R/W Reset Va lu e Description
SD RA M B ank 0 SDRAM 0 0x0000 R/W 0x0 0000 00D0 SDRA M m em or y bank 0.
SD RA M B ank 1 SDRAM 1 0x0008 R/W 0x0 0000 00D0 SDRA M m em or y bank 1.
Device Chip-Select 2 aDCS2 0x0010 R/W 0x0 0000 0000 Configur es DCS#[2] signal.
Device Chip-Select 3 aDCS3 0x0018 R/W 0x0 0000 0000 Configur es DCS#[3] signal.
Device Chip-Select 4 aDCS4 0x0020 R/W 0x0 0000 0000 Configur es DCS#[4] signal.
Device Chip-Select 5 aDCS5 0x0028 R/W 0x0 0000 0000 Configur es DCS#[5] signal.
Device Chip-Select 6 aDCS6 0x0030 R/W 0x0 0000 0000 Configur es DCS#[6] signal.
Device Chip-Select 7 aDCS7 0x0038 R/W 0x0 0000 0000 Configur es DCS#[7] signal.
Device Chip-Select 8 aDCS8 0x0040 R/W 0x0 0000 0000 Configur es DCS#[8] signal.
reserved
RFU9 0x0048 R 0x0 0000 00 00 —
reserved
RFUa 0x0050 R 0x0 0000 00 00 —
reserved
RFUb 0x0058 R 0x0 0000 00 00 —
PC I Addres s Window 0 PCIW0 0x0060 R/W 0x0 0000 00 C0 C onfig ur es PCI Ad dr es s Wind ow 0. Thi s
addr ess wind ow can be accessed by the
CP U or DM A , with the contr oller ac ting
as the PCI-Bus master. See Section
7.4.2 for an example of address
generation.
PC I Addres s Window 1 PCIW1 0x0068 R/W 0x0 0000 00 C0 C onfig ur es PCI Ad dr es s Wind ow 1. Thi s
addr ess wind ow can be accessed by the
CP U or DM A , with the contr oller ac ting
as the PCI-Bus master. See Section
7.4.2 for an example of address
generation.
Controller Internal
Registers and Devices I NTCS 0x0070 R/W 0x0 1Fn0 00EF Configures controller’s internal registers.
The reset value c hang es in a m ulti -
co ntroller conf iguratio n ( s ee S ec tion
5.3.3).
Boot Chip-Select aBOOT CS 0x0078 R/W 0x0 1FC0 002F bC onfig ur es B ootCS # s ignal. The reset
va lue changes in a m ulti- c ontroller
configuration (see Section 5.3.1).
a. When the controller is configured for 32-bit PCI operation (PCI64# negated), the boot memory and the seven DCS
devices can be individually configured by the MEM/LOC bit in the PDAR (Section 5.4) to appear on the memory bus or
the Local Bus. When the contr oller is configured for 64-bit PCI operation (PCI64# asserted), these devices always
appear on the memory bus.
b. The BOO TCS reset value depends on the si ze of the PCI bus, size of boot ROM, and other cond itions. See Se ction
5.4.2 and Section 5.3.
fir st 16 dwords of the controlle r’s inter nal register space. For a single-controller config-
uration, or for the Main Control ler in a multi-control ler confi guration (Section 5. 3.3),
these 16 dwords are located at offsets 0x0078:0x0000 from base address
0x0_1FA0_0000. Boot ROM for a singl e-controller conf igurati on is decoded to base
address 0x0_1FC0_0000, although this changes for a multi-controller configuration
(Table 13).
After reset, the PDARs may be programmed to occupy any valid physical address
space and t o decode phy sical address rang es from 4GB down to 2MB. A maxim um of
15 address bits, SysAD[35:21], can be decoded. 16MB ranges must start at 16MB
boundar ies; 1GB ranges must start at 1GB bounda ries. If the addr ess mappings of two
Physical Device Address Registers overlap, the lower-numbered Physical Device
Address Register decode is selected.
When pr ogramming a PDAR, the regis ter should be read i m me diately af ter writing it .
This ensures that address decoders are properly configured.
5.4.2
PDAR Fields All PDARs have the same bit organizati on, except where noted below.
Bit 3:0 MASK
Address-Decoding Mask and Enable.
This field specifies the number of high-order
SysAD[35:21] address bits to be masked and com-
pared wi th the ADDR field dur ing the dec oding of th is
device’s base ad dress. The field resets to 0x0 for al l
PDARs except INTCS and BOOTCS, bot h of whi ch
reset to 0xF. The value of this field for the INTCS
PDAR always r eads as 0xF and can not b e changed.
Some values of this field disable address decoding.
See Section 5.4.3 for a PDAR address-translation
example.
Mask
Value V alid For PDARs Description
0x 0 All ex c ept INTC S Physical Addres s decode OFF
0x1:0x3 All except INTCS
reserved
/OFF
0x4 All except INTCS 4 Address bits SysAD[35:32] are
masked and compared (4GB
addr es s s pace) .
0x5 All except INTCS 5 Address bits SysAD[35:31] are
masked and compared (2GB
addr es s s pace) .
0x6 All except INTCS 6 Address bits SysAD[35:30] are
masked and compared (1GB
addr es s s pace) .
0x7 All except INTCS 7 Address bits SysAD[35:29] are
masked and compared (512MB
addr es s s pace) .
0x8 All except INTCS 8 Address bits SysAD[35:28] are
masked and compared (256MB
addr es s s pace) .
0x9 All except INTCS 9 Address bits SysAD[35:27] are
masked and compared (128MB
addr es s s pace) .
0xA All except INTCS 10 Address bits SysAD[35:2 6]
are masked and compared
(64 M B address space ) .
0xB All except INTCS 11 Address bits SysAD[35:2 5]
are masked and compared
(32 M B address space ) .
0xC All except INTCS 12 Address bits SysAD[35:24]
are masked and compared
(16 M B address space ) .
0xD All except INTCS 13 Address bits SysAD[35:23]
are masked and compared (8MB
addr es s s pace) .
0xE All except INTCS 14 Address bits SysAD[35:2 2]
are masked and compared (4MB
addr es s s pace) .
0xF All PDARs 15 Addre ss bits SysAD[35:21]
are masked and compared (2MB
addr es s s pace) .
Bit 4 MEM/LOC
Memory or Local Bus Chip-Selects.
1 = Memory Bus.
0 = Local Bus.
V al id f or DCS[ 8:2] and BOOTCS onl y . Resets to 0 f or
DCS [8 :2] . S of twar e s ets t he M EM/ LO C bi t to te ll con -
troller w hich port a ph ysical device is accessible
from. At res et, the BOOTCS PDAR’ s MEM/L OC bit i s
set to 1 if the PCI64# signal is assert ed, and it is
cleared to 0 if PCI64# is negat ed; there is a Serial
Mode EEPROM bit that can overr ide this default
(Secti on 12.4).
The timing charac ter istics of chip-sel ects c onfi gured
for t he Local Bus ar e speci fied i n the Loc al Bus Chi p-
Select T iming Registe rs (L CSTn), Section 8.6.2, and
the Local Boot Chip-Se lect Tim ing Regist er (BCST),
Section 8.6.5.
Bit 5 VISPCI
V isible on PCI Bus.
1 = visible.
0 = not visible.
Resets to 0 for all except INTCS and BOOTCS,
which reset to 1. Software must set this bit to 1 to
allow PCI accesses to this device.
Bi t 7 :6 WIDTH
Data Width of Physical Device.
Writable for DCS[8:2] and BOOTCS. The width value
for INTCS, SDRAM0, SDRAM1, PCI W0, and PCI W1
are fi xed at 0x3 (64 bits). BOO TCS resets as 0x0
and has Seria l Mode EEPROM bits (Section 12.4)
that configure its width. Resets to 0x0 for all others.
Bit 20:8
reserved
Hardwir ed to 0.
Bit 35:21 ADDR
Physical Address For This Device.
These bits, after masking with t he value of the MASK
field, are compared with the incoming high-order
address bits t o decode the physical address space o f
this device. This field resets to 0x0 for all PD ARs,
except I NTCS and BOOTCS. See Sectio n 5.4 .3 for a
PDAR address-translation example.
In a multi -control ler confi guration (Sec tion 5.3), the
reset values for the INTCS and BOOTCS registers
change, base d on the con troller I D. If this is t he Main
Width
Value Description
0x0 Physical device data width 8-bits
0x1 Physical device data width 16-bits
0x2 Physical device data width 32-bits
0x3 Physical device data width 64-bits
Controller (controller ID 0x0), the ADDR field of the
INTCS and BOOTCS registers resets to 0x0 1FA
and 0x0 1FC, r espect ively. If this is not the Main
Controller, the ADDR field of the INTCS and
BOOTCS regist er s resets to the val ue shown bel ow:
Bit 63:36
reserved
Hardwir ed to 0.
5.4.3
PDAR Address
Decoding Example
When the CPU gen erates a 36- bit physic al addr ess, t he ADDR and MASK fi elds of the
PDARs determine where that access goes. For example, suppose that the CPU
addres s range 0x0_2000_00 00 through 0 x0_3FFF_FFFF should go t o SDRAM Bank 0
(the SDRAM0 PDAR ). This is equivalent to saying that when the SysAD[35:29]
address bits are b0000_001, the access should go to SD RAM Bank 0.
In t his ex ample, the MASK a nd ADDR f ields of the PDAR f or SDRAM Bank 0 woul d be
programmed as follows:
MASK = 0x7, which means only compare [35:29]
ADDR[35:21] = b0000_001x_xxxx_xxx
The value in the ADDR fiel d specifies the high-order address bit s that must match the
incomi ng addr ess, and t he MASK fi eld spe cifi es wh ich ADDR bi ts ar e to b e us ed in t he
address comparison. In this example, a MASK value of 0x7 means only compare
[35:29], and th is i s equivalent to a mask of b1111_1110_0000_000 . Thus, when the
CPU generates an access to SDRAM Bank 0, the controller uses only address bits
SysAD[28:0] f rom the CPU. These are the bits t hat were not masked by the SDRAM0
PDAR.
Figure 10: PDAR Address Decoding Exam ple
Controller
ID
INTCS Base
Address Indicated
by ADD R fie ld of
INTCS PDAR at
Reset
BOOTCS Base
Address Indicated
by ADDR fie ld of
BOO TCS PDAR at
Reset
0x0
(Main Co ntroll er ) 0x0 1FA0 00 00 0x0 1FC 0 0000
0x1 0x0 1F80 0000 0x0 0000 0000
0x2 0x0 1F60 0000 0x0 0000 0000
0x3 0x0 1F40 0000 0x0 0000 0000
3
52
12
00
0000001xxxxxxxx ADDR field of PDAR
111111100000000 MASK field of PDAR
0 0 0 0 0 0 1 SysAD[28:0] Address sent to SDRAM0
5.5
CPU Interface
Registers
5.5.1
CPU Status Register
(CPUSTAT)
The TMODE f ield ( bits 5:4) of thi s re
g
ister should be pro
g
ram med as so on as possi bl e
after reset. See Section 5.3.3 for detai ls.
Bit 0 CLDRST
Cold Reset.
1 = cold-r eset the entire s
y
stem .
0 = writin
g
0 has no effect; the bit al wa
y
s reads 0.
Settin
g
this bi t resets the controller, causes it to
assert ColdRes et# to the CPU, and (if PCICR# is
asserted) causes it to assert PCIRST# on t he PCI
Bus. The same a ctions th at are perfor med b
y
setti n
g
this bit are also performed durin
g
power-up (VccOk
input asserte d). Compar e the PCICRST fiel d ( bit 63)
of the PCI Control Re
g
ister (PCICTRL), Section
7.11.1.
Bit 1 WARMRST
Warm Reset.
1 = warm-reset the CPU.
0 = clear the 1.
Settin
g
this bit c auses the contr oller to assert Reset#
to the CPU. The controller and PCI devices are not
reset. After a warm reset, this bit reads 1. The bit can
be clear ed b
y
writin
g
0. Compare the PCIWRST fiel d
(bit 62) of the PCI Cont rol Re
g
ist er (PCICTRL), Sec-
tion 7. 11.1.
Bit 2 DISPC
Disable Parity Checking.
1 = disable parit
y
checkin
g
of CPU write data.
0 = enable parit
y
checkin
g
of CPU write data.
The controller checks even parit
y
when this bi t is
cleared. See Section 5.2.4 for a description of CPU-
relat ed parit
y
g
eneration and checkin
g
.
Table 15: CPU Interface Registers
Regist er Sy mbol Offs et R/W Reset Value Description
CPU Status CPUSTAT 0x0080 R/W 0x0000 0000 0000 0h00 aMiscella neous CP U s tatus and control.
Interrupt Control INTCTRL 0x0088 R/W 0x8888 8888 8888 8888 Interrupt enable and priority.
Int er r upt Status 0 INTSTA T0 0x00 90 R 0x0 000 0000 0000 0000 Int er r upt st atus 0.
Int er r upt Status 1 an d CP U
Interrupt Enable INTS TAT1 0x0098 R/W 0x0001 0000 0000 0000 Inter r upt st atus 1 and CP U interrupt
enable.
Interrupt Clear INTCLR 0x00A0 R/W 0x0000 0000 0000 0000 Interrupt clear.
PCI Interrupt Control INTPPES 0x00A8 R/W 0x0000 0 000 0000 0000 Inter r upt in put sign als polarity an d edge
vs. level sensitivity control.
a. The “h” nibble in this reset value change s in multi -controller configurations (Sect ion 5.3).
Bi t 3 DISC P U PC
Disable Parity Generation.
1 = disable parity generation for CPU reads.
0 = enable parity generation for CPU reads.
The controller generates even parity when this bi t is
cleared. See Section 5.2.4 for a description of CPU-
relat ed parity gener ation and checking.
Bits 5:4 TMODE
No-Target Read Response.
This f ield determines how the control ler responds to
a CPU read request that (a) does not decode to this
controller’ s address space, as specified by this con-
trol ler’ s PDARs (Section 5.4), (b) encounters a time-
out of the CPU-Bus Read Tim er (Sec tion 5.6.4 ), or
(c) encounters a tim eout of the Local -Bus Ready
Ti mer (SUBSCWID plus CONWID f ields of the Lo cal
Bus Chip Sel ect Regi sters , LCSTn, Sect ion 8. 6.2). If
a TMO DE value of 2 or 3 is programmed, the CPU-
Bus Read Timer must be initialized in order for this
featu re to work . Fail ure to l oad a val ue into t his t imer
causes t he system to h ang for a CPU read request to
which no cont roller r esponds. The TMODE fi eld
should be programmed as soon as possible after
reset. See Section 5.3.3 for detai ls.
Bits 7:6
reserved
Hardwir ed to 0.
Bits 9:8 CTRLNUM
Control ler ID Number.
(read-only)
These r ead-only bi ts are s et by the UAR T_DTR# and
UART_TxDRDY# signals duri ng cold reset (Section
TMODE
Value Description
0x 0 Single-c ont r oller config ur ation. Retur n z er os wit h
bad parity.
0x 1 Single-c ont r oller config ur ation. Retur n z er os wit h
good ev en parity.
0x 2 Multi-contr oller c onfig ur ation. If thi s is the M ain
Controller, return ze ros with bad parity aft er time-out.
0x 3 Multi-contr oller c onfig ur ation. If thi s is the M ain
Controller, ret ur n zeros with go od ev en parity after
time-out.
Con t roller ID Base Address of Registers
00 0x1FA0_0000 (Main Controller)
01 0x1F80_0000
10 0x1F60_0000
11 0x1F40_0000
12.0) and determine t he controll er’s address space
in a multi-controller conf igurati on (Section 5. 3).
Bit 10 MAINCTRL
Main Controller.
(read-only)
1 = Main Controller.
0 = not the Main Controller.
Bits 63:11
reserved
Hardwir ed to 0.
5.5.2
Interrupt Control
Register (INTCTRL)
Secti on 11.0 on page 147 gives an ov erview of inter rupts. Each nibble of the INTCTRL
regi ster contains the enable bi t and priorit y bits for each source of a co ntr oller inter rupt.
The thre e least- signi ficant bits of each nibbl e contai n the inte rrupt prio rity assignment.
The most- sig nificant bit of t he n ibb le contains the inter rupt enabl e. When s et, the i nter-
rupting source is enabled t o int errupt the CPU. Enco dings 0 through 5 corr espond to
CPU interrupts 0 through 5. Encodi ng 6 corresponds to the CPU’s NMI# input.
Bits 2:0 CPCEPRI
CPU-Interface Parity-Error Interrupt Priority.
Bit 3 CPCEEN
CPU-Int erf ace Parity- Error Inte rr upt Enable.
1 = enable.
0 = disable .
Bits 6:4 CNTDPRI
CPU No-Tar get Decode Interrupt Priority
.
Same values as Bits 2:0.
Bit 7 CNTDEN
CPU No-Tar get Decode Interrupt Enable.
1 = enable.
0 = disable .
Bits 10:8 MCEPRI
Mem o ry-Ch e ck Error Interrupt Pri o rit y.
Same values as Bits 2:0.
Bit 11 MCEEN
Memory -Check Error Int errupt Enable
.
1 = enable.
0 = disable .
The erro r-checkin g mode (parit y or ECC) is specified
Priority
Value Description
0x 0 T his int er r upt is ass igned to CPU interrupt lev el 0,
Int#[0].
0x 1 T his int er r upt is ass igned to CPU interrupt lev el 1,
Int#[1].
0x 2 T his int er r upt is ass igned to CPU interrupt lev el 2,
Int#[2].
0x 3 T his int er r upt is ass igned to CPU interrupt lev el 3,
Int#[3].
0x 4 T his int er r upt is ass igned to CPU interrupt lev el 4,
Int#[4].
0x 5 T his int er r upt is ass igned to CPU interrupt lev el 5,
Int#[5].
0x 6 T his int er r upt is ass igned to CPU non-m as k able
interrupt, NMI#.
0x7
reserved
in the Memory Control Regist er (MEMCTRL), Sec-
tion 6. 6.1. The type of memory-check err or is
report ed in the M emory Check Error Status Register
(CHKERR), Section 6.6.3.
Bits 14:12 DMAPRI
DMA Controller Interrupt Priority
.
Same values as Bits 2:0.
Bit 15 DMAEN
DMA Controller Interrupt Enable
.
1 = enable all DMA interrupt sources.
0 = disable all DMA interrupt sources.
This bi t is a global enable for the DMA interr upt
sources that are individually enabled by the IE bit in
the DMA Control Registers 0 and 1 (DMACTRLn),
Section 9.5.1. Clearing all bits in DMACTRLn is the
same as clearing the DMAEN bit.
Bits 18:16 UARTPRI
UART Interrupt Priority
.
Same values as Bits 2:0.
Bit 19 UARTEN
Global UART-Interrupt Enable
.
1 = enable all UART interrupt sources.
0 = disable all UART interrupt sources.
This bi t is a global enable for all UAR T interrupt
sources that are individually enabled in the UART
Inter rupt Enable Register (UARTIER), Section
10.4.3. Clearing al l bi ts in UARTIER is the same as
clearing the UARTEN bit.
Bits 22:20 WDOGPRI
Watchdog Ti mer Int errupt Priori ty
.
Same values as Bits 2:0.
Bit 23 WDOGEN
Wat chdog Timer Int errupt Enable
.
1 = enable.
0 = disable .
Setti ng this bit ena bles interr upts on time-out of
Timer 3 Counter Register (T3CNTR, Section 5.6.8).
Bits 26:24 GPTPRI
General-Purpose Timer Interrupt Priority
.
Same values as Bits 2:0.
Bit 27 GPTDEN
General-Purpose Timer Interrupt Enable
.
1 = enable.
0 = disable .
Setti ng this bit ena bles interr upts on time-out of
Timer 2 Counter Register (T2CNTR, Section 5.6.6).
Bits 30:28 LBRTDPRI
Local-Bus Ready Timer Interrupt Priority
.
Same values as Bits 2:0.
This bi t enables inte rrupts on ti me-out of the 12-bi t
counter in the SUBSCWID+CONWID fields of the
Local Bus Chi p Select Registers (LCSTn, Section
8.6.2 ). Th is i nt errupt appl ies t o both read s and write s
on the Local Bus.
Bit 31 LBRTDEN
Local-Bus Ready Interrupt Enable
.
1 = enable.
0 = disable .
Bits 34:32 INTAPRI
PCI Interrupt Signal INTA# Pri ori ty.
Same values as Bits 2:0.
Bit 35 INTAEN
PCI Interrupt Signal INTA# Enable
.
1 = enable.
0 = disable .
Bits 38:36 INTBPRI
PCI Interrupt Signal INTB# Priority
.
Same values as Bits 2:0.
Bit 39 INTBEN
PCI Interrupt Signal INTB# Enabl e
.
1 = enable.
0 = disable .
Bits 42:40 INTCPRI
PCI Interrupt Signal INTC# Priority
.
Same values as Bits 2:0.
Bit 43 INTCEN
PCI Interrupt Signal INTC# Enabl e
.
1 = enable.
0 = disable .
Bits 46:44 INTDPRI
PCI Interrupt Signal INTD# Priority
.
Same values as Bits 2:0.
Bit 47 INTDEN
PCI Interrupt Signal INTD# Enabl e
.
1 = enable.
0 = disable .
Bits 50:48 INTEPRI
PCI Interrupt Signal INTE# Priority
.
Same values as Bits 2:0.
Bit 51 INTEEN
PCI Interrupt Signal INTE# Enabl e
.
1 = enable.
0 = disable .
Bits 55:52
reserved
Hardwir ed to 0.
Bits 58:56 PCISPRI
PCI SERR# Interrupt Pri ori ty
.
Same values as Bits 2:0.
Bit 59 PCISEN
PCI SERR# Interrupt Enable
.
1 = enable.
0 = disable .
Bits 62:60 PCIEPRI
PCI Internal Error Interrupt Priority
.
Same values as Bi ts 2:0. This fi eld s ets t he priority of
interrupts enabled by the PCIEEN bit, described
immediately below. A PCI Internal Error indicates
that something bad happened during a PCI transac-
tion; the fault could lie eith er wit h the PCI device or
the controller.
Bit 63 PCIEEN
PCI Internal Error Inter rupt Enable.
1 = enable.
0 = disable .
This bi t is a global enable for all PCI int errupt
sources that are individual ly enabl ed by bit s 53:48 of
the PCI Contr ol Reg ister ( PCICTRL), Secti on 7. 11.1.
See PCI- Maste r Pari ty Det ectio n (Sect io n 7.4. 5) and
PCI-Target Parity Detection (Section 7.5.4) for
details.
5.5.3
Interrupt Status
Register 0 (INTSTAT0)
Each 16-bit halfword of this register indicates which of the 16 sources are requesting
an int errupt for the lower four non-maskable interru pts to the CPU, Int#[3:0].
Bits 15:0 IL0STAT
CPU Int#[0] Status
.
Bits 31-16 IL1STAT
CPU Int#[1] Status
.
Same values as Bits 15:0.
Bits 47:32 IL2STAT
CPU Int#[2] Status
.
Same values as Bits 15:0.
Bits 63:48 IL3STAT
CPU Int#[3] Status
.
Same values as Bits 15:0.
5.5.4
Interrupt Status 1/CPU
Interrupt Enable
Register (INTSTAT1)
Each of the lower three 16-bit halfwords of this register indicates which of the 16
sources are requesting an int errupt for the upper two non-maskable inte rrupts to the
CPU, Int#[5:4], and the non -mask able interrupt to the CPU, NMI#. The upper portion of
this regist er has the enables f or controll er interr upt output buf fers.
Bits 15:0 IL4STAT
CPU Int#[4] Status.
Same values as Bits 15:0 of INT STAT0 register.
Bits 31-16 IL5STAT
CPU Int#[5] Status.
Same values as Bits 15:0 of INT STAT0 register.
Status Bit Source of Inte rrupt
0 CPU parity-check error (even pa rity)
1 CP U no-target dec ode
2 Memory Check Error
3 DM A Controlle r
4 UART
5 Watch dog timer
6 General-purpose timer
7 Local Bus read time-out
12:8 PCI interrupts INTE# through INTA#
13
reserved
14 PCI SERR#
15 PCI internal error.
Bits 47:32 NMISTAT
CPU NMI# Status.
Same values as Bits 15:0 of INT STAT0 register.
Bit 48 IL0OE
Int#[0] Controller Output Enable
.
1 = enable.
0 = disable .
Bit 49 IL1OE
Int#[1] Controller Output Enable
.
enable.
1 = enable.
0 = disable .
Bit 50 IL2OE
Int#[2] Controller Output Enable
.
enable.
1 = enable.
0 = disable .
Bit 51 IL3OE
Int#[3] Controller Output Enable
.
enable.
1 = enable.
0 = disable .
Bit 52 IL4OE
Int#[4] Controller Output Enable
.
enable.
1 = enable.
0 = disable .
Bit 53 IL5OE
Int#[5] Controller Output Enable
.
enable.
1 = enable.
0 = disable .
Bi t 5 4 NMIOE
NMI# Controller Output Enable
.
buffer enable.
1 = enable.
0 = disable .
Bit 63:55
reserved
Hardwir ed to 0.
5.5.5
Interrupt Clear
Register (INTCLR)
Wr iting a 1 to any of these bi ts causes the cor responding interrupt source to be
cleared, but onl y if the interr upt is edge-triggered. All of the controller’s int errupt out-
puts to the CPU, Int[5:0], are le vel-sensitive. PCI int errup ts can be specified as level-
sensitive or edge-triggered in the PCI Interrupt Control Regist er (I NTPPES), Section
5.5.6. Writ ing a 0 to any of these bits has no ef fect. The bits always read 0.
Bit 15:0 ISCLR
Clear Inter rupt
.
1 = clear interrupt.
0 = writing 0 has no effect. The bits always re ad 0.
Bit 63:16
reserved
Hardwir ed to 0.
5.5.6
PCI Interrupt Control
Register (INTPPES)
Bit 0 I NTAPOL
INTA# Signal Polar ity.
1 = active-Low.
0 = active-High (reset value).
Bit 1 I NTAEDGE
INTA# Signal Edge.
1 = level- sensiti ve.
0 = edge-triggered (reset value).
Bit 2 INTBPOL
INTB# Signal Polarity.
1 = active-Low.
0 = active-High (reset value).
Bit 3 I NTBEDGE
INTB# Signal Edge.
1 = level- sensiti ve.
0 = edge-triggered (reset value).
Bit 4 INTCPOL
INTC# Signal Polarity.
1 = active-Low.
0 = active-High (reset value).
Bit 5 INTCEDGE
INTC# Signal Edge.
1 = level- sensiti ve.
0 = edge-triggered (reset value).
Bit 6 INTDPOL
INTD# Signal Polarity.
1 = active-Low.
0 = active-High (reset value).
Bit 7 INTDEDGE
INTD# Signal Edge.
1 = level- sensiti ve.
0 = edge-triggered (reset value).
Clear Bit Source of Interrupt
0 CPU parity-check error (even parity)
1 CPU no-target decode
2 Memory-Check Error
3 DMA Cont r oller
4 UART
5 Watchdog timer
6 Gen e r al-purpos e t imer
7 Local Bus r ead time-out
12:8 PCI int er r upt si gnals, INTE# t hr ough I NTA#
13
reserved
(always 0)
14 PCI SERR#
15 PCI internal error
Bit 8 INTEPOL
INTE# Signal Polarity.
1 = active-Low.
0 = active-High (reset value).
Bit 9 I NTEEDGE
INTE# Signal Edge.
1 = level- sensiti ve.
0 = edge-triggered (reset value).
Bit 63:10
reserved
Hardwir ed to 0.
5.6
Timer Registers The controller has four timers:
SDRAM Refresh Timer (Ti m er0):
A 16-bit timer that causes an SDRAM refresh
when it expi res. The contr oll er automatically reloads this free-runni ng ti m er.
CPU-Bus Read Timer (Timer1):
A 24-bit timer used to dete rmine CPU bus read
time-outs in a multi-controller configuration. See the description of the TMODE
field in t he CPU Status Regist er (CPUSTAT, Section 5.5.1). When a CPU read
begins, this timer is automatically loaded and begins to count, if enabled.
General-Purpose Timer (Timer2):
A 32-bit timer that generates a CPU interrupt
when it expi res, if the int errupt is enabl ed in the Inter rupt Control Register
(INTCTRL, Secti on 5.5.2). The control ler automatically reloads this free-running
timer.
Watchdog Timer (Timer3):
A 32-bit timer that generates a CPU interrupt when it
expires, if the int errupt is enabled in the Interrupt Control Register (I NTCTRL,
Section 5.5.2). The controll er automatically re loads this free-running timer.
Normally these tim ers count SysClock ticks , but one timer can be specifi ed as a pres-
cale input to another timer. To be used as a prescaler, the timer must be enabled.
The Local-Bus also has a ready-signal timer. This is configured in the Local Bus Chip-
Select Timing Regist ers (LCSTn), Sect ion 8.6.2.
5.6.1
SDRAM Refresh
Control Register
(T0CTRL)
This register is initialized to 0x1 000 0 0186 at reset.
Bits 15:0 T0RLVAL
Timer 0 Refresh Counter Reload Value
.
This value, in SysClock ticks, is automatically re-
loaded i nto the refre sh counter after the counte r
reaches zer o. The r efresh counter c ounts do wn f rom
Table 16: Tim er Registers
Register Symbol Offset R/W Reset Value Description
SDRAM Refresh Control T0CTRL 0x01C0 R/W 0x0000 0001 0000 0186 SDRAM refresh control.
SDRAM Refresh Counter T0CNTR 0x01C8 R/W 0x0000 0000 0000 0000 SDRAM refresh counter.
CP U-Bus Read Time-Out Control T1C TRL 0x01D0 R/W 0x0000 0000 0000 0000 CPU-bus read time -out control.
CP U-Bus Read Time-Out Count er T1CNTR 0x01D8 R/W 0x0000 0000 0000 0000 CPU-bus read time-out c ounte r .
General-Purpose Timer Control T2CTRL 0x01E0 R/W 0x0000 0000 0000 0000 General-purpose timer control.
General-Purpose Timer Counter T2CNTR 0x01E8 R/W 0x0000 0000 0000 0000 G eneral-purpose timer counter.
Watchdog Timer Control T3CTRL 0x01F0 R/W 0x0000 0000 0000 0000 Watchdog timer control.
Wat chdog Timer Counter T3CNTR 0x01F8 R/W 0x0 000 0000 0000 0000 Watchdog time r co unter.
this value. Thus, the time of the count cycle corre-
sponds to 1 plus this register’s val ue. The default
value (0x186 = 390) is the refresh rate for an SDRAM
chip that requir es 4096 refresh cycl es every 32 ms
(i. e., one refre sh every 7.8125 microseconds) for
SysClock running at 50 MHz. This is very conserva-
tive but it allows for successful boot, aft er which the
reload value can be increased.
Bits 31-16
reserved
Hardwir ed to 0.
Bit 32 T0EN
Timer 0
Enable
.
1 = enable (reset value).
0 = disable .
Enabling the timer starts it counting.
Bit 33 T0PREN
Timer 0 Pres cale Enable
.
1 = enable.
0 = disable (reset value) .
If the prescaler is enabled, the controller only starts
counting when the prescaler rea ches zero.
Bits 35:34 T0PRSRC
Timer 0 Pres cale Source
.
00 =
reserved
01 = Timer 1.
10 = Timer 2.
11 = Timer 3.
Bits 63:36
reserved
Hardwired to 0.
5.6.2
SDRAM Refresh
Counter Regis ter
(T0CNTR)
Bits 15:0 T0VAL
Timer 0 Curr ent Timer Value
.
The timer value, in SysClo ck ticks. Refresh is gener-
ated upon reaching 0.
Bits 63:16
reserved
Hardwired to 0.
5.6.3
CPU-Bus Read Time-
Out Control Register
(T1CTRL)
This timer is used to ti m e-out CPU read requ ests to which no resource respo nds. The
timer functions di fferently, dependi ng on whether the TMODE field in th e CPU Status
Register (CPUSTAT), Section 5.5.1, specifies a single-controller or multi-controller
configuration and whether the MAINCTRL field in CPUSTAT specifies a Main Control-
ler.
Bits 23:0 T1RLVAL
Timer 1 Count er Reload Value
.
If the TMODE field in CPUSTAT specif ies a single-
controller configuration (TMODE = 0x0 or 0x1) or if
this controller is not the Main Controller in a multi-
controller configuration (TMODE = 0x2 or 0x3 and
MAINCTRL = 0), the timer is free-running: the
T1RLVAL value, in SysClock ticks, is automatically
re-loaded into the counter after the counter reaches
zero. The counter starts counti ng when it is enabled
by the T1EN bit and counts down from this value.
Thus, the time of the count cycle cor responds to 1
plus thi s register’s value.
If the TMODE field in CPUSTAT specif ies a multi-
controller configurat ion and this is the Main Cont rol-
ler (TMODE = 0x2 or 0x3 and MAINCTRL = 1), the
T1RLVAL value is loaded at t he beginning of any
CPU read cycle , and the counter onl y counts while
the read is in progress.
Bits 31:24
reserved
Hardwir ed to 0.
Bit 32 T1EN
Timer 1 Enabl e
.
1 = enable.
0 = disable (reset value) .
Enabling the timer starts it counting.
Bit 33 T1PREN
Timer 1 Pres cale Enable
.
1 = enable.
0 = disable .
If the prescaler is enabled, the controller only starts
counting when the prescaler rea ches zero.
Bits 35:34 T1PRSC
Timer 1 Pres cale Source
.
00 = Timer 0.
01 =
reserved
10 = Timer 2.
11 = Timer 3.
Bits 63:36
reserved
Hardwir ed to 0.
5.6.4
CPU-Bus Read Time-
Out Counter Regis ter
(T1CNTR)
Bits 23:0 T1VAL
Timer 1
Current Timer Value
.
A CPU-bus read time-out is generated when this
value, in SysClock ticks, reac hes 0. C PU -bus read
time-outs are cont rolled by th e TMODE bits of the
CPU Status Register (Section 5.5.1). The T1VAL
value should be greater than the worst-case
response time required by your slowest device; if a
slow devi ce returns data after the T 1VAL time- out,
the state o f hard ware may become corrupt , re quiring
a reset.
Bits 63:24
reserved
Hardwir ed to 0.
5.6.5
General-Purpose
Timer Control Register
(T2CTRL)
Bits 31:0 T2RLVAL
Timer 2 Count er Reload Value
.
This tim er is free-r unning: the T2RLVAL value, in
SysClock ticks, is automatically re-loaded into the
counter after the counter reaches zero. The counter
start s counting when it is enabled by the T2EN bit
and counts down from this value. Thus, the ti m e of
the count cycle corresponds to 1 plus this register’s
value.
Bit 32 T2EN
Timer 2 Enabl e
.
1 = enable.
0 = disable (reset value) .
Enabling the timer starts it counting.
Bit 33 T2PREN
Timer 2 Pres cale Enable
.
1 = enable.
0 = disable .
If the prescaler is enabled, the controller only starts
counting when the prescaler rea ches zero.
Bits 35:34 T2PRSRC
Timer 2 Pres cale Source
.
00 = Timer 0.
01 =
reserved
10 = Timer 2.
11 = Timer 3.
Bits 63:36
reserved
Hardwir ed to 0.
5.6.6
General-Purpose
Tim er Counter
Register (T2CNTR)
Bits 31:0 T2VAL
Timer 2
Current Timer Value
.
The general-purpose timer i nter rupt is generated
upon re aching 0, if t his interrupt has been enabled by
setting the GPTDEN field of the Interr upt Control
Register (Section 5.5.2).
Bits 63:32
reserved
Hardwired to 0.
5.6.7
W atchdog Ti m er
Control Register
(T3CTRL)
Bits 31:0 T3RLVAL
Timer 3 Count er Reload Value
.
This tim er is free-r unning: the T3RLVAL value, in
SysClock ticks, is automatically re-loaded into the
counter after the counter reaches zero. The counter
start s counting when it is enabled by the T3EN bit
and counts down from this value. Thus, the ti m e of
the count cycle corresponds to 1 plus this register’s
value.
Bit 32 T3EN
Timer 3 Enabl e
.
1 = enable.
0 = disable (reset value) .
Enabling the timer starts it counting.
Bit 33 T3PREN
Timer 3 Pres cale Enable
.
1 = enable.
0 = disable .
If the prescaler is enabled, the controller only starts
counting when the prescaler rea ches zero.
Bits 35:34 T3PRSRC
Timer 3 Pres cale Source
.
00 = Timer 0.
01 = Timer 1.
10 = Timer 2.
11 =
reserved
Bits 63:36
reserved
Hardwired to 0.
5.6.8
W atchdog Ti m er
Counter Regis ter
(T3CNTR)
Bits 31:0 T3VAL
Timer 3
Current Timer Value
.
The watchdog timer interrupt is generated upon
reaching 0, if this interr upt has been enabled by set-
ting the WDOGEN fi eld of the Interrupt Control Reg-
iste r (Section 5. 5.2).
Bits 63:32
reserved
Hardwired to 0.
6.0 Main-Memor y Interface and Regis ters
The controller’ s mem ory interf ace runs at the SysCl ock frequency (up to 100 MHz). It
supports dword and block (burst ) accesse s to one or t wo physical banks of SDRAM
main m em ory. Several t ypes of SDRAM chips are sup ported (each wit h two to four on-
chip vi rtual banks). A 16-bi t count er supports programma ble refresh r ates.
The CPU, PCI-Bus masters, and Local-Bus masters can access SD RAM mem ory
dir ectly i n t he system memor y space, or t hey can confi gure the cont roller’s DMA regi s-
ters for DMA transf ers, as descri bed in Section 9. 0. Mem ory accesses by the CPU,
PCI-Bus maste rs, and DMA cause the m emory i nterf ace to pr ef etch. Th e contro ller pri-
oritizes r equests on the basis of which physi cal memory bank is cur rently open, and
thus which request can be service d mos t qui ckly.
The controll er genera tes and chec ks byte-w ide parity or ECC (single-error correction,
doubl e-erro r detect ion) wi th 64+8 bits of SDRAM. There is no perfor mance penalt y for
this generation and checking. The contr oller al so supports Flash or ROM devices for
boot or other memory spaces.
6.1
Memor
y
Confi
g
uration and
Monitorin
g
Software confi gures and monitors the memory int erface using the following registers:
Physical Device Address Registers (PDARs), Section 5.4 on page 45.
Interrupt Control Register (INTCTRL), Section 5.5.2 on page 52.
Inter rupt Status Regi ster 0 (INTSTAT0), Section 5.5.3 on page 55.
Interrupt Status 1/CPU Interrupt Enable Register (INTSTAT1), Section 5.5.4 on
page 55.
Inter rupt Clear Register (INTCLR), Sect ion 5.5.5 on page 56.
SDRAM Refresh Control Register (T0CTRL), Section 5.6.1 on page 58.
SDRAM Refresh Counter Register (T0CNTR), Sect ion 5.6.2 on page 59.
Memory-Interface Registers, Section 6.6 on page 72.
6.2
Ph
y
sical Loads At 100 MHz , the memory interf ace typica ll y supports up to thre e physical loads on each
data bit, dependi ng on the qualit y of boar d layout and the el ectrical characteristic s of
the devices used (i ncluding any sockets). These loads can be any three of the follow-
ing address-decode ranges specified by the Physical Device Addr ess Registers
described in Section 5.4:
SDRAM Bank 0 (PDAR = SDRAM0)
SDRAM Bank 1 (PDAR = SDRAM1)
Boot ROM (PDAR = BOOTCS, sometimes referred to as Memory Bank 2)
Memory or Local-Bus Device 8 (PDAR = DCS8)
Memory or Local-Bus Device 7 (PDAR = DCS7)
Memory or Local-Bus Device 6 (PDAR = DCS6)
Memory or Local-Bus Device 5 (PDAR = DCS5)
Memory or Local-Bus Device 4 (PDAR = DCS4)
Memory or Local-Bus Device 3 (PDAR = DCS3)
Memory or Local-Bus Device 2 (PDAR = DCS2)
A row of transceiver/buffer s with DCS[8: 2] and BOOTCS behind it.
The SDRAM in the first two address ranges, SDRAM0 and SDRAM1, can be bank-
interleaved. Any of the other address ranges can be populated with Flash or ROM
memory.
When t he controll er i s configured for 32-bi t PCI operati on (PCI64# nega ted), the boot
memor y and the seven DCS[8:2] devices can be ind ividuall y configured by the MEM/
LOC bit in the PDAR (Section 5.4) to appear on the mem ory bus or the Local Bus.
When th e controll er is confi gured for 64-bit PCI operati on (PCI64# asserted), t hese
devices must be on the memor y bus. The BOOTCS# and DCS#[8:2] chip-sele cts for
these loads need not be buf fer ed, because each of thes e bits supports only a single
load. Figure 3 on page 14 shows an exampl e of buffered loads on the mem ory bus.
If more than thr ee loads are placed on the memor y bus, the bus wi ll slow down. Such
confi guration s (e. g., Figu re 4 on page 15) r equire either a slower SysClock or buf fering
on the data, address, and write-enable signals to t hose devices, so that the con troller
only sees three phy sical loads—t wo SDRAM l oads and one addi tional l oad for the buff-
ers.
6.3
Write FIFOs The memory interface has the following internal write FIFOs, each of which holds 64
bytes of data plus ass ociated address and command bi ts:
8-dword (6 4-byte) CPU Writ e FIFO.
8-dword (6 4-byte) PCI Write FIFO.
8-dword (6 4-byte) DMA Writ e FIFO.
These FIFOs are each capa ble of accepting writes at a maximum speed of 640MB/
sec. For e ach of t hese s ources, two addresse s, o ne to each of t he two ph ysi cal bank s,
can be buffered. All of thes e addresses can be writes (singl e dword writes or 4-dwor d
block writes) , allowing up to si x 4-dword blo ck write request s (addres s and command)
and data to be held in the three 8-dword write FIFOs.
6.4
Boot- ROM and
External-D evice
Addressing
Boot ROM can be l ocated e it her on the m em ory bus or on the Local Bus, as specified
by Bit 256 of the control ler initialization data (Section 12.4.2) and in the ME M/LOC bit
of the BOOTCS PDAR (Section 5.4). If PCI64# asserted, indicating a 64-bit PCI Bus,
Boot ROM must be locat ed on the memory bus, because the Local Bus cannot exist
when a 64-bit PCI Bus is implemented. If PCI64# negated at reset, the controller’s
defaul t CPU-initialization location for Boot ROM is the Local Bus.
The Boot ROM bus width i s set by the Seri al Mode EEPROM initializat ion data stream
(Table 34 on page 154). If you have no Serial Mode EEPROM, the def ault width is 8
bits. You can change this after boot , but you cannot boot without a Seri al Mode
EEPROM if the default is wrong.
Flash memory may be used for Boot ROM. Boot mem ory, or a row of buffers bridgi ng
the con tr oller to a second ary b ank of memory or device s, is so meti mes call ed th e
thi r d
memory bank
or
memory bank 2
. The first and second physical banks, SDRAM0 and
SDRAM1, are the
mai n-mem ory banks
.
6.4.1
Memory- Bus
Addressing Of Boot
ROM and External
Devices
The address signals for the two main-memory physical banks, MAbank0[14:0] and
MAbank 1[14:0 ], may al so be u sed to addr ess Boot ROM and othe r devic es locat ed on
the memo ry bus—those devices assoc iat ed wit h the BOOTCS and DCS8 :2 PDARs.
The ad dres s sig nals f or the two physi cal ba nks of mai n memory must be con catenat ed
on the motherboard to obtain a linear 30-bit address for the boot memory or other
devic es. Thi s 30-bit add ress bus ca n suppo rt devices up to 64 bits in wi dth, as foll ows:
Address bits 29:0 for 8-bi t devices.
Address bits 30:1 for 16-bit devices.
Address bits 31:2 for 32-bit devices.
Address bits 32:3 for 64-bit devices.
Figure 11 shows an example of a Flas h device being used for Boot ROM, plus two
ph ysical banks of SDRAM main mem ory.
The sel ection of width for Boot ROM and other d evices is con tr olled by the WI DTH fi eld
in t he BO O TCS and DCS8: 2 PDARs. The controll er’ s M WE# [0] and MWE#[1] signal s
serve as the memory-chips’ wri te- enable (WE) and output-enable (OE), respectively.
The MCS#[1:0], MRAS#[1:0], and the MCAS#[1:0] signals are negated during
accesses to Boot ROM and ext ernal devices , so as to disable t he SDRAMs.
When BOOTCS and DCS8:2 devi ces are located on the Local Bus, rather th an the
memor y bus, they are add ressed with the LOC_AD[ 31:0] signals, as descr ibed in Sec-
tio n 8.0. Much great er timi ng control is availabl e when DCS8:2 devic es are locat ed on
the Local Bus rather than the Memory Bus. There is also potentially severe SDRAM-
performance degradation during accesses to DCS8:2 devices that are located on the
Memory Bus.
6.4.2
Boot-Mem ory Timing Boot memory timing and the enabling of the MRDY# input sig nal are specified in the
Memory Access Timing Register (ACSTIME), Section 6.6.2.
Figure 11: Bank-Interleaved SDRAM Main Memory With Flash Boot Memory
MD[63:0]
DQM
MCS#[1]
MWE#[1]
MCAS#[1]
MRAS#[1]
MAbank1[14:0]
MDC[7:0]
A[14:0]
RAS
CAS
WE
CS
DQM
D[71:0]
A[14:0]
RAS
CAS
WE
CS
DQM
D[71:0]
MCS#L[0]
MWE#[0]
MCAS#[0]
MRAS#[0]
MAbank0[14:0]
VRC5074
System Controller
SDRAM
Bank 0
SDRAM
Bank 1
BOOTCS#
OE
WE
CS D[7:0]
A[14:0]
A[20:15]
MAbank1[5:0]
Flash
Memory
6.5
SDRAM Main
Memory
Main memor
y
consists of two ph
y
sical banks of SDRAM confi
g
ured b
y
two PDARs,
SDRAM0 and SDRAM1. Both banks support onl
y
SDRAM chips, and the
y
both must
be populated b
y
the same t
y
pe of SDRAM chip runn in
g
at S
y
sClock or
g
reater from
amon
g
the followin
g
t
y
pes:
256 Mb, 4-bank
, includi n
g
but not limited to:
• 64M word x 4 bit x 4 bank
• 32M word x 8 bit x 4 bank
• 16M word x 16 bit x 4 bank
• 8M word x 32 bit x 4 bank
64 Mb, 4-bank
, includin
g
but not limited to:
• 16M word x 4 bit x 4 bank
• 8M word x 8 bit x 4 bank
64 Mb, 2-bank
, includin
g
but not limited to:
• 16M word x 4 bit x 2 bank
• 8M word x 8 bit x 2 bank
16 Mb, 2-bank
, includin
g
but not limited to:
• 4M word x 4 bit x 2 bank
• 2M word x 8 bit x 2 bank
• 1M word x 16 bit x 2 bank
The SDRAMT YP f ield of th e M E M CTRL r e
g
ister (Section 6.6.1) specif ies the t
y
pe of
SD R AM ch i p s i n stal le d.
All SDRAM accesses are full-dword (64 bit) accesses. The controller internall
y
imple-
ments partial-dword (less than 64-bit ) write requ ests as read-mer
g
e-writes: it first
reads from the write address, then mer
g
es the part ial -dword write data into the re ad
data, then writes the full dword to memor
y
. Because of this, part ial-dword writes t ake
lon
g
er than full-dword writes.
6.5.1
Bank-Interleaving In t he cont ext o f s
y
stem s contai nin
g
SDRAM memor
y
, th e term
bank
has two dif feren t
meanin
g
s. Sets of SDRAM chips connected to the cont roller’s MAbank 0[14:0] and
MAbank 1[1 4:0] address si
g
nals are called
physic al banks
, bu t individual SDRAM chi ps
are or
g
anized inter nall
y
into
virtual bank s
.
Physical Banks:
Ph
y
sical-bank interleavin
g
provides a perfor m ance boost
because accesses can be under wa
y
to both banks simultaneousl
y
. Un le s s
otherwi se stated, the term
bank-interleaving
refers to the interleavin
g
of ph
y
sical
banks. Fi
g
ure 11 shows a bank-interleaved SDRAM confi
g
uration with a Fl ash
device f or boot memor
y
.
Virtual Banks :
The virtual banks internal to SDRAM chips can also provide some
perfor m ance boost b
y
allowin
g
the controller to have multiple virtual banks open
simultaneousl
y
(two or four virtual banks f or each ph
y
sical bank), thus pro vidin
g
a
g
reater chance of a pa
g
e hit on a memor
y
acces s. In the list of SDRAM t
y
pes at
the be
g
innin
g
of Section 6.5, the “bank” in “256 Mb, 4-bank” refers to virtual
banks, not ph
y
sical banks.
The r em ain in
g
discussion in this data sheet (excep t as note d) refers to ph
y
sical banks,
not virtual banks.
SDRAM in main memory can be located all in one physical bank (0 or 1) or in both
physical banks. If both banks are populated, both must be populated with the same
type of SDRAM chips, fro m among t he type s li sted at the beginni ng of Section 6.5. The
two physical banks can be bank-interleaved to improve performance. Bank-interleav-
ing is specified i n the IL EAVD filed of the MEMCTRL register (Secti on 6.6.1). If only
one bank is populated, the other bank can, for example , be configured for field-
upgrades by providi ng a SIMM or DIMM connector, as long as the SDRAM chips in
both banks are of the same type.
If bank-int erl eaving is enabled in a two-bank configurat ion, the two addr ess ranges
defi ned by the PDARs for t hese banks ( SDRAM0 and SDRAM1) are spli t between t he
two phys ic al SDRAM rows, s o that ha lf of e ach physi cal row corr esponds t o one of the
memor y banks. If bank-inter leaving is disabled in thi s configuration, the address
ranges correspond to physical rows 0 and 1.
6.5.2
SDRAM Chip
Initialization
The controller automati cally conf igures the Mode Registers in side each SDRAM chip
when the ENABLE bit is set in the Memory Control Register (MEMCTRL), Section
6.6.1. Accesses to SDRAM are held off until initiali zation is compl ete. The values writ-
ten to t he Mod e Registers ins ide each SDRAM chip are fix ed at:
CAS latency = 3.
Burst length = 4.
Wrap type = interleaved.
These val ues wil l work wit h any type of 100 MHz SDRAM that us es 3-tick l ate ncy. The
CAS latency is set to 3 because of the 100 MHz speed of the Mem ory Bus (a CAS
latency of 2 can only be used with 66 MHz bus speed).
6.5.3
Direct Connections,
SIMMs, and DIMMs
The controller is designed for direct connection to one or two banks of identical
SDRAM chips, with no additi onal pipeline stages on the memo ry bus. SIMM or DIMM
connect or s can be u sed o n eithe r o r both b anks, bu t the SIMM or DIMM SDRAM chi ps
must be identical, and the clock speed and board layout will determine whether exter-
nal buffer ing i s neede d for the cl ock an d contro l signa ls. SI MMs and DIMMs wi th exte r-
nal register stages are not suppor ted.
6.5.4
Address-Mu ltipl exing
Modes
The co ntroller support s a ddress multiplexing by staggering the address lines, as
shown i n Table 17. The map ping i s dif feren t, depen din g on whether or not th e physic al
banks (SDRAM0 and SDRAM1 PDARs) are interleaved.
The physical banks are selected by the SysAD[13] signal. The virtual banks within
each SDRAM chi p are sel ected by the SysAD[12:11] signals. When physical-bank
int erleav ing is i mplemented , four or eight virtu al banks ar e visi ble to t he contr oller (two
or four virtual banks for each phys ical bank).
6.5.5
Performance The speed of SDRAM memor
y
accesses is determined b
y
the t
y
pe, speed and inter-
leavin
g
of the memor
y
dev ic es ins tall ed. Table 18 lis ts si mul ated m emor
y
performance
for a 100 MH z memor
y
bus.
Table 17: MAbank-to-SysAD Address Mapping
MAbank
Signals
Bank-I nterleaved Sy sAD Mapp ing Non-Ban k- Interlea ved SysA D M appin g
16Mb SDRAM 64Mb SDRAM 256Mb SDRAM 16Mb SDR AM 6 4Mb SDRAM 256Mb SDRAM
Row Column Row Column Row Column Row Column Row Column Row Column
0 10 3 10 3 10 3 10 3 10 3 10 3
1 14 4 14 4 14 4 14 4 14 4 14 4
2 15 5 15 5 15 5 15 5 15 5 15 5
3 16 6 16 6 16 6 16 6 16 6 16 6
4 17 7 17 7 17 7 17 7 17 7 17 7
5 18 8 18 8 18 8 18 8 18 8 18 8
6 19 9 19 9 19 9 19 9 19 9 19 9
720PDAR
number a20 PDAR
number a20 PDAR
number a20 13 20 13 20 13
8 2123 2125 2126 2123 2125 2126
9 2224 2226 2227 2224 2226 2227
10 11 b0 23 b0 23 b0 11 b0 23 b0 23 b0
11 12 12 24 27 24 28 12 12 24 27 24 28
12 b0 b0 11 11 25 29 b0 b0 11 11 25 29
13 12 12 12 12 11 11 12 12 12 12 11 11
14 11 11 11 11 12 12 11 11 11 11 12 12
a. SDRA M is 0 or 1, as determined by SysAD[13].
Table 18: Main Memory Performance for 100 MHz SDRAM
Bypass
Activation a
Bank-
Inter-
leaving
RAS Page
Hit/Miss R/W CPU
Access
Type
Clocks bTotal M emory
Bandwidth Used
(MB/sec)
First
Access Second
Access Min Max
CPU Ac cess to No n-Bank- Int erle aved Mem ory
No No Hit R Single 13 11
Burst 11+4 11+4
Miss Single 27 11
Burst 24+4 11+4
N/A W Single 368 400
Burst 504 560
Yes No N/A R Single 16 11
Burst 16+4 11+4
W Single 344 400
Burst 520 560
CPU Ac cess to Bank- In t erleaved Memory
Accesses to SDRAM are all pipe li ned for high perf ormance, and SDRAM bank-inter-
leavi ng res ults in higher perfor mance. However, the u se of Fl ash memory or ot her non-
SDRAM devices can reduce this performance, because the SDRAM pipeline stalls
during the slower accesses to such memory. Flash memory can be placed on the
memor y bus or on the Local Bus, except that t he Local Bus cannot be implement ed
whil e a 64- bi t PCI Bus is imp lemented. If Flash mem ory dev ices mus t be p laced o n the
memor y bus (which would be the case in a 64-bit PCI Bus implementati on), perfor-
manc e can be maximized by copying the contents of Flash, aft er boot, to SDRAM
memor y, and accessing fr om the SDRAM.
No No N/A R Single 49 11
Burst 14+4 11+4
W Single 150 160
Burst 528 544
No Yes N/A R Single 20 11
Burst 18+4 11+4
W Single 368 400
Burst 504 560
DMA Reads and Writes to a Single Memory Ba nk, with CPU Accessing the Same Memory Bank
No No N/A R Single 43 11
Burst 28+4 21+4
W Single 320 400
Burst 480 736
DMA Re ads and W rites to M emory Bank 1, wit h CPU Accessing Memory Bank 0
No No N/A R Single 22 16
Burst 76+4 62+4
W Single 464 552
Burst 688 784
DMA Writes to Memory Ban k 1, with CPU Acce ssing Memory Bank 0
No No N/A R Single 35 16
Burst 32+4 15+4
W Single 424 512
Burst 736 800
No Yes N/A R Single 43 10
Burst 23+4 13+4
W Single 296 408
Burst 480 736
a. Bypass activat ion occurs when a CPU r equest arrives while the CPU and memory inter-
faces are both idle.
b. For single-dword reads, this is the latency from the assertions of CPUValid# to Cntr-
Valid# . For bur st r eads this is gi ven as
x+y
where
x
is the initial lat ency and
y
is the num-
ber of clocks to transfer the four dwords in the burst.
Table 18: Main Memory Performance for 100 MHz SDRAM (continued)
Bypass
Activation a
Bank-
Inter-
leaving
RAS Page
Hit/Miss R/W CPU
Access
Type
Clocks bTotal M emory
Bandwidth Used
(MB/sec)
First
Access Second
Access Min Max
If a non- SDRAM device is on the memory bus, the worst-c ase latency fr om CPU to
SDRAM occurs for is a block acce ss (32-bytes) to a byte-wide device . Thi s takes 32
individual accesses, each one lasting up to appro ximately 31 clocks. This gives a
latency of close to 1000 clocks for the CPU.
If only SDRAM is on the memory bus, the worst-c ase latency fr om CPU to SDRAM
occurs when DMA and PCI keep memory busy. In this case, worst-case total latency
from CPU to SDRAM is 76 clocks.
6.5.6
Memory Tim ing The controller is designed for 100 MHz SDRAM chips using a 100 MHz SysClock.
However , the board layout is cr itical. Some layouts may require faster SDRAM chips to
ensure prope r timing ma rgins. The timi ng associa ted wit h SDRAMs i s fixe d by the sys-
tem clo ck and a 3-cloc k RAS and CAS l atency ( 3-cloc k latenc y from RAS to CAS, a nd
3-clock laten cy fro m CAS to data on re ads). Thus, SDRAM SI MMs with ex ternal regis-
ter st ages are not supported.
Figur e 12 shows mini mum ti ming of 1 0 c locks fo r a CPU re ad wit h bypass en abled and
memory interface idle. The total SDRAM latency from address-valid to first-data-valid
is 10 SysClocks, of which 6 are due to SDRAM latency, 1 to error-correcti on, 1 to driv-
ing the SDRAM bus, 1 t o drivi ng the CPU bus, and 1 to internal control ler lat ency. See
Secti on 14.0 for ti ming diagrams.
Figure 12: CPU-To- SDRAM Read Timing
6.5.7
Memory Refresh The control ler support s SDRAM refre sh using CAS-befor e-RAS re fresh on all of the
SDRAM types. The rate of the refresh clock i s determined by a programmabl e 16-bi t
counter, the SDRAM Refresh Counter Regi ster (T0CNTR), Section 5.6.2. The refr esh
logi c requests access to the SDRAM each time the counter expi res. This counter
resets to a conserv ative default value and may be chan ged in t he SDRAM Refresh
Control Regist er (T0CTRL, Secti on 5.6.1) after reset. Refr esh is inter spersed with al l
other memory access es. The refresh logic can accumulat e a m aximum of two refresh
requests while wait ing for access to the memory.
6.5.8
Error Checking The controlle r checks even byte-parit y or 8-bit ECC on data cycles during memory
reads, and it gener ates even byte-parit y or 8-bi t ECC on data cycles during memory
writ es. The CHKMODE and CHKDI S bit s of the Memory Control Register (MEMC-
TRL), Section 6.6.1, enable these functions. Errors or reported in the Memory Check
Error Status Regist er (CHKERR) , Sect ion 6.6.3.
All accesses to SDRAM are full dword (64-bit). Any partial-dword write (less than 64-
bit) requi res a read, int ernal me rge, and write. This work s whether you ar e using ECC
or byt e-pari ty. Y o u canno t implemen t byte- par ity and s upport by te writes wi th SDRAM,
because t here i s n o way t o d o indi vidual b it writ es to t he pari ty RAM . I nstead, y ou must
do read-modify-write s, which the controller does i n its error che cking.
Memor y dwor ds that have cor rec table ECC errors are not repor ted as bad pari ty on the
CPU bus. Only memory dwords that hav e uncorrectabl e (multi- bit) ECC errors are
repor ted as b ad parity on th e CPU bus. For deta ils on how parity er rors are reported on
the CPU bus, see Sect ion 5.2.4.
6.5.9
Memory Shari ng in
Multi-Controller
Configurations
In multi-cont roller configurat ions (Secti on 5.3), SDRAM memory attached to one con-
trol ler can be accessed by a bus master associated wit h anot her controller (CPU, PCI-
Bus master, Local-Bus master, or DMA) if both control ler s connect to a PCI Bus, so
that the access can be made via the PCI Bus. Alternativel y, t he CPU can be used to
copy or move data from one contr oller’s memory t o another contr oll er’s memory.
6.6
Memor
y
-Interface
Re
g
isters
6.6.1
Memory Control
Register (MEMCTRL)
Bit 1:0 SDRAMTYP
SDRAM Type
.
The SDRAM memory controller supports two inter-
Table 19: Main Memory Control Regi sters
Register Symbol O ffset R/W RESET VALUE Description
Memory Control MEMCTRL 0x00C0 R/W 0x0000 0000 0000 0080 Miscellaneous mai n memory control.
Memory Access Timing ACSTIME 0x00C8 R/W 0x0000 0000 0000 001F Main memory access timing.
Memory Check Error Status CH KERR 0x00D0 R 0x0000 0000 0000 0000 Main memory ch eck error status.
Value SDRAM T ype
0x 0 16 M b S DRA M, 2-bank
0x 1 64 M b S DRA M, 2-bank
0x 2 64 M b S DRA M, 4-bank
0x3 256Mb SDRAM, 4-bank
leaved mem ory-space banks. The SDRAM chips in
both ban ks must all be the sam e type. The ter m bank
in the SDRAMTYP table above refers not to such
bank-i nterl eaving of the memory space , but r ather to
banks inside the SDRAM chips t hem selves. See
Section 6.5 for an expl anation of t his terminol ogy.
SDRAMTYP must not be changed after the ENABLE
bit (bit 4) is set.
Bit 2 CHKMODE
Error Checking Mode
.
1 = 8-bit ECC on MD[63:0].
0 = even parit y on each byte of MD[63:0].
Select s the t ype of er ror gener at ion and ch ecking on
data cycles. ECC generation and checking is si ngle-
error correction, double-error detection (SECDED).
The MDC[7:0] signals carry the check data.
Bit 3 CHKDIS
Memory-Che ck Disable
.
1 = disable .
0 = enable.
Setting this bit disables memory checks on reads
and writ es, forces zeros on outbound MDC[7:0]
check bit s, and disables generati on of memory-
check int errup ts, wh ich are enabled by the MC EEN
bit of the Interrupt Control Register (INTCTRL, Sec-
tion 5. 5.2).
Bit 4 ENABLE
Memory Controller Enable
.
1 = enable.
0 = disable .
The controller automatically configures the Mode
Registers in each SDRAM chip when the ENABLE
bit is set. The v alues written to the Mode Register are
descri bed in Sect ion 6.5. 2. Accesses to SDRAM are
held off until initialization is complete. If the mem ory
PDAR is init ial ized but the ENABLE bi t i s not set, any
access to memory will hang indefinitely.
Bit 5
reserved
Hardwir ed to 0.
Bit 6 ILEAVD
Bank-Interleaving
.
1 = enable bank-inter leaving, based on the low
address bit, SysAD[13].
0 = disable bank-interleaving.
With bank-inter leaving enabled, any access with
SysAD[13]=0 goes to physical SDRAM bank 0
(addressed by the MAba nk0[14:0] bus), and any
access wit h SysAD[13]=1 goes to physical SDRAM
bank 1 (addressed by the MAba nk1[14:0] bus).
When bank- interleaving is disabled, any access t o
the SDRAM0 PDAR goes to physic al bank 0, and
any access to the SDRAM1 PDAR goes to physical
bank 1.
Bit 7 HOLDLD
Memory Output Hold-Latch Disable.
1 = disable .
0 = enable.
On eac h output a ddress an d cont rol bi t, aft er the co r-
respondi ng flip-fl op, there is a lat ch before the output
buffer. This latch -enable funct ion is dire ctl y off the
SysClock input si gnal an d is no t c onnected to the on-
chip system clock driven by the internal PLL. Thus,
this latch can guarantee holds to ext ernal cir cuitry.
Bit 63:8
reserved
Hardwir ed to 0.
6.6.2
Memory Access
Timing Register
(ACSTIME)
This register controls the timing of non-SDRAM devices on the memor y bus (called
external devices
on the memory bus), such as Flash or ROM. These devices corre-
spond to the BootCS# and DCS#[8:2 ] chi p-select signals and to the BOOTCS and
DCS[8:2] PDA R s.
Bits 4:0 ACCT
Acce ss Cycle Time .
This field specifies the number of SysClocks
required to read or writ e an external devi ce on the
main m emory bus. MWE#[1] is u sed d uring r eads as
the output-enable signal (OE) of the external
devices, and MWE#[0] is used as the read/wr ite
enable sig nal (WE) of t he exte rnal devi ces. The min-
imum tim e th at O E or WE wil l be Low is always one
SysClock cycle. Thi s register all ows that time to be
extende d. T his fiel d r esets t o 0x1F, corre sponding to
a 310 nsec timi ng in a 100 MHz SysClock sys tem.
Bits 7:5
reserved
Hardwir ed to 0.
Bi t 8 DISM R DY
Disabl e Memor y Ready.
1 = disable MRDY# signal.
0 = enable MRDY# signal.
When this bit is 0, the MRDY# input can terminate an
external access. However, this access wil l al so be
terminated by ACCT count completion (bits 4:0,
above). ACCT can be viewed as a bus time-out.
Thus, MRDY# can be used to shorten the timing of
an external dev ice access on the mai n memory bus.
Bits 63:9
reserved
Hardwir ed to 0.
6.6.3
Memory Check Err or
Status Regi ster
(CHKERR)
Bit 35:0 CEADDR
Memory-Check Error Address
.
The address at which the most recent memory-
check error occurred.
Bit 47:36
reserved
Hardwir ed to 0.
Bit 55:48 CESYN
Memory-Check Error Syndrome
.
If the CHKMODE bit is set to ECC in the Memory
Control Register (Section 6.6.1), this byte contains
the syndr ome from the data on whi ch the check error
occurred, as described in Table 20. If the memory
CHKMODE is Parity, this byte contai ns the XORed
even-parity check.
Table 20: ECC-Check Syndromes
Sorted By Syndrome Sorted By Bit Number
ECC
Syndrome Memory Bit
In Erro r ECC
Syndrome Memory Bit
In Error
0x01 check bit 0 0x01 check b it 0
0x02 check bit 1 0x02 check b it 1
0x04 check bit 2 0x04 check b it 2
0x08 check bit 3 0x08 check b it 3
0x 0B data bi t 17 0x10 check bit 4
0x 0E data bi t 16 0x20 check bit 5
0x10 check bit 4 0x40 check b it 6
0x 13 data bit 18 0x80 check bit 7
0x15 data bit 19 0xCE data bit 0
0x16 data bit 20 0xCB data bit 1
0x19 data bit 21 0xD3 data bit 2
0x1A data bit 22 0xD5 data bit 3
0x1C data bit 23 0xD6 data bit 4
0x20 check bit 5 0xD9 data bit 5
0x 23 data bit 8 0xDA data bit 6
0x 25 data bit 9 0xDC data bit 7
0x26 data bit 10 0x23 data bit 8
0x29 data bit 11 0x25 data bit 9
0x2A data bit 12 0x26 data bit 10
0x2C data bit 13 0x29 data bit 11
0x31 data bit 14 0x2A data bit 12
0x34 data bit 15 0x2C data bit 13
0x40 check bit 6 0x31 data bit 14
0x4A data bit 33 0x34 data bit 15
0x4F data bit 32 0x0E data bit 16
0x52 data bit 34 0x0B data bit 17
0x54 data bit 35 0x13 data bit 18
0x57 data bit 36 0x15 data bit 19
0x58 data bit 37 0x16 data bit 20
0x5B data bit 38 0x19 data bit 21
0x5D data bit 39 0x1A data bit 22
0x62 data bit 56 0x1C data bit 23
0x64 data bit 57 0xE3 data bit 24
0x67 data bit 58 0xE5 data bit 25
0x68 data bit 59 0xE6 data bit 26
0x6B data bit 60 0xE9 data bit 27
0x6D data bit 61 0xEA data bit 28
Bit 56 PCHKERR
Parity-Check Error Occurred
.
1 =even-parity er ror occurred.
0 = error cleared.
This bi t is set by the co ntrol ler when an er ror occu rs.
The bit is cleared by setting bit 2 of the Interrupt
Source Clear Regist er (Section 5. 5.5).
Bit 57 ECHKERR
ECC-Check Err or O ccurr ed.
1 = error occu rred.
0x70 data bit 62 0xEC data bit 29
0x75 data bit 63 0xF1 data bit 30
0x80 check bit 7 0xF4 data bit 31
0x8A data bit 49 0x4F data bit 32
0x8F data bit 48 0x4A data bit 33
0x92 data bit 50 0x52 data bit 34
0x94 data bit 51 0x54 data bit 35
0x97 data bit 52 0x57 data bit 36
0x98 data bit 53 0x58 data bit 37
0x9B data bit 54 0x5B data bit 38
0x9D data bit 55 0x5D data bit 39
0xA2 data bit 40 0xA2 data bit 40
0xA4 data bit 41 0xA4 data bit 41
0xA7 data bit 42 0xA7 data bit 42
0xA8 data bit 43 0xA8 data bit 43
0xAB data bit 44 0xAB data bit 44
0xAD data bit 45 0xAD data bit 45
0xB0 data bit 46 0xB0 data bit 46
0xB5 data bit 47 0xB5 data bit 47
0xCB data bit 1 0x8F data bit 48
0xCE data bit 0 0x8A data bit 49
0xD3 data bit 2 0x92 data bit 50
0xD5 data bit 3 0x94 data bit 51
0xD6 data bit 4 0x97 data bit 52
0xD9 data bit 5 0x98 data bit 53
0xDA data bit 6 0x9B data bit 54
0xDC data bit 7 0x9D data bit 55
0xE3 data bit 24 0x62 data bit 56
0xE5 data bit 25 0x64 data bit 57
0xE6 data bit 26 0x67 data bit 58
0xE9 data bit 27 0x68 data bit 59
0xEA data bit 28 0x6B data bit 60
0xEC data bit 29 0x6D data bit 61
0xF1 data bit 30 0x70 data bit 62
0xF4 data bit 31 0x75 data bit 63
Table 20: ECC-Check Syndromes (continued)
Sorted By Syndrome Sorted By Bit Number
ECC
Syndrome Memory Bit
In Erro r ECC
Syndrome Memory Bit
In Error
0 = error cleared.
This bi t is set by the control ler when such an error
occurs. The bit can be cleared by s ett ing Bit 2 of the
ISCLR field in the Interrupt Source Clear Register
(Secti on 5.5.5).
Bit 58 MCHKERR
Multi-Bi t ECC Check Err or
1 = multi-bit ECC error occurred.
0 = no such error.
This bi t is set by the control ler when such an error
occurs. The bit can be cleared by s ett ing Bit 2 of the
ISCLR field in the Interrupt Source Clear Register
(Secti on 5.5.5).
Bit 63:59
reserved
Hardwir ed to 0.
7.0 PCI-Bus Interface and Regis ters
The contr oller’s PCI-Bus interface compli es f ull y , both funct ionally and elect rically , with
the
PCI Local Bus Specification, Revision 2.1
. No exter nal logic or buffering is neces-
sary. The interfa ce implem ents 3. 3 V PCI-compl iant pads (5 V toler ant) usi ng the NEC
CB-C9 process technology.
The interface operates at any of the f oll owing configurati ons:
66 MHz, 64-bit bus (maximum sustained bandwi dth 533 MB/sec)
66 MHz, 32-bit bus (maximum sustained bandwi dth 267 MB/sec)
33 MHz, 64-bit bus (maximum sustained bandwi dth 267 MB/sec)
33 MHz, 32-bit bus (maximum sustained bandwi dth 133 MB/sec)
The con tr oller c an b e a PCI-Bus maste r on b ehal f of the CPU, DMA, or Loc al-Bus mas-
ters. The controll er can also be a PCI target, pro viding external PCI -Bus maste rs wi th
access t o c ontrol ler resourc es (memory, Local -Bus d evi ces, a nd i ntern al contr oller reg-
ist ers such as those that config ure DM A, UART, and timers). The control ler support s
external PCI-Bu s masters with access to the PCI-Bus memor y space, but not to the
PCI I/O spac e.
The contr oller suppo rt s burs t tr ansfers when it is bot h a PCI-Bu s master and target. No
wait states are requir ed. Burst lengths of up to 2MB are sup port ed for both reads and
writ es. The cont roll er also supports 64-bit addressi ng (Dual Addr ess Cycles ), ir respec-
tiv e of whether a 64-bit or 32-bit PCI data bus is implemented, and it suppo rts locked
cycles (Exc lusive Access) as PCI target and ma ster.
The controller can provide PCI Centr al Resource services for up to five other PCI
devic es. Whe n the cont roll er is no t provi ding PCI Cen tral Resource f unct ions i t is ope r-
ating in PCI St and-Alone Mode. Acc ess to the controller’s PCI Configurat ion Space is
supported when the controll er i s operating ei ther as the PCI Central Resource or in
Stand-Alone Mode.
For det ails of PCI int errupt wiri ng, s ee Section 2.2 .6 of the
PCI Local Bus Specifica ti on
.
Throughout this document,
dword
or
doubleword
me ans 8 by tes and
qword
or
quad-
word
means 16 bytes. These definiti ons are MI PS-compatible and differ from those in
the
PCI Local Bus Speci ficati on
, where a dword is 4 byte s and a qword is 8 bytes.
7.1
PCI-Bus
Confi
g
uration and
Monitorin
g
Software confi gures and monitors the PCI-Bus i nterface usi ng the follo w ing registe rs:
Physical Device Address Registers (PDARs), Section 5.4 on page 45.
Interrupt Control Register (INTCTRL), Section 5.5.2 on page 52.
Inter rupt Status Regi ster 0 (INTSTAT0), Section 5.5.3 on page 55.
Interrupt Status 1/CPU Interrupt Enable Register (INTSTAT1), Section 5.5.4 on
page 55.
Inter rupt Clear Register (INTCLR), Sect ion 5.5.5 on page 56.
PCI Interrupt Control Register (INTPPES), Secti on 5.5.6 on page 57.
PCI-Bus Regi sters, Section 7.11 on page 91.
PCI Configu ration Space Regi sters, Section 7.13 on page 105.
7.2
Read and Write
Buffers
The PCI-Bus data paths are shown in Fi
g
ure 13. These paths incl ude the follo win
g
buffers for addresses and data flowin
g
into or out of the controller:
32-entr
y
x 8-b
y
te (256-b
y
te)
PCI Output FIFO
(OUTFIFO) for addresses and data
flowin
g
from contr oller masters and resources to the PCI Bus.
32-entr
y
x 8-b
y
te (256- b
y
te)
PCI Input FIFO
(INFIFO) for addr esses and dat a
flowin
g
from the PCI Bus to controller ma sters and resources.
4-entr
y
x 8-b
y
te (32-b
y
te)
CPU Delayed Read Complet ion (DRC) Buffer
for data
flowin
g
from the PCI Bus to the CPU.
4-entr
y
x 8-b
y
te (32-b
y
te)
DMA Delayed Read Completion (DRC) Buff er
for dat a
flowin
g
from the PCI Bus to the DMA lo
g
ic.
Both the OUTFIFO and I NFIFO hold add ress and data in a multipl exed fas hion. Each
of the 32 entries holds 8 b
y
tes for address or data, plus an additional 13 bits for trans-
acti on t
y
pe, b
y
te-e nables, command and sta tus inf ormation. Thus, each FIFO can hold
several small write bursts or one lar
g
e write burst.
Int errupts on the PCI Bus are not stall ed until the FI FOs empt
y
. The cont roller can re la
y
PCI interrupts to the CPU immediatel
y
.
Figure 13: PCI-I nterface Data Paths
7.3
PC I Co mmands
Su
pp
orted
Table 21 summari zes the PCI commands supported b
y
the controll er as a m aster and
tar
g
et on the PCI Bus.
Table 21: PCI Commands Support ed
C/BE#[3:0] Command As PCI Master
(Controller-to-PCI) As PCI Target
(PCI-to-Controller)
0000 Interrupt Acknow ledge Yes a
ignored
0001 Special Cycle Yes a
ignored
0010 I/O Read Ye s
ignored
0011 I/O Write Yes
ignored
010x
reserved
— a
ignored
0110 Memory Read Yes Yes, as Delayed Read
0111 Memory Write Yes Yes, as Post ed Write
100x
reserved
— a
ignored
1010 Configurat ion Read Ye s Yes, as Delayed Read
1011 Configurat ion Wri te Yes Yes, as Delayed Write
1100 Memory Read Multip le Ye s Yes , as Del ay ed Read
7.4
PCI Master
Transactions
(Controller-to-PCI)
The controller support s bidi rectional data transfer s between the CPU, DMA, or Local-
Bus masters and PCI-Bus me mor
y
and I/O tar
g
ets b
y
beco m in
g
a PCI-Bus master.
The ini tiator of such a transacti on (the CPU, DMA, or a Local- Bus mas ter) accesses
the PCI-Bus resou rce throu
g
h a local ph
y
sical address that co rrespon ds to o ne of two
PCI Address Windows.
The co ntroller can
g
enerate all PCI command t
y
pes (Table 21) as a PCI -Bus master.
For CPU in struct ion-c ache fi lls ( 4-dword bl ock ), th e controll er reads 4 dword s from th e
PC I ta r
g
et, be
g
innin
g
with the first dword in the cache line (add ress = 0), and retur ns
them to the CPU in the correct sub-block order. As Fi
g
ure 13 shows, read data i s
assem bled in the cont rol ler’s 4-entr
y
x 8-b
y
te CPU Dela
y
ed Read Completion (DRC)
Buffer before bein
g
sent to the CPU.
7.4.1
PCI Address Window
Registers
PCI memor
y
and I/O tar
g
ets are accessed throu
g
h the contro ll er’s two PCI Address
Windows. These windows are confi
g
ured b
y
the PCI Address Window Re
g
isters
(PCIW0 and PCIW1, Section 5.4). The re
g
isters have two correspondin
g
PCI Master
(Ini tiator) Re
g
isters (PCIINIT0 and PCIINIT1, Section 7.11.3) which specif
y
PCI
address and other information re
g
ardin
g
transactions ini tiated throu
g
h the PCI
Address Windows.
Secti on 7.4.2
g
ives an example of how the controll er decodes PCI- Bus addresses f rom
the values on the S
y
sAD[31:0] bus, the ADDR and MASK fi elds of the PCIW0 and
PCIW1 PDARs, and the PCIADD fields of the PCIINITn re
g
isters.
7.4.2
PCI Address Decoding
Example
When the CPU
g
enerates a 36-bit ph
y
sical address to a PCI device , the ADDR and
MASK fie lds of the PDARs deter mine where that access
g
oes. For exa mp le, suppose
that the CPU address ran
g
e 0x0_C000_0000 throu
g
h 0x0_DFFF_FFFF should
g
o to
the PCI Bus throu
g
h the PCI Address Window 0 (the PCIW0 PDAR). This is equivalent
to sa
y
in
g
that when the S
y
sAD[35:2 9] address bi ts are b0000_110, the acce ss should
g
o to the PCI Bus.
In this example, the MASK and ADDR fields of the PDAR for PCI Address Window 0
(PCIW0) would be pro
g
rammed as follows:
MASK = 0x7, which means onl
y
compare [35:29]
ADDR[35:21] = b0000_110x_xxxx_xxx
The value in t he ADDR field specifies the hi
g
h-order address bits t hat must ma tch the
incomin
g
addr ess, and t he MASK fi eld spe cifi es whic h ADDR bit s are t o b e used i n the
1101 Dual Addre ss Cycle Yes Yes
1110 Memory Read Line Yes Yes, as Delayed Read
1111 Memory Write and Inval idate Yes aYes, as Posted Write
a. In normal opera tion, the controller does not generate these commands. However, for
test purposes the TYPE field in the PCI Master (Initiator) Register (PCIINITn, Section
7.11.3) can be written so as to gener ate any PCI command.
Table 21: PCI Commands Support ed (continued)
C/BE#[3:0] Command As PCI Master
(Controller-to-PCI) As PCI Target
(PCI-to-Controller)
address comparison. In this example, a MASK value of 0x7 means only compare
[35:29], and th is i s equivalent to a mask of b1111_1110_0 000_000.
When the CPU generates a PCI-Bus access, the controller uses only address bits
SysAD[28:0] fr om the CPU. These are the bits that were not masked by the PCIW0
PDAR. A PCI device can have up to 64 addr ess bits. The two PCIADD fields in the
PCIINI T0 regi ster (Section 7.11.3), PCIADD[ 63:36] and PCIADD[35: 21], specify the
remainder of the PCI address. Thus, in this example, the PCIADD[63:29] bits should
be programm ed with the upper PCI address bits, and the PCIADD[28:21] bits will be
ignored.
Figure 14: PCI Address Decoding Example (64-Bit PCI Address)
7.4.3
PCI-Master Writes The controller supports combining and byte-merging on writes to the PCI Bus. These
funct ions are enabled in the PCI Master (Initiator) Control Registers (PCIINITn, Section
7.11.3). The sections below describe the controller’s handling of these functions. See
Secti on 3.2.6 of the
PCI Local Bus Speci ficati on
for more det ails.
7.4.3.1
Combining When the COM BINING bit is set in the PCIINI Tn register, the control ler combines
writ es to sequential 64- bit dwords into a single PCI-Bus bu rst write. The TYPE fiel d in
the PCII NITn registe r should contai n the value b011 (Memory Write).
Accesses do not need to be ful l dword writes in order to be combined. A byte write to
address 0x0 (dword 0) fo ll owed by a byte write t o address 0xF (dword 1) will be com -
bined into a PCI burst. Each dword in the burst wil l have only a singl e byte-enable
asserted. If a 32-bit PCI Bus is implemented, the burst consists of four 32-bit words.
The fi rs t word has one by te-enable asserted, the second and third ha ve none asserted,
and the fourth word has one ass erted.
7.4.3.2
Byte-Merging W hen the MERGING bit is set i n the PCIINITn register, the controller byte-merges a
sequenc e of individu al writes to the same 6 4-bi t dwo rd into a single PCI- Bus wri te. The
TYPE fiel d in the PCIINITn register shoul d contain the val ue b011 (Memory Write) .
Byte- merging can be done i n any order. A b yte write t o address 0x3, fol lowed b y a byte
writ e to addr ess 0x2, foll owed by a byte write t o 0x0 could all be merged i nto a single
writ e to dwor d 0x0.
If any byte in the upper half of a dword is wri tt en, subse quent writes to the lo wer half
are not merged . Instead , the dword containi ng the modifi ed upper half is writt en to t he
PCI Bus, and t he subsequent writ e to t he lower half of the dword is placed in t he con-
trol ler’s m erge bu ffe r so that mergi ng c an conti nue. This pr even ts th e potent ial re order-
ing of writ es on a 32-bi t PCI Bus.
6
33
63
53
12
92
82
10
0000110xxxxxxxx ADDR field of PCIW0
PCIADD[63:36] PCIADD[35:21] PCIADD fields of PCIINIT0
111111100000000 MASK field of PCIW0
PCIADD[63:36] PCIADD[35:29] SysAD[28 :0 ] Address placed on PCI Bus
If merging i s enabled and a dword has onl y been par tial ly wr itte n (i. e., o ne of t he up per
four bytes has not been wr it ten to), the dword stays in the merge buffer indefini tel y,
wait ing for an addit ional write t hat migh t be mer ged int o this d word. The wr ite doe s not
actually occur on the PCI Bus until a subsequent PCI Master cycle i s requested.
7.4.4
PCI-Master Reads When a read request comes th rough the con troller , as PCI-Bus master , it is issued onto
the PCI Bus to the PCI target. The master from which the read originated (t he CPU,
DMA, or DMA on behalf of a Local- B us master) is kept waiting until the read data is
returned from the PCI target; several clocks elapse for the first data item, and the
prefetching configuration (Section 7.4.4.2) determines latency for subsequent data
ite ms. The read d ata r eturns through the c ontr oller’s INFI FO a nd one of the two 4-entry
x 8-by te Delayed Read Comple tion (DRC) Buffers s hown in Figur e 13, even t hough the
read may be completed on the PCI Bus as a normal (not delayed) read. Thus, if the
CPU issu es a PCI read, the CPU will b e stalled until th e re ad data returns. But th e DMA
will not be affected by the CPU’ s wait ing.
7.4.4.1
Retri ed Reads If a read request coming through the cont ro ller , as PCI -Bus master , is retried by the ta r-
get, the read reques t i s resubmitted at the front of the INFIFO. This allows ot her
reques ts currently i n the INFI FO to be processed fi rs t. I f a re ad reque st has transferred
some but not all of the requested data and gets a target disconnect , the request i s
imme diately retried.
7.4.4.2
Prefet ching on PCI-
Master Reads
By default, the contr oller fet ches the exact amount of data reque sted by the CPU,
DMA, or Local-Bus master. If the TYPE fi eld in the PCI Master (I nitiator) Control Reg-
isters (PCIINITn, Section 7.11.3) is set to b011 (Memory Read) and the PREFETCH-
ABLE bit i s set t o 1, addi ti onal data is pr efetched fr om the PCI Bus during reads. T he
Memor y Read command is f orced to Memory Read Line or Memory Read Multi ple,
depending on the amoun t of dat a to be pr efetched, as follows:
For CPU single -dword reads, t he controll er prefetches the rest of the cur rent 4-
dword block, plus the numbe r of additio nal 4-dword bloc ks specifi ed by the
SINGLE_PFB field of the PCIINITn regi ster. If SINGLE_PFB is all 1s (0x1F), the
controller prefetches forever.
For CPU 4-dword block reads (CPU cache fills), the controller fetches the
request ed b lock, and it pref etches the number of add iti onal bl ocks sp eci fied by the
BLOCK_PFB field of the PCIINI Tn regi ster. If BLOCK_PFB is all 1s (0x3F), the
controller prefetches continuously.
For DMA read s, the DMA logi c indica tes exactl y ho w ma ny dwords are needed to
complete the current DMA. If the transfer is greater than 64 blocks, the controller
prefetches forever.
No prefet ching is done for reads by Local-Bus masters.
A subsequent read by the same master is a prefetch hit if the PREFETCHABLE bit of
the PCI INITn r egist er is st ill set , and t he a ddress i s consecut ive wit h the e nd of the pr e-
vious read. The subsequent read can be a dword, partial dword, or block, but its
address must start on the dword following the last dword of the previous read.
Prefetching stops when:
The prefet ch block cou nt has been fetched (u nless prefetching fo rever).
The INFIFO is full.
The target disconnects or aborts the transaction.
The address crosse s a 2 MB boundar y.
The master does any write.
The master does a read that is not a prefetch hit.
The master does a read to the other PCI Addres s Window.
Another master (CPU or DMA) does any PCI access.
A PCI target read is serviced (i.e., read data is placed in the OUTFIFO).
Prefetched data is discar ded when:
The master does any write.
The master does a read that is not a prefetch hit.
The master does a read to the other PCI Addres s Window.
Another master (CPU or DMA) does any PCI access.
A PCI target read is serviced (i.e., read data is placed in the OUTFIFO).
The master is idle and the IN FIFO is full.
If t he numb er of dwor ds to be f etched c ross es a PCI cach e-li ne boundary, as specif ied
by the PCI Cache-Line Si ze Register (CLSIZ, Section 7.13.7), the Memory Read com-
mand is forced to a Memory Read Multi ple command; otherwise the command is
forced to a Memory Read Line com m and.
7.4.5
PCI-Master Pari ty
Detection
If t he controll er, as PCI master, detects bad even parity on a read or write
data
cyc le,
the controll er:
Completes the access.
Reports the parity err or i n the DPE bit of the PCI Status Register (PCISTS,
Section 7.13.4).
Generates a CPU interrupt, if enabled by the:
• PEREN bit in the PCI Command Regis ter (PCICMD, Section 7.13.3),
• PERIN bit in the PCI Contr ol Regi ster (PCICTRL, Secti on 7.11.1), and
• PCIEEN bit in the Inte rrupt Contro l Regi ster (INTCTRL, Secti on 5.5.2).
On a read, asserts PERR#, if enabled by the:
• PEREN bit in the PCI Command Regis ter (PCICMD, Section 7.13.3).
On a CPU read, forces load parit y to be returned t o the CPU, if enabled by the:
• PEREN bit in the PCI Command Regis ter (PCICMD, Section 7.13.3).
On a DMA r ead, causes the DM A transfer to s top and sets the PRDERR bit i n the
DMA Control Registers (DMACTRLn, Section 9.5.1), if enabled by the:
• PEREN bit in the PCI Command Regis ter (PCICMD, Section 7.13.3).
Asserts SERR#, if enabled by the:
• SERREN bit in the PCI Command Register (PCICMD, Section 7.13.3),
• PERSE bit in the PCI Control Register (PCICT RL, Section 7.11.1), and
• PEREN bit in the PCI Command Regis ter (PCICMD, Section 7.13.3).
7.4.6
PCI I/O Space Cycles When the TYPE field of the PCI Ma ste r (I nitiator) Contro l Registers (PCIINITn, Section
7.11.3) conta ins the value b001, reads and wri tes on the PCI Bus by the control ler, as
PCI master, are to the PCI I/O Space . The PCI spec ificat ion allows onl y 32-bit I/O
accesses. Thus, the ACCESS_32 bit in the PCIINITn register should be set.
Byte- merging can be used (i.e ., the M ERGING bit can b e set i n the PCI INITn r egist er),
but not combining (th e COMBI NING bit must be cle ared in th e PCII NITn r egister) . Onl y
individual 32-bit I/O accesses are supported. Do not attempt bursts to the PCI I/O
Space. Combining must not be used. Do not attempt accesses greater than 32-bits
(i.e. full dword).
The controller drives the low two bits of the PCI address correctly, according to which
byte-enables are asserted. See Section 3.2.2 of the
PCI Local Bus Speci ficati on
for
details.
7.5
PC I Tar
g
et
Transactions
(
PCI-
to-Controller
)
As a target on the PCI Bus, t he controll er responds to PCI Me mory and Configuration
(but not PCI I/O) transactions. All of the controller ’s resources (memory, Local-Bus
devic es, and internal controller registers such as tho se th at configure DMA, UART, an d
timers) are accessibl e to PCI Bus masters. The cont roller acc epts full -speed (no wait-
state) burst reads and writes but implements them as delayed reads and delayed or
posted writes, as shown in Table 21 on page 80.
The controller has el even PCI target address ranges within whi ch it responds as a tar-
get to PCI -Bus masters. These ranges are programmable thr ough the PDARs (all
except the two PCI Addre ss Wi ndow PDARs, as described immediately belo w in Sec-
tion 7.5.1). A t arget address range is onl y visible on the PCI Bus when the VISPCI bit
is set in its PDAR.
Each PDAR, except the two PCI Address Window PDARs, has a cor responding Base
Address Register (BAR) in PCI conf iguration space. Each BAR is 64-bit s wide, with
varyi ng bits appearing hardwired to zero, as specified in the MASK field of t he PDAR.
The PDAR should b e programmed before all owing a PCI master to ac cess the BARs.
When th e controll er decodes a PCI address fo r one of i ts BARs, i t arbitr ates with its
internal CPU, DMA, and Local-Bus logic for access t o the r equested resource. Bursts
are disconnected with a Target Disconnect if the address crosses a 2MB boundary,
which i s the smallest granularity a cont rol ler BAR can have.
7.5.1
PCI Loop-Back
Accesses
When th e controll er is a PCI-Bus master, it is possible for t he controll er to also be a
PCI-Bus target. That is, the CPU, DMA, or a Local- Bus mas ter can access anot her
controller
resource via a loop- back on the PCI Bus, by using a PCI Address W indow
rath er than addr essing the resource di rectly. Howev er, the analo gous type of loop-back
access is not possi ble when the controller is res ponding as a PCI-Bus tar get to a
request by a PCI- Bus master. That is, a PCI- Bus master cannot access a PCI -Bus tar-
get via a loop-back through the controller.
Because the two PCI Address Window PDARs cannot be accessed by PCI-Bus mas-
ters, they have no cor responding Base Address Registers (BARs) in the controller’s
PCI configuration space.
7.5.2
PCI-Target Writes The controller implements PCI target writes as delayed or posted writes. Addresses
and data for posted writes are held in the INFIFO , shown in Figure 13. Any number of
writes can be posted and up to four delayed transactions can be pending simulta-
neousl y . Any additional dela yed transact ion s are unconditionally re tried until one of the
four currently pending transactions complet es.
Confi guration write s are del ayed wri te s. The address and data for a configu rat ion wr it e
is pl aced in the INFIFO, and the PCI transacti on is terminated with Retry. When the
delayed w rite has been performed into the Configuration Register, the transaction is
allowed to complete.
7.5.3
PCI-Target Reads The controller implements PCI target reads as de layed reads. Delayed reads are sp li t
into two parts: a delayed-read request part , issued by the PCI-Bus m aster, and a
delayed-read completion part, which is the data ret urned by the target ed controll er
resource. Delayed reads have the advantage of fr eeing the PCI Bus for other trans ac-
tions while the target of the delayed read takes it s ti m e returning the read data.
The delayed-read request (address and command) is placed in the INFI FO , and t he
PCI tra nsaction is t erminated wit h Retry. The appropriate controller resource is read
from, and the delayed-read completion data is placed in the OUTFIFO. When the
transaction is retried, the target data is driven onto the PCI Bus.
When pr efet ching data for PCI target reads, the controller considers th e BAR
PREFETCHABLE bit (Section 7.13.10), the PCI command, the incrementing type
specified by PCI_AD[1:0], and the valu e in the PCI Cache Li ne Size Register (Section
7.13.7), as shown in Table 22. If the PCI Prefetch Count exceeds 31 dwords, it is
ignored and the contr oller pre fet ches forever.
Table 22: Pre fetching Variables For PCI Target Reads
BAR
PREFETCHABL
E Bit PC I Command Incrementing
Type Specifi ed by
PCI_AD[1:0]
Pr ef et ch C ou nt
(amount of data prefetched
fr om controll er reso urce)
0 Mem or y Read Any None
1 Mem or y Read Linea r re m ainder of PCI Cac he Line
0 Mem or y Read Line Linear re m ainder of PCI Cache Lin e
1 Mem or y Read Line Linear re m ainder of PCI Cache Lin e
plus 1 more PCI Cache Line
0 Mem or y Read Multiple Linear remainder of PCI Cache Line
plus 1 more PCI Cache Line
1 Mem or y Read Multiple Linear remainder of PCI Cache Line
plus 2 more PCI Cache Lines
— Configur ati on Read — None
— Any Anythi ng other than Lin ear None
Prefetching stops when:
The OUT FIFO is full.
The master terminates the transaction.
The address crosse s a 2Mby te boundary.
The Prefet ch Count has been fetched (unless prefetch ing forever).
Unused prefetched data is discarded when:
The master terminates the transaction.
The Discar d Timer for this delayed transaction expir es.
7.5.4
PCI-Target Parity
Detection
If t he controll er, as PCI target , det ects bad even parity on an
address
cycle, the con-
troller:
Reports the parity err or i n the DPE bit of the PCI Status Register (PCISTS,
Section 7.13.4).
Generates a CPU interrupt, if enabled by the:
• PEREN bit in the PCI Command Register (PCICMD, Section 7.13.3),
• AERIN bit in the PCI Contr ol Regi ster (PCICTRL, Secti on 7.11.1), and
• PCIEEN bit in the Inte rrupt Contro l Regi ster (INTCTRL, Secti on 5.5.2).
Asserts SERR#, if enabled by the:
• SERREN bit in the PCI Command Register (PCICMD, Section 7.13.3), and
• AERSE bit in the PCI Control Register (PCICT RL, Sect ion 7.11.1), and
• PEREN bit in the PCI Command Register (PCICMD, Section 7.13.3).
Ignores the access.
If the cont ro ller, as PCI targe t, det ects ba d eve n pari ty on a PCI t arget write
data
cycl e,
the controll er:
Completes the write.
Asserts PERR#, if enabled by the:
• PEREN bit in the PCI Command Register (PCICMD, Section 7.13.3).
On a write to SDRAM, forces bad parity or ECC to be written to that address, if
enabled by the:
• PEREN bit in the PCI Command Register (PCICMD, Section 7.13.3).
On a write to the controller’s internal registers, i ncluding timers, DMA, and UAR T,
the data is ignored (not written), if enabled by the:
• PEREN bit in the PCI Command Register (PCICMD, Section 7.13.3).
7.6
64-Bit PCI Bus The controll er optionally supports a 64-bit PCI Bus. In t his case, the controll er’s 32-bi t
Local Bus cannot be used, because the LOC_AD[31:0] signals and other Local-Bus
signals are reallocated for use on the PCI Bus, as described in Section 8.5.
Two functions are involved in this 64- bit PCI Bus support: th e controll er’s PCI -Bus
width, and the PCI 64-bit Bus Extension, as defined in the PCI Specification. The two
functions are enabled as fol lows:
Control ler’s 64-Bit PCI- Bus W idth:
Enabled w hen PCI64# is asserted during the
assertion of PCIRST#.
PCI 64-Bit Bus Extension (per PCI Specification):
Enabled when REQ64# is
asserted by the PCI Central Resource during the assertion of PCIRST# , and
dynamically negotiated on a per-transaction basis using REQ64# and ACK64#.
The possible confi gurations using thes e two signals are:
If PCI64# is ne gated dur ing PCIRST#, the contr oll er implemen ts a 32-bit PCI Bus,
irre spective of t he stat e of REQ64#.
If (a ) PCI64# is asserted during the assertion of PCIRST#, (b) the cont rol ler is not
the PCI Central Reso urce and the REQ64# input from the PCI Central Resource
is negat ed durin g the asser tion o f PCIRST #, the con trol ler’ s 64- bit PCI behavior is
disabl ed and the high 32 bits of the controller’ s 64-bit PCI Bus are always driven
to prevent them from floating.
If, during the assertion of PCIRST#, PCI64# is assert ed and REQ6 4# is asserted
(i.e ., the PCI Central Resource ass ert s REQ6 4# to the controller or the controll er
itsel f is the PCI Central Resource), the cont roller attempts to initiate 64-bit data
transactions whenever possible to improve performance. The controller also
responds properly as a 64-bit target.
When t he controller i s configured for 64- Bit PCI-Bus width, the control ler only initiates
32-bit tra nsactions when the ACCESS_32 bit is set in the PCI Master (I nitiat or) Regis-
ters 0 and 1 (PCIINITn), Section 7.11.3. This bit must be set when the controller, as
PCI-but master, access es the PCI I/O Space or Confi guration Space. The
ACCESS_32 bit resets to 0.
7.7
Dual Address Cycl e
(DAC) Support
The controlle r supports Dual Address Cycles (DAC) as both a PCI mast er and target,
thus supporting 64-bit addressing. As a PCI master, the control ler automatically uses
64-bit addressing when the high PCIADD field (bits 63:32 in the corresponding PCI-
INITn register) are non-zero.
7.8
PC I C e n t ral
Resource Support
Every PCI Bus must have a PCI Central Resource that provides speci al functi ons for
that bus. In systems which have multi ple PCI Buses, each PCI Bus m ust ha ve its own
Central Resource. The contro ll er performs PCI Cent ral Resource functio ns wh en the
PCICR# input is asserted to the controller at reset.
7.8.1
Central Resource
Functions
The controller can optio nally provide som e or all of these PCI Centr al Resource func-
tions. These fun ctions are enabl ed when PCICR# is asserted at reset and sof tware
configures various fi elds in the PCI Control Re gister (PCI CTRL), Section 7.11.1, and
PCI Arbiter Regis ter (PCIARB), Section 7.11.2.
When the PCICR# input is asserted to the controller at reset:
PCI Clo cks:
The control ler’ s PCLK[ 4:0] signal s are all outpu ts that can be
connected to the CLK input on up to five other PCI devices. The controller it self
always uses PCLK[0] as its PCI-Bus clock. See Sect ion 7.9 for det ails.
PCI-Bus Arbitrati on:
The controller’s REQ#[4:0] signals are all inputs that can be
connected to the REQ# output f rom up to five other PCI devi ces, and its
GNT#[4:0] signals are all output s that can be connected to the GNT# inp uts from
these other PCI devices.
CPU Interrupts:
The controller’s INTA# signal is bidirectional, rather than an
output, so tha t the co ntr oller can acce pt up to five PCI inter rupts on I NT A# through
INTE#. It forwards these interrupts to the CPU, as specified in Section 5.5.2.
PCI Reset:
The controller’s PCIRST# si gnal is an output rather than in put, and
this signal can be conne cted to the RST# input on up to fi ve other PCI device s.
The controller asserts PCIRST# in any of the following cases:
• On Power-Up.
• When the CLDRST bit is set in the CPU St atus Register (CPUSTAT), Sect ion
5.5.1.
• When the PCICRST or PCIWRST bit is set in t he PCI Contr ol Register
(PCICTRL) , Section 7.11.1.
64-Bit Bus Extension:
The controller configures 64- bit PCI-Bus oper ation by
asserting its REQ64# output at the end of reset. See Section 7.6 for details.
PCI Configuration Cycles:
The controller is responsible for generating IDSEL
inputs to othe r PCI devices on the same PCI Bus, during CPU accesses the PCI
Configuration Space (Section 7.12). Section 7.12.3 illustrates how these IDSEL
inputs may be gene rated.
7.8.2
Central Resource
Terminology
When the controller is not providing PCI Central Resource functions, it is operating in
PCI
Stand-Alone Mode
. For exampl e, in a system where there is already a CPU and
controlle r providing host and Central Resour ce functions, addit ional memory or Local -
Bus capabilit y can be provided by a second controller in PCI Stand-Alone Mode, as
shown in Fi gure 5 on page 16 and Figure 6 on page 17. Thi s capability is especial ly
useful if the Main Controller has a 64-bi t PCI, thus remov ing its Local Bus.
It i s possible to have multi ple control lers on a singl e CPU and have all controll ers on
the same PCI Bus. In this case, only one controller should provide the Central
Resourc e functi ons and the ot hers shoul d operate i n Stand-Al one Mode. The c ontroll er
can support a CPU in Stand-Alone Mode. However, if the CPU is not the Main CPU in
the sys tem, care must be ta ken when configur in g cont roller resour ces at boot time. For
exam ple, two CPUs should not simultaneously att em pt to modify t he controll er config-
uration and control regist ers. The PCIWRST bit in the PCI Control Register (PCIC-
TRL), Sect ion 7.11.1, mus t be used car efully i n thi s case.
The concepts of PCI Centr al Resource and Main Contr oller (Section 5. 3.2) are unre-
lat ed. The contr olle r can be a Main Contro ller for a gi ven CPU, but that CPU might not
be the Main CPU in the syst em , and th e Main Contr oller for that CPU, or any other
CPU in t he system, might not provide the PCI C entral Re source for the system.
7.8.3
External Arbitration External arbitr ation logic can be used. For exa mple, it would be needed if more than
fiv e PCI d evices need to arbitr ate with the cont rol ler, or if a custom arbi tration protocol
is desired. Even with external arbitration logic , the controll er can optionall y perform al l
other PCI Central Resource functions.
The controller’ s arbiter is di sabled by:
Negatin g the PCICR# input, thus dis abling
all
Central Reso urce functi ons by the
controller, or
Setting the ARBDISABLE bit (bit 63) of the PCI Arbiter Regist ers (PCIARB,
Section 7.11.2), thus disabling only the arbitration function, but leaving the other
Central Resource functions enabled.
When th e controll er’s internal arb iter is disabled, REQ#[0] i s an output to the external
arbi ter, GNT#[0] is a n input f rom the exter nal arbiter , and REQ#[ 4:1] and GNT#[4:1] are
unused inputs.
7.9
PCI Clockin g The controller generat es the PCI cl ocks, PCLK[4: 0], based on either the external
PCLKIN signal or a synchr onous multipl e of the CPU SysClock. The sour ce for the
controlle r’s gene rat ion of PCLK[4:0] is con trolled by the CLKSEL[2:0] field in the PCI
Control Register (PCICTRL, Section 7.11. 1), as shown in Table 23. At reset, the CLK-
SEL[0] bit takes the state of the M66EN (66 MHz Enable) input signal, and the CLK-
SEL[2:1] bits are set via t he Seri al Mode EEPROM bit s. These bits should only be
changed while the PCI Bus is reset; other wise, PCLK[4:0] ma y gli tch.
If the PCI clock is generated by external logic via the PCLKIN input, the external clock
logi c m ust foll ow the M66EN signal on the PCI Bus; i.e., it must only generate a clock
greater than 33 MHz when M 66EN is asserted. The clock skew betwee n PCLKIN and
the PCLK[4:0] outpu ts i s several nanoseconds.
The PCISYNC bit in the PCI Control Register (PCI CTRL, Section 7.11.1) indicates
whether PCLK[4:0] is synchronous to Sys Clock. This affects the performance of hand-
shake si gnals between the PCI logic and the rest of th e cont roller . The cont roller clear s
thi s bit at r eset. When it is set by software, it indi cates that s ign als passing bet ween the
PCLK[4:0] and SysClock timing domains are synchr onized and do not need re- syn-
chronization to avoid metastability. However, even if PCLK[4:0] are sourced from
SysClock, and thus are a synchronous multiple of SysClock, PCLK[4:0] are not skew-
contr olle d and the e dges a re no t aligned t o Sy sClock, due to cl oc k skew int ernal to the
controller. Thus, it is generally not advisable to set the PCISYNC bit.
The controller always uses the PCLK[0] input as its PCI clock, but the controller can
either recei ve or gen erat e the PCI clocking for the system. When the PCICR# input is
negated (i.e. the controller is not providing PCI Central Resource functions), PCLK[0]
is enabl ed as the PCI clock in put, and PCLK[4:1] are fl oated. When PCICR# is
asser ted, PCLK[ 0] is enab led as t he PCI cloc k input (for the con tr oller’s PCI inte rface) ,
and PCLK[4:0] are all enabled as outputs. In this Central Resourc e configuration,
PCLK[4:0] are five separate, identic al copies of the PCI cloc k.
Table 23: PCLK[4:0] Source Specification
CLKSEL PCLK Source When used
000 PCLK frequency is 1/3 SysClock For 33 MHz PCI Bus with SysClock > 66 MHz
001 PCLK frequency is 2/3 SysClock For 66 MHz PCI Bus with SysClock > 66 MHz a
a. CLKSEL = 001 us es the cont roller’s internal 2x mul tiplying PLL. To stay within the spec-
ified operating range of this PL L, 112.5 MHz >= SysClock >= 67.5 MHz.
010 PCLK frequency is 1/2 SysClock For 33 MHz PCI Bus with SysClock <= 66 MHz
011 PCLK frequency is equal to SysClock For 66 MHz PC I Bus with SysClock <= 66 MHz
10x PCLK is driven by signal PCLKIN Any combination of SysClock and PCLK
11x
reserved
All devic es on the PCI Bus must opera te at t he same clock speed. If dif ferent PCI c lo ck
speeds m ust be suppor ted , this can be do ne in a multi-control ler configuration ( Section
5.3) . For example, two control lers can be connec ted to a single CPU, with one control-
ler running at 33 MHz and the other at 66 MHz, as shown in Figur e 7 on page 18.
7.10
PCI Locked Cycles The controll er’s bidirect ional LO CK# signal provides a mechanism for obtain ing exclu-
sive acc ess to PCI targets, as def ined in the
PCI Local Bus Specific ati on
, Section 3.6.
As a PCI master, the contr oller can asser t LOCK#. As a PCI t arget, the cont roller
responds to the assertion of LOCK#.
To impleme nt l ocking when the contr oller is the PCI master, software for the in it iator
(CPU or DMA) sets the LOCK bit in the PCI Master (Initiator) Registers 0 and 1 (PCI-
INITn ), Section 7. 11.3, an d then perform s a PCI-Bus read . This l ocks the 16- byt e read
region using the LOCK# protocol. No other PCI device is allowed to access that 16-
byte region duri ng the read.
You can us e the PCI LOCK# protoc ol to main tain semaphor es. Howev er the
PCI Local
Bus Specification
recommends against this , advi sing instead that a software protocol
be used. This is mainly for compatibil ity reasons, becau se not al l systems may imp le-
ment LOCK# properly (if at all). Furthermore, using LOCK# may be inefficient. In par-
tic ular, you cannot have multiple simul taneous locks. Only have one 16-byte regi on
can be locked on the entire bus at any one time.
This l ocking mechanism aff ects only PCI-Bus accesses. It does not pr event the CPU
from acc essi ng an area of the cont roll er’ s memor y that is lo cked by a PCI-Bus ma ster.
However, the CPU can prevent PCI-Bus masters from accessing a 16-byte region of
the controller’s memor y by first sett ing the LOCK bit in the PCII NITn register and then
accessing the controller’s memory with a loopback access.
7.11
PCI-Bus Registers
7.11.1
PCI Control Register
(PCICTRL)
Bit 0 PCISYNC
PCI-Synchroniz ed.
1 = synchroni zed.
0 = not synchronized.
When set , thi s bit indi cates tha t si gnals pass ing
between the PCLK[4:0] and SysClock timing
Table 24: PCI-Bus Registers
Regist er Symb ol Offs et R/W Reset Value Descripti on
PCI Control PCICTRL 0x00E0 R/W 0x?000 0000 8000 000? aMi s c ellaneous PCI con trol.
PCI Arbiter PCIARB 0x00E8 R/W 0x0050 0011 1100 003F PCI arbiter control.
PC I Mas ter (Initiator ) 0 PCIINI T0 0x00F0 R/W 0x0 000 0000 0000 8406 Cont r ol for PCI A ddr ess Window 0.
PC I Mas ter (Initiator ) 1 PCIINI T1 0x00F8 R/W 0x0 000 0000 0000 8406 Cont r ol for PCI A ddr ess Window 1.
PCI Error PCIERR 0x00B8 bR/W 0x0000 0000 0000 0000 Addres s of PCI internal error.
a. The question marks (?) indicate that the reset value depends on the CLKSEL, PCIWRST and PLL_STBY fields of PCIC-
TRL, which in turn depen d on external inputs during reset.
b. Note the non-con s ecutive address.
domains are synchronized and do not need re- syn-
chronization to avoid metastabil ity. Res ets to 0.
This
bit i s provid ed for testi ng purposes only. Do not set it
to 1 for nor mal operation! Setting this bit will not pro-
vide a sig nificant performan ce inc rease and may
cause undesirable behavior.
Bit 3:1 CLKSEL[2:0]
PCLK[4:0] Output Source Sele cti ons
.
Even when PCLK[4 :0] ar e a sync hronous m ultipl e of
SysClock, they are not skew-control led, and the
edges are not aligned with SysClock. Thi s fi eld has
no effect when PCICR# is neg ated because in that
case the PCLK[4:0] outputs float. At reset, the CLK-
SEL[0] bi t takes the state of the M66EN input signal,
and the CLKSEL[ 2:1] bits are set via t he Seri al Mode
EEPROM bits 260:259.
Bit 7:4 CPUHOG
Minimum Number of Accesses by CPU.
The minimum number of cons ecutive CPU accesse s
to PCI resources through the PCI Output FIFO
(OUTFIFO) bef ore the CPU is forced to allow
another contr oller resource to tak e contr ol of the PCI
Bus. 1 to 15 means 1 to 15 consecutive accesses, 0
means 16 cons ecutive accesses. Resets to 0 (16
accesses). The limit counter starts counting wi th the
first CPU access, irrespective of when another con-
trol ler resour ce request s the PCI Bus. The PCI-Bus
CPUHOG and DMAHOG fields are the sof tware
interface to the Progr amma ble 2-W ay Arbiter , shown
in Figure 1 on page 12.
Bit 11:8 DMAHOG
Minimum Number of Accesses by DMA.
The minimum num ber of consecutive PCI-Bus
accesses the DMA may perform through the PCI
Output FI FO (OUTFIF O) before the DMA is forced t o
allo w another control ler resource to take cont rol of
the PCI Bus. 1 to 15 means 1 to 15 consecutive
accesses, 0 means 16 consecutive accesses.
Resets to 0 (16 accesses). The limi t count er starts
coun ting with the first DMA access, irrespect ive of
CLKSEL
Value Description
000 PCLK[4:0] frequency is 1/3 SysClock
001 PCLK[4:0] frequency is 2/3 SysClock (uses 2x PLL)
010 PCLK[4:0] frequency is 1/2 SysClock
011 PCLK[4:0] frequency is equal to SysClock
10x PCLK[4:0] is driven by PCLKIN signal
11x
reserved
when another control ler resource requests the PCI
Bus. This behavior of the limit counter differs from
that of the CPUHOG, PCIHOG and DMAHOG fields
in the Loca l Bus Configuration Register (LCNFG,
Section 8.6.1).
Bit 12
reserved
Hardwir ed to 0.
Bit 13 FAPER
Force Address-Pari ty Errors
.
1 = force even-parity errors on address es when con-
troller is PCI master; i.e., generates odd parity.
0 = normal even-parit y generation on addr esses
(reset value).
Bit 14 FDPER
Force Data-Parity Errors
.
1 = force even- parity err ors on data when controller
is PCI master (writes) or target (reads); i.e., gener-
ates odd parity.
0 = normal even-parit y generation on dat a (reset
value).
Bit 15 FIFOSTAL L
PCI Output FIFO Stal l
. (r ead-only)
1 = PCI Out put FIFO (OUTFIFO) is stalled.
0 = PCI Output FIFO (OUTFI FO) not stall ed (r eset
value).
Bit 23:16 RTYLIM
Retry Limit.
Specifies how many consecutive retries the control-
ler accepts fro m a single target. 0 mean s no li mit,
non-zer o values are multip lied by 28 ( 8-bit shift ed) to
derive the actual retry limit. Resets to 0 (no limit).
Bit 31:24 DISCTIM
Discard Time-Out.
When cont rol ler performs a delayed read as a PCI
target , and the master does not repeat th e request
within the DISCTIM number of PCI clocks,
PCLK[4:0], the controller discards the read data to
prevent deadlocks. 0 means 216 clocks, non-zero
values are multi plied by 28 (8-bit s hifted) to derive t he
actual discard time-out. Resets to 0x80 (215 PCI
clocks).
The fol lowing f ive bits enab le t he controll er’s capt ure, into th e PCI Error Regi ster ( Sec-
tion 7.11.4), of the PCI address at which a PCI error occurred. These ar e controll er
internal errors , i n which the controller was the master and/or target of t he PCI transac-
tion. All bits reset to 0.
Bit 32 TACH
Target -Abort Address Capture
.
1 = enable capture of target-abort address when
controller is PCI master.
0 = disable this capture.
Bit 33 MACH
Master-Abort Address Capture.
1 = enable capture of master-abort address when
controller is PCI master.
0 = disable this capture.
Bit 34 RTYCH
Retry-Limit Exceeded Address Capture.
1 = enable capture of retry-limit-exceeded address
when controller is PCI mast er.
0 = disable this capture.
Bit 35 PERCH
Data-Par ity Error Address Capture
.
1 = enable capture of data-parity error address (on
reads or writes) when contr oller is PCI master.
0 = disable this capture.
This bi t is independent of t he Parity Err or Response
(PEREN) bit in the PCI Configuration Command
Register (Section 7.13.3).
Bit 36 DTIMCH
Discard-Timer Expired Addr ess Capture.
1 = enable capture of di scard-ti m er expired address
when controller is PCI target.
0 = disable this capture.
This is o nly an e rr or when it occ urs on r eads i n which
the data i s not pr efetchable. If the data is prefetch-
able, then it is silently discarded. Data is prefetch-
able if the PREFETCHABLE bit in the PCI Base
Address Register ( BAR) for this devi ce (Section
7.13.10) is set, or the PCI command was a Memory
Read Line or Memory Read Multipl e.
Bit 39:37 ERRTYPE
Er ror Type.
(read- only)
Indic ates the type of PCI error whose address was
captured in the PCI Error Regi ster (Secti on 7.11.4).
Resets to 0. Cleared to 0 when the PCI Error Regis-
ter is cleared.
ERRTYPE Meaning C ontroller was
000 No error
001 Target A bor t Ma s ter
010 Master A bor t Ma s ter
011 Retry Limit Exceeded Master
100 Data Re ad Parity Error Master
101 Data Write Parity Error Master
110 Discard Timer Expired Target
111
reserved
The following seven bits ena ble the assertion of SERR# as an output. All bits reset to
0. The SER R# Enable (SER REN) bit in the PCI Com mand Register (Section 7.13.3)
must be set i n order to drive SERR#.
Bit 40 TASE
Target -Abort SERR# Enable.
1 = assert SERR# on target-abort when controller is
PCI master.
0 = disable this assertion.
Bit 41 MASE
Master-Abort SERR# Enable.
1 = asser t SERR# on master-abort whe n controller is
PCI master.
0 = disable this assertion.
Bit 42 RTYSE
Retry-Limit-Exceeded SERR# Enable.
1 = assert SERR# on retr y-li mit- exceeded when con-
tro lle r is PCI m a st e r.
0 = disable this assertion.
Bit 43 PERSE
Data-Par ity Error SERR# Enable.
1 = asser t SERR# on data even -par ity error (reads or
writes) when controller is PCI master.
0 = disable this assertion.
Such data parity errors only occur if the Parity Error
Response (PEREN) bit is set in the PCI Command
Register (Section 7.13.3).
Bit 44 DTIMSE
Discard-Timer Expired
SERR# Enable
.
1 = assert SERR# on discard-timer expired when
controller is PCI target.
0 = disable this assertion.
Discar d-ti mer expire d is only an error when it o ccur s
on reads in which the data is not prefetcha ble. If th e
data is pr efetchable, it is silently discarded. Dat a is
prefet chable if the PREF ETCHABLE bit in the PCI
Base Address Register (BAR) for this device (Sec-
tion 7.13.10) is set, o r the PCI command was a Mem-
ory Read Line or Memory Read Multiple.
Bit 45 AERSE
Address-Parit y Err or SERR# Enabl e.
1 = assert SERR# on address even-parity error for all
PCI trans actions.
0 = disable this assertion.
Address parity er rors only occur if the Parit y Err or
Response (PEREN) bit is set in the PCI Command
Register (Section 7.13.3).
Bit 46 INT1SE
Int#[1] SERR# Enable.
1 = assert SERR# when Int#[1] is asserted.
0 = disable this assertion.
This fun ction should only be enabled when the con-
trol ler needs to indicat e a system error to a PCI host
CPU,
and
the cont roller is not t he Main CPU in the
system. The function is independent of the state of
the Int#[1] Controller Output Enable (IL1OE) bit in
the I nterru pt Status 1/ CPU I nterrupt Enabl e Regist er
(Section 5.5.4). The PCI SERR# Interrupt Priority
(PCISPRI) field of the Interrupt Control Register
(Secti on 5.5.2) should not be equal to 0x1 (no l oop-
back).
Bit 47
reserved
Hardwir ed to 0.
The following six bits (53:4 8) enable the assertion of a PCI Internal Error interrupt, if
such interr upts are enabled by the PCIEEN bit of t he Interrupt Control Regis ter (INTC-
TRL, Sect ion 5.5. 2). All six bits rese t to 0. A
PCI Internal Error
indicates that somet hing
bad happ ened d uring a PCI transac tion; the f ault could l ie ei the r with t he PCI device or
the controll er.
Bi t 4 8 TAIN
Target -Abort PCI Internal Error Enable.
1 = assert PCI internal err or on target- abort when
controller is PCI master.
0 = disable this assertion.
Bi t 4 9 MAIN
Master-Abort PCI Inter nal Error Enable.
1 = assert PCI internal err or on master-abort when
controller is PCI master.
0 = disable this assertion.
Bit 50 RTYIN
Retry-Limit-Exceeded PCI Internal Error Enable.
1 = assert PCI internal err or on retry- li m it -exceed ed
when controller is PCI mast er.
0 = disable this assertion.
Bit 51 PERIN
Data-Parity Error PCI Internal Error Enable.
1 = asser t PCI int ernal error on d ata even-parit y error
(reads or writes) when contro ll er is PCI master.
0 = disable this assertion.
This bi t is independent of t he Parity Err or Response
(PEREN) bi t i n the PCI Comm and Register (Section
7.13.3).
Bit 52 DTIMIN
Discard-Timer Expired
PCI Inte rnal Err or Enable
.
1 = assert PCI inte rnal error on discar d-timer exp ir ed
when controller is PCI target.
0 = disable this assertion.
Discar d-ti mer expire d is only an error when it o ccur s
on reads in which the data is not prefetcha ble. If th e
data is pr efetchable, it is silently discarded. Dat a is
prefet chable if the PREF ETCHABLE bit in the PCI
Base Address Register (BAR) for this device (Sec-
tion 7.13.10) is set, o r the PCI command was a Mem-
ory Read Line or Memory Read Multiple.
Bit 53 AERIN
Address-Parit y Err or PCI Internal Error.
1 = assert PCI internal err or on address even-parit y
err o r fo r all PC I tr an s a c tio n s .
0 = disable this assertion.
Address parity er rors only occur if the Parity Error
Response (PEREN) bit is set in the PCI Command
Register (Section 7.13.3).
Bit 55:54
reserved
Hardwir ed to 0.
Bit 56 INTAEN
Int#[ 0]-On-INTA# Enable.
1 = enable INTA# to be dri ven with Int #[0] value.
0 = disable (reset value).
This fun cti on should only be enabled when the con-
trol ler needs to inter rupt the CPU when a PCI int er-
rupt occ urs,
and
the cont roller is not the Main CPU in
the system. The function i s indepe ndent of the st ate
of the Int#[0] Control ler O utput Enable (I L0O E) bit i n
the I nterru pt Status 1/ CPU I nterrupt Enabl e Regist er
(Section 5.5.4). The Interrupt Signal INTA# Priority
(INTAPRI) field of the Interr upt Control Register
(Secti on 5.5.2) should not be equal to 0x0 (no l oop-
back).
Bit 58:57
reserved
Hardwir ed to 0.
Bit 59 LATDIS
Input-Latch Di sable.
1 = disable .
0 = enable (reset value).
The PCI signal s have input latches which are nor-
mally closed when the PCI clock is High. This helps
to ensure the 0-ns hold time on these inputs. When
this bit is set, the input latches are transparent.
Bit 60 PLL_SYNC
PLL Synchronization.
1 = reset s the di vide- by-2 at the ou tput of the cont rol-
ler’s internal 2x mult iplyin g PLL. Used for test pur-
poses.
0 = no explicit synchronization (reset value).
Bit 61 PLL_STBY
PLL Standby.
1 = turn off the PLL (reset value).
0 = turn on the PLL.
If PCICR# is asser ted and the CLKSEL[2:0] fi eld in
the PCI Control Register (Secti on 7.11.1) is 001, the
controller automatically clears this bit at the end of
reset to enable it s int ernal PLL. Aft er the PLL is
turned on, the system must give it time to lock up
before clearing the PCI Warm Reset bit (bit 62,
immediately below). The current PLL specification
(CB-C9 Mul ti pl ying APLL Data Sheet)
requi res a tlock
of 100ms.
Bit 62 PCIWRST
PCI Warm Reset.
1 = PCI warm reset.
0 = normal operation.
This bi t functions dif fer ently, depending on the con-
trol ler’ s configuration, as shown in table below.
Setting this bit allows the CPU to program the PCI
Config urat ion Space Registers (Sec tion 7.13) befor e
making the controller visible as a PCI target.
Bit 63 PCICRST
PCI Cold Reset
.
1 = reset cont roller PCI logi c and (i f PCICR# is
asserted) assert PCIRST#.
0 = normal operation (reset value).
When this bit is set, all PCI configuration reg ist ers
take their reset values, and all data and pending
operations in the PCI FIFOs are lost.
7.11.2
PCI Arbite r Re gist er
(PCIARB)
This register control s the operation of the PCI arbiter when t he controller perfor m s the
PCI Central Resource functions (PCICR# asserted). Up to six devices can request
access to the PCI Bus: fi ve request via the REQ# [4: 0] signals and the sixth is the con-
trol ler its elf as a PCI-Bus master (i nit iator).
The controller implement s three-level rota ti ng priori ty arbitr ati on. Each of the six
reques tors can be i n any (or sever al) of three groups. For any given access, one group
will h ave t he highest prio rity, as sho wn in Table 25. For any gro up, th e longes t- pending
request has prior ity. If ther e is no req uestor in that group, then the longest-pending
request at the next -l owest priority gro up wins.
PCICR#
Signal CPU
Present Function of PCIWRST Bit
as serted alway s PCIRST # signal is asserted w hile this b it
is set. Resets to 1.
negated yes All PCI accesses to contro ller as target
are ret r ied while this bit is set.
Rese ts to 1.
negated no All PCI accesses to controller as targ et
are ret r ied while this bit is set.
Rese ts to 0.
Bit 5:0 GROUP0
Requestor s Allowed In Group 0
.
Resets t o 0x3F (all 1s), which all ows all requ estors in
Group 0.
Bit 7:6
reserved
Hardwir ed to 0.
Bit 13:8 GROUP1
Requestor s Allowed In Group 1
.
Same bit-values as the GR OU P0 fi eld. Resets to
0x00, which allows no requestors in Group 1.
Bit 15:14
reserved
Hardwir ed to 0.
Bit 21- 16 GROUP2
Requestor s Allowed In Group 2
.
Same bit-values as the GR OU P0 fi eld. Resets to
0x00, which allows no requestors in Group 2.
Bit 23:22
reserved
Hardwir ed to 0.
Bit 27:24 CONS0
Group 0 Highest-Priority Consecutive Accesses.
The number of consecutive accesses for which
Group 0 has highest prior ity. 1 to 15 means 1 to 15
consecutive accesses, 0 mean s 16 consecutive
accesses . Resets t o 0x1. (See t he exampl e following
Bit 63, below.)
Bit 31:28 CONS0n
Group 0 Non-Highest-Priority Consecutive
Accesses.
The number of consecutive accesses for which
Group 0 does not have highest priority. 1 to 15
means 1 to 15 con secutive accesses, 0 mean s 1 6
consecutive accesses. Re sets to 0x1. (See t he
example followi ng Bit 63, below. )
Bit 35:32 CONS1
Group 1 Highest-Priority Consecutive Accesses.
Of the Group 0 non-highest-pri ori ty access es, the
Table 25: Three-Level Rotating PCI-Bus Arbitr ation Priori ty
when Highest-Priority Lev el Is: ... Middle-Priority Level Is: ... And Low est-Priority Level Is:
Group 0 Group 1 Group 2
Group 1 Group 2 Group 0
Group 2 Group 0 Group 1
Bit Requestor
0 REQ#[0] allowe d
1 REQ#[1] allowe d
2 REQ#[2] allowe d
3 REQ#[3] allowe d
4 REQ#[4] allowe d
5 Co ntroll er allowed
number of consecutive accesses for which Group 1
has highest priority. 1 to 15 means 1 to 15 consecu-
tive accesses, 0 means 16 consecut ive acces ses.
Resets to 0x1. (Se e the example following Bit 63,
below.)
Bit 39:36 CONS2
Group 2 Highest-Priority Consecutive Accesses.
Of the Group 0 non-highest-pri ori ty access es, the
number of consecutive accesses for which Group 2
has highest priority. 1 to 15 means 1 to 15 consecu-
tive accesses, 0 means 16 consecut ive acces ses.
Resets to 0x1. (Se e the example following Bit 63,
below.)
Bit 43:40 PARK0
Group 0 Park Count (in PCI clocks).
If t he current Group is 0, and t he next-to-be-granted
Group is al so 0, and there are no Group 0 req uests
asserted, then i nstead of immediat ely granti ng
access to a lower-pr ior ity-gr oup requestor, arbitra-
tion i s park ed in Group 0 for this many PCI cloc ks.
During this time , onl y Group 0 requestors are ser-
viced. Resets to 0.
Bit 47:44 PARK1
Group 1 Park Count (in PCI clocks).
Same parame ter-type as PARK0. Resets to 0.
Bit 51:48 PARK2
Group 2 Park Count (in PCI clocks).
Same parame ter-type as PARK0. Resets to 0.
Bit 54:52 DEFGNT
Default Grant Devi ce.
This f ield sp ecifi es the dev ice that is gran ted the bus
when there ar e no requests asserted on REQ#[4:0]
and the Park Counter (PAR K2:0) has expired.
Resets to 0x5 (controller is default). Asserting the
default grant does not modify the rotating priority
group.
Bit 62:55
reserved
Hardwir ed to 0.
Bit 63 ARBDISABLE
Arbi t rat o r D isa ble.
1 = disable .
0 = enable (reset value).
Disabl es the internal arbiter, even if PCICR# is
DE FGNT Value Defa ul t device
0 GNT#[0] device
1 GNT#[1] device
2 GNT#[2] device
3 GNT#[3] device
4 GNT#[4] device
5 Controller (reset value)
7:6 No defa ult asserted
assert ed. W hen thi s bit is s et to 1 ( disabl ed), t he con-
troller uses REQ#[0] and GNT#[0] to comm unicate
with an ext ernal arbi ter.
The
CONS0
throu gh
CONS2
field s are used to sp ecify t he number of PCI acces ses in
which each arbitration group has priority. Group 0 is highe st pr iority for
CONS0
con-
secut ive acce sses, followed by
CONS0n
consecut ive accesses, sp li t b etween Group 1
and Group 2. Consideri ng just the
CONS0n
accesses, Grou p 1 is hig hest priority for
CONS1
consecutive accesses, followed by Group 2 highest for
CONS2
consecutive
accesses.
Here is an e xampl e: ass ume
CONS0
= 5,
CONS0n
= 3,
CONS1
= 4,
CONS2
= 3. Then
highest priority wil l be: 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 1, 1, 0,
0, 0, 0, 0, 1, 1, 2...
Total Arbitration Events =
CONS0
+
CONS0n.
Fraction that Group 0 accesses gets PCI Bus =
CONS0
/ Total Arbitration Event s.
Fraction that non-Group 0 accesses gets bus =
CONS0n
/ Total Arbitr ati on
Events.
Fracti on of non-Group 0 accesses that Group 1 gets bus =
CONS1
/
(CONS1
+
CONS2).
Fracti on of non-Group 0 accesses that Group 2 gets bus =
CONS2
/
(CON S1
+
CONS2).
7.11.3
PCI Master (Initiator)
Registers 0 and 1
(PCIINITn)
There ar e two PCI Master ( Ini tiator) Regi sters, PCIINIT0 and PCII NIT1, one for each of
the two PCI Addre ss Windows speci fied by Physical Device Addr ess Register s PCIW0
and PCIW1 (Section 5.4), respectively. These address windows can be accessed by
the CPU, DMA, or Local- Bus devic es with t he contro ller act ing as the PCI-Bus maste r .
The PCIINI T0 and PCII NIT1 regist ers both have the same for mat:
Bit 0
reserved
Hardwir ed to 0.
Bit 3:1 TYPE
PCI Command Type.
The upper thr ee bits of the 4- bit PCI comm and type
(Table 21) driven on C/BE#[3:0] at the beginning of
the PCI access. Resets to b011 (Memory Read and
Memory Wr ite). The low bit of the command type is 0
for rea ds and 1 for writes. As PCI-Bus master, the
controller can access any PCI space and perform
any vali d PCI comm and. The PCI I/O Space, for
example, can be accessed by programmi ng the
TYPE fie ld to b001; the PCI Configuratio n Space can
be accessed by progr amming the TYPE field to
b101. See Section 7.4.3 for more information.
Bit 4 ACCESS_32
32-Bit Access.
1 = 32-bit .
0 = PCI-Bus width as initialized (32- or 64-bit).
Setti ng this bit forces a PCI access to be a 32-bi t,
even if t he 64-bit bus ext ension is implemented
(PCI64# asserted at reset). Normally, when a 64-bit
PCI Bus is implem ented, the controller attempts a
64-bi t access and f alls back to 32-bit only if t he target
requires it. This bit must be set when the control ler,
as PCI-Bus master, accesses the PCI I/ O Space or
Configurati on Space. Resets to 0.
Bit 5 LOCK
PCI LOCK#.
1 = acquire or maintain Exclu sive Access.
0 = no lock (reset value).
See Section 3.6 of the
PCI Local Bus Speci ficati on
for det ail s on Exclusive Access and the LOCK# sig-
nal.
Bit 6 COMBINING
Burst-Combining
.
1 = combine bursts on memo ry writes.
0 = do not combine bursts (reset value).
Burst- com bining consists of combini ng a sequence
of burst writes to sequential locations into a single
PCI-Bus t ransaction. See Sectio n 7.4. 3 for detail s.
Bit 7 MERGING
Byte-Merging
.
1 = merge bytes on memor y wri tes.
0 = do not merge bytes ( reset value).
Byte-merging consists of merging a sequence of
individual byte or word writes into a single dword
PCI-Bus t ransaction. See Sectio n 7.4.3 for detai ls.
Bit 8 PREFETCHABLE
Prefet ch Enable.
1 = enable prefetching on memory reads.
0 = disable (reset value).
On reads, setting this bit enables the controller to
prefet ch additional data beyond that whic h is i mme-
diate ly requested by t he CPU or DMA. See Section
7.4.4.2 for detail s.
Bit 9 CONFIGTYPE
PCI Confi guration-Space Access Type.
1 = type 1 access.
0 = type 0 access (reset value).
When the con troller initiat es accesses to the PCI
Configuration Space, this bit indicates whether they
are Type 0 or Type 1 accesses. Type 0 accesses
(PCI_AD[ 1:0] = 00) select a dev ice on the same PCI
Bus that the cycle is being run. Type 1 accesse s
(PCI_AD[ 1:0] = 01) pass the conf iguration request
on to another PCI Bus.
Bits 14:10 SINGLE_PFB
Singl e-Dword Prefet chable.
For CPU-initiated single dword (non-block) Memory
Read commands with the PREFETCHABLE bit set,
this field specifies the number of 4-dword blocks to
prefet ch beyond the first block. See Sect ion 7.4.4.2
for det ail s. Resets to 0x01.
Bits 20:15 BLOCK_PFB
Block Prefetchable.
For CPU-initiated block Memory Read commands
with the PREFETCHABLE bit set, t his field specifies
the number of 4-dword bl ocks to pref etc h beyond the
fir st block. See Section 7.4.4.2 for det ail s. Resets to
0x01.
Bits 35:21 PCIADD
PCI Address (Lower).
The lower PCI phy sical addres s bits. These bi ts ar e
to be masked by the MASK field of the PDAR (Sec-
tion 5.4). Resets to 0x0. The CPU provi des the low-
est address bits—those from bit 0 up to the highest
bit mas ked by the MASK field. See the PCI Address
Decoding Exam ple, Section 7.4.2.
Bits 63:36 PCIADD
PCI Address (Upper).
The upper PCI physic al address bits. Resets to 0x0.
See the PCI Address Decoding Example, Section
7.4.2.
7.11.4
PCI Error Register
(PCIERR)
This register captures the PCI addr ess of last uncl eared PCI error, if address capture
is enabled by bits 36:32 of th e PCI Control Register (Sect ion 7.11.1). Writing anything
to this register clears it to 0, and also clears the PCI Control Register ERRTYPE to 0.
Due to c loc k synch roni za tion req uirem ents, it may ta ke s evera l CPU cl ocks for t his r eg-
ist er (a nd ERR TYPE) to be cleared aft er th is r egister is writ ten.
Bit 0 IS_CPU
In itiator Is CPU .
1 = on PCI master error, master was CPU.
0 = on PCI master error, master was not CPU (re set
value).
Five types of PCI master errors are reported by this
bit. For PCI targ et errors (Discard Ti mer Expired) this
bit i s alway s 0. The ty pe of master or targ et error is
report ed in the ERRTYPE field of the PCI Control
Regist er (PCI CTRL), Section 7.11.1.
Bit 1
reserved
Hardwir ed to 0.
Bit 63:2 ADDR
PCI Error Address.
The PCI ad dres s where a n er ror occ urred. Resets to
0.
7.12
PCI Confi
g
uration
S
p
ace C
y
cles
The controller support s a PCI Configuration Space, as defin ed in the
PCI Local Bus
Specification
. Only the Main CPU in a PCI system should run PCI Configurat io n Space
cycl es. When it do es so, the PCI Centr al Resou rce (Se ction 7.8) is respon sible for gen-
erating the IDSEL inputs (Section 7. 12.3) to PCI devices. These IDSEL inputs are the
chip-select s during PCI Configuration Space acces ses by the Main CPU. The PCI
Central Resource itself does not have a PCI Configuration Space.
The regi sters that ma ke up the PCI Configuration Space ar e described i n Section 7.13.
Sett ing the PCIWRST bit in the CPU St atus Register (CPUSTA T), Section 5.5.1, allows
the CPU to pro gram the PCI Configur ation Space register s before making the control -
ler visibl e as a PCI tar get.
The concepts of PCI Configuration Space Cycles and Main Controller (Section 5.3.2)
are unrelated. The controll er can be a Main Controller for a given CPU, but that CPU
might not be th e Main CPU in the s ystem, an d the Ma in Control ler f or that CPU, or any
other CPU in t he syste m, might not provi de the PCI Central Resource for the sy stem.
Only the Main CPU in a PCI system should run PCI Configuration Space Cycles.
7.12.1
As PCI-Bus Master
and Target
As a PCI-Bus master, the controller acces ses the PCI Configur ati on Space when the
TYPE field in the PCI Master (Initiator) Registers (PCIINITn, Secti on 7.11.3) contains
the value b101. W hen this is done, reads a nd writes on the PCI Bus are Configuration
Reads and Co nfi guration Writes. As a PCI master, the contro ller can generate any
arbitrary PCI Configuration Address, whether Type 0 or Type 1.
As a PCI target, the controller responds only to PCI Configuration transactions ( a)
when it s IDSEL i nput is ass erted a nd (b) t hat ar e Type 0 (devi ce o n this bus) and F unc-
tio n Numbe r 0. All PCI Configurati on wri tes to the controller are delayed writes. The
address and data for a configuration write is placed in the INFIFO, and the PCI trans-
action is terminated with Retry. When the delayed write has been performed into the
Configurati on Regis ter, the transactio n is allowed to complete. This mechanism is nor-
mally used to configur e the cont roll er when it is in PCI Stand- Alone Mode (i .e., wh en it
is not the Central Resource), but it can also be used when the co ntr oller i s the Central
Resource; i.e. the controller can talk to itself in PCI Configuration Space.
7.12.2
Configuration
Mechanisms
The controller does not use the PCI Configuration Mechanism #1 or #2, described in
Secti on 3.7.4.1 and 3.7.4.2 of the
PCI Local Bus Speci ficati on
. Because the VR5000
CPU has more than 32 physical address bits , the entire Configuration Space can be
memor y-mapped into the normal CPU address space. Every 32- bit Configuratio n
Address can b e access ed directl y by prop erly setting th e PCIADD fi eld in the PCIINI Tn
register (Sec tion 7.11.3). When this is done, the PCIADD field spec if ies the upper
addres s bits and t he CPU generates th e lower addr ess bits . Addresses are generat ed
the same way for memory, I/O, and Configuration Space.
During Configurati on Space acc esses, the low two bits of the PCI address specify the
type of access. The type is con tr olled by the CONFIGTYPE field of the PCIINITn reg-
ist er. For Type 0 (device on this bus) the low two address bits are b00. For Type 1
(devi ce across a bri dge) the l ow two bits are b01. Th e Type 0 and Type 1 ac cess es are
il lustrated in Figure 3-19 of t he
PCI Local Bus Speci ficati on
.
Only 32 -bit Configur at ion Space a cces ses are al lowed by the
PCI Local Bus Spec ifica-
tion;
64-bit accesses should not be attem pted. The ACCESS_32 bit should be set in
the PCII NITn regi ster. Combini ng (Secti on 7.4. 3.1) and Mer gin g (Secti on 7.4.3 .2) may
be used.
7.12.3
Generating IDSEL
Inputs
The IDSEL ( Initiali zation Device Select) input to a PCI device is us ed as the chip- select
durin
g
PCI Confi
g
uration Space accesses. These IDSEL inputs should be
g
enerated
b
y
the PCI Central Resource. This can be done b
y
resistive couplin
g
to the
PCI_AD[3 1:16] si
g
nals. The controller is desi
g
ned so that th e
Implementation Note:
System Generation of IDSEL
, in Sect ion 3.7.4 of the
PCI Local Bus Specification
can
be followed.
The controll er pr e-dr ives addresses durin
g
Confi
g
urati on Space c
y
cles in order to pro-
vide additional time f or the resistivel
y
coupled IDSEL si
g
nals to become valid before
the controll er asserts FRAME#. The address is driven 8 clocks before FRAME# is
asserted.
7.13
PCI Confi
g
uration
S
p
ace Re
g
isters
Table 26 summarizes the re
g
ist ers that make up the PCI Confi
g
urati on Space. These
re
g
ist ers ar e visible to the PCI Central Resource when the contr oller’s IDSEL input is
asser ted. The Confi
g
uration Space re
g
ist ers are al so visi ble in the control le r’ s inter nal
re
g
ist er address space (Table 8). The internal add ress is determined b
y
addin
g
an off-
set of 0x200 to the base addr ess of the Control ler Internal Re
g
ister s and Devices
(INTCS) PDAR, and then addin
g
the offset of the Confi
g
uration Space re
g
ister shown
in Table 26. This provides two paths for accessin
g
the same re
g
ister.
Some re
g
ister bits are writ able o nl
y
when acces sed via the i nter nal re
g
ist er spa ce, and
the
y
appear read-onl
y
to PCI-Confi
g
uration-Space accesses. This allows flexibilit
y
in
pro
g
rammin
g
the controller and
y
et retains compatibilit
y
with the PCI speci ficati on.
.
Table 26: PCI Configuration Space Register Summary
Name Symbol Offset R/W Reset Value Description
PC I Vendor ID VID 0x 01:0x00 R 0x1033 Vendor ID for NE C, assigne d by P CI
Special Interest Group.
PC I Device ID DID 0x03:0x02 R 0x005A Device ID fo r the c ont r oller, ass igned by
NEC.
PC I Command PCICM D 0 x 05:0x0 4 R/W 0x0000 or
0x 0006 aCoars e c ontrol of PCI interf ac e.
PCI Status PCISTS 0x07:0x06 R/W 0x02A0 Status of PCI events.
PC I Revision ID REV ID 0 x 08 R 0x 01, 0x02, or 0x 03 Devic e r ev is ion.
PC I Class Code CLAS S 0 x 0B - 0x 09 R 0x06 0000 Dev ice type.
PCI Cache Line Size CLSIZ 0x0C R /W 0x00 Syste m cache-line size, in 32-bit w ords.
PCI La tency Timer ML TIM 0x0D R/W 0x 00 Minimum guaranteed clocks for PCI Bus
master.
PC I Heade r Type HTYPE 0x 0E R 0x00 Configur ation r egister layout.
BIST
u nim plemented
0x0F R 0x00
Hardwired to 0.
PCI Base Address
Register Control BARC 0x17:0x10 R/W 0x0000 0000 0000 0004 PCI base address of the controller’s
internal control regi s ters and devices .
This register corresponds to the INTCS
Physical Device Addre ss Register
(Section 5.4).
PCI Base Address
Register 0 BAR0 0x1F-0x18 R/W 0x0000 0000 0000 0000 PCI base address of RAM bank 0. This
register corresponds to the SDRAM0
Physical Device Addre ss Register
(Section 5.4).
PCI Base Address
Register 1 BAR1 0x27:0x20 R/W 0x0000 0000 0000 0000 PCI base address of RAM bank 1. This
register corresponds to the SDRAM1
Physical Device Addre ss Register
(Section 5.4).
PCI Cardbus CIS
Pointer
unimplemented
0x2B-0x28 R 0x0000 0000
Hardwired to 0.
PCI Sub-System
Vendor ID SSVID 0x2D-0x2C R(W) b
de pends on var ious
conditions
Read- only v alue set from Ser ial Mode
EEPROM.
PCI Sub-System ID SSID 0x2F-0x2E R(W) b
de pends on var ious
conditions
Read- only v alue set from Ser ial Mode
EEPROM.
Expansion ROM
Base Address
unimplemented
0x33:0x30 R 0x0000 0000
Hardwired to 0.
reserved
— 0x3B-0x34 R 0x00
Hardwired to 0.
PC I I nterrupt Line I NTLIN 0x3C R/W 0xFF Interrupt - s ignal r outing inf or m ation.
PC I I nterrupt Pin INTPIN 0x3D R 0x01 The c ontrol ler dr ives INTA#
PCI Min_Gnt
unimplemented
0x3E R 0x00
Hardwired to 0.
PCI Max_Lat
unimplemented
0x3F R 0x00
Hardwired to 0.
PCI Base Address
Register 2 BAR2 0x 47:0x40 R/W 0x 0000 0000 0000 0000 PCI bas e address of de v ic e s elect ed by
DCS# [2]. Th is r egister corr es ponds to
the DCS2 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register 3 BAR3 0x 4F-0x48 R /W 0x0000 0000 0000 0000 PCI base addr es s of de v ic e s elect ed by
DCS# [3]. Th is r egister corr es ponds to
the DCS3 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register 4 BAR4 0x 57:0x50 R/W 0x 0000 0000 0000 0000 PCI bas e address of de v ic e s elect ed by
DCS# [4]. Th is r egister corr es ponds to
the DCS4 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register 5 BAR5 0x 5F-0x58 R /W 0x0000 0000 0000 0000 PCI base addr es s of de v ic e s elect ed by
DCS# [5]. Th is r egister corr es ponds to
the DCS5 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register 6 BAR6 0x 67:0x60 R/W 0x 0000 0000 0000 0000 PCI bas e address of de v ic e s elect ed by
DCS# [6]. Th is r egister corr es ponds to
the DCS6 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register 7 BAR7 0x 6F-0x68 R /W 0x0000 0000 0000 0000 PCI base addr es s of de v ic e s elect ed by
DCS# [7]. Th is r egister corr es ponds to
the DCS7 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register 8 BAR8 0x 77:0x70 R/W 0x 0000 0000 0000 0000 PCI bas e address of de v ic e s elect ed by
DCS# [8]. Th is r egister corr es ponds to
the DCS8 Physical Device Address
Regis ter (S ec tion 5 .4).
PCI Base Address
Register BOOT BAR B 0x7F- 0x78 R /W 0x 0000 0000 0000 0004 PCI base address of the Boot ROM. Th is
register corresponds to the BOOTCS
Physical Device Addre ss Register
(Section 5.4).
reserved
— 0xFF-0x80 R 0x00
Hardwired to 0.
a. PCICMD resets to 0x0000 when PCICR# is negated, or to 0x0006 when PCICR# is asserted.
b. Read-only from PC I Configuration S pace, read-write from the controller’s internal r egister space.
Table 26: PCI Configuration Space Register Summary (continued)
Name Symbol Offset R/W Reset Value Description
7.13.1
PCI Vendor ID
Register (VID)
Bit 15:0 VID Hardwired to 0x1033 for NEC PCI devi ces. Assi
g
ned
b
y
PCI Special Interest Group (SIG).
7.13.2
PCI Devi ce ID Regi st er
(DID)
Bit 15:0 DID Hardwired to 0x005A for the controller. Assi
g
ned b
y
NEC.
7.13.3
PCI Command
Register (PCICMD)
Bit 0 IOEN
PCI
I/O Space Target Enable.
1 = (not valid)
0 = disable. (hardwired to 0)
As a PCI-Bus tar
g
et, th e contr oller res ponds onl
y
to
PCI memor
y
and confi
g
uration space accesse s, not
to PCI I/O spac e accesses (althou
g
h it can perform
accesses to PCI I/O space as a PCI-Bus ma ster).
Bit 1 MEMEN
PCI Memory Space Target Enable.
1 = enable. (reset value when PCICR# asserted)
0 = disable . (r eset value wh en PCICR# ne
g
ated)
Enables the control ler to respo nd to PCI memor
y
space accesses as a PCI-Bus tar
g
et.
Bit 2 BMASEN
PCI-Bus Master Enable.
1 = enable. (reset value when PCICR# asserted)
0 = disable . (r eset value wh en PCICR# ne
g
ated)
Enables the controller to act as a master on the PCI
Bus.
Bit 3 SPCEN
PCI Special Cycle Enable.
1 = (not valid)
0 = disable. (hardwired to 0)
The controller i
g
nores Special C
y
cles.
Bit 4 MWIEN
Memory Write and Invalidate Enable.
1 = (not valid)
0 = disable. (hardwired to 0)
In normal operation, the control le r does not
g
enerat e
Memor
y
Write and Invalid ate accesses. However , f or
testin
g
purposes the TYPE field in the PCI Master
(Ini tiator ) Re
g
ister (PCII NITn, Se ction 7.11.3) can be
pro
g
rammed so as t o
g
enerate an
y
PCI command
listed in Table 21.
Bit 5 VGA
VGA Palette Snoop.
1 = (not valid)
0 = disable. (hardwired to 0)
The controller is not a VGA device.
Bit 6 PEREN
Parity Err or (PERR# ) Enabl e.
1 = respond to even-pari t
y
data err or.
0 = ignore such parity errors (reset value).
See PCI- Maste r Pari ty Det ectio n (Sect io n 7.4. 5) and
PCI-Target Parity Detection (Section 7.5.4) for
details on parity-error handling.
Bit 7 WCYC
Wait -C ycle C o n trol.
1 = (not valid)
0 = no address or data stepping. (hardwired to 0)
The controller does not do address or data stepping
(although it does pre-drive addresses during PCI
Configurati on Space Cycles so that IDSEL wi ll be
valid when the controller asserts FRAME#, as
described in Section 7. 12).
Bit 8 SERREN
System Err or (SERR#) Enable.
1 = assert SERR# sig nal on system error.
0 = disable SERR# assertion (reset value).
See Section 7.4.5, Section 7.5.4 and Section 7.11.1
(bit s 46:40) for det ails on parity-error handling.
Bit 9 FBBEN
Fast Back-to-Back Enable.
1 = enable fast back-to-back transactions.
0 = enable such transactions (reset value).
This bi t s pecifies wh ethe r the contr oll er , as master , is
allowed to perform fast back-to-back PCI-Bus trans-
actions.
Bit 15:10
reserved
Hardwir ed to 0.
7.13.4
PCI Status Register
(PCISTS)
These status bit s are set to 1 when the indi cated event occurs. W riting a 1 to a bit
causes it to be cleared to 0.
Bit 4:0
reserved
Hardwir ed to 0.
Bit 5 66M
66 MHz Capabl e.
1 = enabled. (hardwired to 1)
0 = (not valid)
Bit 6 UDF
User-Definable Features Supported.
1 = (not valid)
0 = disable. (hardwired to 0)
The controller does not support User Definable Fea-
tures.
Bit 7 FBBC
Fast Back-to-Back Capable.
1 = capable of f ast back-to- back. (hardwired to 1)
0 = (not valid)
This bi t spec if ies whether the controll er, as target, is
capable of accepti ng fast back-to-back PCI- Bus
transactions.
Bit 8 DPR
Data-Parity E rror Reported.
1 = master or target asserted PERR#.
0 = parity error cleared (reset value).
The controller sets this bit if the controller initiated a
PCI transaction and asserted PERR# on a read or
detected asserted PERR# by the target on a write.
This bi t can only be set if the PEREN bit is set in the
PCI Command Register (Secti on 7.13.3).
Bit 10:9 DEVSEL
DEVSEL# Timing .
Hardwir ed to 01, to specify that the contr oller uses
medium response time (2 clocks after the address
phase) when driving the DEVSEL# output signal as a
PCI target.
Bit 11 STA
Signaled Target -Abort.
1 = (not valid)
0 = no Target -Abort generated. (hardwir ed to 0)
The controller never generates Target Abort.
Bit 12 RTA
Received Target-Abort.
1 = control ler, as mas ter, recei ved a Target-Abort.
0 = Target-Abort cleared (reset value).
Bit 13 RMA
Received Master-Abort.
1 = controller, as master, received a Master-Abort.
0 = Master-Abort clea red (reset val ue).
Bit 14 SSE
Signal ed System Error.
1 = controller asserted SERR#.
0 = system error cleared (reset value).
The controller sets this bit if the controller asserted
SERR# (i.e. detected an address even -parity error or
other system error). This bit can only be set if the
SERREN bit is set in the PCI Command Regist er
(Secti on 7.13.3).
Bit 15 DPE
Detected Parity Error.
1 = control ler detect ed an even-parit y error.
0 = parity error cleared (reset value).
This bi t is set on any even-parity error (address or
data, read or wri te) even if the PEREN bi t i s cl eared
in the PCI Command Regi ster (Secti on 7.13.3).
7.13.5
PCI Revision ID
Register (REVID)
Bit 7:0 REVID
Revi sion ID.
Hardwir ed to i ndicate the version of t he controll er.
Tapeout Revision ID
July 1997 0x01 (pre-production)
March 1998 0x02
7.13.6
PCI Class Code
Register (CLASS)
Bit 7:0 PROGINT
Programming Interface Code.
Hardwir ed to 0x00.
Bit 15:8 SUBCL
Sub-Class Code.
Hardwir ed to 0x00 i ndicatin
g
a Host Brid
g
e.
Bit 23:16 BASECL
Base Class Code
.
Hardwir ed to 0x06 i ndicatin
g
a Brid
g
e Device.
7.13.7
PCI Cache-Line Size
Register (CLSIZ)
Bits 7:0 CLSIZ
Cache-Line Size.
The PCI ca che-li ne si ze, in unit s of 32 -bit words. T he
controller uses this value to determine how much
data to pr efetch duri n
g
PCI tar
g
et reads, and for
command coercion on pre fetchable PCI master
reads. Val id values are 0, 1, 2, 4, 8, 16, 32, 64, 128
wo rd s . Writin
g
an
y
thin
g
else for ces the value to 0.
Resets to 0.
7.13.8
PCI Latency Timer
Register (MLTI M)
Bi t 7 :0 MLTIM
Latency Timer.
This re
g
ister specifies, in PCI clocks, the mini mum
number of PCI c locks t hat th e contro ller can h old the
bus as a master after its GNT#[n] is ne
g
ated. Resets
to 0.
7.13.9
PCI Header Type
Register (HTYPE)
Bit 6:0 HTYPE
Header Type.
Hardwir ed to 0x00, indicatin
g
header t
y
pe 0.
Bit 7 SINGLEFN
Single Function.
Hardwired to 0. The controller is a sin
g
le-function
PCI devic e.
7.13.10
PCI Base Address
Register s (BARn)
The controlle r has 11 Base Address Re
g
ist ers ( BARs), correspondin
g
to 11of the
PDARs (Section 5.4 on pa
g
e 45). The BARs are used to cont rol PCI-Bus master
access to control ler r esources. The two PCI Address Window PDARs do not have cor-
respondin
g
BARs, as explained in Section 7. 5.1. Thus, the BARs in clude:
BARs must be pr o
g
ramme d with non- overl appin
g
PCI addre sses. I f the Vi sibl e on PCI
Bus (VISPCI ) bit is clea red in the corres pondin
g
PDAR, all BAR bits for the dev ice are
forc ed to 0, the bits can not be writ ten, and no acces s t o the corr espondin
g
resource is
allowed from the PCI Bus.
BAR PDAR(s)
Base Address Reg ister 0 (BAR0) SDRAM0
Base Address Reg ister 1 (BAR1) SDRAM1
Base Address Reg ister8:2 (BAR8:2) DCS[8:2]
Base Address Reg ister Boot (BARB) BOOTCS
Base Address Reg ister Control (BARC) INTCS
Bit 0 SPACE
Memory Space Indicator.
1 = PCI I /O space. (not valid)
0 = PCI memory space. (hardwired to 0)
As a PCI-Bus target, the contr oller res ponds only to
PCI memory and configuration space accesses, not
to PCI I/O space accesses (although it can perform
accesses to PCI I/O space as a PCI-Bus master).
Bit 2:1 TYPE
Type.
Hardwir ed to b10, indic ati ng that the controller’s
address space can be located anywhere in a 64-bit
address space.
Bit 3 PREFETCHABLE
Prefetchable.
1 = enable prefetching on reads to this region.
0 = disable prefetching in this region (reset value).
When set, this bit indic ates that the devi ce ret urns all
bytes on r eads, regardl ess of byt e-en ables, and that
writ es can be me rged without cau sing errors. Read-
only vi a PCI Confi gurat ion Space (offset shown i n
Table 26. Read-writ e when accessed as an i nternal
register (offset shown in Table 26, pl us 0x200).
Bit 63:4 BASEADDR
Base Address.
The PCI star ting address for this device. Bits 31:21
are for ced to 0, if masked by the MASK field in the
corresponding PDAR (Section 5.4). Bits 20:4 are
hardwired to 0. Resets to 0.
7.13.11
PCI Sub-System
Vendor ID (SSVID)
Bit 15:0 SSVID
Sub-System Vendor ID.
This ID i s iss ued to sub-system or add-in board ven-
dors by the PCI Special Int erest Group. It is i nten ded
to uniquely ident ify the board or sub-system where
the PCI devi ce resides. Reset value pro vided by
Serial Mo de EEPROM. Read-onl y via PCI Configu-
rati on Space (offset shown in Table 26). Read-wri te
when accessed as an inte rnal regist er (of fset shown
in Table 26, plus 0x200).
7.13.12
PCI Sub-System ID
(SSID)
Bit 15:0 SSID
Sub-System ID.
This ID is vendor-specific, and can be used to iden-
tify board revisions. Reset value provided by Serial
Mode EEPROM. Read-only via PCI Configuration
Space (offset shown in Table 26. Read-write when
accessed as an internal register (offset shown in
Table 26, plus 0x200).
7.13.13
PCI Interrupt Line
Register (INTLIN)
Bit 7:0 INTLIN
PCI Interrupt Line.
Holds the PCI interrupt-si
g
nal r outin
g
code for use b
y
s
y
stem sof tware. See Sec ti on 2.2 .6 of the
PCI Local
Bus Specification
for an example. The contr oller
i
g
nores the contents of thi s re
g
ister. Resets to 0xFF.
7.13.14
PCI Interrupt Pin
Register (INTPIN)
Bit 7:0 INTPIN
PCI Interrupt Pin.
Hardwir ed to 0x01, i ndicat in
g
that the c ontroller use s
INTA# to reque st a PCI interrupt.
8.0 Local-Bus Interfac e and Registers
The LO C_AD[31:0] and PCI_AD[ 63:32] signal s, and a few ot her rel ated s ignals , share
the same pi ns on t he controller package, so that when the controller’s PCI inter face is
configured for 32-bit operation, a 32-bit Local Bus is available for I/O and memory
devices (su ch as boot memory).
The Local-Bus interface consists of:
LOC_CLK: a Local-Bus clock, which SysClo ck divided by 4 or 2.
LOC_AD[31:0]: a 32-bi t mult iplexed address and data bus.
LOC_A[4:0]: a 5-bit de-multipl exed low-address and byte-enable bus.
LOC_ALE: Address latch enable.
LOC_FR#: Frame indication.
LOC_RD#, LOC_WR#: Read and writ e signals (or a single RD/W R# signal).
LOC_RDY#: Ready (acknowledge) .
LOC_BR#, LOC_BG#, LOC_BGACK#: Bus arbitration (68000 or Intel mode).
Two additio nal signals control devic es that can be located either on the Local Bus or
the memo ry bus:
BootCS#: Boot ROM chip-select.
DCS#[8:2] : 7 programmable chip-selects.
The controller can be a Local-Bus master (on behalf of the CPU, DMA, or PCI-Bus
masters) or a Local-Bus target for accesses by masters on the Local- Bus. A Local-Bus
master obtains control of the Local Bus through arbitration (68000 or Intel mode).
When th e controll er grants contr ol, it tri -states all of i ts Local-Bus out puts exce pt
LOC_CLK and LOC-BG#, so that the Local-Bus master can access other Local-Bus
devices directly, or access controller resources (memory, PCI-Bus targets, or the con-
troller’s internal registers). When a Local-Bus master accesses controller resources,
the controll er’ s DMA logic carri es out the Local-Bus m aster’s request. Local -Bus mas-
ters cannot access Local-Bus targets through the controller; instead, they must do so
directly on the Local Bus, without the help of the controller.
The contr olle r support s burst t ransfer s on the Local Bus. See Secti on 8.3.2.2 and Sec-
ti on 8. 4 . 1 for de ta il s .
8.1
Loc al-Bus
Confi
g
uration and
Monitorin
g
Soft ware config ures and moni tors the Loca l-B us int erfac e using t he fol lowing regis ters:
Physical Device Address Registers (PDARs), Section 5.4 on page 45.
Interrupt Control Register (INTCTRL), Section 5.5.2 on page 52.
Inter rupt Status Regi ster 0 (INTSTAT0), Section 5.5.3 on page 55.
Interrupt Status 1/CPU Interrupt Enable Register (INTSTAT1), Section 5.5.4 on
page 55.
Inter rupt Clear Register (INTCLR), Sect ion 5.5.5 on page 56.
Local-Bus Registers, Sect ion 8.6 on page 120.
Figur e 16 shows an exampl e of a Local-Bus con fi guration t hat i mpleme nts SRAM a nd
an external UART ( in additi on to the controller’s internal UART) . The SRAMs re spond
to byte-enable signals, allowing single- byte granularity on writes. The connections to
the external 16550 UAR T shows how the LO C_ A[4: 0] signals can b e used directly for
devices with sm all address spaces.
8.2
Device Chip-Select
Configuration
The seven pro grammable DCS[8:2] chip-selec ts can be used t o access devices on the
Local Bus or the Memor y Bus, as s pecified in the M E M/LOC bi t in the Physi cal Device
Address Registers (PDAR, Section 5.4) for each chi p-select. The chip- selects have a
flexible address ma p, which al lows from 2M B to 4GB per chi p-select. The Local Bus’ s
control signals can be configured to customize the shape of a Local-Bus cycle in the
Local -Bus Chip-Sel ect Ti ming Regist er (LCSTn, Sect io n 8.6.2). F or ex ample, the f ields
of the LCSTn re gister speci fy polari ty of the chip- select and read/write (LOC _RD# or
LOC_WR#) signals, the time from ad dres s-val id to chip-sel ect asser ted, th e time from
chip-select asserted to read/write assert ed, the duration of read/wri te, read/wr ite
negated to chip-select negated, chip-select negated to address invali d, and bus idle
time after chi p-select negated.
Ready (LOC _RDY#) support is available, per chi p-select, for Local-Bus devi ces that
do not respond in a fixed amou nt of time (as speci fied in the LCSTn register).
LOC_RDY# may be sampl ed dire ctly of f th e Local Bus or after unde rgoing do ubl e s yn-
chronization by the contr oller. In LOC_RDY# mode, all bus si gnals are extended until
LOC_RDY# is received fro m the target. The negat ion of the read/write comma nd can
be specified as relati ve to the asser tion of LOC_RDY#, and the rem aining bus signals
can be speci fied as relati ve to the nega tion of read/ write , as descri bed abov e. A 12-bit
programmable timer (up to 4K Local- Bus clocks) is available as a LOC_RDY# watch-
dog ti mer . This timer should be prog rammed to a val ue higher than the sl owest devi ce
on the Local Bus. The timer begins counting down when a LOC_RDY#-response bus
cycle begins. If a LOC_RDY# is not received before the timer reaches zero, the cycle
terminates as though a LOC_RDY# were received, and an inte rrupt is gener ated, if
enabled by the LBR TDEN bit of the Interrupt Control Regist er (I NTCTRL, Section
5.5.2).
Figure 15: Example Local-Bus Configuration
LOC_RD#
LOC_A[4:0]
LOC_ALE
LOC_AD[31:0]
D[7:0]
A[2:0]
CS0
CS1
CS2
ADS
DCS#[4]
DCS#[3]
OE
WE
CS D[7:0]
A[14:0]
OE
WE
CS D[7:0]
A[14:0]
OE
WE
CS D[7:0]
A[14:0]
OE
WE
CS D[7:0]
A[14:0]
Latch
LE
DQ
Latch
LE
DQ
LOC_WR#
LOC_ADDR[31:0]
LOC_AD[31:24]
LOC_AD[23:16]
LOC_AD[15:8]
LOC_AD[7:0]
LOC_BE[3:0]
LOC_BE[3]
LOC_BE[2]
LOC_BE[1]
LOC_BE[0]
RD
WR
RD
WR
LOC_AD[7:0]
LOC_A[2:0]
LOC_FR#
16550
UART
32K x 8
SRAM
32K x 8
SRAM
32K x 8
SRAM
32K x 8
SRAM
VRC5074
System Controller
8.3
Local-Bus Master
Transactions
(Cont roll er - to-Local
Bus)
The controller becomes the master of the Local Bus and initi ates a Local Bus c
y
cle b
y
assertin
g
LOC_FR#. When LOC_FR# is asserted, no othe r device ma
y
drive Local
Bus si
g
nals, with the exce pti ons of providin
g
response data to re ad requests and arbi-
tratin
g
for control of the bus b
y
asserti n
g
LOC_BR#.
8.3.1
Timing Durin
g
the first clock of a Local-Bus c
y
cle, the LOC_AD[ 31:0] bus con tains the add ress
of t he request . LOC_ALE is ass erted f or the firs t half of th is cl ock c
y
cle t o enable e xte r-
nal l atchin
g
of the Local-Bus address. The Local Bus supports b
y
te-addressin
g
in the
local address space. Therefore, if a 16-bit device is used on t he Local Bus, LOC_AD[1]
would be the least-si
g
nifi cant address bit wired to that device. Si m il arl
y
, if a 32-bit
device is used, LOC_AD[2] would be the least-si
g
nificant address bit wired to that
device.
Also du rin
g
the first cloc k of a Local-Bus c
y
cle, the L OC_A[3:0] si
g
nals car r
y
acti ve-low
b
y
te-enables—in effect, BE#[3:0] for the Local Bus— while LOC_AD[31:0] carries the
address. The LOC_ALE si
g
nal ma
y
also be used to externall
y
latch both the address
and the b
y
te-enables. For example, when a 16-bit res ource is accessed, LOC_A[1:0]
are the b
y
te-enables durin
g
the first Local-Bus clock. When a 32-bi t resource i s
accessed, LOC_A[ 3:0] are the b
y
te-enables.
Durin
g
the remainder of a non-block bus c
y
cle, i .e. from the second Local -Bus clock
throu
g
h the end of the bus c
y
cle, LOC_A[4:0] car ri es the five low- address bits (the
same bit s that were carried on LOC_AD[4 :0] bit s when LO C_ALE was acti ve) while
LOC_AD[31:0] carri es the data. If all address spaces for Local -Bus devices are less
than or equal t o 32 b
y
tes, the LO C_A[4:0] bi ts ma
y
be used in place of ext ernall
y
latch-
in
g
the address from the LOC_AD[4:0] bus.
Durin
g
the remai nder of the b us c
y
cle , the appr opria te DCS[8:2 ] ch ip-select and e ither
the LOC_RD# or LOC_WR# si
g
nal are as serted , accord in
g
to the pol arit
y
speci fied b
y
the CON_POL bit of the device’s Local -Bus Chip-Select Ti min
g
Re
g
ister (LCSTn, Sec-
tio n 8.6.2) . When LOC_RD# or LOC_WR# is ne
g
ated, which is ei ther a sp ecifi ed dura-
tion or after the detection of the LOC_RDY# si
g
nal (as spec ified in the CONWID and
SUBSCWID fields of the LCSTn re
g
ister), the c
y
cle ends with the ne
g
ation of
LOC_FR#. A new c
y
cle ma
y
be
g
in, a s in dicate d b
y
the assertion of LOC_FR#, after
the bus-idle t ime specifi ed b
y
the BUSIDLE field of the LCSTn re
g
ister.
Fi
g
ure 16 shows an exam ple r ead a ccess on the Loca l Bus. The CSON, CSOFF, COF-
HOLD, CONSET, CONWID, and BUSIDLE values are sof tware-confi
g
urati on fi elds in
the Local Bus Chip-Sel ect T imin
g
Re
g
ist ers (LCSTn), Sect ion 8.6.2.
If
y
ou have onl
y
32-bi t devi ces on an extern al boa rd, none of which u se burst transfers,
y
ou can connect the LOC_AD[31:0] bus to the external board without connectin
g
the
LOC_A[4:0] bus.
Figure 16: Local-Bus Read
8.3.2
Dword vs. Block
Requests
Requests to resources with dat a siz es lar
g
er than t he width of the device cause multi-
ple bus c
y
cles on the Lo cal Bus . For exa mple, a wor d r equest to a 16-b it d evice resu lts
in two Lo cal-Bus c
y
cles. However , multiple Local- Bus c
y
cles r esult in
g
from a dword (or
less) request look dif ferent than multiple Local-Bus c
y
cl es re sul tin
g
from a Block
request.
8.3.2.1
Dword Requests Multiple Local-Bus c
y
cles resultin
g
from a dw ord (or less) req uest loo k like su ccess ive
separate requests on the Local Bus. Each bus c
y
cle has its own address, data (for
writes) and control si
g
nals asserted. These requests differ from random requests in
that the
y
cannot be i nterrupted b
y
reques ts from other internal cont roller maste rs (CPU
or DMA) or from external Local-Bus masters.
The number of local c
y
cles resulti n
g
from a dword req uest varies, dependin
g
on the
size of the resource and the size of the request . The controller’s Loca l-Bus interface
perf orms onl
y
as man
y
bus reques ts as necessar
y
to complete the request. For exam-
ple, a tri-b
y
te write b
y
the CPU to a b
y
te-wi de Local-B us device results in onl
y
three
Local-Bus write c
y
cles. The onl
y
additional dela
y
for these t
y
pes o f accesses is one
S
y
sClock per b
y
te, half-word, or word of data (dependin
g
on the size of the resource
bein
g
addressed) for which no b
y
te-enables are asserted. In the case of the tr i- b
y
te
exam ple, there would be five S
y
sClock dela
y
s around and/or between Local-Bus
c
y
cles in which the control ler inspects the b
y
te-enables fro m the requester to det er-
mine if a bus c
y
cle must be performed.
8.3.2.2
Block Requests Block requests (32-b
y
te cache line requests) to Local-Bus devices al wa
y
s result in
multi ple re quests on t he Loca l Bus. A bl ock request to a b
y
te-wide device results in 3 2
reads or writes. Block requests to half-word devices result in 16 reads or wri tes, and
block requests to word devices result in 8 reads or writes.
These are not separate Local-Bus cycl es, as described above for the case of m ult iple
cycles resulting from a dword request. Rather, these look like one, long Local-Bus
cycl e wit h mu lt iple assertions of LOC_RD# or LOC_W R#. Ther e is one LOC_FR#, one
LOC_ALE du ring the first half of the bus clock, and t he address and byte-enables are
only on the L OC_AD[31:0] and LOC_A[ 4:0] buses d uring the first bus clock, as s hown
in Figure 17. The low-order address bits are driven on LOC_A[4:0] to indicate which
part of the block is being transferred. The byte-enables must all be asserted, since a
full port-size unit of data i s to be read or wr itten on each assertio n of LOC_RD# or
LOC_WR#.
The LO C_A[4:0] bi ts must be connecte d to devices responding to block requests; dur-
ing block requests, these are the only address bits that increment after each unit of
data is read or written. As described above, these bits contain byt e addresses . There-
fore, LOC_A[0] i s the l east-signifi cant addre ss bit wired to a byte device, LOC_A[ 1] is
the le ast-si gnif icant add ress bit wired to a half- word devic e, and LOC_A[2] is the leas t-
signi ficant bit wired to a word devi ce.
Figure 17 shows an exampl e block write to a byte- wide device on the Local Bus. The
CSON, CSOFF, COFHOLD, CONSET, CONWID, BUSIDLE, and SUBSCWID values
are software-c onfiguration fields in the Local Bus Chip-Select Timing Registers
(LCSTn), Sectio n 8.6.2.
Figure 17: Local- B us Block Write To Byte-Wide Device
When the ARBEN bit is set in the Local Bus Configu rat ion Register (LCNFG, Section
8.6.1), ext ernal Local-Bus devices are allowed to arbitrate for and gain control of the
Local Bus.
8.4
Arbit ration for
Loc al-Bu s Control
The ARBMODE bit in the Local Bus Configuration Register (LCNFG, Sect ion 8.6.1)
specifies one of two bus-arbit ration modes. Based on this sel ection, t he LO C_BR#,
LOC_BG#, and LOC_BGACK# signals are configured to functi on as:
68000 Mode:
• LOC_BR# = bus request (BR#)
• LOC_BG# = bus gra nt (BG#)
• LOC_BGACK# = bus-grant acknowledge (BGACK#)
Intel Mode:
• LOC_BR# = bus hold (HOLD)
• LOC_BG# = bus- hold acknowledge (HLDA)
When a Local-Bus master gains control of t he bus, the controller tri-states al l of its
Local-Bus output s except LOC_CLK and LOC-BG#. If multiple masters are imple-
mented on the Local Bus, ext ernal logi c mus t ar bit rate among those m asters. If multi-
ple masters with different arbit ration modes are implemented, external logic mu st
arbitrate among those masters and present a single arbitration mode to the controller.
8.4.1
Signal Redefini tion f or
Local-Bus Masters
When a Local-Bus master gains control of t he Local Bus, the definitions of the
LOC_A[4:0] signal s change, as fol lows:
LOC_A[4]:
Determines where the Local-Bus master’s request is targeted:
• LOC_A[ 4] = 1 requests a
controller (non-Loc al-Bus)
tar g e t.
• LOC_A[ 4] = 0 requests a
Local-Bus
tar ge t.
LOC_A[3:0]:
•For
cont ro ll e r targets:
The control ler floa ts i ts LOC_A[3:0] si gnals and these
bits become address bits [35:32] inside the controller. These bits are
concatenated with the 30-bi t addr ess latched from the LOC_AD[31:2] bus to
form a 36-bit physi cal address. LOC_AD[1:0] are assumed to be 0; all
access es to cont roll er resou rce s b y Local -Bus master s are assu med to be 32-
bit accesses, because there are no byte-enable signals. This mechanism
all ows externa l Local-Bus masters to access the entir e controll er address
space. LOC_AD[1 :0] specif y the length of the access. If LOC_AD[1:0] = 00, a
singl e 32-bit word i s tr ansfer red. If LOC_AD[1:0] = 01, a block of eight 32-bit
words is transferred as a burs t. On reads, the controll er asserts LOC_RDY#
to indicate when dat a is valid.
•For
Local-Bus
targets:
LOC_A[3:0] carry implemen tat ion-dependent
information.
Thus, the LOC_A[4] bit distingui shes two, separate address spaces, one for non-
Local -Bus co ntrol ler res ources (memor y, PCI-Bus dev ices, or controll er regi ste rs) and
another for Local -Bus targets. Accesses by the Local- Bus ma ster to control ler
resources are implemented by the DMA logic, as described in t he next section.
Accesses by the Local-Bus master to Local-Bus targets are implemented directly
between the two devices, in a separa te address space and wit hout the assistance of
the controll er (except for LOC_CLK, which the controlle r continues to drive).
8.4.2
Local-Bus Target
Transactions (Local
Bus-to-Controller)
When a Local-Bus master requests a contr oller res ource, the controller’s DMA logi c
carr ies out th at request . The DMA logic must be in a recept ive state bef ore the cont rol-
ler grants the Local-Bus master contr ol of the Local Bus. The controller does this,
regardless of whether the request is targeted to an internal cont roller resource or to a
Local-Bus device, because the target of the cycle is not known until the Local-Bus
master’s bus cycle begins. The effect on non-Local-Bus DMA activi ty depends on
whether the Local-Bus maste r i s targeting a controller r esource or a Loca l-Bus d evice:
Control ler-Resour ce Target, LOC_A[4] = 1:
If the Local-Bus master is t argeting a
controller resour ce, non- Local-Bus DMA activ it y to/from that resour ce is del ayed
until the Local-Bus master’ s request has completed. However, DMA activity to /
from other resources can continue in par allel with the Local-Bus master’s bus
request.
Local-Bus Target, LOC_A[4] = 0:
If the Local-Bus master is target ing a Local-Bus
device, DMA act ivity i s fre e to resume immediately because the DMA logic is not
involved with the Local-Bus activity.
The following types of accesses by Local-B us masters are not supported:
Loop-Back Requests via the Controller
. Requests to Local- Bus targets through
the contr oller’s internal log ic (i.e., when LOC_A[4] = 1) are not allowed, becau se
these requests will cause a deadlock. As described above, a Local-Bus master’s
request for controller resources is carried out via the DMA logic. When the DMA
logic requests the Loca l Bus, it is held off unti l the Local Bus is free. But the Loc al
Bus will not be free until t he DMA co mpletes it s request . The r esult is deadlock. If
such an access is attempted, the cont rol ler discards writ e data and t erminates
read requests by retu rni ng all 0s as data.
Loop-Back Requests via a PCI- Bus Device
. The same deadlock scenario
described above would occur for loop-back requests via the PCI Bus. Such
requests must not be att em pted.
Non-Word Accesses:
All requests by Local- B us m asters to cont roller r esources
are assumed t o be 32-bit word width, because there are no byte-enable signals in
this direction. Size information in the request is ignored. The controller always
performs 32-bit operations.
8.5
Local Bus vs. 64-bit
PC I B u s
When PCI 64# is asse rted, the cont roll er i mplements a 64- bit PCI Bus. I n this case, the
controller reconfigures the functions of several Local -Bus signals, as follows:
LOC_AD[31:0]:
becomes PCI_AD[63:32]
LOC_ALE:
becomes REQ64#, request 64-bit transfer on PCI Bus.
LOC_CLK:
becom es ACK64#, acknowledge 64-bit transfer on PCI Bus.
LOC_A[3:0]:
becom e C/BE#[ 7:4] , the byte-en ables for PCI_AD[63:32].
LOC_A[4]:
becomes PAR64, the even-parit y bit for PCI_AD[63: 32] and C/
BE#[7:4].
Table 4 on page 27 lists all of these signal reconfigurations. If any of the seven Local-
Bus DCS#[8 :2] chip- sel ects are t o be used in this conf iguration, they must be acce ssed
on the memory bus by setting the MEM/LOC bit in the Physical Device Address Reg-
ist ers (PDAR, Secti on 5.4). The lo cation of the BOOTCS is automatical ly moved to the
memor y bus when PCI64# is assert ed.
8.6
Local-Bus Registers Local-Bus masters, if ena bled to arbit rate for cont rol of Local Bus by the ARBEN field
of thi s register, may access the co ntrolle r’s resources (mem ory, PCI-Bus dev ices,
DMA, and the controll er’s int ernal regis ters) or oth er Local-Bus devices.
8.6.1
Local Bus
Configuration
Register (LCNFG)
Bit 0 ARBMODE
Local-Bus Arbit ration Mode.
1 = 68000 mode (i.e. BR, BG, BGACK).
0 = Intel mode (i.e. HOLD, HLDA).
For 68000 mode, t he BR# , BG#, and BGACK# si
g
-
nals serve as the 68000 BR, BG, and BGACK si
g
-
nals, respectivel
y
. For Intel mode, the BR# and
BGACK# si
g
nals se rve as the I ntel HOLD and HLDA
si
g
nals, respectivel
y
.
Bit 1 ARBEN
Local-Bus Arbit ration Enable.
1 = enable Local-Bus masters to arbitrate for control
of the Local Bus.
0 = disable Local-Bus masters from controllin
g
th e
Local Bus.
Clearin
g
this bit preven ts access t o controlle r
re sources. Settin
g
the bit allows Local-Bus devices
to arbitrate for control of the Local Bus, usin
g
the
arbit ration mode specified b
y
the ARBMODE bit.
Bits 3:2
reserved
Hardwir ed to 0.
Bits 4 FLCLCLK
Fast C lock.
1 = LOC_CLK runs at S
y
sClock divided b
y
2.
0 = LOC_CLK runs at S
y
sClock divided b
y
4.
This bit res e ts to 0 .
Table 27: Local-Bus Regi sters
Regist er Sy mbol O f f set R/W Reset Value De scription
Local Bus Configuration LCNFG 0x0100 R/W 0x0 0000 0000 Local Bus configuration
reserved
— 0x0108 R 0x0 0000 0000 —
Local Bus Chip-Select Timing 2 aLCST2 0 x0110 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[2] signal.
Local Bus Chip-Select Timing 3 aLCST3 0 x0118 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[3] signal.
Local Bus Chip-Select Timing 4 aLCST4 0 x0120 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[4] signal.
Local Bus Chip-Select Timing 5 aLCST5 0 x0128 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[5] signal.
Local Bus Chip-Select Timing 6 aLCST6 0 x0130 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[6] signal.
Local Bus Chip-Select Timing 7 aLCST7 0 x0138 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[7] signal.
Local Bus Chip-Select Timing 8 aLCST8 0 x0140 R/W 0x0 0000 0000 Local Bus cycle timi ng for DCS#[8] signal.
reserved
— 0x0148 R 0x0 0000 0000 —
Dev ic e Chip-Select Muxing and
Output Ena bles DCS FN 0x0150 R/ W 0x0 0000 0000 Dev ic e CS s ourc e m ux ing and output- enabl es
Device Chip-Selects As I/O Bi ts DCSIO 0x0158 R/ W 0x0 0000 0000 Device chip-select signals as I/O signals.
reserved
— 0x0160 R 0x0 0000 0000 —
reserved
— 0x0168 R 0x0 0000 0000 —
reserved
— 0x0170 R 0x0 0000 0000 —
Local Boot Chip-Select Timing aBCST 0x0178 R/W 0x0 0 03F 8E3F Local-Bus cycl e timing for BootCS# signal.
a. When the controller is configured for 32-bit PCI operation (PCI64# negated), the boot memory and the seven DCS
devices can be individually configured by the MEM/LOC bit in the PDAR (Section 5.4) to appear on the memory bus or
the Local Bus. When the contr oller is configured for 64-bit PCI operation (PCI64# asserted), these devices always
appear on the memory bus.
Bits 15:5
reserved
Hardwir ed to 0.
Bits 19:16 DMAHOG
Minimum Number of Accesses by DMA.
The minimum num ber of consecutive Local-Bus
cycles the DMA may perform before the DMA is
fo rce d to allo w the CPU or a PC I-B us maste r to ta ke
control of the Local Bus. 0x0 means 1 access, 0xF
means 1 6 consecutive accesses . Resets to 0x 0. The
limi t is only enfor ced when another resource
requests the Local Bus. The Local- B us DMAHOG,
PCIHOG and CPUHOG fields are the softwar e inter-
face to t he Programmabl e 3-Way Arb iter, shown in
Figure 1 on page 12.
Bits 23:20 PCIHOG
Minimum Nu mber of Accesses by PCI.
The minimum num ber of consecutive PCI-inte rface
accesses to Local-Bus resources before the PCI
interface is forced to allow another controller
resour ce to ta ke cont rol o f the Local Bus. 0x0 means
1 access, 0xF means 16 consecutive accesses.
Resets to 0x0. The limit is only enforced once
another resource requests the Local Bus.
Bits 27:24 CPUHOG
Minimum Number of Accesses by CPU.
The minimum number of cons ecutive CPU accesse s
to Local-Bus resources before the CPU is forced to
allo w another control ler resource to take cont rol of
the Local Bus. 0x0 means 1 access, 0xF means 16
consecutive accesses. Re sets to 0x0. The lim it is
only enforced once another resource request s the
Local Bus.
Bit 63:28
reserved
Hardwir ed to 0.
8.6.2
Local Bus Chip-Select
Timing Registers
(LCSTn)
The eight identical LCSTn registers conf igure bus-cycle timi ng characteristi cs on the
Local Bus. The seven LCST8:2 registers corre spond to the DCS#[8:2] device chip-
select signals, which themselves are configured in their PDARs (Section 5.4). One
more register, BCST, corresponds to the BootCS# signal, which is also configured by
its PDAR.
Bit 0 CSON
Chip-Select On (Asserted).
1 = assert DCS#[n ] one clock after valid address.
0 = assert DCS#[n ] wit h valid address.
The vali d address referred to is on the
LOC_AD[31:0 ] bus. Assert ing DCS#[ n] with the vali d
address means in the clock that LOC_FR# is
asserted. Be careful when using LOC_A[4:0] with
CSON cleared to 0, because DCS#[n] will assert
while LOC_A[4:0] drives byte-enables, one clock
before LOC_A[31:0] drives the address.
Bits 2:1 CONSET
Command-O n Set.
The number of clocks, after the assertion of
DCS#[n], that the LOC_RD# or LOC_W R# signal is
asserted. When zero, the command (LOC_RD# or
LOC_WR#) is asserted coinc ident with DCS#[n].
Bits 8:3 CONWID
Command-On Width (or Local-Bus Ready Timer).
When the RDYMODE bi t (bit 22) is cle ared, this fiel d
specifies the duration of LOC_RD# or LOC_WR#
signal assertion. The CONWID val ue can range from
1 to 64 LOC_CLKs. The durat ion of assert ion is the
CONWID value, pl us 1. For exam ple, a CONWID
value of 000000b specifies a 1-clock duration of the
read or write command. A CONWID value of
000111b speci fies an 8-clock asse rtion, and so on.
When the RDYMODE bit ( bit 22) is set , i ndicating th e
LOC_RDY# signal is being used, the CONWID field
is concat enated with the SUBSCWID field to form a
12-bit Local-Bus Ready Ti m er for LOC_RDY#, with
CONWID be ing the lower 6 bits. I nterrupt s based on
this timer are enabled by the LBRTDEN bit of the
Interrupt Control Register (INTCTRL, Section 5.5.2).
Bits 14:9 SUBSCW ID
Subsequent Command-On W idt h (or Local-Bus
Ready Timer).
When the RDYMODE bi t (bit 22) is cle ared, this fiel d
specifies the duration of LOC_RD# or LOC_WR#
signal (co mmand) assertion for subsequent portions
of a block- trans fer cycle. The CONWID value can
range fr om 1 to 64 LOC_CLKs. The duration of
assertion is the CONWID value, plus one.
When the RDYMODE bit ( bit 22) is set , i ndicating th e
LOC_RDY# signal is being used, the SUBSCWID
field is concatenat ed with the CONWID field to fo rm
a 12-bi t L ocal-Bus Ready Timer for LOC_RDY#, with
SUBSCWID being t he upper 6 bits. If used, this timer
should be programmed to a value higher than the
slowest device on the Local Bus. The timer beg ins
counting down when a LOC_RDY#-response bus
cycle begins. If a LOC_RDY# is not received before
th e timer reaches zero , the cycle terminate s as
though a LOC_RDY# were received, and an inter-
rupt i s generated, if enabled by the LBR TDEN bit of
the Interrupt Control Register (INTCTRL, Section
5.5.2).
Bits 16:15 CSOFF
Chip-Select Off.
This field specifies the number of LOC_CLKs, aft er
LOC_RD# or LOC_WR# is negated , that DCS#[ n] is
negated. When zero, DCS#[n] is negated coincident
with th e read or write si gnal. When non-zero,
DCS#[n] i s negated that number of clocks after the
read or write signal is negated.
Bits 18:17 COFHOLD
Command- Frame Hold.
This field specifies the number of LOC_CLKs, aft er
DCS#[n] i s negated, that the comm and-frame is
extended (LOC_FR# held asserted). When zero,
LOC_FR# is nega ted c oinci dent wit h the negat ion of
DCS#[n]. When non-zer o, LOC_FR# is nega ted that
number of clocks after the negation of DCS#[n].
Bits 21:19 BUSIDLE
Bus Idle.
This field specifies the minim um numb er of
LOC_CLKs between the negation and re-assertion
of LOC_FR# for a subsequent cycle. There is a two-
clock minimum impose d by the cont ro l logic. The idle
time increases i f the subsequent cycle is less th an a
dword and one or more of the least-si gnificant byte-
enables from the master is negated (thi s delay is
caused by logic that searches through the
requestor’s byte-enables so that only necessary
Local-Bus cyc les are performed).
Bit 22 RDYMODE
Ready Mode.
1 = LOC_RDY# determines access duration.
0 = fixed tim ing for accesses, per bit s 14:3.
If RDYM ODE is set, the CONWID and SUBSCWID
fiel ds (bits 14: 3) become a Local-Bus Ready T imer
for LOC_RDY#. This ti m e-out timer works for both
reads and wri tes on the Local Bus.
Bit 23 RDYSYN
LOC_RDY# Synchronize.
1 = synchroni ze LOC_RDY# to SysClock.
0 = do not synchronize LOC_RDY# to SysClock.
If th is bit is set , the LOC_RDY# si gnal is a ssumed t o
be asynchr onou s to SysCl ock, and t he contr oller will
syn chronize it to SysCl ock. This imposes a 2-cl ock
delay at the end of the access.
Bits 25:24 CONOFF
Command Off .
This field specifies the number of LOC_CLKs, aft er
LOC_RDY# is asserted, that the LOC_RD# or
LOC_WR# sign al (c om ma nd) i s negated. When
zero, the command is negated coincident with the
assertion of LOC_RDY# (or two clocks later if
LOC_RDY# requires synchronizati on). When non-
zero, th e command is negat ed that nu mber of c locks
after LOC_RDY# is asserted.
Bit 26 CS_POL
Chip-Select Polarity.
1 = DCS#[n] is activ e-Hi gh.
0 = DCS#[n] is active-Low.
Bit 27 CON_POL
Command Pola ri ty.
1 = LOC_RD# and LOC_WR# are acti ve-High.
0 = LOC_RD# and LOC_WR# are acti ve-Low.
Bits 63:28
reserved
Hardwir ed to 0.
8.6.3
Device Chip-Select
Function Regi ster
(DCSFN)
This r egist er speci fies t he functi onali ty of t he DCS#[8:2] si gnals. These si gnals ca n be
used as device chip-selects, whose operation is control led by the corresponding PDAR
(Sect ion 5. 4) and Loc al-B us Chip Select T i ming Regist er (LCSTn , Section 8.6.2 ). Al ter-
natively, they can be used for general -purpose I/O bits, addit ional UART modem con-
trol functions , or DMA hardware handshaking.
The DCSFN reg ister an d the DCS[8:2] PDARs must b e pr ogram med befor e accessi ng
devices selected by the DCS#[8: 2] signals.
Bits 2:0 DCSFN2
DCS#[2] Si gnal Function
.
Bit 3
reserved
Hardwir ed to 0.
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L2IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS2, Section 5.4.
b011 General-purpose output whose value is
pr ogr amm ed by bit 8 of the DCSLO UT field in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b101 The UA RT_RTS # output signal is ena bled on
the DCS#[2] pin.
Al l other values
reserved
Bits 6:4 DCSFN3
DCS#[3] Si gnal Function
.
Bit 7
reserved
Hardwir ed to 0.
Bits 10:8 DCSFN4
DCS#[4] Si gnal Function
.
Bit 11
reserved
Hardwir ed to 0.
Bits 14:12 DCSFN5
DCS#[5] Si gnal Function
.
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L3IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS3, Section 5.4.
b011 General-purpose output whose value is
pr ogr amm ed by bit 9 of the DCSLO UT field in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b110 The UA RT_CTS # output signal is ena bled on
the DCS#[3] pin.
Al l other values
reserved
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L4IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS4, Section 5.4.
b011 General-purpose output whose value is
pr ogrammed by bit 10 of the DCS LOUT fiel d in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b110 The UA RT_D CD# output signal is enabled on
the DCS#[4] pin.
Al l other values
reserved
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L5IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS5, Section 5.4.
Bit 15
reserved
Hardwir ed to 0.
Bits 18:16 DCSFN6
DCS#[6] Si gnal Function
.
Bit 19
reserved
Hardwir ed to 0.
Bits 22:20 DCSFN7
DCS#[7] Si gnal Function
.
Bit 23
reserved
Hardwir ed to 0.
b011 General-purpose output whose value is
pr ogrammed by bit 11 of the DCS LOUT fiel d in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b110 The UART_XIN output signal is enabled on the
DCS#[5] pin.
Al l other values
reserved
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L6IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS6, Section 5.4.
b011 General-purpose output whose value is
pr ogrammed by bit 12 of the DCS LOUT fiel d in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b101 The DMA hardware handshaking DMA_ACK#
output si gnal is enable d on the DC S #[6] pin.
See Section 9.4.
Al l other values
reserved
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L7IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS7, Section 5.4.
b011 General-purpose output whose value is
pr ogrammed by bit 13 of the DCS LOUT fiel d in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b110 The DMA hard ware h ands haki ng DM A_R EQ#
input signal is enabled on the DCS#[7] pin.
See Section 9.4.
Al l other values
reserved
Binary Value Signal Function
Bits 26:24 DCSFN8
DCS#[8] Si gnal Function
.
Bits 63:27
reserved
Hardwir ed to 0.
8.6.4
Device Chip-Selects
as I/O Bits Register
(DCSIO)
The DCSIO register is used to re ad input and wri te output when any of th e DCS#[8:2]
signals are speci fied to be used fo r general-pur pose I/O in the Device Chip-Select
Functi on Register (DCSFN, Sect ion 8.6.3). Bit s 6:0 of the DCSIO regis ter represent
inputs on the DCS[8:2 ] si gnals. Bits 14:8 re present outputs on the DCS[8:2 ] si gnals.
The input bits are synchronized internal ly by the contr oller to SysClock.
Bit 0 DCSL2IN
DCS#[2] In put Synchroniz ed.
The input value on DCS#[2], synchronized internall y
to SysClock.
Bit 1 DCSL3IN
DCS#[3] In put Synchroniz ed.
The input value on DCS#[3], synchronized internall y
to SysClock.
Bit 2 DCSL4IN
DCS#[4] In put Synchroniz ed.
The input value on DCS#[4], synchronized internall y
to SysClock.
Bit 3 DCSL5IN
DCS#[5] In put Synchroniz ed.
The input value on DCS#[5], synchronized internall y
to SysClock.
Bit 4 DCSL6IN
DCS#[6] In put Synchroniz ed.
The input value on DCS#[6], synchronized internall y
to SysClock.
Bit 5 DCSL7IN
DCS#[7] In put Synchroniz ed.
The input value on DCS#[7], synchronized internall y
to SysClock.
Binary Value Signal Function
b000 Gen er al-pur pose input whose value can be
re ad in the DCS L8IN field of th e Dev ice Chip-
Selects as I/O Bits Register (DCSIO), Section
8.6.4. Reset va lue.
b001 The co ntroller’s mem ory interfac e or Local-
Bu s interf ac e dr ives the signal, depend ing on
the MEM/LOC bit in Physical Devi ce Address
Register DCS8, Section 5.4.
b011 General-purpose output whose value is
pr ogrammed by bit 14 of the DCS LOUT fiel d in
the Device Chip-Selects as I/O Bits Register
(DCSIO), Section 8.6.4.
b110 The DMA hardware handshaking DMA_EOT#
input signal is enabled on the DCS#[8] pin.
See Section 9.4.
Al l other values
reserved
Bit 6 DCSL8IN
DCS#[8] In put Synchroniz ed.
The input value on DCS#[8], synchronized internall y
to SysClock.
Bit 7
reserved
Hardwir ed to 0.
Bits 14:8 DCSLOUT
DCS#[8:2] Val ue.
The value to drive on DCS#[8:2] if these signals are
enabled by the DCSOE[8: 2] bit s in the DCSFN regi s-
ter (Sec tion 8.6.3) .
Bits 63:15
reserved
Hardwir ed to 0.
8.6.5
Local Boot Chip-
Select Timing Register
(BCST)
This registe r has the same form at at the LCST8:2 regist ers (Secti on 8.6.2). The reset
value for the BCST regi ster is 0x0 003F 8E3F. So, at reset the timing param eters for
the Boot Chip-Sele ct (BOOTCS) Physical Device Addres s Re gister (Sect ion 5.4) are:
Reset
Value
Bit 0 CSON 1
Bits 2:1 CONSET 3
Bits 8:3 CONWID 7
Bits 14:9 SUBSCW ID 7
Bits 16:15 CSOFF 3
Bits 18:17 COFHOLD 3
Bits 21:19 BUSIDLE 7
Bit 22 RDYMODE 0
Bit 23 RDYSYN 0
Bits 25:24 CONOFF 0
Bit 26 CS_POL 0
Bit 27 CON_POL 0
Bits 63:28
reserved
0
This co nfigur es BOOTCS for the slowes t possi ble boot ROM. Af ter boot , you may con-
figure this register to allow faster access, depending on the timing requirements for
your boot ROM.
9.0 DMA Controller and Registers
The controller support s DMA transfers, from any physical address to any phys ical
address, on two chainable channel s. Thus, DMA transfers can occur:
From:
• Memory,
• PCI-Bus device,
• Local-Bus device, or
• Controller’s int ernal registers
To:
• Memory,
• PCI-Bus device,
• Local-Bus device, or
• Controller’s int ernal registers
The DM A logi c inc ludes a 32- entry x 8-b yte (2 56-b yte) DMA FIFO tha t is use d to b uf fer
transfers. The controller is capable of performing unalig ned read and write transfers
from and to main memory at a maximu m rate of 640M b/s. The controller is al so capa-
ble of transferring from and to the PCI Bus at the maximum PCI transfer rate of 533
MB/ sec (64-bit , 66 MHz), 266 MB/sec (64-bi t, 33 MHz or 32-bit , 66 MH z), or 133 MB/
sec (32-bit, 33 MHz).
9.1
DMA Confi
g
uration
and M onitor in
g
Software confi gures and monitors the DMA logic usi ng the follo wing registers:
Interrupt Control Register (INTCTRL), Section 5.5.2 on page 52.
Inter rupt Status Regi ster 0 (INTSTAT0), Section 5.5.3 on page 55.
Inter rupt Clear Register (INTCLR), Sect ion 5.5.5 on page 56.
DMA Registers, Section 9.5 on page 133.
Device Chi p-Select Function Register (DCSFN), Section 8.6. 3 on page 125.
9.2
DMA Tran sfer
Mechanism
The DMA transfer mecha nism is configured by soft ware and operates autonomous ly
thereafter. If both DMA chann els are confi gured for tran sfers, the sec ond channel will
automat ical ly begin tr ansfer ring when the fir st chan nel complet es. This is call ed
chain-
ing
.
9.2.1
Configur ation and
Enabling
The controlle r contains two set s of DMA registers , for Channel 0 and Channel 1 (Sec-
tio n 9.5). Each regist er set co ntrol s a separat e DMA transfer. One set of register s may
be writ ten or read while the other set is con tr olling a transfer. Active regi sters can be
read, but writing of the acti ve registers is limited to the writing of only the DMA Reset
(DRST) and Suspend DMA (SU) bits in the DMA Control Register (Sec ti on 9.5.1).
Tran sfers on the two channels can be chained (lin ked), so that th e comp let ion of a
transfer on one channel causes the second cha nnel to begin transferring.
The controlle r’s DMA regi sters can be confi gured by any mast er at tached to any of
controlle r int erfaces. T ypically thi s is the CPU, but i t may be any device on the PCI or
Local Bus. To begin a DMA transf er , software specifies the sourc e address, des tination
addres s, length of tr ansfer , end-of -transfer inter rupt, and transfer enable (the GO bit) i n
the DMA Control Register fo r that channel.
9.2.2
Operation When the transfer has been enabl ed, the controller begins by acquiring access to the
resour ce that i s the source of the data transf er . When access to the source i s granted,
the cont roller begins re ading d ata at t he high est rate supported by the source and plac-
ing t he data in i ts 32 x 8-byt e DMA FIFO. When the FIF O reache s its hi gh-water mark,
the controll er requests access to the dest ination of the tr ansfer. When access to the
desti nation is g rant ed, the controller begi ns writing the data at the highe st rate possible
supported by the destination.
If, during a transfer, the DMA FIFO becomes f ull, the controller rel eases control of the
data source until the FIFO is emptied to its low-water mark. The cont roller then reac-
quires the data source and co nti nues filling t he FIFO. If the FIFO b ecom es empty, the
controller releases the data desti nation until the FIFO has been fille d to it s high-water
mark. The control ler then reacquires the data destination and co ntinues emp tyi ng the
FIFO.
When t he c orrect number of byte s has been r ead from the sour ce, the con trol ler sto ps
filling the FIFO but conti nues empt ying the FIFO until the l ast t rans fer c ompletes. Then
the controll er issues a DMA-comple te i nterrupt to the CPU, i f enabled as described i n
the next sectio n, below.
9.2.3
Completion When a tr ansfer fin ishes, the cont roller generates an interr upt to the CPU, if the int er-
rupt is enabl ed by the DM AEN bit in the Interrupt Cont rol Regist er (INTCTRL, Section
5.5.2) and the IE fi eld in the DMA Control Register for that DMA channel (DMACTRL,
Secti on 9.5.1). The control ler checks the st atus of the other set of DMA control regis -
ters to determine if anot her transfer is configured (chai ned); if so, the next DMA trans-
fer begins automatical ly.
If any error occurs, the controller stops the current DMA trans fer, sets one of the
Stopped On An Error (bits 34:32) in the DMA Control Register for that DMA channel
(DMACTRL , Section 9.5. 1), and generates an interrupt, if enab led.
9.3
Data Ali
g
ner The contr oller aut oma ticall y handles unali gned DM A transfers. The ali gner suppo rts
block reads and writes even when both the source and destination addresses are not
ali gned on dword boundar ies.
The al ign er packs d ata i nto t he DMA FIF O in t he ali gnment re quired b y th e desti nation
address. Figure 18 shows the operation of the aligner for a DMA transaction starting
from source address 0003 to st arting destinati on address 0007.
Figure 18: Unaligned DMA Transfer Example
9.4
DMA Hardware
Handshakin
g
DMA transfers can be initiated ei ther entirel
y
in soft ware, or in software accomp anied
b
y
hardware handsh akin
g
. When th e Hardware Han dshak e Enable ( HHSEN) bit is set
to 1 in the DMA Co ntr ol Re
g
ist er (DMACTRLn, Section 9.5.1) , and th e DCSFNn and
DCSOEn fiel ds in the Device Chip-Select Funct ion Re
g
ister (DCSFN, Section 8.6.3)
contains the appr opriate values, the con troller implements hardware handshakin
g
b
y
reconfi
g
urin
g
the functions of the DCS#[8:6] si
g
nals, as follows:
DCS#[6] becomes DMA_ACK# (output).
DCS#[7] becomes DMA_REQ# (input).
DCS#[8] becomes DMA_EOT# (input).
Byte 7 Byte 6 B yt e 5 Byt e 4 Byte 3 B yt e 2 Byte 1 Byte 0
54321
13 12 11 10 9 8 7 6
21 20 19 18 17 16 15 14
27 26 25 24 23 22 Source
DMA FIFO
Destination
Dat a Align er
Byte 7 Byte 6 B yt e 5 Byt e 4 Byte 3 B yt e 2 Byte 1 Byte 0
1
98765432
17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
27 26
Byte 7 Byte 6 B yt e 5 Byt e 4 Byte 3 B yt e 2 Byte 1 Byte 0
1
98765432
17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
27 26
9.4.1
External DMA
Requests
An external device can use the DMA_REQ# input b
y
itself to request a transfer. If the
device uses the DMA_ACK# output, the devi ce mu st al so use the DMA_REQ# input .
Usin
g
the DMA_REQ# input b
y
itself, without the DMA_ACK# output, ma
y
cause diffi -
culties in determinin
g
when i t is saf e to ne
g
ate DMA_REQ#. The Hardwar e Handshake
Desti nation (HHSDEST) bit in the DMA Control Re
g
ist er specifies whether the source
or destination does the hardware handshake with the controller.
An external device requests a DMA transfer b
y
assertin
g
DMA_REQ#. The controller
responds b
y
assertin
g
DMA_ACK# and be
g
ins readin
g
data from the source and writ-
in
g
it to the desti nation. When t he ext ernal device ne
g
ates DMA_REQ#, t he control ler
ne
g
ates DMA_ACK#. For each of thes e assertion/ ne
g
ation c
y
cles, one block of data
(32 b
y
tes) is read until t he DMA transfer count
g
o es to zero.
Block s a re al i
g
ned on 32-b
y
te bou ndar ies. The fi rst and last tr ansfers ma
y
be less t han
32 b
y
tes , b ec ause the
y
ma
y
onl
y
transfer part of a block. If th e requestin
g
device can
source or sink anot her block, the device can re-assert DMA_REQ# one cl ock after
ne
g
atin
g
it.
9.4.2
End Of Transfer The external device can use the DM A_EOT# input to abort a DMA transfer, but onl
y
if
the DMA source is doin
g
the handshak in
g
(HHSDEST=0 in DMACTRLn). DMA errors
ma
y
be report ed b
y
asser tion of the DMA_EO T# i nput , if t his func tion is en abl ed b
y
the
HHSEOT bit in t he DMA Control Re
g
ister. When such an error is reported, t he cont rol-
ler aborts the associated DMA transfer, treatin
g
it as if the DMA transfer count had
g
one to zero. This is the DMA_EOT# input’s onl
y
function.
9.5
DMA Re
g
isters The controller contains two sets of DMA re
g
ister s, for Channel 0 and Channel 1, each
of whi ch contro ls a separ ate DMA trans fer. One set of re
g
isters ma
y
be writ ten or read
whil e the other set is acti ve (control lin
g
a transfer). Active re
g
ister s can be read, but
writin
g
of the active re
g
isters is l imited to t he DMA Reset (DRST) and Susp end DMA
(SU) bits i n the DMA Control Re
g
ist er (Section 9.5).
9.5.1
DMA Control
Registers 0 and 1
(DMACTRLn)
Bits 19:0 BLKSIZE
Block Size.
The number of b
y
tes (up to 1 MB) to be transf erred.
0 = 1 MB.
Bits 21:20
reserved
Hardwir ed to 0.
Table 28: DMA Contr ol Registers
Register Symbol Offset R/W Reset Value Description
DM A Control 0 DMACTRL0 0x0180 R/W 0x0000 0000 0000 0000 DMA co ntrol set 0.
DMA Source Address 0 DMASR CA0 0x0188 R/W 0x0000 0000 0000 0000 DMA so urce address set 0.
DMA Destination Address 0 DMAD ESA0 0x0190 R/W 0x0000 0000 0000 0000 DMA d estination address set 0.
DM A Control 1 DMACTRL1 0x0198 R/W 0x0000 0000 0000 0000 DMA co ntrol set 1.
DMA Source Address 1 DMASR CA1 0x01A0 R/W 0x0000 0000 0000 0000 DMA source address set 1.
DMA Destination Address 1 DMAD ESA1 0x01A8 R/W 0x0000 0000 0000 000 0 DMA destination address set 1.
reserved
— 0x01B0 R 0x0000 0000 0000 0000 —
reserved
— 0x01B8 R 0x0000 0000 0000 0000 —
Bit 22 HHSDEST
Hardware Handshake By Source or Destination.
1 = destinat ion handshakes with contr oller.
0 = source handshakes with cont roller.
When the DCSFN[8:6] fi elds in the Device Chip-
Select Muxing and Output-Enables Register
(DCSFN, Section 8.6.3) contain the val ue 0x2, the
DCS#[8:6] signals become the DMA_EOT#,
DMA_REQ#, and DMA_ACK# signals, respec ti vely.
These signals are used for DMA handshaking with
the controller. The HHSDEST bit specifies whether
the source or destination of the DMA transfer does
the hardware handshake. The HHSDEST bit is valid
only if handshaking is enabled by the HHSEN bit.
Bit 23 HHSEN
Hardware Hands hake Enable.
1 = enable.
0 = disable .
This bi t is vali d only when at least one of the
DCSF N [8:6] f ields in the Device Chi p -Select Muxing
and Output-Enables Register (DCSFN, Section
8.6.3) contains t he val ue 0x2 a nd the corresponding
DCSOEn bit is set in the DCSFN register.
Bit 24 DRST
DMA Reset.
1 = reset.
0 = no reset.
When this bit is set to 1, any DMA in process is ter-
mina ted an d re se t afte r co m p l e t io n of the b us cyc le
in pr oces s. Thi s bit automati call y clea rs to 0 af ter t he
DMA channel has been success ful ly reset. This bit
takes pr ece dence over all ot her bi ts in t he DMA Con-
trol Registers; values written to other bits in the reg-
iste r are disregar ded when the DRST bit is set.
Bit 25 SRCINC
Source-Address Incremen ting.
1 = increment source address.
0 = do not increment source addr ess.
Setti ng thi s bit causes the contro ller to in cremen t the
DMA source address for each read.
Bit 26 DESINC
Destination- Address Incrementing.
1 = increment destination address.
0 = do not increment destination address.
Setti ng thi s bit causes the contro ller to in cremen t the
DMA destination address for each write.
Bit 27 SU
Suspend DMA.
1 = suspend current transfer.
0 = restar t suspended transfer.
This bi t suspends the current DMA transf er af ter
completion of current cycle. All register values are
preser ved. The sus pended transfer may be r estarted
by clearing the SU bit. Thi s bit ma y be set and
cleared without considerat ion of the other bit s in this
regis ter , except t he DMA Reset (DRST) bi t; changi ng
bits other than SU and DRST have no effect after a
DMA transfer has start ed.
Bit 28 GO
St ar t Tran s fe r
.
1 = start DMA transf er.
0 = (no eff ect).
When s et to 1, thi s bit causes DM A to begin wit h the
parameters spe cif ied in the DMA Control Registers.
The bit aut om ati cally res ets after th e tra nsfer com-
pletes. Clea ri ng the b it in software has no effect; the
DMA transfe r will continue .
Bit 29 IVLD
In te rrupt Vali d .
1 = th is DMA channel gen erated an int errupt on com-
pleti on of it’s last transfer.
0 = clear interrupt.
This bi t automatical ly resets when t he GO bit is set
for a new transfer .
Bit 30 IE
Inter rupt Enable.
1 = enables int errupt on completion of the tr ansfer
specif ied by this channel.
0 = disable such interrupts.
The DMAEN field in the Interrupt Control Register
(INTCTRL, Secti on 5.5.2) is a global enable for the
IE fields in the two DMA Control Registers. If the
transfer in either DMA channel complet es, and
DMAEN is set, the contr oller generates an inter rupt
to the CPU. The IVLD bit, above, specifies which
channel caused the int errupt.
Bit 31 BZ
Busy
. (r ead only)
1 = a DMA controlled by this register is currently in
process.
0 = DMA not in process.
This bit may be polled.
Bit 32 MRDERR
Memory Read Error.
1 = transf er stopped on a memory read error.
0 = no such error.
Bit 33 PRDERR
PCI Read Error.
1 = transf er stopped on a PCI-Bus rea d error.
0 = no such error.
Bit 34 UDRDERR
Undecodable Read Error.
1 = transf er stopped on an undecodable read error.
0 = no such error.
Bit 35 HHSEOT
Hardware Hands hake Error.
1 = DMA stopped on DMA_EOT asser ti on.
0 = no such error.
Bits 63:36
reserved
Hardwir ed to 0.
9.5.2
DMA Source Address
Register 0 and 1
(DMASRCAn)
Bits 35:0 DMASRCA
DMA Source Start ing Address.
The start ing source (read) address for this tr ansfer.
This reg ister remains stati c thr oughout the DMA
trans fer , al though setting the SRCINC bit of the DMA
Control Register (Sec tion 9.5.1) causes source
(read) addresses to be inc remented.
Bits 63:36
reserved
Hardwir ed to 0.
9.5.3
DMA Destination
Address Register 0
and 1 (DMADESAn)
Bits 35:0 DMADESA
DMA Destination Starting Address.
The star ting destin ation ( writ e) addre ss f or this t rans-
fer. This register remains static throughout the DMA
trans fer , al th ough setting the DESINC bit of the DMA
Control Register (Sec tion 9.5.1) causes destination
(write) addresses to be incremented.
Bits 63:36
reserved
Hardwir ed to 0.
10.0 Serial Port and Registers
The controlle r implem ents one serial port with the NEC NY16550L UAR T Mega Func-
tio n. Thi s UART is functi onally ide nti cal to the National Semiconductor NS16550D.
Details of its function can be found in the
CB-C8VX/VM ASIC Fami ly 0.5 micron Stan-
dard Cel l User’s Man ual, Mega Functi on NY16550L UART, Prelimi nary, 4 October
1996
.
10.1
Serial -Por t
Confi
g
uration and
Monitorin
g
Software confi gures and monitors the serial-por t l ogic using the f oll owing regist ers:
Interrupt Control Register (INTCTRL), Section 5.5.2 on page 52.
Inter rupt Status Regi ster 0 (INTSTAT0), Section 5.5.3 on page 55.
Inter rupt Clear Register (INTCLR), Sect ion 5.5.5 on page 56.
Serial-Port Registers, Section 10.4 on page 139.
Device Chi p-Select Function Register (DCSFN), Section 8.6. 3 on page 125.
At reset, the UART_DTR# and UART_TxDRDY# signals define the controller’s I D in a
multi -controll er config uration, as descr ib ed in Secti on 12.0. Howev er, this con figuration
does not affect the operat ion of the UART it self.
10.2
Additional UAR T
Si
g
nals
The controller pinouts always carry the UART_DSR#, UART_DTR#,
UAR T_RxDRDY#, UART_TxDRDY# signals. After reset, howev er, the DCS#[5:2] sig-
nals can be reconfi gured to provide the following addit ional UART mode m-control si g-
nals:
DCS#[2] becomes UART_RTS# (output).
DCS#[3] becomes UART_CTS# (input ).
DCS#[4] becomes UART_DCD# (output).
DCS#[5] becomes UART_XIN (inp ut).
These addi tional sig nals are implemented when s oftware write s the appropriate values
to the DCSFNn and DCSOEn fields in the Device Chip- S elect Function Regi ster
(DCSFN, Section 8.6.3).
10.3
UART Cl ocking The UART can be clocked from either an external input or b
y
an internall
y
-
g
enerated
clock. The internal cl ock has a frequen c
y
of S
y
sClo ck divi ded b
y
12. To achieve a
desired baud rate, the UART Divisor Latch (see Section 10. 4.4 and Section 10.4.5)
must be pro perl
y
pro
g
rammed. The rel ati onship be tween UART cl ock frequen c
y
, baud
rate, and divisor value is:
baud_rate = UART_c lock_frequenc
y
/(divi so r_ va lue * 16 )
where for internall
y
-
g
enerated clock:
UART_clock_frequenc
y
= SYS_CLK_freq / 12
Table 29
g
ives divisor values for several different input clock frequencies. The actual
baud rate ma
y
var
y
si
g
nificantl
y
from the desired baud ra te.
Table 29: UART Clock-Rate Divisor Values
Internal
Clo ck S ource External
Cloc k S ou rce
UART_XIN = 1.8432MHz SysClock = 99.5328MHz SysClock = 88.4736MHz SysClock = 73.728MHz
Baud Rat e Divisor Perce nt
Error Di visor Percent
Error Divisor Per cent
Error Divisor Percent
Error
50 2304 10368 9216 7680
75 1536 6912 6144 5120
110 1047 0.026% 4713 0.006% 4189 0.002% 3491 0.003%
134.5 857 0.058% 3854 0.007% 3426 0.001% 2855 0.001%
150 768 3456 3072 2560
300 384 1728 1536 1280
600 192 864 768 640
1200 96 432 384 320
1800 64 288 256 213 0.156%
2000 58 0.690% 259 0.077% 230 0.174% 192
2400 48 216 192 160
3600 32 144 128 107 0.312%
4800 24 108 96 80
7200 16 72 64 53 0.629%
9600 12 54 48 40
19200 6 27 24 20
38400 3 14 3.571% 12 10
5760029874.762%
10.4
Serial-Port
Registers
10.4.1
UART Receiver Data
Buffer Register
(UARTRBR)
This r e
g
iste r holds rec eive data . It is onl
y
accesse d when t he Divis or Lat ch Access Bit
(DLAB) is cl eared to 0 in the UART Line Control Re
g
ister (UARTLCR), Section 10.4.8.
Bits 7:0 UDATA
UART Receive Data
. (read-onl
y
)
Bits 63:8
reserved
Hardwir ed to 0.
10.4.2
UART Transmitter
Data Holding Register
(UARTTHR)
This re
g
ister holds transmit data. It is onl
y
access ed whe n t he Divisor Latc h Acc ess Bit
(DLAB) is cl eared to 0 in the UART Line Control Re
g
ister (UARTLCR), Section 10.4.8.
Bits 7:0 UDATA
UART Transmit Data
. (write-onl
y
)
Bits 63:8
reserved
Hardwir ed to 0.
10.4.3
UART Interrupt Enable
Register (UARTIER)
This re
g
ister is used to enable UART i nterrupts. It is onl
y
accessed when the Divisor
Latch Access Bit (DLAB) is set to 1 in the UAR T Line Control Re
g
iste r (U A R T LCR),
Secti on 10.4 .8. Th e UAR TEN fiel d in the I nterru pt Cont rol Re
g
ister ( INTCTRL, Sec tion
5.5.2) is a
g
lobal enable fo r interrup t sources enabled b
y
this re
g
ister.
Bit 0 ERBFI
Enable Receive-Buffer-F ull Interrupt .
1 = enable receive-data-available interrupt.
0 = disable such interrupt.
The receive-buffer-ful l st ate is report ed in the UART
Line Status Re
g
ist er (UARTLSR, Secti on 10.4.10).
Table 30: Serial-Port Register Summary
Register Symbol Offset R/W Reset Value Description
UART Receiver Data Buffer UARTRBR 0x0300 R 0x0000 0000 0000 00XX UART receiver data DLAB a = 0
UART Transmitter Data Holding UARTTHR 0x0300 W 0x0000 0000 0000 00XX UART transmit data DLAB a = 0
UART Interrupt Enable UARTIER 0x0308 R/W 0x0000 0000 0000 0000 UART interrupt enable DLAB a = 0
UART Divisor Latch LSB UARTDLL 0x0300 R/W 0x0000 0000 0000 00XX UART divisor latch LSB DLAB a = 1
UART Divisor Latch MSB UARTDLM 0x0308 R/W 0x0000 0000 0000 00XX UART divisor latch MSB DLAB a = 1
UART Interrupt ID UARTIIR 0x0310 R 0x0000 0000 0000 0001 UART interrupt ID
UA RT FIFO Contro l UARTFCR 0x0310 W 0x0000 0000 0000 0000 UART FIFO cont r ol
UART Line Control UARTLCR 0x0318 R/W 0x0000 0000 0000 0000 UART line control
UART Modem Control UARTMCR 0x0320 R/W 0x0000 0000 0000 0000 UART modem control
UART Line Status UARTLSR 0x0328 R/W 0x0000 0000 0000 0060 UART line status
UART Modem Status UARTMSR 0x0330 R/W 0x0000 0000 0000 0000 UART modem status
UART Scratch UARTSCR 0x0338 R/W 0x0000 0000 0000 00XX UART scratch
a. Divisor Latch Access Bit (DLAB) in the UART Line Control R egister (Section 10.4.8)
Bit 1 ETBEI
Enable Transmitter-Buff er-Empt y Int errupt
.
1 = enable transmit-buffer-empty interrupt.
0 = disable such interrupt.
The transmit-buffer -empty state is reported in the
UART Line Status Register (UARTLSR, Section
10.4.10).
Bit 2 ELSI
Enable Line-Stat us Interrupts.
1 = enable line-status-error interrupt.
0 = disable such interrupts.
Line st atus er rors ar e rep orted in th e UART Li ne Sta-
tus Regis ter (UARTLSR, Sect ion 10.4.10) .
Bit 3 EDSSI
Enable Modem -Status Int errup ts.
1 = enable modem-status-change interrupt.
0 = disable such interrupts.
Modem sta tus changes a re re port ed in bits 3:0 of t he
UART Mode m Status Register (UARTMSR, Sect ion
10.4.11).
Bits 63:4
reserved
Hardwir ed to 0.
10.4.4
UART Divisor Latch
LSB Register
(UARTDLL)
This regist er is only accessed when the Divisor La tch Access Bit ( D LAB) i s set to 1 in
the UART Line Control Register (UAR TLCR), Section 10.4.8.
Bits 7:0 DIVLSB
UART Divisor Latch Least-Significant Byte (LSB).
See the 16550 data sheet for details on the relation
between divisor values and baud rate.
Bits 63:8
reserved
Hardwir ed to 0.
10.4.5
UART Divisor Latch
MSB Regi ste r
(UARTDLM)
This regist er is only accessed when the Divisor La tch Access Bit ( D LAB) i s set to 1 in
the UART Line Control Register (UAR TLCR), Section 10.4.8.
Bits 7:0 DIVMSB
UART Divi sor Latch Most-Si gnific ant Byt e (MSB).
See the 16550 data sheet for details on the relation
between divisor values and baud rate.
Bits 63:8
reserved
Hardwir ed to 0.
10.4.6
UART Interrupt ID
Register (UARTIIR)
Bit 0 INTPENDL
UART Interrupt Pending
. (read- only)
1 = no interrupt pending.
0 = interrupt pending.
Bits 3:1 UIID
UART Interrupt ID
. (read- only)
Bits 5:4
reserved
Hardwir ed to 0.
Bits 7:6 UFIFOEN
UART FIFO Enabled
. (read- only)
Both of the se bit s are set to 1 when the transm it/
recei ve FIFO is enabl ed in the UFIFOEN0 bit is set in
the UART FIFO Control Register (UARTFCR, Sec-
tion 10. 4.7).
Bits 63:8
reserved
Hardwir ed to 0.
10.4.7
UART FIFO Control
Register (UARTFCR)
Bit 0 UFIFOEN0
UART FIFO Enable
. (write-only)
1 = enable receive and transmit FIFOs.
0 = disable and clear receive and transmit FIFOs.
Bit 1 URFRST
UART Receiv er FI FO Reset
. (wr ite -onl y)
1 = clear rec eive FIFO and reset counter.
0 = no clear.
Bit 2 UTFRST
UART Transmitter FIFO Reset
. (wr i te - on ly)
1 = clear transm it FIFO and reset counter.
0 = no clear.
Bits 5:3
reserved
Hardwir ed to 0.
Interrupt
ID# Priority Source of Interrupt
0x3 Highest
Receiver Line Status:
Overrun Error,
Parity, Framing Error, or Break
Int errupt. The int errupt is clea red when
the UART Li ne S tatus Register
(UARTLSR) is read.
0x2 Second
Re c eiv ed Data A v ailable:
Receiver
Data Available or Trigger Level
Reached. The interrupt is cleared when
the UART Re c eiv er Dat a B uffer
Register (UARTRBR) is read .
0x6 Second
Ch ar ac ter Tim e- Out Indica tion:
No
change in re ceiver FIFO d uring the last
four c harac ter tim es and FIFO is not
empty. The interrupt is cleared when
the UART Re c eiv er Dat a B uffer
Register (UARTRBR) is read .
0x1 Third
Trans m itter Holding Regis ter Em pty:
The inter r upt is cleared when the
UAR T T r ans m itter Data Holding
Register (UARTTHR) is written or this
UART Interrupt ID Registe r (UARTIIR)
is read.
0x0 Fourth
Modem Status:
CTS#, DSR#, or
DCD#. The interrupt is cleared when
the UART Modem Sta tus Register
(UARTMSR) is read.
Bits 7:6 URTR
UART Receive FIFO Trigger Level
.
When the tri gger level i s reached, a Receive-Buffer-
Full interrupt is generated, if enabled by the ERBFI
bit in th e UART I nterrupt Enable Register ( UAR TIER,
Section 10.4.3).
Bits 63:8
reserved
Hardwir ed to 0.
10.4.8
UART Line Control
Register (UARTLCR)
Bits 1:0 WLS
Word Leng th Sel ect.
11 = 8 bits.
10 = 7 bits.
01 = 6 bits.
00 = 5 bits.
Bit 2 STB
Stop Bits.
1 = 2 bits (except 1.5 stop bits for 5-bit words).
0 = 1 bit.
Bit 3 PEN
Parit y Enabl e.
1 = generate par it y on writes, check it on read s.
0 = no parity generation or checking.
For the UART, even or odd parity can be generated
or chec ked, as spe cifi ed in Bi t 4 (EPS). T his i s un like
parit y on the CPU, mem ory and PCI Bus interfaces,
which is always
even
parit y.
Bit 4 EPS
Even-Parity Sel ect.
1 = even parit y.
0 = odd parity.
Bit 5 USP
Stick Parity.
1 = force generated and checked parity to EPS.
0 = normal parity generation and checking.
This bi t is only val id when parit y is enabled (PEN bit
set).
Bit 6 USB
Set Break.
1 = force UART_TxDRDY# signal output Low (0).
0 = normal o peration of UART_TxDRDY# signal out-
put.
Bit 7 DLAB
Divisor Latch Access Bit.
1 = access baud-rate div isor at off set 0x030 0:308.
0 = access TxD/RxD and IE at offset 0x0300:308
When this bit is set, the UART accesses the UART
Receiv e Trigge r Level Number o f Byt es in Receiver FIFO
0x0 01
0x1 04
0x2 08
0x3 14
Divis or Lat ch LSB Register (UARTDLL, Section
10.4. 4) at offset 0x0300, and t he UART Divis or La tch
MSB Register (UARTDLM , Section 10.4.5) at offset
0x308. W hen the bit is cleared, the UART accesses
the UART Receiver Data Buffer Regist er (UAR-
TRBR, Sect io n 10.4.1) on reads at offset 0x0300, t he
UART Trans mitter Data Holdi ng Register (UART-
THR, Sect ion 10. 4.2) on write s at of fset 0x0300, and
the UART Inter rupt Ena ble Regi ster ( UARTIER, Sec-
tion 10. 4.3) on any access at offset 0x0308.
Bits 63:8
reserved
Hardwir ed to 0.
10.4.9
UART Modem Control
Register (UARTMCR)
This re gister cont rol s the state of external UART_DTR# and UART_RTS# modem -
control signals and of the loop-back test.
Bit 0 DTR
Data Terminal Ready.
1 = negate UART_DTR# signal.
0 = assert UART_DTR# signal.
Bit 1 RTS
Request To Send.
1 = negate UART_RTS# signal.
0 = assert UART_RTS# signal.
This bi t has an effect only if the DCS#[2] pin has
been programmed, after reset, to carry the
UART_RTS# signal. See Section 10.2.
Bit 2 OUT1
Out 1.
1 = OUT1# state active.
0 = OUT1# state inactive (reset value).
This is a user-defined bit that has no associated
external signal. Software c an write to the bit, but this
has no effect.
Bit 3 OUT2
Out 2.
1 = OUT2# state active.
0 = OUT2# state inactive (reset value).
This is a user-defined bit that has no associated
external signal. Software c an write to the bit, but this
has no effect.
Bit 4 LOOP
Loop-Back Test
.
1 = loop-back.
0 = normal operation.
This is an NEC internal test function.
Bits 63:5
reserved
Hardwir ed to 0.
10.4.10
UART Line Status
Register (UARTLSR)
This re
g
ister reports the cur rent state of the trans m it ter and receiv er lo
g
ic.
Bit 0 DR
Receive-Data Ready.
1 = receive data buffer ful l.
0 = receive data buffer not full.
Receive data is stored in the UART Recei ver Data
Bu ffe r R e
g
ist er (UARTRBR, Section 10.4.1).
Bit 1 OE
Receive-Data Overrun Error.
1 = overrun error on receive data.
0 = no such error.
Bit 2 PE
Receive-Data Parity Error
.
1 = parit
y
error on receive data.
0 = no such error.
Bit 3 FE
Receive-Data Frami ng Err or
.
1 = framin
g
error on receive data.
0 = no such error.
Bit 4 BI Break Int errupt.
1 = break received on UART_RxDRDY# si
g
nal.
0 = no break.
Bit 5 THRE
Transmitter Holding Register Empty
.
1 = transmit ter holdi n
g
re
g
ister empt
y
.
0 = transmit ter holdi n
g
re
g
ister not empt
y
.
Tr ansmit data is stored i n the UART Tr ansmitter Data
Holdin
g
Re
g
i st e r (U A RTT H R , Sec tion 1 0. 4 .2 ).
Bit 6 TEMT Transmitter Empt
y
.
1 = transmit ter holdi n
g
and shift re
g
iste rs emp t
y
.
0 = transmit ter holdi n
g
or shif t re
g
ister not empt
y
.
Bit 7 RFERR
Receiver FIFO Error.
1 = parit
y
, framin
g
, or break error in receiver buffer.
0 = no such error.
Bits 63:8
reserved
Hardwir ed to 0.
10.4.11
UART Modem Status
Register (UARTMSR)
This re
g
ister reports the cur rent state of and chan
g
es in vari ous contro l si
g
nals.
Bit 0 DCTS
Delta Clear To Send.
1 = UART_CTS# state chan
g
ed since this re
g
ister
was last read.
0 = no such chan
g
e.
Bit 1 DDSR
Delta Dat a Set Ready.
1 = UART_DSR# input si
g
nal chan
g
ed since thi s
re
g
ister was last read.
0 = no such chan
g
e.
Bit 2 TERI
Trailing Edge Ring Indi cator
.
1 = RI# state chan ged since this r egister la st read.
0 = no such change.
RI# is not implement ed as an ext ernal signal, so this
bit is never set by the controller.
Bit 3 DDCD
Delta Data Carrier Detect.
1 = UART_DCD# state changed since this regi ster
was last read.
0 = no such change.
Bit 4 CTS
Clear To Send.
1 =UART_CTS# stat e active.
0 = UART_CTS# state inactive.
This bi t is the c om ple men t of the UART _CTS# input
signal . If the LOOP bit in the UART Modem Co ntr ol
Regist er ( UARTMCR), Section 10.4.9, i s set to 1, th e
CTS bit is equiva lent to the RTS bit i n the UART-
MCR.
Bit 5 DSR Data Set Ready.
1 = UART_DSR# state active.
0 = UART_DSR# state inactive.
This bit is the comp lement of the UART_DSR# inpu t
signal . If the LOOP bit in the UART Modem Co ntr ol
Regist er ( UARTMCR), Section 10.4.9, i s set to 1, th e
DSR bit is equival ent to the DTR bit in the UART-
MCR.
Bit 6 RI Ring Indicator.
1 = not va lid .
0 = always reads 0.
This bit has no associated external signal.
Bit 7 DCD Data Carrier Detect.
1 =UART_DCD# state active.
0 = UART_DCD# state inactive.
This bi t is the complement of the UART_ DCD# input
signal . If the LOOP bit in the UART Modem Co ntr ol
Regist er ( UARTMCR), Section 10.4.9, i s set to 1, th e
DCD bit is equival ent to the OUT2 bit in the UART-
MCR.
Bits 63:8
reserved
Hardwir ed to 0.
10.4.12
UART Scratch
Register (UARTSCR)
This register contains a UAR T reset bit plus 8 bit s of space for any software use.
Bits 7:0 USCR
UART Scrat ch Regi ster.
Available to software for any purpose.
Bit 8 URESET
UART Reset.
1 = reset UART.
0 = no reset.
This bit always reads 0.
Bits 63:9
reserved
Hardwir ed to 0.
11.0 Interrupts
The controlle r supports interrup ts t o the CPU on it s Int # or NM I# inputs from a vari ety
of ca uses, and it suppor ts re-ro uting o f int errupt s to a PCI host CPU. Th e followi ng r eg-
isters are used to configure, report status, and clear interrupts:
Interrupt Control Register (INTCTRL), Section 5.5.2 on page 52
Inter rupt Status Regi ster 0 (INTSTAT0), Section 5.5.3 on page 55
Interrupt Status 1/CPU Interrupt Enable Register (INTSTAT1), Section 5.5.4 on
page 55
Inter rupt Clear Register (INTCLR), Sect ion 5.5.5 on page 56
PCI Interrupt Control Register (INTPPES), Secti on 5.5.6 on page 57
Watchdog Timer Control Register (T3CTRL), Section 5.6.7 on page 61
General-Purpose Timer Control Register (T2CTRL), Section 5.6.5 on page 60
Memory Control Register (MEMCTRL), Section 6.6. 1 on page 72
Memory Check Error Stat us Register (CHKERR), Section 6.6.3 on page 74
PCI Control Register (PCICTRL), Section 7.11.1 on page 91
PCI Error Register (PCIERR), Section 7.11.4 on page 103
PCI Command Register (PCICMD), Section 7.13.3 on page 107
PCI Status Regist er (PCISTS), Section 7.13.4 on page 108
PCI Interrupt Line Register (INTLIN), Section 7.13.13 on page 112
PCI Interrupt Pin Register (INTPIN), Section 7.13.14 on page 112
PCI Control Register (PCICTRL), Section 7.11.1 on page 91
Local Bus Chip -Select Timing Registers (LCSTn) , Section 8.6. 2 on page 122
DMA Control Regi sters 0 and 1 (DMACTRLn), Section 9.5. 1 on page 133
UART Inter rupt Enable Register (UARTIER), Section 10.4.3 on page 139
UART Inter rupt ID Register ( U ARTIIR), Section 10.4.6 on page 140
UART Line Status Register (UARTLSR), Sect ion 10.4.10 on page 144
UART Modem Status Register (UARTMSR), Section 10.4.11 on page 144
For details on wiring PCI inter rupt s, see Section 2.2.6 of the
PCI Local Bus Specifica-
tion
.
On reset , all inter rupts are enab led onto Int#0 by defau lt . Af te r re set, each in ter rupt can
be separately enabled and pr ogrammed to interrupt the CPU on any of its seven inter-
rupts, Int# [5:0] and NMI#. Most of the inte rrupt confi guration i s done in the Inter rupt
Control Regist er (INTCTRL), although other re gisters must also be confi gured for
some of the i nterrupts . Each of the seven CPU interrupts are separ ately enabled.
Each CPU interrupt has a 16-bit status field in the Interrupt Status Register 0
(INTSTAT0) or Interrupt St atus 1/CPU Int errupt Enabl e Register (INTSTAT1). The sta-
tus f iel d shows which interrupt sour ce or sources are reque sting servi ce for a particu lar
CPU inter rupt level . A cle ar bit is available for each int errupt source, altho ugh these
bits only function for edge-triggered interrupts.
When t he controll er i s the PCI Central Resource (PCICR# asser ted at reset), t he con-
trol ler’ s INTA# signal is bidirectional, rather than an output, so that the control ler can
accept up to five PCI interrupts on INT A# t hro ugh INTE#. It forwards these interrup ts t o
the CPU, as spec ified in Inter rupt Control Register (INTCTRL), Section 5.5. 2. When
the controller is not the PCI Central Resource (PCICR# negat ed at res et), interr upts
may be serviced by a PCI host CPU. CPU Interrupt Leve l 0 (Int#[0] ) may be driven onto
PCI interr upt signal INTA#, and CPU Int errupt Level 1 (I nt#[1]) ma y be driven ont o the
PCI system error signal, SERR#.
Table 31 sum m arizes the reg isters used to c onfi gure and monitor the causes of these
interrupts. For details, see the register descriptions referenced in this table.
Table 31: Interrupt Configuration and Reporting Registers
Interrupt T ype Interrupts Configured In: Interrupt Status Reported In: Interrupts Cleared In:
CPU Parity Errors INTCTRL (Section 5.5.2) INTSTST0 (Section 5 .5.3)
INTSTST1 (Section 5.5.4) INTCLR (Section 5.5.5)
CP U No- Target Decode INTCT RL ( S ec tion 5.5.2) INTSTS T0 (Section 5.5.3)
INTSTST1 (Section 5.5.4) INTCLR (Section 5.5.5)
Memory Errors
(p ar ity or E CC) INTCTRL (S ec ti on 5.5.2)
MEMCTRL (Section 6.6.1) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4)
CHKERR (Section 6 .6.3)
INTCLR (Section 5.5.5)
DM A Events INT CTRL (Sec tion 5.5.2)
DMACTRLn ( S ecti on 9.5.1) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4)
DMACT RLn (S ec tion 9.5.1)
INTCLR (Section 5.5.5)
UART Events INTCTRL (Section 5.5.2)
UAR TI E R ( S ec tio n 10.4.3) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4)
UARTIIR (Section 10.4.6)
UARTLSR (Section 10.4.10)
UARTMSR (Section 10.4.11)
INTCLR (Section 5.5.5)
Wat c hdog T im er INT CTRL (Secti on 5.5.2)
T3CTRL (Section 5.6.7) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4) INTCLR (Section 5.5.5)
General-Purpose Timer INTCT RL ( S ec ti on 5.5.2)
T2CTRL (Section 5.6.5) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4) INTCLR (Section 5.5.5)
Loc al-B us Ready Ti m er INTCT RL ( S ec ti on 5.5.2)
LCSTn (Section 8.6.5) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4) INTCLR (Section 5.5.5)
PCI Interrupts
(INTE# through INTA#) INTCTRL (Sec tion 5.5.2)
INTPPES (Section 5.5.6)
PCICTRL (Section 7.11.1)
PCICMD (Section 7.13.3)
INTLIN (Section 7.13.13)
INTPIN (Section 7.13.14)
INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4)
PCIE RR ( S ec tio n 7.11.4)
PCIS TS ( S ec tio n 7.13.4)
INTCLR (Section 5.5.5)
PCI SERR# (System Error) aI NTCTRL (S ec ti on 5.5.2)
PCICTRL (Section 7.11.1) INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4)
PCIE RR ( S ec tio n 7.11.4)
PCIS TS ( S ec tio n 7.13.4)
INTCLR (Section 5.5.5)
PCI Internal Error bI NTCTRL ( S ec tion 5.5.2)
INTPPES (Section 5.5.6)
PCICTRL (Section 7.11.1)
INTSTST0 (Section 5.5.3)
INTSTST1 (Section 5.5.4)
PCIE RR ( S ec tio n 7.11.4)
PCIS TS ( S ec tio n 7.13.4)
INTCLR (Section 5.5.5)
a. A
PCI System Error
is an address- or data-parit y error on a PCI Special C ycle, or any other ser ious syst em error.
b. A
PCI Internal Error
indicates that somethi ng bad happened du ring a PCI transa c tion; the fault could lie either with the
PCI device or the controller.
12.0 Reset and Initialization
At reset, the controller begins the CPU initialization from Serial Mode EEPROM or by
self-initiali zation. Immediatel y after this ini ti alization, the controller’ s Physical Devi ce
Address Registers (PDARs) and Boot RO M are loc ated at the addresse s descr ibed in
Secti on 5.4.1. Only the address ranges for Boot ROM (BOOTCS) and the cont roller’s
internal re gisters (INTCS) are accessible at reset. The address spaces of the two
SDRAM banks, SDRAM0 and SDRAM1, and t he address spac es of t he device chip-
selects, DCS#[8:2], power up in the disabled state so that main memory and the
devices asso ciated with DCS#[8:2] are not acces sible. After the boot sequence, soft -
ware may configure the PDARs to support mem ory a ccesses, as describ ed in Section
5.4.
12.1
T
y
pes of Reset The controller supports the foll owing types of r eset:
Power-Up Reset:
When the VccO k input from external circuitry transitions
between negated and asserted, the cont roller :
• resets its internal registers and state.
• asserts ColdReset# and Reset# to the CPU.
• asserts PCIRST# on the PCI Bus, if PCICR# is asserted to the controller.
• samp les the configurati on signals descr ibed in Secti on 12.2, below.
• runs the CPU initi ali zation procedure described in Section 12.3, bel ow.
Cold Reset:
When the CLDRST bit is set i n the CPU Stat us Regis ter (CPUSTAT),
Section 5.5.1, t he controll er performs the same actions as f or Power-Up Reset,
above.
Warm Reset:
When the WARMRST bi t is set i n the CPU Status Register
(CPUSTAT), Section 5.5.1, the control ler:
• asser ts R e set# to the CP U.
PCI Cold Reset:
When the PCICRST bit is set in the PCI Control Register
(PCICTRL), Section 7.11.1, the controller:
• resets its PCI logic, incl uding resett ing all PCI configurati on register s to their
reset values (al l data and pending operati ons in the PCI FIFOs are lost).
• if PCICR# is asserted, assert s PCIRST# on the PCI Bus.
PCI Warm Reset:
When the PCIWRST bit is set in the PCI Control Register
(PCICTRL), Section 7.11.1, th e controll er functions differently, depending on t he
controller’s configuration:
• if PCI CR# is asserted, the controll er asserts PCIRST# on the PCI Bus.
• if PCICR# is negated, all PCI accesses to the controller as PCI target are
retried.
The remai ning part s of thi s chapter relate only to th e first two type s of reset—Power-Up
and Cold Reset .
12.2
Power-Up and Cold
Reset Configuration
Signals
Several si
g
nals are sampled at Power- Up and Cold Reset to determine the follo win
g
properties of the controller ’s operation:
Endian Mode:
The CPU inter face can operate in l it tle-endi an or bi
g
-endian mode.
(The memor
y
, PCI-Bus, and Local-Bus interfaces alwa
y
s operate i n li tt le-endian
mode).
PCI-Bus and Local-Bus Width:
Either a 64-bi t PCI Bus and no Local Bus, or a 32-
bit PCI Bus and a 32-bit Local Bus.
PCI Central Resource Function:
The controller can operate either as the PCI
Central Resource or in the PCI Stand-Alone Mode.
Base Addres s of Control ler Registe rs and Boot ROM:
The def aul t base a ddresses
for co n troller internal re
g
ister s and Boot ROM are 0x0 1FA0 0000 and
0x0 1FC0 0000, res pectivel
y
. However, these base addresses are diff erent if
multi ple controllers ar e used in a s
y
stem.
Controller ID in Multi-Controller Configurations:
When multipl e controllers are
used in a s
y
stem, each controll er has its own ID number.
The controller drives the CPU's Reset# and ColdReset# si
g
nals. Alternativel
y
, software
can cause a CPU cold and warm reset b
y
writ in
g
to the CLDRST or WARMRST bit in
the CPU Interf ace Re
g
ist ers (Section 5.5 on pa
g
e 50).
Table 32 and Table 33 show the si
g
nals that the controller samples on reset. The con-
trol ler samples the two UART si
g
nals for this purpose onl
y
on the risin
g
ed
g
e of Cold-
Reset#. The other si
g
nals (Bi
g
Endian, PCI6 4# and PCICR#) must be sta tic at all times.
Table 32: Endian and PCI Reset Configuration Signals
Si gna l Sam pl ed
at Res et Wh en Negat ed
At Res et When Asserted
At Re set
BigEndian aThe cont r oller implement s a Little-E ndian
CPU in terfa c e. The co ntroll er im plements a Big-Endian
CP U interf ac e.
PCI64# The cont r oller implement s a 32- bit PCI
Bus:
• REQ64# becomes LOC_ALE.
• ACK64# becomes LOC_CLK.
• C/BE#[7:4] becomes LOC_A[3:0].
• PAR64 becomes LOC_A[4].
• PCI_A D[63:32] bec om es
LOC_AD[31:0].
• The controller’s default location for
Boot ROM is the Local Bus.
The cont r oller implements a 64-bit P CI
Bus:
• L OC_ALE becomes RE Q64 #.
• LOC_CLK becomes ACK64#.
• LOC_A[3:0] becomes C/BE#[7:4].
• LOC_A[4] becomes PAR64 .
• L OC_AD[ 31:0 ] becomes
PCI_AD[63:32].
• The controller’s default location for
Boot ROM is the memo ry bus.
PCICR# The cont r oller is not the P CI Cen tral
Resource:
• PC LK[ 0] is an i npu t and P CLK[4: 1] ar e
floated.
• REQ#[0] is an output and REQ#[4:1]
are unused inputs.
• GNT #[0] i s an input a nd GNT #[4: 1] a re
floated.
• INTA# is an output.
• PCIRST# is an input.
The cont r oller is the PCI Central
Resource:
• PCLK[4:0] are all outputs, and the
controller u ses PCLK[0] as its PCI-Bus
clock.
• R E Q#[4:0] are all inputs .
• GNT#[4:0] are all out puts.
• INTA# is bidirectional.
• P CIRST# is an ou tput .
• The controll er c onfig ur es 64-bit PCI
operation with its REQ64# output.
• The controll er generates PCI
Configuration Space cycles.
12.3
PCI Reset
Sequencing
When PCICR# is asserted, t he controll er is t he PCI Central Resour ce and drives
PCIRST#. The PCI Bus is held in re set until the CPU clear s the PCIWRST bit in the
PCI Control Re
g
ist er (PCICTRL, Section 7. 11.1).
When PCICR# i s ne
g
ated, and there i s no CPU attache d to the contr oller , the controll er
holds all of its lo
g
ic in reset while the PCIRST# input is asserted. After PCIRST# is
ne
g
ated, the controller co mes out of rese t. All PCI acces ses t o the contr oller are ret ried
until the cont roller completes readin
g
the Serial Mode EEPROM.
When PCICR# is ne
g
ated, and a CPU is at tached to the cont rol ler, all contro ll er lo
g
ic
and the CPU are held in reset while th e PCIRST# i nput is asser ted. After PCIRST# i s
ne
g
ated, the controll er and th e CPU are brou
g
ht out of reset. All PCI accesses to the
controlle r are retried until the controller com pletes readin
g
the Serial Mode EEPROM,
and the CPU has clea red t he PCIRST bit in t he PCI Contr ol Re
g
ister.
12.4
CPU and Controller
Initialization
On b oth power-up and c old resets, the controller dri ves t he CPU' s ColdRes et# si
g
nal.
The cont roll er als o cont rols the CPU's seri al m ode-in itiali zati on seq uence imm ediate l
y
after the CPU wakes up from power-up or cold reset. From the CPU’s point of view at
reset, th e controller pretends to be the CPU’s Serial Mode EEPROM ( Section 12.4.2).
If the s
y
stem has no Serial Mode EEPROM, the controller
g
enerates a default data
str eam. If th e s
y
stem ha s a Serial Mode EEPROM, the controller is connected between
it and the CPU and monitors t he passin
g
th ro u
g
h of serial mo de data, makin
g
an
y
required corrections.
12.4.1
Reset Signal Control The co ntr olle r needs ex ternal a nal o
g
circuitr
y
to provide the VccOk si
g
nal, as spec if ied
in the
V
R
5000 Bus Interface User’s Manual
. The controller’s internal PLL is held in
reset as lon
g
as VccOk is ne
g
ated. Bet ween the time VccOk is as ser ted to the control -
ler, and the controller ne
g
ates ColdReset# to the CPU, the internal controller PLL is
lockin
g
up. The skew-cont rolled cl ock from the PLL is onl
y
used inside the controller
a. The BigEndian signal is ORed with Endian Bit (EB) of the Serial Mode EEPROM initial-
ization sequenc e to determine the C PU’s endian mode.
Table 33: Base-Address and ID Reset Config uration Signal s
Sign al Samp led at Re set
Controll er
I D Numb er
Base Address
Of Controller’ s
Internal Regis t ers
After Res et
(PDAR = IN TCS)
Base Address
Of Boot ROM After
Reset
(PDAR = BOOTCS)
UART_DTR# UART_TxDRDY#
0000
(Main Controller) 0x0 1FA0_000 0 a
a. This i s the base addr ess for all single-controller configurati ons, and for the Main Control-
ler in a mult i-controller configuration.
0x0 1 FC0 0000
0 1 01 0x0 1F80_0000
disabled
1 0 10 0x0 1F60_0000
disabled
1 1 11 0x0 1F40_0000
disabled
after ColdReset # is negated. Bef ore then, all acti ve logic is ru nning off an unbuffered
raw clo ck .
The controller internally synchr onizes VccOk to SysCl k. If the asser ti on of VccOk
meets setup and hold ti me s, VccOk needs be asser ted for a minimum of onl y one
SysC lk.
When t he externa l circ uit ass erts VccOk, the contr olle r conti nues to asset ColdReset #
to the CPU and begi ns to read the initializ ati on sequence (Se ction 12.4.2) while still
holdi ng the CPU in reset. After the controller reads a byte of mode info rmation, it
asserts CntrVccOk to the CPU and counts 64K SysClocks before synchron ously
negating ColdReset#. 64 SysClocks la ter, the controll er nega tes Rese t#. When a col d
software reset occurs, the same sequence tak es place, alt hough the reset in dication
originates internally.
When a warm sof tware reset occurs, the con tr oller synchronously asserts Reset# for
64 SysClocks. The ColdReset# signal remains negated throughout a warm software
reset and the contr oller’s oth er operations are unaffected.
12.4.2
Init ial ization Sequence The CPU n eeds a seri al s tream of init iali zati on data, as de fined i n Secti ons 5.2 an d 5.3
of the
V
R
5000 Bus Inter face User’s Manual
. This data stream may come f rom a Ser ial
Mode EEPROM or f rom the control ler itse lf (sel f-ini ti alizat ion).
If t he Seri al Mode EEPROM alt ernative is chosen, the SGS-Thomson M93C46-W or
the Microchi p Technology 93AA46 Serial EEPROM, or equivalent, mu st be used. The
EEPROM must support the following feat ures:
64 x 16 configuration.
Sequential read operation.
3.3V supply voltage.
Microwire bus interface.
Clock fr equency of 800 kHz (SysClock/128).
If the s elf-init ia lization alt ernative is chosen, the PROM_SD si gnal mus t be pulled up. If
an alternate sour ce is used, care must be taken to provide the CPU with contr oller-
compatible initialization data.
12.4.2.1
Connecti ng the Serial
Mode EEPROM
The M93C46-W Serial EEPROM (or equivalent) has separate DATA- IN and DATA-
OUT signals, but the controll er has only one bi directi onal signal , PROM_SD, to wh ich
the EEPROM data signals shoul d connect and on which both address and data
appear.
Figur e 19 illust rates the connections . T he EEPROM’s DA TA-IN an d DA T A-OUT si gnals
should be tied to gether and then connected to the controller ' s PRO M_SD signal. (For
details on how these signals should be tied together, see the SGS-Thomson Applica-
tion Note AN394
Microwire EEPROM Common I/O Oper ation
.) The controller's
PROM_CLK output sho uld be connected to EEPROM's SERIAL_CLOCK input. The
controlle r’s BigEndi an signal shoul d be connected to the EEPROM’ s CHIP_SELECT
signal and tied to either Vcc or GND through a resistor. The controller can then drive
BigEndi an to s elect the EEPROM and rea d its init ializat ion dat a. Aft er init iali zati on, the
controlle r uses BigEndian as an in put to indicate the endian mode for t he controll er.
Resistors RBE1 and RBE2
or
RLE1 and RLE2 must be used to select t he endian mode for
the cont roller and the CPU; f our r esist ors ar e is shown in Fi gur e 19 bu t only t wo should
be used.
Figure 19: Serial Mode EEPROM Signal Connections
12.4.2.2
Ini tiali z a tion Da ta Upon power -up or cold reset i n the Serial Mode EEPROM ini ti alizat ion alternative, the
controlle r sends a read command and an addr ess (locati on 0) to the Serial Mo de
EEPROM to obt ain a b yte of mode inf ormati on. The EEPROM wi ll d rive a 0 on its Data
Out pin during the clo ck in which the cont roller is sending its final address bit . Since the
controlle r is sending an address of 0, ther e is no bus conflict, and the EEPROM Dat a
In and Data Out pins can be tied together.
Then, the controll er asse rts the CntrVccOk signa l to the CPU and monitors the CPU’s
ModeClock output. When ModeClock goes Low, the controller shifts the first initializa-
tion byte out of a hol ding register (corrected if necessary), dri ves it onto the ModeOut
signa l (t o the CPU’s ModeIn), a nd reads the next by te fr om the Ser ial Mode EEPROM.
This process continues until all mode information is read from the Serial Mode
EEPROM and provided to the CPU. Since ModeCl ock runs at SysClock divide d by
256, and PROM_ CLK runs at SysClock di vided by 128, the controller can read mode
data and provide a continuous uni nterrupted stream to the CPU.
The cont roll er passes 25 6 bits of config urati on data to t he CPU, begin ning wit h bit 0 of
the s erial data stream f rom the EEPROM. In a ddi tion, t he EEPROM co ntains 37 bits of
controller-specific configuration data. Table 34 shows the complete set of CPU and
controller init ializat ion data.
12.4.3
In-Circuit
Program ming of the
Serial Mode EEPROM
The Seri al Mode EEPROM cann ot be wri tten u nder CPU cont rol. However, with appr o-
priate external circuitry, in-circuit programming of the EEPROM can be accomplished
when th e VccOk signal is Lo w. At that time, the co ntrol ler i s in r ese t with i ts PROM_SD
bidirectional signal tri-stated and its PROM_CLK output driven Low. To program the
Table 34: Serial Initialization Data Stream
Bit Function
Defa ult Value
Generated By
Controller When No
Serial Mode EEPROM
Is Present
Restrictions
Enf orce d By
Controller aDescription
0
reserved
, Must be 0. 0
none
First bit shifted out of Seri al Mode EEPROM.
4:1 XmitDatPat 0 (DDDD) Bits 4:3 forced to 0 See Section 5.3 o f the
VR5000 Bus Interface
User’s Manual,
7:5 SysCkRatio 0 (multiply by 2)
none
Se e S ec tion 5.3 of the
VR5000 Bus Interface
User’s Manual,
8 EndBit 0 (little-endian)
none
Se e S ec tion 5.3 of the
VR5000 Bus Inter face
User’s Manual,
10:9 Non-Block Write 2 (pipelin ed wr ite s ) For c ed to 2 See Sect ion 5.3 of t he
VR5000 Bus Inter face
User’s Manual,
11 TmrIntEn 0 (timer interrupt
enabled)
none
Se e S ec tion 5.3 of the
VR5000 Bus Interface
User’s Manual,
12 Secondary Cache Enable 0 (secondary cache
disabled)
none
Se e S ec tion 5.3 of the
VR5000 Bus Interface
User’s Manual,
14: 13 DrvOut 2 (100%)
none
Se e S ec tion 5.3 of the
VR5000 Bus Inter face
User’s Manual,
15
reserved
, Must be 0. 0
none
Se e S ec tion 5.3 of the
VR5000 Bus Inter face
User’s Manual,
17:16 Se c ondary Cac he Siz e 0 (5 12K byte )
none
Se e S ec tion 5.3 of the
VR5000 Bus Interface
User’s Manual,
255:18
reserved
, Must be 0. 0
none
Se e S ec tion 5.3 of the
VR5000 Bus Inter face
User’s Manual,
256 Controller Boot ROM
Location 0 if PCI64# negated
1 if PCI64# asserted
none
0 = Local Bus
1 = Memory Bus
See description of MEM/LOC bit in PDAR
(Section 5.4).
258:25 7 Contr oller B oot ROM S iz e 0 (8 b its)
none
0 = 8 bits
1 = 16 bits
2 = 32 bits
3 = 64 bits
Se e descript ion of WI DTH fie ld in PDAR (Section
5.4).
260:25 9 Contr oller P CI Cloc k Sp eed 0
none
See description of CLKSEL fi eld in PCICTRL
(Section 7.11.1).
276:261 Controller PCI SSVID 0
none
See description of SSVID regi st er (Section
7.13.11).
292:27 7 Contr oller P CI SSID 0
none
See description of SSID regi st er (Section
7.13.12).
a. If a Seri al Mode EEPROM is present, the controller monitors and if necessary corrects the values o f certain parameters.
This funct ion ensures that the CP U-controller interface operates as int ended.
EEPROM in-circuit, hold VccOk Low, OR the external EEPROM clock with
PROM_CLK from the controller, and drive the data into the EEPROM. Drive the exter-
nal EEPROM cl ock Low upon comp letion, and tri-state the external data source. Al ter-
nati vely, jumpe rs can be used to conne ct PROM_SD, PROM_CLK, and t he BigEndi an
chip-select for this in-circui t programming configuration.
When the controller is the Main Controller in a multi-controller configuration (Section
5.3. 1), i t is the onl y con trol ler that can d rive PROM_CLK; th e other control lers tri -stat e.
Theref ore, a third technique of in-circuit progr amming is to h old VccOk Low t o th is Main
Controller and tempor arily drive its UART_TxDRDY# or UAR T_DTR# input High. By
doing this, the c ontroll er thinks it i s not the Main Co ntr oller, and both PROM_CLK and
PROM_SD are tri-s tate. Ext ernal circui try can then drive thes e signals such tha t i n-ci r-
cuit EEPROM programming can proceed.
13.0 Endian-Mode Software Issues
13.1
Overview The native endian mode f or MIPS processors , l ike Motorola and IBM 370 proce ssors,
is
big-endian
. However, the nati ve m ode for Intel (which developed the PCI stand ard)
and VAX processors is
little-endian
. For PCI-compatibilit
y
reasons, most PCI peri ph-
eral chips, includin
g
the VRC5074 controll er, operate nativel
y
in
little-endian
mode.
While the VRC5074 controller is nativ el
y
little-endian, it supp ort s either bi
g
- or little-
endian mode on the CPU interface. The state of the Bi
g
Endian si
g
nal at reset or the
Bi
g
Endian ( BE) bit of the Seria l Mode EEPROM initi aliz ation se quence (Sec tion 12. 0)
deter mines thi s endian mode. However , there are impor tan t consider ations when usin
g
the cont roller i n a m ixed-en dian de si
g
n. The most important aspect of the endian issue
is which b
y
te lanes of the S
y
sAD bus are act ivated for a par ti cular address.
If the bi
g
-endian mode is implemented for the CPU interface, the controller swaps
b
y
tes wit hin words and halfwords that are comin
g
in and
g
oin
g
out on the S
y
sAD bu s.
All of t he controller’s oth er i nterface s operate in little-endian mode. The re are a number
of impl ications associat ed with this:
Data in memor
y
is al w a
y
s ordered in little-endian mode, even with a bi
g
-endian
CPU interface.
Litt le-end ian bit -field s and other data s truct ure s that spa n two or more b
y
tes (such
as bit- fi elds withi n re
g
isters or FIFOs) are fra
g
men ted when t he CPU interface is
bi
g
-endian. The content s of t hese data structures are b
y
te-swizzled, so that the
bits are arran
g
ed [7:0] , [15:8], [23: 16], [31:24], [39 :32] , [47:40], [55:48 ], [63:56],
rather than [63:0].
Bi
g
-endian devices on the PCI Local Bus or the I/O Local Bus must be b
y
te-
swapped external to th e contr oller.
The sections below vi ew the endian issue from a pro
g
ramme r’s perspect ive. The
y
descr ibe how to i mplement mixed- endian desi
g
ns and how to make code endian-inde-
pendent.
13.2
Endia n Modes The endian mode of a device refers to its word-addressin
g
method and b
y
te order:
Big-Endian
devices address data items at the
big end
(most- si
g
nifi cant bit
number). The most-si
g
nifi cant b
y
te (MSB) in an addressed data ite m is at th e
lowest
address.
Little-Endian
devices address data items at the
little en d
(l east-si
g
nificant bit
number). The most-si
g
nifi cant b
y
te (MSB) in an addressed data ite m is at th e
highest
address.
Fi
g
ure 20 shows the bit and b
y
te order of t he two e ndian modes , as it applies to b
y
tes
within word-sized data items. The
bit orde r
within b
y
tes is the same for both modes.
The bi
g
(most-si
g
nificant) bit is on the left side, and the litt le (least-si
g
nifi cant) bit is on
the ri
g
ht side. Onl
y
the
bit ord er
of sub-i tems is reversed within a lar
g
er addressable
data item (half word, word, doubl eword, quadword) when crossin
g
between the t wo
endia n modes . The s ub- items’
order of si gni fic ance
within the lar
g
er d ata item r emai ns
the same. For example, the least- si
g
nificant halfword (LSHW) in a word is alwa
y
s to
the ri
g
ht and the most-si
g
nificant halfword (MSHW) is to th e lef t.
Figure 20: Bit and Byte Order of Endian Modes
If t he access type matches the data-i tem type, no swapping of data sub-items is nec-
essar y. Thus, when making hal fword acc esses into a dat a array consist ing of h alfwor d
data (Fi gure 21), no byte-swapping takes pla ce. In this case, data-item
bit or der
is
reta ined bet ween t he two endi an mod es. The co de t hat sequen tial ly acce sses the hal f-
word data array would be identical r egardless of t he endian protocol of its CPU. The
code would be endian-independent.
Figure 21: Halfword Data-Array Exampl e
Byte 0
MSB
Byte 1 Byte 2 Byte 3
LSB
Big-Endian
31 024 23 16 15 8 7
Byte 4 Byte 5 Byte 6 Byte 7
Word
Address 0
4
Byte 3
MSB
Byte 2 Byte 1 Byte 0
LSB
Little-Endian
31 024 23 16 15 8 7
Byte 7 Byte 6 Byte 5 Byte 4
0
4
Big End Little End
MSB = Most-Sign ifican t Byte
LSB = Least - Significant Byt e
Word
Address
A B C D
E F G H
I J K L
M N O P
HW3
HW2
HW1
HW0
A B C D
E F G H
I J K L
M N O P
HW3
HW2
HW1
HW0
Big-Endian Little-Endian
A B C D
E F G H
I J K L
M N O P
A B C D
E F G H
I J K L
M N O P
MSHW
LSHW
MSHW
LSHW MSHW
MSHW
LSHW
LSHW
A B C D E F G H
I J K L M N O P E F G H A B C D
M N O P I J K L
Halfword
addresses
need to be
reversed to
maintain
pro per or der.
Order
Lost
Order
Retained
Data extraction
usi ng s equential
word accesses
Data extraction
usi ng s equential
halfword accesses
Halfword
Data Array
However, when makin g half word access es int o a data array consi sting of word dat a
(Figure 22), access to the
more-significant
halfword requir es the address correspond-
ing to the
less-significant
halfwor d (and vice versa). Such code is not endian-indepen-
dent. A supergroup access (e.g. accessing two halfwords simultaneously as a word
from a hal fword data ar ray ) causes the sa me pro blem. Suc h pr oblem s also arise when
a halfword access is made into a 32-bit I/ O register, whereas a word access int o a 32-
bit register create s no probl em .
Figure 22: Word Data-Array Example
13.3
LAN Con tr o ller
Exam
p
le
The AMD AM79C791 LAN controller is one example of how a PCI-Bus device that is
natively little- endian adapts to mixed-endian enviro nm ents. This LAN controller pro -
vides l imited supp ort f or big -endian sys tem int erf aces. Its de si gners ass umed on ly two
data types: a 32-bit word corresponding to the width of I/O register s, and an 8-bit byte
corresponding to the width of the Ethernet DMA FIFO.
13.3.1
DMA Accesses from
Ethernet FIFO
Ethernet data packets consist of bytes. To maximize bus bandwidth, these bytes are
transfe rred via 32-bit word DMA accesses into memory. This acces s-data mismatch
corresponds to the supergroup scenario shown at the bottom of Figure 21. The mis-
match me ans that a byte-s wa p mus t be performed to allow the little-endian LAN con-
trol ler to access the big-en dian memory. The LAN controller provi des its own inte rnal
hardware for this byt e-swap.
13.3.2
Wor d Accesses to I/O
Registers
The LA N c ontrol ler’s de signer s assu med that th e 32-bit inter nal I/O r egist ers wo uld be
accessed by 32-bit word transfers. In that cas e, t he access type and da ta t ype matc h,
and no swapping of bytes or halfwords is needed because order of si gnificance is th e
same for both en dia n modes . For such wor d t ransf ers, the I/O r egist er m odel i s endi an-
A B C D E F G H
I J K L M N O P
W1
W0
Big-Endian
A B C D E F G H
I J K L M N O P
W1
W0
Little-Endian
A B C D
E F G H
I J K L
M N O P
E F G H
A B C D
M N O P
I J K L
A B C D E F G H
I J K L M N O P A B C D E F G H
I J K L M N O P
LSHW
MSHWLSHW
MSHW
Halfword
addresses
need to be
reversed to
maintain
proper order.
Order
Retained
Order
Lost
Data extraction
usin g s equent ial
word accesses
Data ext r ac tion
using sequential
halfword accesses
W ord
Data Array
independent, and the LAN control ler’s design ers di d not provide in ternal swapping
hardware for non-word accesses into the I/O registers.
Wo rd a ccesses offer the advantage that the register address values documented in the
AM79C97 1 Technical Manual can be us ed wi thout c hange (although of fset s for i ndivi d-
ual regist er f ields suc h as the PCI Latency Timer must be i gnor ed). Th e posit ion of indi -
vidual regis ter fields as well as byte posi tion wit hin these fie lds would also re ma in t he
same as documented in the Technical Manual.
13.3.3
Byte or Halfword
Accesses to I/O
Registers
Word accesses can cause some i nconvenience (e.g. shadow register s) when modify-
ing onl y one or two fields with in a 32-bit PCI register. In this case, byte or halfwor d
access to the 32-bit register may be simpler. This type of transfer is analogous to the
halfword access i nto a data array consisting of word data types, shown in Figure 22.
Such acces ses are mismatched to the defined da ta t ype and must be
cross-addressed
to get the byte or half word o f interes t. The AM 79C791 LAN cont roll er does not prov ide
big-endian hardware support to deal with byt e or halfword tr ansfers int o the I/O regis-
ters . Code wr itt en to pe rf orm byt e or half word acces ses into the 32- bi t I/ O regist ers wi ll
not be endian-independent.
The I/O register-field addresses docum ented in the AM79C971 Technical Manual are
based on a register model deriv ed from a litt le- endian perspective. The number order
of these addresses progresses from right (least -signif icant) to lef t. However, a b ig-
endia n system will respond to all address es as if t he number order progr esses from le ft
(mo st-signi fica nt) to right . To access the desired byte or halfword, the address order
docum ented in the Technical Manual must be reversed.
The fi elds o f the PCI St atus Regi ster and PCI Com mand Reg ister ar e t wo examples of
frequently used I/O register fields. The address offsets documented in the Technical
Manua l are 0x06 and 0x04, re spectivel y . The PCI Command Regi ster field i s located in
the l ess-si gnif icant halfwor d of t he 32- bit I /O regi ster that i s als o locat ed at off set 0x 04.
The PCI Command Register field shares t he same offset wi th its 32-bi t re gister
because of the littl e-endi an n umber orde r . In a b ig-endi an system , the more- signi fica nt
halfword (i.e. PCI Status Regi ster fiel d) woul d share the same offset value with it s 32-
bit register. So, i f the of fset 0x04 is used to access the PCI Comm and Regi ster fi eld, a
big-endian system would actually access the PCI Status Register field. To access the
proper halfwor d, the of fset s must be exchanged bet ween t he two 16-bi t regi ster fiel ds.
In other words th ere must be a re versal (or swapping) of number order, relative to the
information document ed in the Technical Manual.
These special addressing considerat ions are comp letely ind ependent of the operand
point ers associ ated wit h the CPU regist er used as sourc e or destination. The source or
desti nati on withi n the CPU’s re gister fil e can be at any locat ion, s ize, o r ali gnment wit h-
out altering the transfer results. A common error is to byte-swap CPU register data
when tr ansferring a halfword t o or from a 32-bi t r egister . The or der of significance is the
same for bot h endian modes, so no byt e-swa p is neede d. This is pure ly an addr ess ing
probl em.
Table 35 and Table 36 show how the offsets in the AM79C971 Technical Manual are
swapped with the other offset s to produ ce the proper cross-addressed offset required
by big- endian syst ems. The determini ng facto rs fo r the swap are the values of the two
least-significant bits of the offsets. Accordi ng to the AM 79C971 Technical Manual, the
PCI Command Register field has the offset 0x04. Table 36 shows that the offset 0x06
is needed to access t he PCI Comm and Register field. The tw o least-si gnificant bits of
0x04 are b00, which conver t to b10 to give the r esult of 0x06h.
13.4
GUI Controller
Example
The Cirr us Logic CL-GD54 65 GUI controll er is another example of a PCI-Bus device
that offers some m ixed-endian support. The designers of this GUI controll er assu med
thre e data typ es: 3 2-bit word, 16- bit hal fword, and 8-bit byte. Unlike t he LAN contr oller
which could make certain assumpti ons as to data type (for I/O register or DMA FIFO
access es), the GUI ha rdware c annot det er mine what data t ype will be used during any
particula r data transfer; any data ty pe m ight be involved in an y I/O register or RDRAM
access.
The data type must be known for a gi ven bus tr ansfer so that the appropriate byt e or
halfword swap can be performed. The data types may change from bus cycle to the
next; one softwar e task may be o perati ng in p arall el wit h an d independ ently of anot her
software task. One of the easiest methods to accommodate such an environm ent,
with out semaphor es and s uch, is to provi de add ress aper tures i nto the memory spa ce.
The aperture scheme calls for GUI har dware resources to be mirror ed int o three
addres s r anges. Depen ding o n whi ch add res s range se lected , a s pecif ic dat a type and
data swap is used. Chapter 13 of the CL-GD5465 Techni cal Manual gives details of
these three apertures.
13.4.1
Wor d Accesses to I/O
Registers
The GUI controller’s internal 32-bit I/O registers can be accessed with 32-bit word
transfers. In this case, the access type and data t ype match; no swapping of bytes or
halfwords is re quired because th e order of signi fi cance is the same for both endian
modes . With such wor d t ransfers, t he I/O r egist er model is en dia n-indep endent, so the
fir st address aperture described in the CL-GD5465 Technical Ma nual is used.
Wo rd accesses have the advantage that the register address values docum ented in
the Technical Manual can be used without change (alt hough offsets for ind ivi dual reg-
ist er fiel ds such as the PCI Latency Timer must be ignored). The position of individu al
register fields as well as byt e position withi n these fiel ds also remains the same as
shown in the Technical Manual.
Table 35: Cro ss-Addr essing for Byte Accesses Into a 32-bit I/O Register
Least-Significant Bits of Offse t
From AM79C971 Technical Manual Least-Significant Bits of Offse t
Required by Big-Endian System
b00 b11
b01 b10
b10 b01
b11 b00
Table 36: Cro ss-Addressing for Halfword Accesses into a 32-bit I/ O Register
Least-Significant Bits of Offse t
From AM79C971 Technical Manual Least-Significant Bits of Offse t
Required by Big-Endian System
b00 b10
b10 b00
13.4.2
Byte or Halfword
Accesses to I/O
Registers
As in the LAN- controll er example, b
y
te or halfword access ma
y
be simpler than word
access es when mo dif
y
in
g
onl
y
one or two fields within a 32- bit I/O re
g
ister . This t
y
pe of
transfer is analo
g
ous to the hal fword access int o a data arra
y
consistin
g
of word data
t
y
pes, shown in Fi
g
ure 22. Such accesses are mismatched to the defined data t
y
pe
and must be swapped to
g
et the b
y
te or halfword of interest. Code written t o perform
b
y
te or hal fword ac cess es into t he 32 -bit wo rd I/O r e
g
ist ers wil l not be e ndi an-inde pen-
dent.
There are two methods to perform b
y
te or halfword accesses into the GUI controller.
The first method is the use of the apertures for halfword-swap (second aperture) and
b
y
te-swap (third aperture). This method has the advanta
g
e that th e li ttle-endian
addresses documented in the Technical Manual are the same as those used b
y
bi
g
-
endian code, except for the addition of the offset required to select the appropriate
aperture. (As of this printin
g
, the second aperture remains unverified and has
g
ener-
ated some confusion resulti n
g
from poor documentation or improper implement ation.)
The second m ethod of perfor m in
g
b
y
te or halfword accesses is to
cross-address
the
transfer. Care must be taken, however, when referencin
g
the CL-GD5465 Technical
Manual. The I/O re
g
ister field addresses documented in the Technical Manual are
based on a little-endian re
g
ist er mode l. The numb er o rder of th ese addresses pr o
g
ress
from ri
g
ht (least-si
g
nificant) to left. However, bi
g
-endi an s
y
stems respond to addre sses
as if t he number order pro
g
resses from left (most-si
g
nificant) to ri
g
ht. To access the
desir ed b
y
te or hal fword, the addr ess order docu mented in t he Techni cal Manual must
be reversed.
13.4.3
Accesses to RD RAM The CL-GD5465 G UI controll er’ s int ernal pixel and video en
g
ines constrai n the
RDRAM to be little-endian. Here a
g
ain, bi
g
-endian s
y
stems have a few problems
accessin
g
data sub
g
roups, such as a sin
g
le b
y
te access into a 32-bit data t
y
pe. Sub-
item accesses are also a factor for RDRAM and the cross-addressin
g
and address
apertures solutions are the same as those descri bed in Section 13.4.2. Super
g
roup
access are also enc ountered with RDRAM. T his si tuation i s menti oned in Sec tion 1 3.2
and sh own i n Fi
g
ure 22. A specif ic GUI -or iente d exam ple of thi s wou ld be an 8 -bit data
t
y
pe, such as a pixel, which is t ransferred four-a t-a-ti me to max imize PCI-Bus band-
width.
There ar e two method s for de alin
g
with supe r
g
roup tr ansfers. First is the address-ape r-
ture method, used in the sub-item scenario of Sec ti on 13.4.2. The thi rd aper ture, b
y
te-
swap, i s used t o pr ovide t he prope r da ta swap f or the f our 8- bit pi xel c ase. The second
aperture, hal fword-swap, is used to transfer such thi n
g
s as two 16-bit pixel s simulta-
neousl
y
.
The second aperture m ethod requir es that the data or der i n the CPU re
g
ist er be
swapped prior to an RDRAM write access, or immediatel
y
after an RDRAM read
access. To continue wit h the previous four-pi xel transf er example, the b
y
te number-
order of the four pixels in the CPU re
g
ist er would be reversed. Now t he pixel numb er-
order increases, startin
g
from the ri
g
ht side of t h e r e
g
ister (fi rst pixel ori
g
inall
y
on left,
now o n ri
g
ht). Then, the four pixels are written i nto the RDRAM with a s tandard 32-bi t
word transfer (first aperture). The case of two 16-bit pixels requires the two halfwords
to be swapped, but not the or der of the two b
y
tes inside the halfwords. This second
method is probabl
y
more time-consumin
g
and is not recommended.
14.0 Timing Diagrams
This secti on sh ows ti ming diagrams for t he c ontroll er’s var ious op erat ions on the m em-
ory bus and PCI Bus. The followin g notation is used:
A or An
mea ns Address or sequential Address number
D or Dn
mean s Data or sequential Data-item number
14.1
CPU Accesses to
Loca l Memor
y
Figur e 23 thr ough F igure 32 show the t i ming for CPU accesses to t he cont roll er’ s loc al
memory, including:
CPU Single-Byte Memory Read (Figure 23)
CPU Single-Byte Memory Write (Figure 24)
CPU Eight-Byte Mem ory Read ( Figure 25)
CPU Eight-Byte Mem ory Write (Figure 26)
CPU Block (32-Byte) Memor y Read (Fi gure 27)
CPU Block (32-Byte) Memory Write (Figure 28)
CPU Back-To-Back Eight-Byte Memory Read (Figure 29)
CPU Back-To-Back Eight-Byte Memory Write (Figure 30)
CPU Back-To-Back Block (32-Byte) Memory Read (Figure 31)
CPU Back-To-Back Block (32-Byte) Memory Wr ite (Figure 32)
All SDRAM accesses are full-dword (64 bit) accesses. The controller internally imple-
ments partial -dword (less than 64-bit) write requ ests as read-m erge-writes: it first
reads from the write address, then merges the partial- dword write data int o the re ad
data, then writes the full dword to memory. Because of this, partial-dword writes take
longer than full-dword writes.
Figure 23: Singl e-Byte Memory Read
Figure 24: Single-Byte Memory Write
Figure 25: Eight-Byte Memory Read
Figure 26: Eight-Byte Memor y W rite
Figure 27: Block Memo ry Read
Figure 28: Block Memo ry Writ e
Figure 29: Back-To-Back Eight-Byte Memory Reads
Figure 30: Back-To-Back Eight-Byte Memory W rites
Figure 31: Back-To-Back Block Memory Reads
Figure 32: Back-To-Back Block Memory Writes
14.2
PCI-Bus Accesses Fi
g
ure 33 thr ou
g
h Fi
g
ure 39 show the timin
g
for various transactions on the PCI Bus,
includin
g
:
Control ler as PCI-Bus Master
• PCI Memor
y
Write/Read (Fi
g
ure 33)
• PCI Memor
y
B
y
te Writes, With B
y
te-Mer
g
in
g
(Fi
g
ure 34)
• PCI Memor
y
B
y
te Read, With Prefetchin
g
(Fi
g
ure 35)
• PCI Memor
y
Ei
g
ht-B
y
te Writes, With Combinin
g
(F i
g
ure 36)
• PCI Memor
y
Dual Address C
y
cl e (D A C) Wr ite /Re ad (F i
g
ure 37)
Controller as PCI-Bus Tar
g
et
• PCI-Bus Master Read/Write to Controller Memor
y
(Fi
g
ure 38)
• PCI-Bus Master Read/Write to Controller’s Internal Re
g
is te rs (Fi
g
ure 39)
All ti m in
g
examples use a 33 MHz PCI-Bus cloc k and Medium tar
g
et DEVSEL.
Figure 33: PCI Memory W ri te/Read
Figure 34: PCI Memory Byte Writes, With Byte-Merging
Figure 35: PCI Memory Byte Read, With Prefetchi ng
Figure 36: PCI Memory Eight-Byte Writes, With Combining
Figure 37: PCI Memory Dual Address Cycle (DAC) Write/Read
Figure 38: PCI-Bus Master Read/Writ e to Controller Memory
Figure 39: PCI-Bus Master Read/Wr ite to Controller’s Inter nal Regi sters
14.3
Local-Bus Accesses Fi
g
ure 40 t hrou
g
h Fi
g
ure 47 show the t imin
g
for vari ous tr ansac tions on the Local Bus,
includin
g
:
Control ler as Local- B us M aster
•CPU B
y
te W ri te/Read to 8-Bi t Local-Bus Tar
g
et (Fi
g
ure 40)
• CPU Four-B
y
te Write/Re ad to 8-Bit Local-Bus Tar
g
et (Fi
g
ure 41)
• CPU Ei
g
ht-B
y
te Write/Read to 8-Bit Local-Bus Tar
g
et (Fi
g
ure 42)
• CPU Burst Write/Re ad to 32- Bit Local-Bus Tar
g
et (Fi
g
ure 43)
Control ler as Local- B us Tar
g
et
• Local-Bus Master Four-B
y
te Write/Read to Controller Memor
y
, 68000 Mode
(Fi
g
ure 44)
• Local-Bus Master Burst Write/Read to Controller Memor
y
, 68000 Mode
(Fi
g
ure 45)
• Local-Bus Master Four-B
y
te Write/Read to Controller Memor
y
, Inte l Mode
(Fi
g
ure 46)
• Local-Bus Master Burst Write/Read to Controller Memor
y
, Inte l Mode (Fi
g
ure
47)
Figure 40: CPU Byte Writ e/Read to 8-Bit Local-Bus Target
Figure 41: CPU Four-Byt e W rite/Read to 8-Bit Local-Bus Target
Figure 42: CPU Eight-Byte Write/Read to 8-Bit Local-Bus Tar get
Figure 43: CPU Burst W rite/Read t o 32-Bit Local-Bus Targ et
Figure 44: Local-Bus Maste r Four-Byte Wr ite/Read to Contr oller Memory, 68000 Mode
Figure 45: Local-Bus Maste r Burst Wri te/Read to Control ler Memory, 68000 Mode
Figure 46: Local-Bus Maste r Four-Byte Wr ite/Read to Contr oller Memory, Int el Mode
Figure 47: Local-Bus Maste r Burst Wri te/Read to Control ler Memory, Intel Mode
15.0 Testing
The controller does not suppor t JTAG tes ti ng or any other type of boundary scan . It
does, h owever , support bo ard-level testing. Table 37 shows the board-level tes t modes
that can be configured with the TEST#, SMC and TEST_SEL inputs.
In the
Wi ggle Mod e
, the BigEndian signal beco me s an o utput and al l other signals are
inputs. Bi gEndian is driven by the XOR of all other signals. This mode can be used by
a board tester to ver ify connectivity to all con troller signals.
Table 37: Test-Mode Conf iguration
TEST# SMC TEST_SEL Description
0 0 0 All Outputs Tri-State
001
unused, reserved
010
unused, reserved
011
unused, reserved
1 0 0 Normal Operation
1 0 1 Normal Operation, with PLL by-passed
110
unused, reserved
1 1 1 Wiggle Mode
16.0 Electrical Specifications
16.1
Terminolo
gy
Table 38: Terminol ogy for Absolute Maximum Ratings
Item Symbol Meaning
Power supply voltage VDD Range of v oltag es which will not c aus e destruct ion or re duc e reliabil ity
when applied to the VDD pin.
Input v oltag e VIRange of voltages which will not c aus e destruct ion or re duc e reliabil ity
when applied to the input pin.
Output voltage VORange of v oltages which will not c aus e destruct ion or re duc e reliabil ity
when applied to the output pin.
Input current IIAllowable absolute value of current which will not cause latchup when
applied to the input pin.
Output current IOAllowable absolu te value of DC cu r r ent whic h will not c aus e dest r uc tion
or reduce reliabi lity when flowing to or from the output pin .
Operatin g am bient
temperature TARange of am bient temperatur es for norm al logi c al operation.
Storage temperature Tst
g
Range of ele m ent tem per atur es which will not c aus e destruct ion or
redu c e r eliabil ity in the st ate wher e neither v olt age no r c ur r ent is applied.
Table 39: Terminol ogy for Recommended Operating Condit ions
Item Symbol Meaning
Power supply voltage VDD Range of a v oltag e for norm al logi c al operation when VSS = 0 V.
Input voltage, high VIH Indicates a high-level voltage applied to the cell-based IC input that
allows nor ma l op eratio n of the inp ut bu ffer. App lyin g a voltag e of the Min.
valu e or above ens ures that the input voltage is at hig h lev el.
Input voltage, low VIL Indica te s a low- lev el v oltag e a pplied t o the cel l-ba sed IC i npu t th at al low s
norma l op eratio n of the in put buf fer . Appl ying a volt ag e of th e Max. val ue
or bel ow ensur es that th e input vo ltage is at low leve l.
Positive trigger
voltage VPRefers to the input leve l at which the output level is inver te d when the cell-
base d IC inpu t is c hanged from low- level to high- level.
Negative t r igger
voltage VNRefers to the input leve l at which the output level is inver te d when the cell-
based IC input is changed from high- level to low-level.
Hysteresis voltage VHRefers t o th e differe nce betw een the positive trigger volta ge and neg ative
trigger voltage.
Input rise time tri Indicates the limit value of the time in which the input voltage applied to
the cell-based IC rises from 10% to 90%.
Input fall tim e tfi Indicates the limit value of the time in which the input voltage applied to
the cell-based IC input falls from 90% to 10%.
Table 40: Terminology for DC Characteristics
Item Symbol Meaning
Static current
consumption IDDS In dica tes t he curre nt tha t fl ows in from th e p ower su pply pi n at a spe cif ied
supp ly v oltag e with out chan ging th e v oltage of the input and output pins.
O f f- s tat e outp ut
current IOZ For a 3-state ou tp ut, this valu e indicates the current that flows throug h the
output pin at specif ied voltag e when the outpu t is at high im pedance.
Output short-circuit
current IOS Curre nt that fl ows out when th e output p in is short-circuited to G ND, when
output is at high level.
16.2
Absolute Maxim u m
Ratings
16.3
Recommende d
Operating Range
Input leakage current IICurrent that f lows through the inpu t pin whe n a v oltage is applied to the
input pin.
Output current, low IOL Curre nt that flows t o the outpu t p in at a specif i ed low- lev el out put v olta ge.
Output current, high IOH Cur r ent that flows from t he outp ut pin at a spec ifi ed high- level output
voltage.
Output voltage, low VOL Indicates a low-level output voltage when output is open.
Output voltage, high VOH Indicates a high-level output voltage when output pin is open.
Table 40: Terminology for DC Characteristics (continued)
Item Symbol Meaning
Table 41: Absolute Maximum Ratings
Item Symbol Conditions Ratings Unit
Power supply voltage VDD –0. 5 to +4.6 V
Input voltage a
a. Apply voltage to the input pins only after the power supply voltage has bee n applied.
VIVI < VDD + 0.5 V –0.5 to +4.6 V
Output voltage VOVO < VDD+ 0.5 V –0.5 to +4. 6 V
Output current: IO
IOL = 1.0 mA FV0A 3 mA
IOL = 2.0 mA FV0B 7 mA
IOL = 3.0 mA FO09 , F V 09 10 mA
IOL = 6.0 mA FO04 , F V 04 20 mA
IOL = 9.0 mA FV01, FV0 1 30 mA
IOL = 12.0 mA FO02 , F V 02 40 mA
IOL = 18.0 mA FO03 60 mA
IOL = 24.0 mA FO06 75 mA
Operatin g am bient temperatu r e TA–40 to +85 °C
Storage temperature Tst
g
–65 to +150 °C
Table 42: Recommended Operating Range
Item Symbol Conditions Min. Typical Max. Unit
Power supply voltage VDD 3.0 3.3 3.6 V
Input voltage, high VIH 3V inter fa ce 2 .0 VDD V
Input voltage, low VIL 00.8V
Positive trigger vol tage VP1.50 2.70 V
Negative t r igger voltag e VN0.60 1.40 V
Hysteresis voltage VH1.10 1.50 V
Input voltage, high VIH 5V inter fa ce 2 .0 5.5 V
Input voltage, low VIL 00.8V
Positive trigger vol tage VP2.20 2.55 V
Negative t r igger voltag e VN0.84 1.01 V
Hysteresis voltage VH1.36 1.54 V
16.4
DC Characteris ti cs The “+” and “–” next to the cur rent val ue in the table indicate the curr ent direction. Cur-
rent flowin
g
into the device is “+” and curr ent flo wi n
g
out of the dev ice is “ –”. Structur-
all
y
, the CMOS 5V output buffer has no DC output Hi
g
h level.
Input rise time tri Normal input 0 200 ns
Input fall tim e tfi 0 200 ns
Input rise time tri Schmitt input a010ms
Input fall tim e tfi 010ms
a. Use a Schmitt trigger input bu ff er for input si gnals with very slow rise or fall time s.
Table 42: Recommended Operating Range (continued)
Item Symbol Conditions Min. Typical Max. Unit
Table 43: DC Characteristic s
VDD = 3.3V ± 0.3V; TA = –40 to +85°C; Tj = –40 to +125°C
Item Symbol Conditions Min. Typical Max. Unit
Static current consumption: a
H49-M97 IDDS VI = VDD or GND — 40 800 µA
E80-H10 IDDS — 20 400 µA
Step sizes othe r than the
above IDDS — 10 200 µA
OFF-state output curren t IOZ VO = VDD or GND — — ± 10 µA
Output short-circuit current b IOS VO = GND — — –250 mA
Input leakage current:
Normal inp ut IIVI = VDD or G N D — ±10–4 ±10 µA
With pull-up resistor (50 kΩ)I
IVI = GND 36 89 165 µA
With pull-up resistor (5 kΩ)I
IVI = GND 284 654 1305 µA
With pull-down resistor (50
kΩ)IIVI = VDD 28 79 141 µA
Pull-up resistor (50 kΩ)R
PU — 21.8 37.1 83.1 kΩ
Pull-up resistor (5 kΩ)R
PU —2.85.010.6kΩ
Pull-down resistor (50 kΩ)R
PD — 25.6 41.9 105.8 kΩ
Output current low:
3.0 mA type FO09 IOL VOL= 0.4 V 3.00 — — mA
6.0 mA type FO04 IOL VOL= 0.4 V 6.00 — — mA
9.0 mA type FO01 IOL VOL= 0.4 V 9.00 — — mA
12.0 mA type FO02 IOL VOL= 0.4 V 12.00 — — mA
18.0 mA type FO03 IOL VOL= 0.4 V 18.00 — — mA
24.0 mA type FO06 IOL VOL= 0.4 V 24.00 — — mA
Output current high:
3.0 mA type FO09 IOH VOH = 2.4 V –3.00 — — mA
6.0 mA type FO04 IOH VOH = 2.4 V –6.00 — — mA
9.0 mA type FO01 IOH VOH = 2.4 V –9.00 — — mA
12.0 mA type FO02 IOH VOH = 2.4 V –12.00 — — mA
18.0 mA type FO03 IOH VOH = 2.4 V –18.00 — — mA
16.5
AC Specifi cations
16.5.1
Clock Timing Table 44 shows the timin
g
requir em ents for S
y
sClock wit h and wit hout L2 cache, and
for PCLK[ 0] wi th an i nter nal and an external arbiter.
16.5.2
CPU, Memor y, Local
Bus and Interrupt
Signals
Table 45 shows the timin
g
requirements, relati ve to S
y
sClock, for t he si
g
nals on the
CPU Bus, Memor
y
Bus, Local-Bus, and the in terrupt si
g
nals (both CPU and PCI inter-
rupt si
g
nals). Fi
g
ure 48 defi nes the setup, hold, and val id parameters.
Figure 48: AC Timing Waveforms
24.0 mA type FO06 IOH VOH = 2.4 V –24.00 — — mA
Output voltage low VOL IOL = 0 mA — — 0.1 V
Output voltage high VOH IOH = 0 mA VDD - 0.1 — — V
a. The static current consumption increases if an I/O block with a pull-up or pull-down
resistor is used.
b. O utput short-circuit current is 1 second or less and only 1 pin of the chip.
Table 43: DC Characteristic s (continued)
VDD = 3.3V ± 0.3V; TA = –40 to +85°C; Tj = –40 to +125°C
Item Symbol Conditions Min. Typical Max. Unit
Table 44: SysClock and PCLK[0] Timing Requirem ents
Signal Min. Period Min. Low Max. High Units Notes
SysClock 11.6 5. 0 5.0 ns Without L2 ca c he
SysClock 13.5 5. 0 5.0 ns With L2 c ac he
PCLK[ 0] 15. 7 12.0 5.0 ns With external PCI ar biter
PCLK[ 0] 15. 7 5.0 5.0 ns With internal PCI ar bite r
Table 45: Signal Timing Relat ive to SysClock
Signal Output
Min. Valid Output
Max. Va lid Output
Pin Load Input
Min. Setup Input
Min. H old Units
BigEndian 7.5 17.8 50 — — ns
BootCS# 2.8 9.5 50 — — ns
CntrValid# 3.9 9.6 50 1.5 0.0 ns
CntrVccOk 5.9 13.2 50 — — ns
ColdReset# 5.7 13.4 50 — — ns
CPUVa li d # ———4.50.0ns
DCS#[8:2] 2.8 10.4 50 1.0 0.2 ns
DQM 2.8 6.7 80 — — ns
INTA# 2.2 7.8 50 1.3 0.0 ns
INTB# ———1.30.0ns
INTC# ———1.30.0ns
INTD# ———1.30.0ns
INTE# ———1.20.0ns
Int#[5:0] 4.2 11.2 50 — — ns
LOC_ A[4: 0] 2.3 8.4 50 5.2 0.0 ns
LOC_AD[31:0] 2.3 12.6 50 4.2 0.0 ns
LOC_ALE 2.3 14.2 50 4.4 0.0 ns
LOC_BG#
or
HLDA
3.4 9.5 50 — — ns
LOC_BGACK# ———3.00.0ns
LOC_BR#
or
HOLD
———3.30.0ns
LOC_CLK 2.2 5.6 50 — — ns
LOC_FR# 3.0 8.3 50 5.0 0.0 ns
LOC_RD# 3.0 8.3 50 3.5 0.0 ns
LOC_RDY# 2.8 8.0 50 10.7 0.0 ns
LOC_WR# 3.0 8.3 50 5.1 0.0 ns
MAbank0[14:0] 2.4 8.6 80 — — ns
MAbank1[14:0] 2.5 7.8 80 — — ns
MCAS#[1:0] 3.5 7.2 80 — — ns
MCS#[1:0] 3.5 7.3 80 — — ns
MCWrRdy# 3.6 8.3 50 — — ns
MD[63:0] 2.0 8.1 40 1.0 0.5 ns
MDC[7:0] 2.8 9.5 40 1.2 0.1 ns
ModeClock ———1.01.6ns
ModeOut 4.6 11.8 50 — — ns
MRAS#[1:0] 3.5 7.5 80 — — ns
MRDY# ———3.00.0ns
MWE#[1:0] 3.5 7.3 80 — — ns
NMI# 4.4 10.8 50 — — ns
PROM_CLK 5.2 11.9 50 — — ns
PROM_SD 4.8 10.2 40 1.0 1.2 ns
Reset# 5.9 13.4 50 — — ns
16.5.3
PCI-Bus Int erface Table 46 shows the timin
g
requir em ents, rela ti ve to PCLK[0], for si
g
nals on the PCI
Bus, except for the PCI interrupt si
g
nals which are inc luded in Table 45.
ScDOE# 3.3 9.1 50 — — ns
ScMatch ———1.00.2ns
ScWord[1:0] 2.3 9.1 50 1.0 0.1 ns
SysAD[63:0] 2.5 9.3 50 2.0 0.1 ns
SysADC[7:0] 1.9 9.5 50 1.3 0.1 ns
SysClock See Table 44 ns
SysCmd[8:0] 3.3 9.9 50 3.6 0.3 ns
UART_DSR#ns
UART_DTR# 5.0 11.8 50 1.0 1.1 ns
UART_RxDRDY# ns
UART_TxDRDY# 5.1 11.9 50 1.0 1.1 ns
VccOk ———1.90.0ns
WrRdy# 3.3 8.3 50 1.0 0.2 ns
Table 45: Signal Timing Relat ive to SysClock (continued)
Signal Output
Min. Valid Output
Max. Va lid Output
Pin Load Input
Min. Setup Input
Min. H old Units
Table 46: Signal Timing Relat ive to PCLK[0]
Signal Output
Min. Valid Output
Max. Va lid Output
Pin Load Input
Min. Setup Input
Min. H old Units
ACK64# 5.1 10.3 50 5.8 2.2 ns
C/BE#[7:0] 5.0 15.0 50 7.3 2.6 ns
DEVSEL# 5.0 9.9 50 8.4 2.4 ns
FRAME# 5.5 13.8 50 8.6 2.5 ns
GNT#[0] 5.2 9.3 50 10.6 2.5 ns
GNT#[4:1] 5.1 9.3 50 — — ns
IDSEL ———1.02.2ns
INT[E:A]# See Table 45 ns
IRDY# 5.2 12.5 50 8.6 2.3 ns
LOCK# TBD TBD TBD TBD TBD ns
M66EN Static s ignal . T ie High or Low per T able 3 ns
PCI_AD[63:0] 5.1 13.0 50 1.0 2.9 ns
PAR 5.0 9.2 50 1.0 2.3 ns
PAR64 5.0 9.4 50 1.4 2.0 ns
PCI64# S tatic s ignal . T ie High or Low per T able 3 ns
PCICR# S tatic s ignal . T ie High or Low per T able 3 ns
PCIRST# 5.9 11.8 50 2.1 2.5 ns
PCLK[0] See Table 44 ns
PERR# 4.8 9.0 50 1.0 2.4 ns
REQ#[0] 5.4 10.2 50 1.0 2.6 ns
REQ#[4:1] ———1.32.8ns
REQ64# 5.3 15.1 50 1.0 2.2 ns
SERR# 4.9 9.2 50 1.0 2.2 ns
STOP# 5.1 10.4 50 8.1 2.4 ns
TRDY# 5.0 10.5 50 8.5 2.3 ns
17.0 Pinout
The con tr oller i s packaged in a 500- pin TBGA p ackage. Table 47 s hows the pin a ssi gn-
ments, sorted by signal nam es (left si de), pin number (middle), and gri d number (rig ht
side). Figure 49 on page 210 shows the package diagram.
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
AGND 170 AJ28 1 NC A1 A1 NC 1
AGND 345 AD4 2 PCLK3 B1 A2 NC 116
AVDD 247 AE3 3 GND C1 A3 SysAD0 115
AVDD 458 AF25 4 GND D1 A4 SysAD3 114
BigEndian 171 AJ29 5 PCI_AD31 E1 A5 SysAD7 113
BootCS# 160 AJ18 6 PCI_AD28 F1 A6 SysAD10 112
C/BE#0 339 V4 7 REQ#3 G1 A7 SysAD13 111
C/BE#1 427 R5 8 REQ#2 H1 A8 SysAD18 110
C/BE#2 334 N4 9 C/BE#3 J1 A9 SysAD20 109
C/BE#3 9 J1 10 PCI_AD22 K1 A10 SysAD23 108
CntrValid# 223 B4 11 PCI_AD19 L1 A11 SysAD28 107
CntrVccOk 324 C4 12 PCI_AD16 M1 A12 SysAD31 106
ColdReset# 500 E6 13 FRAME# N1 A13 SysAD36 105
CPUValid# 224 B3 14 SERR# P1 A14 SysAD39 104
DCS #2 see Table
4 on page
27
156 AJ14 15 GND R1 A15 GND 103
DCS #3 see Table
4 on page
27
261 AH14 16 VDD T1 A16 SysAD47 102
DCS #4 see Table
4 on page
27
42 AK13 17 PCI_AD12 U1 A17 SysAD48 101
DCS #5 see Table
4 on page
27
155 AJ13 18 DEVSEL# V1 A18 SysAD51 100
DCS #6 see Table
4 on page
27
260 AH13 19 PCI_AD7 W1 A19 SysAD56 99
DCS #7 see Table
4 on page
27
357 AG13 20 PERR# Y1 A20 SysAD59 98
DCS #8 see Table
4 on page
27
41 AK12 21 PCI_AD1 AA1 A21 SysADC0 97
DEVSEL# 18 V1 22 LOC_AD30 PCI_AD62 AB1 A22 SysADC3 96
DQM 265 AH18 23 LOC_AD28 PCI_AD60 AC1 A23 SysADC5 95
FRAME# 13 N1 24 GND AD1 A24 SysCmd2 94
GND 3 C1 25 LOC_AD23 PCI_AD55 AE1 A25 SysCmd5 93
GND 4 D1 26 NC AF1 A26 SysCmd8 92
GND 15 R1 27 LOC_AD22 PCI_AD54 AG1 A27 ScMatch 91
GND 24 AD1 28 VDD AH1 A28 Int#1 90
GND 36 AK7 29 NC AJ1 A29 Int#5 89
GND 48 AK19 30 NC AK1 A30 NC 88
GND 53 AK24 31 LOC_AD14 PCI_AD46 AK2 AA1 PCI_AD1 21
GND 65 AD30 32 LOC_AD10 PCI_AD42 AK3 AA2 PCI_AD0 136
GND 103 A15 33 LOC_AD9 PCI_AD41 AK4 AA3 LOC_AD31 PCI_AD63 243
GND 146 AJ4 34 LOC_AD6 PCI_AD38 AK5 AA4 VDD 342
GND 167 AJ25 35 LOC_AD3 PCI_AD35 AK6 AA5 GND 433
GND 226 D3 36 GND AK7 AA26 GND 464
GND 244 AB3 37 LOC_A3 C/BE#7 AK8 AA27 VDD 377
GND 248 AF3 38 LOC_A1 C/BE#5 AK9 AA28 MDC4 282
GND 251 AH4 39 LOC_CLK ACK64# AK10 AA29 MDC3 179
GND 256 AH9 40 LOC_RDY# AK11 AA30 MDC2 68
GND 269 AH22 41 DCS#8 see Table
4 on page
27
AK12 AB1 LOC_AD30 PCI_AD62 22
GND 277 AF28 42 DCS#4 see Table
4 on page
27
AK13 AB2 LOC_AD29 PCI_AD61 137
GND 287 T28 43 INTE# AK14 AB3 GND 244
GND 328 G4 44 INTD# AK15 AB4 LOC_AD27 PCI_AD59 343
GND 336 R4 45 INTA# AK16 AB5 VDD 434
GND 351 AG7 46 UART_DTR# AK17 AB26 MWE#0 463
GND 374 AD27 47 MRDY# AK18 AB27 MCS#0 376
GND 417 E5 48 GND AK19 AB28 NC 281
GND 420 H5 49 MAbank110 AK20 AB29 MDC6 178
GND 421 J5 50 MAbank16 AK21 AB30 MDC5 67
GND 422 K5 51 MAbank13 AK22 AC1 LOC_AD28 PCI_AD60 23
GND 423 L5 52 MAbank11 AK23 AC2 LOC_AD26 PCI_AD58 138
GND 424 M5 53 GND AK24 AC3 LOC_AD25 PCI_AD57 245
GND 425 N5 54 TEST_SEL AK25 AC4 VDD 344
GND 426 P5 55 TEST# AK26 AC5 GND 435
GND 428 T5 56 NC AK27 AC26 GND 462
GND 429 U5 57 NC AK28 AC27 VDD 375
GND 430 V5 58 NC AK29 AC28 MRAS#0 280
GND 431 W5 59 NC AK30 AC29 MCAS#0 177
GND 432 Y5 60 MAbank010 AJ30 AC30 MDC7 66
GND 433 AA5 61 MAbank06 AH30 AD1 GND 24
GND 435 AC5 62 MAbank03 AG30 AD2 LOC_AD24 PCI_AD56 139
GND 437 AE5 63 MAbank00 AF30 AD3 PCLKIN 246
GND 438 AF5 64 MWE#1 AE30 AD4 AGND 345
GND 440 AF7 65 GND AD30 AD5 PCICR# 436
GND 441 AF8 66 MDC7 AC30 AD26 VDD 461
GND 443 AF10 67 MDC5 AB30 AD27 GND 374
GND 444 AF11 68 MDC2 AA30 AD28 MCAS#1 279
GND 445 AF12 69 MD61 Y30 AD29 MCS#1 176
GND 446 AF13 70 MD58 W30 AD30 GND 65
GND 447 AF14 71 MD53 V30 AE1 LOC_AD23 PCI_AD55 25
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
GND 448 AF15 72 MD50 U30 AE2 PCI64# 140
GND 449 AF16 73 MD49 T30 AE3 AVDD 247
GND 450 AF17 74 MD45 R30 AE4 LOC_AD21 PCI_AD53 346
GND 452 AF19 75 MD40 P30 AE5 GND 437
GND 453 AF20 76 MD37 N30 AE26 GND 460
GND 454 AF21 77 MD32 M30 AE27 MAbank04 373
GND 456 AF23 78 MD29 L30 AE28 MAbank01 278
GND 459 AF26 79 MD24 K30 AE29 MRAS#1 175
GND 460 AE26 80 MD21 J30 AE30 MWE#1 64
GND 462 AC26 81 MD19 H30 AF1 NC 26
GND 464 AA26 82 MD14 G30 AF2 NC 141
GND 466 W26 83 MD11 F30 AF3 GND 248
GND 468 U26 84 MD8 E30 AF4 LOC_AD19 PCI_AD51 347
GND 471 P26 85 MD4 D30 AF5 GND 438
GND 473 M26 86 MD0 C30 AF6 LOC_AD12 PCI_AD44 439
GND 475 K26 87 NC B30 AF7 GND 440
GND 477 H26 88 NC A30 AF8 GND 441
GND 478 G26 89 Int#5 A29 AF9 VDD 442
GND 479 F26 90 Int#1 A28 AF10 GND 443
GND 480 E26 91 ScMatch A27 AF11 GND 444
GND 481 E25 92 SysCmd8 A26 AF12 GND 445
GND 482 E24 93 SysCmd5 A25 AF13 GND 446
GND 483 E23 94 SysCmd2 A24 AF14 GND 447
GND 485 E21 95 SysADC5 A23 AF15 GND 448
GND 487 E19 96 SysADC3 A22 AF16 GND 449
GND 489 E17 97 SysADC0 A21 AF17 GND 450
GND 492 E14 98 SysAD59 A20 AF18 MAbank113 451
GND 494 E12 99 SysAD56 A19 AF19 GND 452
GND 496 E10 100 SysAD51 A18 AF20 GND 453
GND 498 E8 101 SysAD48 A17 AF21 GND 454
GNT#0 228 F3 102 SysAD47 A16 AF22 MAbank014 455
GNT#1 120 E2 103 GND A15 AF23 GND 456
GNT#2 419 G5 104 SysAD39 A14 AF24 NC 457
GNT#3 327 F4 105 SysAD36 A13 AF25 AVDD 458
GNT#4 227 E3 106 SysAD31 A12 AF26 GND 459
IDSEL 232 K3 107 SysAD28 A11 AF27 MAbank07 372
Int#0 200 B27 108 SysAD23 A10 AF28 GND 277
Int#1 90 A28 109 SysAD20 A9 AF29 MAbank02 174
Int#2 395 D26 110 SysAD18 A8 AF30 MAbank00 63
Int#3 301 C27 111 SysAD13 A7 AG1 LOC_AD22 PCI_AD54 27
Int#4 199 B28 112 SysAD10 A6 AG2 LOC_AD20 PCI_AD52 142
Int#5 89 A29 113 SysAD7 A5 AG3 LOC_AD18 PCI_AD50 249
INTA# 45 AK16 114 SysAD3 A4 AG4 VDD 348
INTB# 359 AG15 115 SysAD0 A3 AG5 LOC_AD11 PCI_AD43 349
INTC# 157 AJ15 116 NC A2 AG6 VDD 350
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
INTD# 44 AK15 117 PCLK4 B2 AG7 GND 351
INTE# 43 AK14 118 PCLK2 C2 AG8 VDD 352
IRDY# 128 N2 119 VDD D2 AG9 LOC_A4 PAR64 353
LOC_A0 C/BE#4 257 AH10 120 GNT#1 E2 AG10 VDD 354
LOC_A1 C/BE#5 38 AK9 121 PCI_AD30 F2 AG11 LOC_RD# 355
LOC_A2 C/BE#6 151 AJ9 122 PCI_AD27 G2 AG12 VDD 356
LOC_A3 C/BE#7 37 AK8 123 PCI_AD26 H2 AG13 DCS#7 see Table
4 on page
27
357
LOC_A4 PAR64 353 AG9 124 REQ#1 J2 AG14 VDD 358
LOC_AD0 PCI_AD32 150 AJ8 125 PCI_AD23 K2 AG15 INTB# 359
LOC_AD1 PCI_AD33 255 AH8 126 PCI_AD20 L2 AG16 UART_DSR# 360
LOC_AD10 PCI_AD42 32 AK3 127 PCI_AD17 M2 AG17 VDD 361
LOC_AD11 PCI_AD43 349 AG5 128 IRDY# N2 AG18 MAbank114 362
LOC_AD12 PCI_AD44 439 AF6 129 LOCK# P2 AG19 VDD 363
LOC_AD13 PCI_AD45 145 AJ3 130 PAR R2 AG20 MAbank17 364
LOC_AD14 PCI_AD46 31 AK2 131 PCI_AD15 T2 AG21 VDD 365
LOC_AD15 PCI_AD47 144 AJ2 132 PCI_AD11 U2 AG22 MAbank10 366
LOC_AD16 PCI_AD48 250 AH3 133 PCI_AD9 V2 AG23 VDD 367
LOC_AD17 PCI_AD49 143 AH2 134 PCI_AD6 W2 AG24 NC 368
LOC_AD18 PCI_AD50 249 AG3 135 PCI_AD4 Y2 AG25 NC 369
LOC_AD19 PCI_AD51 347 AF4 136 PCI_AD0 AA2 AG26 NC 370
LOC_AD2 PCI_AD34 149 AJ7 137 LOC_AD29 PCI_AD61 AB2 AG27 VDD 371
LOC_AD20 PCI_AD52 142 AG2 138 LOC_AD26 PCI_AD58 AC2 AG28 MAbank08 276
LOC_AD21 PCI_AD53 346 AE4 139 LOC_AD24 PCI_AD56 AD2 AG29 MAbank05 173
LOC_AD22 PCI_AD54 27 AG1 140 PCI64# AE2 AG30 MAbank03 62
LOC_AD23 PCI_AD55 25 AE1 141 NC AF2 AH1 VDD 28
LOC_AD24 PCI_AD56 139 AD2 142 LOC_AD20 PCI_AD52 AG2 AH2 LOC_AD17 PCI_AD49 143
LOC_AD25 PCI_AD57 245 AC3 143 LOC_AD17 PCI_AD49 AH2 AH3 LOC_AD16 PCI_AD48 250
LOC_AD26 PCI_AD58 138 AC2 144 LOC_AD15 PCI_AD47 AJ2 AH4 GND 251
LOC_AD27 PCI_AD59 343 AB4 145 LOC_AD13 PCI_AD45 AJ3 AH5 LOC_BG# HLDA 252
LOC_AD28 PCI_AD60 23 AC1 146 GND AJ4 AH6 LOC_AD7 PCI_AD39 253
LOC_AD29 PCI_AD61 137 AB2 147 LOC_AD8 PCI_AD40 AJ5 AH7 LOC_AD4 PCI_AD36 254
LOC_AD3 PCI_AD35 35 AK6 148 LOC_AD5 PCI_AD37 AJ6 AH8 LOC_AD1 PCI_AD33 255
LOC_AD30 PCI_AD62 22 AB1 149 LOC_AD2 PCI_AD34 AJ7 AH9 GND 256
LOC_AD31 PCI_AD63 243 AA3 150 LOC_AD0 PCI_AD32 AJ8 AH10 LOC_A0 C/BE#4 257
LOC_AD4 PCI_AD36 254 AH7 151 LOC_A2 C/BE#6 AJ9 AH11 LOC_WR# 258
LOC_AD5 PCI_AD37 148 AJ6 152 LOC_ALE REQ64# AJ10 AH12 LOC_BR# HOLD 259
LOC_AD6 PCI_AD38 34 AK5 153 LOC_FR# AJ11 AH13 DCS#6 see Table
4 on page
27
260
LOC_AD7 PCI_AD39 253 AH6 154 LOC_BGACK# AJ12 AH14 DCS#3 see Table
4 on page
27
261
LOC_AD8 PCI_AD40 147 AJ5 155 DCS#5 see Table
4 on page
27
AJ13 AH15 NC 262
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
LO C_AD 9 P C I _ A D41 33 AK4 156 DCS #2 se e T a ble
4 on page
27
AJ14 AH16 VccOk 263
LOC_ALE REQ64# 152 AJ10 157 INTC# AJ15 AH17 UART_TxDRDY# 264
LOC_BG# HLDA 252 AH5 158 M66EN AJ16 AH18 DQM 265
LOC_BGACK# 154 AJ12 159 UART_RxDRDY# AJ17 AH19 MAbank111 266
LOC_BR# HOLD 259 AH12 160 BootCS# AJ18 AH20 MAbank18 267
LOC_CLK ACK64# 39 AK10 161 MAbank112 AJ19 AH21 MAbank14 268
LOC_FR# 153 AJ11 162 MAbank19 AJ20 AH22 GND 269
LOC_RD# 355 AG11 163 MAbank15 AJ21 AH23 MAbank012 270
LOC_RDY# 40 AK11 164 MAbank12 AJ22 AH24 SysClock 271
LOC_WR# 258 AH11 165 MAbank013 AJ23 AH25 NC 272
LOCK# 129 P2 166 MAbank011 AJ24 AH26 NC 273
M66EN 158 AJ16 167 GND AJ25 AH27 NC 274
MAbank00 63 AF30 168 NC AJ26 AH28 NC 275
MAbank01 278 AE28 169 NC AJ27 AH29 MAbank09 172
MAbank02 174 AF29 170 AGND AJ28 AH30 MAbank06 61
MAbank03 62 AG30 171 BigEndian AJ29 AJ1 NC 29
MAbank04 373 AE27 172 MAbank09 AH29 AJ2 LOC_AD15 PCI_AD47 144
MAbank05 173 AG29 173 MAbank05 AG29 AJ3 LOC_AD13 PCI_AD45 145
MAbank06 61 AH30 174 MAbank02 AF29 AJ4 GND 146
MAbank07 372 AF27 175 MRAS#1 AE29 AJ5 LOC_AD8 PCI_AD40 147
MAbank08 276 AG28 176 MCS#1 AD29 AJ6 LOC_AD5 PCI_AD37 148
MAbank09 172 AH29 177 MCAS#0 AC29 AJ7 LOC_AD2 PCI_AD34 149
MAbank010 60 AJ30 178 MDC6 AB29 AJ8 LOC_AD0 PCI_AD32 150
MAbank011 166 AJ24 179 MDC3 AA29 AJ9 LOC_A2 C/BE#6 151
MAbank012 270 AH23 180 MD62 Y29 AJ10 LOC_ALE REQ64# 152
MAbank013 165 AJ23 181 MD59 W29 AJ11 LOC_FR# 153
MAbank014 455 AF22 182 MD54 V29 AJ12 LOC_BGACK# 154
MAbank10 366 AG22 183 MD51 U29 AJ13 DCS#5 see Table
4 on page
27
155
MAbank11 52 AK23 184 MD48 T29 AJ14 DCS#2 see Table
4 on page
27
156
MAbank12 164 AJ22 185 MD44 R29 AJ15 INTC# 157
MAbank13 51 AK22 186 MD39 P29 AJ16 M66EN 158
MAbank14 268 AH21 187 MD36 N29 AJ17 UART_RxDRDY# 159
MAbank15 163 AJ21 188 MD31 M29 AJ18 BootCS# 160
MAbank16 50 AK21 189 MD28 L29 AJ19 MAbank112 161
MAbank17 364 AG20 190 MD23 K29 AJ20 MAbank19 162
MAbank18 267 AH20 191 MD20 J29 AJ21 MAbank15 163
MAbank19 162 AJ20 192 MD15 H29 AJ22 MAbank12 164
MAbank110 49 AK20 193 MD12 G29 AJ23 MAbank013 165
MAbank111 266 AH19 194 MD9 F29 AJ24 MAbank011 166
MAbank112 161 AJ19 195 MD5 E29 AJ25 GND 167
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
MAbank113 451 AF18 196 MD1 D29 AJ26 NC 168
MAbank114 362 AG18 197 ModeOut C29 AJ27 NC 169
MCAS#0 177 AC29 198 NMI# B29 AJ28 AGND 170
MCAS#1 279 AD28 199 Int#4 B28 AJ29 BigEndian 171
MCS#0 376 AB27 200 Int#0 B27 AJ30 MAbank010 60
MCS#1 176 AD29 201 ScDOE# B26 AK1 NC 30
MCWrRdy# 397 D24 202 SysCmd7 B25 AK2 LOC_AD14 PCI_AD46 31
MD0 86 C30 203 SysCmd4 B24 AK3 LOC_AD10 PCI_AD42 32
MD1 196 D29 204 SysCmd1 B23 AK4 LOC_AD9 PCI_AD41 33
MD2 298 E28 205 SysADC4 B22 AK5 LOC_AD6 PCI_AD38 34
MD3 392 F27 206 SysADC1 B21 AK6 LOC_AD3 PCI_AD35 35
MD4 85 D30 207 SysAD60 B20 AK7 GND 36
MD5 195 E29 208 SysAD57 B19 AK8 LOC_A3 C/BE#7 37
MD6 297 F28 209 SysAD52 B18 AK9 LOC_A1 C/BE#5 38
MD7 391 G27 210 SysAD49 B17 AK10 LOC_CLK ACK64# 39
MD8 84 E30 211 SysAD46 B16 AK11 LOC_RDY# 40
MD9 194 F29 212 SysAD43 B15 AK12 DCS#8 se e Table
4 on page
27
41
MD10 296 G28 213 SysAD38 B14 AK13 DCS#4 se e Table
4 on page
27
42
MD11 83 F30 214 SysAD35 B13 AK14 INTE# 43
MD12 193 G29 215 SysAD30 B12 AK15 INTD# 44
MD13 295 H28 216 SysAD27 B11 AK16 INTA# 45
MD14 82 G30 217 SysAD22 B10 AK17 UART_DTR# 46
MD15 192 H29 218 SysAD19 B9 AK18 MRDY# 47
MD16 476 J26 219 SysAD14 B8 AK19 GND 48
MD17 389 J27 220 SysAD11 B7 AK20 MAbank110 49
MD18 294 J28 221 SysAD8 B6 AK21 MAbank16 50
MD19 81 H30 222 SMC B5 AK22 MAbank13 51
MD20 191 J29 223 CntrValid# B4 AK23 MAbank11 52
MD21 80 J30 224 CPUValid# B3 AK24 GND 53
MD22 293 K28 225 PCIRST# C3 AK25 TEST_SEL 54
MD23 190 K29 226 GND D3 AK26 TEST# 55
MD24 79 K30 227 GNT#4 E3 AK27 NC 56
MD25 474 L26 228 GNT#0 F3 AK28 NC 57
MD26 387 L27 229 PCI_AD29 G3 AK29 NC 58
MD27 292 L28 230 REQ#4 H3 AK30 NC 59
MD28 189 L29 231 PCI_AD24 J3 B1 PCLK3 2
MD29 78 L30 232 IDSEL K3 B2 PCLK4 117
MD30 291 M28 233 REQ#0 L3 B3 CPUValid# 224
MD31 188 M29 234 PCI_AD18 M3 B4 CntrValid# 223
MD32 77 M30 235 TRDY# N3 B5 SMC 222
MD33 472 N26 236 STOP# P3 B6 SysAD8 221
MD34 385 N27 237 NC R3 B7 SysAD11 220
MD35 290 N28 238 PCI_AD14 T3 B8 SysAD14 219
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
MD36 187 N29 239 PCI_AD10 U3 B9 SysAD19 218
MD37 76 N30 240 PCI_AD8 V3 B10 SysAD22 217
MD38 289 P28 241 PCI_AD5 W3 B11 SysAD27 216
MD39 186 P29 242 PCI_AD3 Y3 B12 SysAD30 215
MD40 75 P30 243 LOC_AD31 PCI_AD63 AA3 B13 SysAD35 214
MD41 470 R26 244 GND AB3 B14 SysAD38 213
MD42 383 R27 245 LOC_AD25 PCI_AD57 AC3 B15 SysAD43 212
MD43 288 R28 246 PCLKIN AD3 B16 SysAD46 211
MD44 185 R29 247 AVDD AE3 B17 SysAD49 210
MD45 74 R30 248 GND AF3 B18 SysAD52 209
MD46 382 T27 249 LOC_AD18 PCI_AD50 AG3 B19 SysAD57 208
MD47 469 T26 250 LOC_AD16 PCI_AD48 AH3 B20 SysAD60 207
MD48 184 T29 251 GND AH4 B21 SysADC1 206
MD49 73 T30 252 LOC_BG# HLDA AH5 B22 SysADC4 205
MD50 72 U30 253 LOC_AD7 PCI_AD39 AH6 B23 SysCmd1 204
MD51 183 U29 254 LOC_AD4 PCI_AD36 AH7 B24 SysCmd4 203
MD52 286 U28 255 LOC_AD1 PCI_AD33 AH8 B25 SysCmd7 202
MD53 71 V30 256 GND AH9 B26 ScDOE# 201
MD54 182 V29 257 LOC_A0 C/BE#4 AH10 B27 Int#0 200
MD55 285 V28 258 LOC_WR# AH11 B28 Int#4 199
MD56 380 V27 259 LOC_BR# HOLD AH12 B29 NMI# 198
MD57 467 V26 260 DCS#6 see Table
4 on page
27
AH13 B30 NC 87
MD58 70 W30 261 DCS#3 see Table
4 on page
27
AH14 C1 GND 3
MD59 181 W29 262 NC AH15 C2 PCLK2 118
MD60 284 W28 263 VccOk AH16 C3 PCIRST# 225
MD61 69 Y30 264 UART_TxDRDY# AH17 C4 CntrVccOk 324
MD62 180 Y29 265 DQM AH18 C5 SysAD1 323
MD63 283 Y28 266 MAbank111 AH19 C6 SysAD5 322
MDC0 378 Y27 267 MAbank18 AH20 C7 SysAD9 321
MDC1 465 Y26 268 MAbank14 AH21 C8 SysAD12 320
MDC2 68 AA30 269 GND AH22 C9 SysAD17 319
MDC3 179 AA29 270 MAbank012 AH23 C10 SysAD21 318
MDC4 282 AA28 271 SysClock AH24 C11 SysAD26 317
MDC5 67 AB30 272 NC AH25 C12 SysAD29 316
MDC6 178 AB29 273 NC AH26 C13 SysAD34 315
MDC7 66 AC30 274 NC AH27 C14 SysAD37 314
ModeClock 300 C28 275 NC AH28 C15 SysAD42 313
ModeOut 197 C29 276 MAbank08 AG28 C16 NC 312
MRAS#0 280 AC28 277 GND AF28 C17 SysAD50 311
MRAS#1 175 AE29 278 MAbank01 AE28 C18 SysAD53 310
MRDY# 47 AK18 279 MCAS#1 AD28 C19 SysAD58 309
MWE#0 463 AB26 280 MRAS#0 AC28 C20 SysAD61 308
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
MWE#1 64 AE30 281 NC AB28 C21 SysADC2 307
NC 29 AJ1 282 MDC4 AA28 C22 SysADC6 306
NC 237 R3 283 MD63 Y28 C23 SysCmd3 305
NC 1 A1 284 MD60 W28 C24 SysCmd6 304
NC 116 A2 285 MD55 V28 C25 WrRdy# 303
NC 312 C16 286 MD52 U28 C26 ScWord1 302
NC 88 A30 287 GND T28 C27 Int#3 301
NC 87 B30 288 MD43 R28 C28 ModeClock 300
NC 281 AB28 289 MD38 P28 C29 ModeOut 197
NC 59 AK30 290 MD35 N28 C30 MD0 86
NC 58 AK29 291 MD30 M28 D1 GND 4
NC 262 AH15 292 MD27 L28 D2 VDD 119
NC 30 AK1 293 MD22 K28 D3 GND 226
NMI# 198 B29 294 MD18 J28 D4 VDD 325
PAR 130 R2 295 MD13 H28 D5 Reset# 416
PCI64# 140 AE2 296 MD10 G28 D6 SysAD2 415
PCI_AD0 136 AA2 297 MD6 F28 D7 SysAD6 414
PCI_AD1 21 AA1 298 MD2 E28 D8 VDD 413
PCI_AD2 341 Y4 299 PROM_CLK D28 D9 SysAD16 412
PCI_AD3 242 Y3 300 ModeClock C28 D10 VDD 411
PCI_AD4 135 Y2 301 Int#3 C27 D11 SysAD25 410
PCI_AD5 241 W3 302 ScWord1 C26 D12 VDD 409
PCI_AD6 134 W2 303 WrRdy# C25 D13 SysAD33 408
PCI_AD7 19 W1 304 SysCmd6 C24 D14 VDD 407
PCI_AD8 240 V3 305 SysCmd3 C23 D15 SysAD41 406
PCI_AD9 133 V2 306 SysADC6 C22 D16 SysAD44 405
PCI_AD10 239 U3 307 SysADC2 C21 D17 VDD 404
PCI_AD11 132 U2 308 SysAD61 C20 D18 SysAD54 403
PCI_AD12 17 U1 309 SysAD58 C19 D19 VDD 402
PCI_AD13 337 T4 310 SysAD53 C18 D20 SysAD62 401
PCI_AD14 238 T3 311 SysAD50 C17 D21 VDD 400
PCI_AD15 131 T2 312 NC C16 D22 SysADC7 399
PCI_AD16 12 M1 313 SysAD42 C15 D23 VDD 398
PCI_AD17 127 M2 314 SysAD37 C14 D24 MCWrRdy# 397
PCI_AD18 234 M3 315 SysAD34 C13 D25 ScWord0 396
PCI_AD19 11 L1 316 SysAD29 C12 D26 Int#2 395
PCI_AD20 126 L2 317 SysAD26 C11 D27 VDD 394
PCI_AD21 332 L4 318 SysAD21 C10 D28 PROM_CLK 299
PCI_AD22 10 K1 319 SysAD17 C9 D29 MD1 196
PCI_AD23 125 K2 320 SysAD12 C8 D30 MD4 85
PCI_AD24 231 J3 321 SysAD9 C7 E1 PCI_AD31 5
PCI_AD25 330 J4 322 SysAD5 C6 E2 GNT#1 120
PCI_AD26 123 H2 323 SysAD1 C5 E3 GNT#4 227
PCI_AD27 122 G2 324 CntrVccOk C4 E4 PCLK0 326
PCI_AD28 6 F1 325 VDD D4 E5 GND 417
PCI_AD29 229 G3 326 PCLK0 E4 E6 ColdReset# 500
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
PCI_AD30 121 F2 327 GNT#3 F4 E7 SysAD4 499
PCI_AD31 5 E1 328 GND G4 E8 GND 498
PCICR# 436 AD5 329 VDD H4 E9 SysAD15 497
PCIRST# 225 C3 330 PCI_AD25 J4 E10 GND 496
PCLK0 326 E4 331 VDD K4 E11 SysAD24 495
PCLK1 418 F5 332 PCI_AD21 L4 E12 GND 494
PCLK2 118 C2 333 VDD M4 E13 SysAD32 493
PCLK3 2 B1 334 C/BE#2 N4 E14 GND 492
PCLK4 117 B2 335 VDD P4 E15 SysAD40 491
PCLKIN 246 AD3 336 GND R4 E16 SysAD45 490
PERR# 20 Y1 337 PCI_AD13 T4 E17 GND 489
NC 141 AF2 338 VDD U4 E18 SysAD55 488
NC 26 AF1 339 C/BE#0 V4 E19 GND 487
NC 457 AF24 340 VDD W4 E20 SysAD63 486
NC 168 AJ26 341 PCI_AD2 Y4 E21 GND 485
NC 272 AH25 342 VDD AA4 E22 SysCmd0 484
NC 368 AG24 343 LOC_AD27 PCI_AD59 AB4 E23 GND 483
NC 275 AH28 344 VDD AC4 E24 GND 482
NC 274 AH27 345 AGND AD4 E25 GND 481
NC 370 AG26 346 LOC_AD21 PCI_AD53 AE4 E26 GND 480
NC 57 AK28 347 LOC_AD19 PCI_AD51 AF4 E27 PROM_SD 393
NC 169 AJ27 348 VDD AG4 E28 MD2 298
NC 273 AH26 349 LOC_AD11 PCI_AD43 AG5 E29 MD5 195
NC 369 AG25 350 VDD AG6 E30 MD8 84
NC 56 AK27 351 GND AG7 F1 PCI_AD28 6
PROM_CLK 299 D28 352 VDD AG8 F2 PCI_AD30 121
PROM_SD 393 E27 353 LOC_A4 PAR64 AG9 F3 GNT#0 228
REQ#0 233 L3 354 VDD AG10 F4 GNT#3 327
REQ#1 124 J2 355 LOC_RD# AG11 F5 PCLK1 418
REQ#2 8 H1 356 VDD AG12 F26 GND 479
REQ#3 7 G1 35 7 DC S #7 s ee Ta ble
4 on page
27
AG13 F27 MD3 392
REQ#4 230 H3 358 VDD AG14 F28 MD6 297
Reset# 416 D5 359 INTB# AG15 F29 MD9 194
ScDOE# 201 B26 360 UART_DSR# AG16 F30 MD11 83
ScMatch 91 A27 361 VDD AG17 G1 REQ#3 7
ScWord0 396 D25 362 MAbank114 AG18 G2 PCI_AD27 122
ScWord1 302 C26 363 VDD AG19 G3 PCI_AD29 229
SERR# 14 P1 364 MAbank17 AG20 G4 GND 328
SMC 222 B5 365 VDD AG21 G5 GNT#2 419
STOP# 236 P3 366 MAbank10 AG22 G26 GND 478
SysAD0 115 A3 367 VDD AG23 G27 MD7 391
SysAD1 323 C5 368 NC AG24 G28 MD10 296
SysAD2 415 D6 369 NC AG25 G29 MD12 193
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
SysAD3 114 A4 370 NC AG26 G30 MD14 82
SysAD4 499 E7 371 VDD AG27 H1 REQ#2 8
SysAD5 322 C6 372 MAbank07 AF27 H2 PCI_AD26 123
SysAD6 414 D7 373 MAbank04 AE27 H3 REQ#4 230
SysAD7 113 A5 374 GND AD27 H4 VDD 329
SysAD8 221 B6 375 VDD AC27 H5 GND 420
SysAD9 321 C7 376 MCS#0 AB27 H26 GND 477
SysAD10 112 A6 377 VDD AA27 H27 VDD 390
SysAD11 220 B7 378 MDC0 Y27 H28 MD13 295
SysAD12 320 C8 379 VDD W27 H29 MD15 192
SysAD13 111 A7 380 MD56 V27 H30 MD19 81
SysAD14 219 B8 381 VDD U27 J1 C/BE#3 9
SysAD15 497 E9 382 MD46 T27 J2 REQ#1 124
SysAD16 412 D9 383 MD42 R27 J3 PCI_AD24 231
SysAD17 319 C9 384 VDD P27 J4 PCI_AD25 330
SysAD18 110 A8 385 MD34 N27 J5 GND 421
SysAD19 218 B9 386 VDD M27 J26 MD16 476
SysAD20 109 A9 387 MD26 L27 J27 MD17 389
SysAD21 318 C10 388 VDD K27 J28 MD18 294
SysAD22 217 B10 389 MD17 J27 J29 MD20 191
SysAD23 108 A10 390 VDD H27 J30 MD21 80
SysAD24 495 E11 391 MD7 G27 K1 PCI_AD22 10
SysAD25 410 D11 392 MD3 F27 K2 PCI_AD23 125
SysAD26 317 C11 393 PROM_SD E27 K3 IDSEL 232
SysAD27 216 B11 394 VDD D27 K4 VDD 331
SysAD28 107 A11 395 Int#2 D26 K5 GND 422
SysAD29 316 C12 396 ScWord0 D25 K26 GND 475
SysAD30 215 B12 397 MCWrRdy# D24 K27 VDD 388
SysAD31 106 A12 398 VDD D23 K28 MD22 293
SysAD32 493 E13 399 SysADC7 D22 K29 MD23 190
SysAD33 408 D13 400 VDD D21 K30 MD24 79
SysAD34 315 C13 401 SysAD62 D20 L1 PCI_AD19 11
SysAD35 214 B13 402 VDD D19 L2 PCI_AD20 126
SysAD36 105 A13 403 SysAD54 D18 L3 REQ#0 233
SysAD37 314 C14 404 VDD D17 L4 PCI_AD21 332
SysAD38 213 B14 405 SysAD44 D16 L5 GND 423
SysAD39 104 A14 406 SysAD41 D15 L26 MD25 474
SysAD40 491 E15 407 VDD D14 L27 MD26 387
SysAD41 406 D15 408 SysAD33 D13 L28 MD27 292
SysAD42 313 C15 409 VDD D12 L29 MD28 189
SysAD43 212 B15 410 SysAD25 D11 L30 MD29 78
SysAD44 405 D16 411 VDD D10 M1 PCI_AD16 12
SysAD45 490 E16 412 SysAD16 D9 M2 PCI_AD17 127
SysAD46 211 B16 413 VDD D8 M3 PCI_AD18 234
SysAD47 102 A16 414 SysAD6 D7 M4 VDD 333
SysAD48 101 A17 415 SysAD2 D6 M5 GND 424
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
SysAD49 210 B17 416 Reset# D5 M26 GND 473
SysAD50 311 C17 417 GND E5 M27 VDD 386
SysAD51 100 A18 418 PCLK1 F5 M28 MD30 291
SysAD52 209 B18 419 GNT#2 G5 M29 MD31 188
SysAD53 310 C18 420 GND H5 M30 MD32 77
SysAD54 403 D18 421 GND J5 N1 FRAME# 13
SysAD55 488 E18 422 GND K5 N2 IRDY# 128
SysAD56 99 A19 423 GND L5 N3 TRDY# 235
SysAD57 208 B19 424 GND M5 N4 C/BE#2 334
SysAD58 309 C19 425 GND N5 N5 GND 425
SysAD59 98 A20 426 GND P5 N26 MD33 472
SysAD60 207 B20 427 C/BE#1 R5 N27 MD34 385
SysAD61 308 C20 428 GND T5 N28 MD35 290
SysAD62 401 D20 429 GND U5 N29 MD36 187
SysAD63 486 E20 430 GND V5 N30 MD37 76
SysADC0 97 A21 431 GND W5 P1 SERR# 14
SysADC1 206 B21 432 GND Y5 P2 LOCK# 129
SysADC2 307 C21 433 GND AA5 P3 STOP# 236
SysADC3 96 A22 434 VDD AB5 P4 VDD 335
SysADC4 205 B22 435 GND AC5 P5 GND 426
SysADC5 95 A23 436 PCICR# AD5 P26 GND 471
SysADC6 306 C22 437 GND AE5 P27 VDD 384
SysADC7 399 D22 438 GND AF5 P28 MD38 289
SysClock 271 AH24 439 LOC_AD12 PCI_AD44 AF6 P29 MD39 186
SysCmd0 484 E22 440 GND AF7 P30 MD40 75
SysCmd1 204 B23 441 GND AF8 R1 GND 15
SysCmd2 94 A24 442 VDD AF9 R2 PAR 130
SysCmd3 305 C23 443 GND AF10 R3 NC 237
SysCmd4 203 B24 444 GND AF11 R4 GND 336
SysCmd5 93 A25 445 GND AF12 R5 C/BE#1 427
SysCmd6 304 C24 446 GND AF13 R26 MD41 470
SysCmd7 202 B25 447 GND AF14 R27 MD42 383
SysCmd8 92 A26 448 GND AF15 R28 MD43 288
TEST# 55 AK26 449 GND AF16 R29 MD44 185
TEST_SEL 54 AK25 450 GND AF17 R30 MD45 74
TRDY# 235 N3 451 MAbank113 AF18 T1 VDD 16
UART_DSR# 360 AG16 452 GND AF19 T2 PCI_AD15 131
UART_DTR# 46 AK17 453 GND AF20 T3 PCI_AD14 238
UART_RxDRDY# 159 AJ17 454 GND AF21 T4 PCI_AD13 337
UART_TxDRDY# 264 AH17 455 MAbank014 AF22 T5 GND 428
VccOk 263 AH16 456 GND AF23 T26 MD47 469
VDD 16 T1 457 NC AF24 T27 MD46 382
VDD 28 AH1 458 AVDD AF25 T28 GND 287
VDD 119 D2 459 GND AF26 T29 MD48 184
VDD 325 D4 460 GND AE26 T30 MD49 73
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
VDD 329 H4 461 VDD AD26 U1 PCI_AD12 17
VDD 331 K4 462 GND AC26 U2 PCI_AD11 132
VDD 333 M4 463 MWE#0 AB26 U3 PCI_AD10 239
VDD 335 P4 464 GND AA26 U4 VDD 338
VDD 338 U4 465 MDC1 Y26 U5 GND 429
VDD 340 W4 466 GND W26 U26 GND 468
VDD 342 AA4 467 MD57 V26 U27 VDD 381
VDD 344 AC4 468 GND U26 U28 MD52 286
VDD 348 AG4 469 MD47 T26 U29 MD51 183
VDD 350 AG6 470 MD41 R26 U30 MD50 72
VDD 352 AG8 471 GND P26 V1 DEVSEL# 18
VDD 354 AG10 472 MD33 N26 V2 PCI_AD9 133
VDD 356 AG12 473 GND M26 V3 PCI_AD8 240
VDD 358 AG14 474 MD25 L26 V4 C/BE#0 339
VDD 361 AG17 475 GND K26 V5 GND 430
VDD 363 AG19 476 MD16 J26 V26 MD57 467
VDD 365 AG21 477 GND H26 V27 MD56 380
VDD 367 AG23 478 GND G26 V28 MD55 285
VDD 371 AG27 479 GND F26 V29 MD54 182
VDD 375 AC27 480 GND E26 V30 MD53 71
VDD 377 AA27 481 GND E25 W1 PCI_AD7 19
VDD 379 W27 482 GND E24 W2 PCI_AD6 134
VDD 381 U27 483 GND E23 W3 PCI_AD5 241
VDD 384 P27 484 SysCmd0 E22 W4 VDD 340
VDD 386 M27 485 GND E21 W5 GND 431
VDD 388 K27 486 SysAD63 E20 W26 GND 466
VDD 390 H27 487 GND E19 W27 VDD 379
VDD 394 D27 488 SysAD55 E18 W28 MD60 284
VDD 398 D23 489 GND E17 W29 MD59 181
VDD 400 D21 490 SysAD45 E16 W30 MD58 70
VDD 402 D19 491 SysAD40 E15 Y1 PERR# 20
VDD 404 D17 492 GND E14 Y2 PCI_AD4 135
VDD 407 D14 493 SysAD32 E13 Y3 PCI_AD3 242
VDD 409 D12 494 GND E12 Y4 PCI_AD2 341
VDD 411 D10 495 SysAD24 E11 Y5 GND 432
VDD 413 D8 496 GND E10 Y26 MDC1 465
VDD 434 AB5 497 SysAD15 E9 Y27 MDC0 378
VDD 442 AF9 498 GND E8 Y28 MD63 283
VDD 461 AD26 499 SysAD4 E7 Y29 MD62 180
WrRdy# 303 C25 500 ColdReset# E6 Y30 MD61 69
Table 47: Pinout Sorted By Signal Name, Pin Number, and Grid Number (conti nued)
Signal
Name Alternate
Signal Pin
#Grid
#Pin
#Signal
Name Alternate
Signal Grid
#Grid
#Signal
Name Alternate
Signal Pin
#
18.0 Package
Figure 49 shows the controlle r’s 500- pin TBGA package.
Figure 49: 500-Pi n TBGA Packa ge
φφ
φ
φφ
NOTES
*1
ITEM MILLIMETERS INCHES
A
D
G
H
J
K
40.00±0.20
40.00±0.20
0.80
1.40
0.15
0.60±0.10
1.575±0.008
0.024
0.031
0.055
0.006
1.575±0.008
B 39.60±0.15 1.559±0.006
C 39.60±0.15 1.559±0.006
F 1.27 (T.P.) 0.050 (T.P.)
E 1.585 0.062
N 0.25 MIN. 0.009 MIN.
M 0.30 0.012
S 2.0 0.079
R 2.0 0.079
T 3.0 0.118
X 22.73 0.895
W 22.73 0.895
P 0.10 0.004
Q 3.0 0.118
+0.004
–0.005
L 0.75±0.15
φ
0.030+0.006
–0.007
Each ball centerline is located within 0.30 mm ( 0.012 inch) of
its true position (T.P.) at maximum material condition.
*2 Each ball centerline is located within 0.10 mm ( 0.004 inch) of
its true position (T.P.) at maximum material condition.
500 PIN TAPE BGA (HEAT SPREADER TYPE) (40x40)
A123.00 MAX. 0.906 MAX.
A223.00 MAX. 0.906 MAX.
+0.30
–0.20
+0.20
–0.10 +0.009
–0.004
+0.012
–0.008
S500N7-H6
Z 0.20 0.008
Y C 0.40 C 0.016
BA
S
A
QR
ST
B W
Index mark
A B
D
A1
LMM
MSAB*1
*2P S
J
H
G
(Z)
N
detail of A part detail of B part
FE
A2
CY
X
KS
Appendix A Revi sion 2 Errat a
The following bugs or revision-specific states exist for Revision 2 of the controller.
A.1
Serial Conf igur ati on
Stream
The controller generates the default serial configuration stream incorrectly (See Sec-
tio n 12.4. 2). Use an external Serial Mode EEPROM, connect ed to t he controller. Ther e
is no need to connect a Serial Mode EEPROM to the CPU.
A.2
PCI-Bus Interface
A.2.1
Revision ID The PCI Revision ID regi ster has the value 0x02.
A.2.2
PCI Tim ing P r o b lems The PCI bus does not m eet the 66 MHz PCI specif ication, due to setup/hold timing on
a variety of signals. Thus, the PCI Bus cannot be clocked at 66 MHz.
A.2.3
PCI Loopback Reads I f t he controll er initiates a PCI read, and the target is the same controller, bad thi ngs
happen. This bug appli es to all PCI read s, i ncluding PCI conf igura ti on cycles .
For example, the CPU can only read the contr oller’s PCI confi guration registers by
accessing them directly wit h the internal addr ess descr ibed in Section 7.12. The CPU
cannot access these registe rs via PCI configuration cycles on the PCI Bus.
A.2.4
PCI LOCK# The cont roll er does not gener ate or r espond to PCI locked cycl es. If PCI l ock ed cycles
are being used by ot her devices in the system , t he LO CK# sig nal on controller should
be tied off (driven with a constant value 0 or 1), otherwise controller may not properly
complete del ayed transactions as a target.
If multiple VRC5074 controll ers are connected to a CPU, both controllers can be con-
nected to LOCK# if LOCK# is pulled up.
A.2.5
PCI Address Parity
Error
When a par ity error occurs during an access by a PCI-Bus master to the cont roller as
target, the con troller accepts the access. Here's what happens:
1. The external master does an access (e.g. a write) to somewhere. During the
address pha se ther e is a p arit y err or . Th is means th e addres s i s cor rupted, and thi s
access should be ignored by all targets! (but see Section 3.8.2.2. in th e
PCI Local
Bus Specification
.)
2. The controll er decodes the corrupted address and thi nks this access is for it. The
controller completes the access (if a write to SDRAM, then bad dat a gets writt en).
The controller can assert SERR# and/or interrupt the CPU when a PCI address error
occurs, as descri bed in Section 7. 5.4. This shoul d be considered a catastrophic sys-
tem error. Reset is an appropriate response.
Most or all PCI targets wi ll respond normally to a PCI access with an address parit y
error. Also most PC systems will assert NMI#, causing a system pani c or reset.
A.2.6
PCI Target Prefetch
May Cause OUTFIFO
Overrun
When a PCI read is per formed with the control ler as the target, and pref etching is
enabled with the PREFETCHABLE bit in the PCI Maste r (I nitiat or) Control Regist ers
(PCIINITn, Section 7.11.3), a data overrun may occur in the OUTFIFO. Prefetching
must not be used on PCI target reads. This means:
The PREFETCHABLE bit must be cleared i n the Base Address Regis ter. See
Section 7.13.10.
Memory Read Line and M emo ry Read Multiple com ma nds mu st not be used.
Only Memory Read should be used.
If bot h the PREFETCHABLE bi t and th e cache line size register (CLSIZ, Section
7.13. 7) are cle ared to 0, Memory Read an d Memory Read Multipl e commands may st ill
cause overru ns, but only if there are many pending PCI writes th at use up t he OUT-
FIFO’s 32-dword capacity.
For example, writ ing 8 to t he CLSIZ register causes the controller to fetch 8 words (4
dwords) du ri ng PCI t arget reads, using four dword en tries i n the O UTFIFO. The re can
be a maximum of four outstanding reads, which would use 16 of the OUTFIFO’s 32
dword entries. In thi s case, an OUTFIFO ove rrun will occur if there are, at the same
time, more than four outstanding PCI writes.
See Secti on 7.4.4.2 for more information on prefet ching during target reads.
A.3
Secondary Cache in
Multi-Controller
Configuration
Secti on 5.3 describes the controller’s operation with mult ip le ex ternal agent s. When L2
cache is enabled there can be problems with the ScDOE# si gnal driven by the control-
ler:
There must be multiple controller s (e. g. multipl e external agents A and B).
L2 cache must be enabled.
Agent B must be a VRC5074 control ler. Agent A may be a controller or a
compatible device.
If L2 cache miss occurs on a block read to agent A, that agent responds w ith the
correc t read da ta. Ther eaf ter , wheneve r a non-bl ock re ad i s perfor med to agent B,
the ScDOE# signal is incorrectly left high (negated) at the end of the transaction.
This can cause subsequent transactions to be cor rupted.
There are several wor karounds :
Do not allow cacheable accesses to agent A.
After any cacheab le a ccess to agent A, the fi rst ac cess to agent B must b e a block
read cache miss. This will cause the state of ScDOE# to be set properly.
Agent B must be the Main Controller (see Section 5.3.2). After any cacheable
access to agent A, the first access to agent B must cause a CPU-Bus Read
Timeout (seeSection 5. 3.3). This will cause the state of ScDOE# to be set
properly.
Put a strong pull down resistor on ScDOE#. Aft er agent B leaves ScDOE# in a
high stat e, there are a minim um of three idle clocks before ScDOE# mus t be lo w
for a subsequent cache hit.
A.4
UART External
Clock
Secti on 10.2 and Sect ion 8.6. 3 descri be how DCS#[5] can opt ionall y be confi gured as
the UART_XI N sig nal. This f eature doe s not work. The UART m ust be clock ed wi th t he
internally-generated UART clock (SYS_CLK divided by 12).
Appendix B Index
Numerics
MCAS#, 23
MCS#, 23
MRAS#, 23
MWE#, 23
ScCWE#, 38
ScDCE#, 38
ScWord, 22, 38
MAbank0, 23
MAbank1, 23
ScLine, 38
CLKSEL, 92
DSC#, 29
C/BE#, 24
DSC#, 29
LOC_A, 25, 119
LOC_AD, 25, 28
PCI_AD, 25
DSC#, 29
GNT#, 24, 25
LOC_A, 25, 119, 27
PCLK, 25, 26, 90
REQ#, 25, 26
DC S#, 137
DSC#, 29
Int#, 21, 37
DSC#, 29
MD, 23
PCI_AD, 25
SysAD, 22, 38
64-Bit PCI Bus, 87
66M, 108
C/BE#, 24, 25, 27
DSC#, 29
MDC, 23
SysADC, 22, 38
DCS, 110, 114
DCS#, 27, 132
DSC#, 29
SysCmd, 22, 38
A
AC Specific atio ns, 194
ACCESS_32, 1 01
ACCT, 74
ACK64#, 24, 25
ACSTIME, 72, 74
ADDR, 48, 49, 81, 103
Address Decoding Example, 49, 81
Address Mapping, 69
Address Space Summary, 36
Address-Multiplexi ng Modes, 68
AERIN, 97
AERSE, 95
ARBDISABLE, 100
ARBEN , 121
Arbitration, 89, 98
Local Bus, 118
Arbitration Priorit y, 99
ARBMOD E, 118, 121
B
Bank-Interleaved SDRAM, 66
Bank-Interleaving, 67
Banks
Physical, 67
Virtual, 67
BAR0, 105, 110
BAR1, 106, 110
BAR2, 106, 110
BAR3, 106, 110
BAR4, 106, 110
BAR5, 106, 110
BAR6, 106, 110
BAR7, 106, 110
BAR8, 106, 110
BARB , 106, 110
BARC, 105, 1 10
BARn, 110
Base Address, 150
Base Address Registers, 110
BASEADDR, 111
BASECL, 110
baud rate, 138
BCST, 121, 129
BE, 4 1
BI, 144
BigEndia n, 21, 37, 4 1, 150
BLKSIZE, 133
BLOCK_PFB, 103
BMASEN, 107
Boot Chip-Select, 45
Boot R OM, 64, 150
Boot ROM Location, 154
Boot R OM Size, 154
BOOTCS, 45, 64, 110
BootCS#, 23, 27
Branches to Unaligned Addresses, 41
Burst len gth, 68
burst transfers, 78, 113
Bus Width, 13
BUSIDLE, 124, 129
Byte-Merging, 82
BZ, 135
C
Cache, 39, 40
Cache Errata, 214
CAS latency, 68, 71
CAS-before-R AS refresh, 71
CEADDR, 74
Central Resource Functions, 88
CESY N, 75
Chip-Sel ect, 114
CHKDIS, 72, 73
CHKERR, 72, 74
CHKMODE, 72, 73
CLA SS, 105, 110
CLD RS T, 50, 149
Clocking, 90
UART, 138
CLS IZ, 105, 110
CNTDEN, 52
CNTDPRI, 52
CntrValid#, 21, 38, 39
CntrVccOk, 21, 38
COFHOLD, 124, 129
Cold Reset, 149
ColdReset#, 21, 37, 149
COMBINING, 102
Combining, 82
CON_POL, 125, 129
CONFIGTYPE, 102
Configuration, 103
CONOFF, 124, 129
CONS0, 99
CONS 0n, 99
CONS1, 99
CONS2, 100
CONSET, 123, 129
controller, 19
Controller Boot ROM Location , 154
Controller Boot ROM Size, 154
Controller ID, 150
Controller PCI C lock Speed, 154
CONWI D, 123, 129
CPCEE N, 40 , 52
CPCEP RI , 52
CPU Accesses to Local Memory, 162
CPU and Controller In itializ ation, 151
CPU Configura tion, 37
CPU Delayed Read Completion (DRC) Buffer ,
79
CPU Interface, 1
CPU Interface Registers, 31, 37, 50
CPU No-Target Decode, 148
CPU Pa rit y Erro rs , 148
CPU Re ads, 40
CPU Status, 50
CPU St atus Register, 50
CPU Write FIFO, 64
CPU-Bus Read Time-Out Control Register ,
59
CPU-Bus Read Time-Out Counter Register,
60
CPU- Bus Signals, 21, 37
CP UHOG, 92, 122
CPU-Interface Data Path, 38
CPU-Interface FIFO, 38, 39
CPUSTAT, 50
CPUValid#, 21, 38
CS_POL, 125, 129
CSOFF, 123, 129
CSON, 122, 129
CTRLNUM, 51
CTS, 145
D
DA C, 88
Data Aligner, 131
daughter board, 16
DCD, 145
DCS2, 45
DCS3, 45
DCS4, 45
DCS5, 45
DCS6, 45
DCS7, 45
DCS8, 45
DCSF N, 121
DCSFN2, 125
DCSFN3, 126
DCSFN4, 126
DCSFN5, 126
DCSFN6, 127
DCSFN7, 127
DCSFN8, 128
DCSIO, 121, 128
DCSL2IN, 12 8
DCSL3IN, 12 8
DCSL4IN, 12 8
DCSL5IN, 12 8
DCSL6IN, 12 8
DCSL7IN, 12 8
DCSL8IN, 12 9
DCSLOUT, 129
DCTS, 144
DDCD, 145
DDSR, 144
DEFGNT, 100
DE SI NC, 134
Device Chip Selects, 45
Device Chip-Select Configuration, 114
Device Chip-Select Function Register, 125
Device Chip-S el ects as I /O Bi ts Register, 128
DEVSEL, 109
DEVSEL#, 24
DID, 105, 107
DIMMs, 68
DISCPUPC, 40, 51
DISCTIM, 93
DIS MRDY, 74
DISPC, 40, 50
DIVLSB, 140
DIVMSB, 140
DLAB, 142
DMA, 3
DMA Config urati on and Monitoring, 13 0
DMA Control Registers 0 and 1, 133
DMA Controller and Registers, 130
DMA Data Aligner, 131
DMA Delayed Read Completion (D RC)
Buffer, 79
DMA Destination Ad dress Register 0 and 1,
136
DMA Events, 148
DMA External Requests, 133
DMA Hardware Handshakin g, 132
DMA Hardware-Handshake Signals, 29
DMA Registers, 32, 133
DMA Source Address Register 0 and 1, 136
DMA Transfer Mechanism, 130
DMA Wr ite FIFO, 64
DMA_ACK#, 27, 29
DMA_EOT#, 27, 29
DMA_REQ#, 27, 29
DMACTRL0, 133
DMACTRL1, 133
DMACTRLn, 133, 148
DMADESA, 136
DM ADESA0, 1 33
DM ADESA1, 1 33
DMAEN, 53
DMAHOG, 92, 122
DMAPRI, 53
DMASRCA, 136
DMASRCA0, 133
DMASRCA1, 133
DMASRCAn, 136
doubleword, 19
DPE, 109
DPR, 109
DQM, 23
DR, 144
DRC, 79
DRST, 134
DrvOut, 154
DSR, 145
DTIMCH, 94
DTIMIN, 96
DTIMSE, 95
DTR, 143
Dual Address Cycle (DAC), 88
Dual Address Cycles, 78
dword, 19
E
ECC, 72, 73, 75
ECHKERR, 76
EDSSI, 140
Electrical Specifications, 191
ELSI, 140
ENABLE, 73
End Of Transfer, 133
EndBit, 154
Endian Configuration, 41
Endian Mode, 13, 150
Endian-Mo de Software Issues, 156
EPS, 142
ERBFI, 139
Errata, 213
Error Checking, 72
ERRTYPE, 94
ETBEI, 140
Exclusive Access, 78
external agent, 19
external devices, 19, 74
External External, 89
External-Device Addressing, 64
ExtRqst#, 37
F
FAP ER, 9 3
FBBC, 108
FBBEN, 108
FDPER, 93
FE, 144
Fea tures, 1
FIFOSTALL, 93
FLCLCLK, 121
FRAME#, 24
G
gene ral-purp ose I/O, 27
General-Purpose Timer, 148
General- Purpose Ti mer Control Register, 60
General- Purpose Timer Counter Register, 61
GO, 135
GPTDEN , 53
GPTPRI, 53
GR OUP0 , 99
GR OUP1 , 99
GR OUP2 , 99
H
HHSDEST, 134
HHSEN, 134
HHSEOT, 136
HLDA, 28
HOLD, 28
HOLDLD, 74
HTYPE, 105, 110
I
I/O
general-purp ose I/O bits, 27
I/O Space, 85
IDSEL, 24, 105
IE, 135
IL0O E, 56
IL0STAT, 55
IL1O E, 56
IL1STAT, 55
IL2O E, 56
IL2STAT, 55
IL3O E, 56
IL3STAT, 55
IL4O E, 56
IL4STAT, 55
IL5O E, 56
IL5STAT, 55
ILEA VD, 73
INFIFO, 79
Initialization, 149
Initialization Data, 153
Initializat ion Se quence, 152
INT1SE, 95
INTA#, 24, 25
INTAEDGE, 57
INTAEN, 54, 97
INTAPOL, 57
INTAPRI, 54
INTB#, 24
INTBEDGE, 57
INTBEN, 54
INTBPOL, 57
INTBPRI, 54
INTC#, 24
INTCEDGE, 57
INTCEN, 54
INTCLR, 50, 56
INTCPOL, 57
INTCPRI, 54
INTCS, 45, 110
INTCTRL, 50, 52, 1 48
INTD#, 24
INTDEDGE, 57
INTDEN, 54
INTDPOL, 57
INTDPRI, 54
INTE#, 24
INTEEN, 54
INTEPRI, 54
Inter nal Architecture, 11
Internal Registers, 150
Internal R egist ers and Devices, 45
Interrupt Clear, 50
Interrupt Clear Register, 56
Interrupt Configuration and Reporting
Registers, 148
Interrupt Control, 50
Interrupt Control Register, 52, 57
Interrupt Enable, 5 0
Interrupt Status, 50
In terrupt Status 1/CP U Interrupt Enable
Register, 55
In terrupt Status Register 0, 55
Interrupts, 147
INTLIN, 106, 112, 148
INTPENDL, 140
INTPIN, 106, 112, 148
INTPPES, 50, 57, 148
INTSTAT0, 50, 55
INTSTAT1, 50, 55
IOEN, 107
IRDY # , 24
IS_CPU, 103
ISCLR, 57
IVLD, 135
J
JTAG, 190
JTCK, 37
JTDI, 37
JTDO, 37
JTTMS#, 38
L
L2 Cache E rr ata, 214
LATDIS, 97
latency
RAS and CAS, 71
LB RTDEN, 54
LB RTDPRI, 53
LCNFG, 121
LCST2, 121
LCST3, 121
LCST4, 121
LCST5, 121
LCST6, 121
LCST7, 121
LCST8, 121
LCSTn, 122, 148
LOC_ALE, 26, 28
LOC_BG#, 28
LOC_BGACK #, 28
LOC_BR#, 28
LOC_CLK, 24, 25, 28
LOC_FR#, 28
LOC_RD#, 28
LOC_RDY #, 28
LOC_WR# , 28
Local Boot Chip-Select Timing Regi ster, 129
Local Bus, 2, 19
Local Bus Chip-Select Timing Registers , 122
Local Bus Configuratio n Register, 121
Local Bus vs. 64- bit PCI Bus, 120
Local-Bus Accesses, 181
Local-Bus Configuration and Monitoring, 113
Local-Bus Interface and Register s, 113
Local -Bus Mast er Transa ctions ( Cont roll er -to-
Local Bus), 116
Local-Bus Ready Timer, 148
Local-Bus R egisters, 32, 120
Local-Bus Signals, 27
Local-Bus Target Tra nsactions (Local Bus-to-
Con tro lle r), 11 9
Local-Bus Timing, 116
Local-Bus Width, 13, 150
LOCK, 102
LOCK#, 25, 213
Locked Cycles, 91
locked cycles, 78
LOOP, 143
Loop-Back Acc esses, 85
Loop-Back Re quests, 120
M
M66EN , 25
MACH, 94
MAIN, 96
Main Controller, 19
MAINCTRL, 52
Main-Memory Interface and Registers, 63
MASE, 95
MASK, 47, 49, 81
MCEEN, 52
MCEPRI, 52
MCHKERR, 77
MCW rRdy#, 21
MEM/LOC, 48, 64
MEMCTRL, 72, 148
MEMEN, 107
Memory Access Timing Register, 65, 74
Memory Access T imi ng Regi ster (ACSTIME),
65
Memory B us, 63
Memory C heck Error Status R egist er, 74
Memory Configuration and Monitoring, 63
Memory C ontrol Register, 72
Memory Errors, 148
Memory Interface, 1
Memory Performance, 69
Memory R efresh, 71
Memory Sharing, 72
Memory Timing, 71
Memory-Bus Signals, 23
Memory-Interface Registers, 31, 72
MERGING, 102
MLTIM, 105, 110
ModeClock , 21, 38
ModeIn, 38
ModeOut, 21, 38
mod ule, 19
MRDERR, 135
MRDY#, 23
Multi- Contr oller C onfig uration , 13, 1 8, 40, 72,
150
MWIEN, 107
N
NMI#, 22, 38
NMIOE, 56
NMISTAT, 56
Non- Block Write, 154
O
OE, 144
OUT1 , 143
OUT2 , 143
OUTFIFO, 79
OUTFIFO Overrun Errata, 214
P
Pack age, 210
PAR, 25
PAR64, 25, 27
parity, 72
Parity Checking and Generation, 40
Parity Det ection, 84, 87
PARK0, 100
PARK1, 100
PARK2, 100
PCHKERR, 76
PCI Address Decoding Example, 81
PCI Address Parity Error Errata, 213
PCI Address Window Registers, 81
PCI Address Windows, 45
PCI Arbiter Register, 98
PCI Base Address Registers, 110
PCI Bus, 2, 87
PCI Bus 64-Bit vs. Loca l Bus, 120
PCI Cache-Line Size Register, 110
PCI Cent ral Re source, 13 , 16, 17 , 18, 7 8, 88 ,
89, 150
PCI Class Code Register, 110
PCI Clock Speed, 154
PCI Clo cking, 90
PCI Cold Reset, 149
PCI Command Register, 107
PCI Commands Supported, 80
PCI Config urat ion Space, 25
PCI Configuration Space Cycles, 103
PCI Configuration Space Registers, 33, 105
PCI Control R egister, 91
PCI Data Paths, 80
PCI Device ID Re gister, 107
PCI Error Register, 103
PCI Header Type Register, 110
PCI I /O Space Cycles, 85
PCI Input FIFO, 79
PCI Internal Error, 148
PCI I nter rupt Control Register, 57
PCI Interrupt Line Register, 112
PCI Interrupt Pin Register, 112
PCI Interrupts, 148
PCI Latency Timer Regi ster, 110
PCI LOCK# Errata, 213
PCI Locked Cyc les, 91
PCI Loopback Read Errata, 213
PCI Master (Initiator) Registe rs 0 and 1, 101
PCI Mast er T r ansa cti ons (Con trol le r-t o-PCI ),
81
PCI OUTFIFO Overrun Errata, 214
PCI Output FIFO, 79
PCI Reset Sequencing, 151
PCI Revision ID Register, 109
PCI SERR# (System Error), 148
PCI Stand-Alone Mode, 13, 19
PCI Status Register, 108
PCI Sub-System ID, 111
PCI Sub-System Vendor ID, 111
PCI Target Transactio ns (P CI-to-Controller),
85
PCI Timing Errata, 213
PCI Vendor ID R egister, 107
PCI Warm Reset, 149
PCI Write FIFO, 64
PCI64#, 25, 150
PCIADD, 103
PCIARB, 91, 98
PCI-Bus, 150
PCI-Bus Accesses, 173
PCI-Bus Configuration and Moni toring, 78
PCI-Bus Int erface and Registers, 78
PCI-Bus Interface Errata, 213
PCI-Bus Registers, 32, 91
PCI-Bus Signals, 24
PCI-Bus Width, 13
PCICMD, 105, 107, 148
PCICR#, 25, 150
PCI CRST, 98, 149
PCI CTRL, 91, 148
PCIEEN, 54
PCIEPRI, 54
PCI ERR, 91, 103
PCIHOG, 122
PCIINIT0, 91
PCIINIT1, 91
PCIINITn, 101
PCI-Master Parity Detection, 84
PCI-Master Reads, 83
PCI-Master Writes, 82
PCI RST#, 25, 149
PCISEN, 54
PCISPRI, 54
PC IST S , 105, 10 8
PCISYNC, 9 1
PCI -Target Parity Detection, 87
PCI-Target Reads, 86
PCI-Target Writes, 86
PCIW0, 45
PCIW1, 45
PCIWRST, 98
PCLKIN, 26
PDAR Field s, 46
PDARs, 31, 36, 69
PE, 144
PEN, 142
PERCH, 94
PEREN, 107
PERIN, 96
PERR#, 26
PERSE, 95
Physical Banks, 67
Physical Device Address Registers, 31, 36
physical lo ads o n the memor y b us, 14, 15, 63
Pinout, 198
PLL_STBY, 97
PLL_SYNC, 97
Po we r-Up Re set , 149
PRDERR, 135
PREFETCHABLE, 86, 102, 111
Prefetching, 86
Pref etching on PCI-Maste r Reads, 83
PROGINT, 110
PROM_CL K, 22
PROM_SD, 22
Q
quad word, 19
qword, 19
R
RAS latency, 71
RdRdy #, 38, 40
RDYMODE, 124, 129
RDYSY N, 124, 129
Reference Documents, 19
Release#, 38
REQ64#, 25, 26
Reset, 149
reset, 13
Reset Configuration Signals, 150
Reset Signal Control, 151
Reset#, 22, 38, 149
Resource-Accessibility Summary, 34
Retr ied Reads, 83
REVID , 105, 109
Revision ID Errata, 213
RFERR, 144
RFU9, 45
RFUa, 45
RFUb, 45
RI, 145
RMA, 109
RTA, 10 9
RTS, 1 43
RTYCH, 94
RTYIN, 96
RTYLIM, 93
RTYSE, 95
S
ScCLR#, 38
ScDOE#, 22, 38, 39
ScMatch, 22, 38, 40
Sc TCE#, 38
Sc TDE#, 38
ScTOE#, 38
ScValid# , 38
SDRAM Bank 0, 45
SDRAM Bank 1, 45
SD R AM Ch ip In itializatio n , 68
SDRAM Refresh Control Re gister, 58
SDRAM Refresh Counter Register, 59
SDRAM0, 45, 110
SDRAM1, 45, 110
SDRAMTYP, 72
Secondary Ca che Enabl e, 154
Secondary Ca che in Multi-Controller
Configuration Errata, 214
Secondary Cache Size, 154
Serial Configuration Stream Errata, 213
Serial Mode EEPROM, 152
Serial Port, 3
Serial Port and Registers, 137
Ser ial-Po rt Configura tion an d Monitori ng, 137
Serial-Port Registers, 34, 139
Serial-Port Signals, 29
SERR#, 26
SERREN, 108
Signal Redefinition for Local-Bus Masters,
119
Signal Summary, 21
SIMMs, 68
SIN GLE_PF B, 102
SINGLEFN, 110
SMC, 30
SPACE, 111
SPCE N, 107
SRCINC, 134
SSE, 109
SSID, 106, 111, 154
SSV ID, 106, 111 , 154
STA, 109
Stand-Alone Mode, 13, 16, 17
STB, 142
STOP#, 26
SU, 134
SUBCL, 110
SU BS CW ID, 123, 129
SysAd Flow Control, 39
SysCkRa tio, 154
SysClock, 22, 38
SysCmdP, 38
System Configuration, 37
System Design, 13
T
T0CNTR, 58, 59
T0 CTRL , 58
T0EN, 59
T0PREN, 59
T0 PR SRC, 59
T 0 R LVAL, 58
T0VAL, 59
T1CNTR, 58, 60
T1CTRL, 40, 58, 59
T1EN, 60
T1PREN, 60
T1PRSC, 60
T 1 R LVAL, 59
T1VAL, 60
T2CNTR, 58, 61
T2CTRL, 58, 60, 148
T2EN, 61
T2PREN, 61
T2 PR SRC, 61
T 2 R LVAL, 60
T2VAL, 61
T3CNTR, 58, 62
T3CTRL, 58, 61, 148
T3EN, 61
T3PREN, 61
T3 PR SRC, 61
T 3 R LVAL, 61
T3VAL, 62
TACH, 93
TAIN, 96
TASE, 95
TEMT, 144
TERI, 145
Terminology, 19, 67, 89
TEST#, 30
TEST_SEL, 30
Testing, 190
THRE, 144
Timer Registers, 32, 58
Timers, 3
Timing
Local Bus, 116
Timing Diagrams, 162
TMODE, 40, 51
TmrIntEn, 154
TRDY#, 26
TYPE, 101, 111
U
UART, 3, 137
UART Clocking, 138
UART Divisor Lat c h LSB Register, 140
UART Divisor Lat c h MSB Register, 140
UART Events, 148
UAR T External Clock Errata, 215
UART FIFO Control Register, 141
UART Interrupt Enable Register, 139
UART Interrupt ID Register, 140
UART Line Control Register, 142
UART Line Status Register, 144
UART Modem Control Register, 143
UART Modem Stat us Register, 144
UART Receiver Data Buffer Register, 139
UART Scratch Register, 145
UART Signals, 29
UART Transmitte r Data Holding Register,
139
UART_CTS#, 27, 29
UART_DCD#, 27, 29
UART_DSR#, 29
UART_DTR#, 29
UART_RTS #, 27, 29
UART_RxDRDY#, 29
UART_TxDRDY#, 29
UART_XIN, 27, 29
UARTDLL, 139, 140
UARTDLM, 139, 140
UARTEN, 53
UARTFCR, 139, 141
UARTI ER, 139, 148
UARTI IR, 139, 140
UARTLCR, 139, 142
UARTLSR, 139, 144
UARTMCR, 139, 143
UARTMSR, 139, 144
UAR TPRI, 53
UARTRB R, 139
UARTSCR, 139, 145
UARTTHR, 139
UDATA, 139
UDF, 108
UDRDERR, 135
UFIFOEN, 141
UFIFOEN0, 141
UIID, 141
URESE T, 146
URFRST, 141
URTR, 142
USB, 142
USCR, 145
USP, 142
UTFRST, 141
Utility Signals, 30
V
ValidIn#, 38
ValidOut#, 38
VccOk, 22, 38, 149
VGA, 107
VID, 105, 107
Virtual Banks, 67
VI SPCI, 48
W
Warm Reset, 149
WARMRST, 50, 149
Watchdog Timer, 148
Watchdog Timer Control Register , 61
Watchdog Timer Counter R egister, 62
WCYC, 108
WD OGEN , 53
WDOGPRI, 53
WIDTH, 48
WLS, 142
Wrap type, 68
WrRdy#, 22, 38, 39
X
XmitDatPat, 154