TLE6240GP - Siemens Semiconductors

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Power Semiconductors

Application Note

TLE 6220 / TLE 6230 / TLE 6240 GP

Quad, Octal and 16-fold Smart Power Low-Side Switches for

Automotive Engine Management/Powertrain Applications

by Claus Preuschoff

Introduction

Modern Engine Management/Powertrain Systems call for high integrated intelligent Power

Semiconductors under respect of today’s and tomorrow’s environmental and safety regu-

lations. The enlarging number of loads - from a few milliamperes up to 100 A - must be

driven in a intelligent way in combination with a real time fault monitoring. These require-

ments demand that protection and fault diagnostics be present in the module to keep

emission levels and maintain system reliability.

The new Siemens chip set of multiple channel low-side switches covers all these require-

ments by embedded protection functions and diagnostic feedback via Serial Peripheral

Interface (SPI) in surface-mount packaging with integrated heat slug (Power SO Package)

µC1

RAM

Flash-

EPROM

EEPROM

µC2

Spark Plugs

In je ct o r C o ils

secondary air pum p relay

start relay

climate control relay

alternator

engine speed output

diagnosis lamp

cooling fan relay

canister purge valve

idle speed control

fuel pump relay

camshaft control

lam bda heating

ADC

Digital Signals

Ignition on/off

cam shaft position

vehicle speed

gear se lction

CAN

Analog Signals

Battery voltage

Engine Tem perature

In ta k e Air Te mp .

Air Qu antity

T h rottle p o s ititio n

O xygen sensor

Figure 1. ECU Block Diagram

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1 Overview

Modular concept

To fulfill the different platform requirements the design engineer needs a modular chip

concept for ECU design in order to reduce the time to market. So the new Siemens chip

set of multiple channel low-side switches follows one simple principle:

+ + + If you know one device you know all devices + + +

Coming out with a Quad-, Octal- and a 16-fold channel device with identical key features

an adjustment to specific ECU needs is easily possible. The devices may be used like a

construction set.

SPI

OUT1

OUT4

4 x 0.4 Ω

IN1

IN4

OUT1

OUT4

8 x 1 Ω

SPI

IN1

IN4

OUT5

OUT8

OUT1

OUT8

8 x 1 Ω

SPI

IN1

IN4

OUT9

OUT16

8 x 0.4 Ω

IN9

IN12

Quad

TLE 6220GP

Octal

TLE 6230GP 16-fold

TLE 6240GP

Figure 2 Modular Concept of TLE 62x0 GP Chip Set

Common Features

• Short circuit protection

• Overtemperature protection (selective)

• Overvoltage protection

• Serial Interface for data input and diagnostic output (2 bit per

channel according SPI protocol)

• In addition to the serial control of the outputs it is possible to

control some channels direct in parallel for PWM applications

(see figure 2)

• Parallel inputs high or low active programmable

• General fault flag

• Low quiescent current

• Compatible with 3V micro controllers

• Electostatic discharge (ESD) protection

Power SO Package

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Detailed Block Diagram TLE 6230 GP

All channels can be controlled via serial interface (SPI). In addition to this serial control it is

possible to control channel 1 to 4 direct in parallel with a separate input pin. The input pins

are either high or low active (programmable via PRG-pin).

FAULTRESET

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

Channel 1

IN2

SCLK

IN1

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

IN3

IN4

SPI

Interface

16 bit

Normal functi on

SCB/Overload

Open load

short to ground

&Output Stage

PRG VS

GND

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2 Protection Functi ons and Faul t Detection

Each output is protected by embedded protection functions. Each of the output stages has

its own zener clamp. This causes a overvoltage limitation at the power transistor during

inductive load switch off transients. The outputs are provided with a current limitation set

to minimum of 1A or 3A (TLE 6220 GP: 4 x 3A; TLE 6230 GP: 8 x 1A; TLE 6240 GP: 8 x

1A, 8 x 3A).

2.1 Overload, Short Circuit and Overtemperature Protection

A key design consideration is the device’s ability to handle unsafe current levels. As with

the existing HITFET®, the overload protection - which includes short circuit and overtem-

perature protection - acts in stages. This means that if the internal current limit ID(lim) is ex-

ceeded, the output stage is not switched off immediately, but the current is limited to ID(lim)

and the corresponding bit combination (SPI register) is set (early warning).

The device thus operates in the analogue region, and the voltage between drain and

source increases. This leads to a rise in the chip temperature due to the increasing power

dissipation. To prevent the maximum junction temperature being exceeded, a temperature

sensor of the affected channel switches off the output stage. Thus the device protects it-

self.

2.1.1 Driving a Lamp

For loads with capacitive behaviour, such as a lamp when being switched, the inrush cur-

rent can be eight or ten times the steady state value. The TLE 62xx GP device are well

suited for this applications because of its internal current limitation which increases lamp

operating lifetime. Figure 3 shows the switching of a lamp with a nominal current of around

0.8 A. The ‘inrush current’ here is limited to around 1.3 A.

ID(lim)

ID(NOM)

ID/A

VDS

12V

VIN

inrush

Figure 3 Switching of a Bulb

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The bottom trace on the oscillogram shows the drain-source voltage during switching.

Next to the oscillogram, the output characteristics are shown with the corresponding op-

erating points during the switching operation. Initially the current is limited to ID(lim) for a

voltage of VDS ≈ 8V (inrush). The operating point then moves along the curve in the direc-

tion shown by the arrow, until the nominal current at VDS = ID(NOM) x RON is reached.

2.1.2 Short Circuit Protection

If there is a permanent short circuit and the channel is switched on, the current is only lim-

ited by the internal current limitation (ID(lim)) of the device. This leads to an increasing chip

temperature (depending on the cooling conditions). If the temperature of the chip rises to

170 °C (typ.), the device automatically switches itself off.

The device is designed as 'restart on cooling' type, i.e. the temperature needs only to fall

10 K (typ.) in order for the device to switch back on again. Each channel has its own tem-

perature sensor, i.e. the others continue their operation.

VDS

ID(lim)

VIN

Figure 4 Short Circuit Condition

Figure 4 shows a transition from normal operation (0.8A) into short circuit condition. The

current is limited to ID(lim) and the device shuts off after reaching the 170 °C junction tem-

perature. After cooling down the device restarts automatically (VIN permanent On).

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2.2 Switching of Inductive Loads: Overvoltage Protection

Each channel has an active zener-diode clamp between drain and gate, in order to protect

the device against overvoltage when using inductive loads (e.g. inductors, relays, motors).

When the channel is switched off and the voltage across the inductive load rises above

45V, the zener diode will start to conduct and control the gate, so keeping the MOSFET

on. Compared to Avalanche Breakdown, the switch-off energy in this case is considerably

larger. Figure x displays the switching of a solenoid, clearly showing the point of switching

(change of inductivity).

VIN

VDS

Figure 5 Switching of a Solenoid

A short switch-off time with a large di/dt exists with no chance of damage to the device,

due to the active zener diode clamp.

Application Example:

The switching-off of a relay is a typical exam-

ple for demonstrating the inductive overvolt-

age behaviour. If one channel is used to drive

a relay, no external free-wheeling diode is

necessary, as VDS is limited by the device

itself.

This overvoltage protection function does not

require a supply voltage.

Channel x

VBB

Gate D

Figure 6 Driving a relay

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The mentioned faults in the previous chapter (overload, short circuit, overtemperature)

would influence the lifetime of the device, if there would be no protection against them.

There are other faults which may occur without stress for the device, but strong negative

influence on the application and on emission levels. These faults are "open load” and

"short circuit to ground”.

3 Fault Detection

There are four different conditions each channel can work, which the driving microcontrol-

ler must be able to distinguish definitely.

3.1 Overload (OV), Short circuit to battery (SCB) or Overtemperature

Overload or short to battery do only stress the device in ON-state.

As soon as the current limit ID(lim) is reached the bit combination HL

(s. diagnosis chapter) is set as an "early warning” for an operating

condition, which may lead to an overtemperature.

I. e. when an incandescent load is switched on and the current is

limited only temporarily, HL is reported as early warning. If there is

a permanent overload or short circuit and the junction reached

170°C the device protects itself and switches the affected channel

off until the junction temperature has decreased.

3.2 Open load (OL)

The open load test is performed in OFF-state. A current source is applied to the drain to

pull the output below the threshold of the open load reference voltage which is typ. 3V ac-

cording data sheet. LH bit combination is set.

Remark

If there is an open load condition and the channel is switched on,

no fault is recognized.

⇒ For ”open load” detection the respective channel

has to be switched off for t ≥ tD(fault) = 100µs typ.

ID ≥ ID(lim)

⇒ OV, SCB

VBat

VDS < 3V

⇒ open load

VBat

≈

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3.3 Short to Ground (SCG)

Short to ground condition is also detected in off state.

If the mentioned current source pulls VDS below a second threshold (2V typ.) SCG is de-

tected and the respective bit combination LL is set.

Remark

If the channel is switched on during a SCG condition no fault is

detected.

⇒ For SHG detection the respective channel has to be

switched off for t ≥ tD(fault) = 100µs typ.

3.3.1 Open load and short to ground; Influence on the application

In off-state and normal condition (no fault) the drain-source voltage VDS = VBat. So a de-

creasing drain-source voltage is an appropriate method for open load detection.

Using two different thresholds is a good idea for distinction. It is described in the following.

3.3.2 Influence on application

In Engine Management/Powertain application an injector is a typical load. The influence

on the application at open load or short to ground condition is shown in the following fig-

ures.

It is evident, that a wrong fault detection in this application is not allowed, so another key

design consideration is the device ability to distinguish definitely between open load and

short to ground condition.

VBat

VDS < 2V ⇒ SCG

VBat

VDS < 2V ⇒ SCG

Injection in on- and off-state

⇒ danger of catalyst damage

VDS < 3V

⇒ open load

VBat

≈

No injection, neither in on-, nor in off-state

⇒ The engine operates with 3 cylinders,

”Limp-home to the workshop” is possible

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3.3.3 Realisation in practice

Open load

In case of an open load condition the drain voltage decreases so the diode starts to con-

duct and the internal current source is able to pull the drain down. This starting current

flow causes a voltage drop at R. When the VDS reaches the open load detection voltage

VDS(OL) = 3V (typ.) open load is detected and latched into the fault register.

VBat

VDS ≈ 3V ⇒ OL

100µ

Short to ground

In difference to the open load condition the drain must be pulled down actively. This exter-

nal short circuit must enable a current from at least -100 µA outside the drain. This short

to ground detection current is measured internally and the corresponding fault register is

set. When this current threshold is reached VDS(SCG) = 2V (typ.) is measurable at the drain.

VBat

ISCG = -100µA ⇒ SCG

100µ

SCG

3.4 Normal function

If there is no fault and the device is within its operational range, it works under normal

function conditions. HH-bit combination is set in ON-state as well as in off-state.

Remark

Normal function is also reported, although there is an overload or short circuit condition,

but the respective channel is switched off.

⇒ ID(lim) is not reached → no stress for the device

Normal function is also reported, although there is an open load or short to ground condi-

tion but the respective channel is switched on.

⇒ OL, SHG-condition are only recognised in off-state

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Operation condition Detection in

Off-state On-state

Bit combination

Normal function X

with no fault X

with no fault

with OV, SCB X

with OL, SCG

Overload (OV), SCB, Overtemperature X HL

Open load (OL) X LH

Short to ground (SCG) X LL

Table 1 Status detection in different operation modes

4 Serial Per i pheral Interface (SPI) for Output Stage Control and Di-

agnostic Feedback

The TLE 6220, 6230, 6240 GP provide a serial peripheral interface (SPI) to control the

power DMOS switches, as well as diagnostic feedback.

The serial interface consists of a chip select (

), serial clock (SCLK), serial data input

(SI) and a serial data output (SO). To enable serial data transfer, the CS is brought low

while SCLK is low. At this time the current fault status (two bits per channel) are loaded

into the shift register. As each of the consecutive rising edges of SCLK occurs, the state of

the SI pin will be clocked into the device. Simultaneously at each rising clock, the diagnos-

tic information is output on the SO pin. Figure 7 shows the cyclic serial data transfer.

SCLK

Figure 7 Cyclic serial data transfer via SPI

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The features, the behaviour, protection function described up to now are valid f or all three

devices, the TLE 6220, 6230, 6240 GP.

The octal switch (TLE 6230 GP) is now used to describe the output stage control and the

diagnostic feedback in principle.

4.1 Output Stage Control (TLE 6230 GP)

Each output is independently controlled by an output latch and a common reset line, which

disables all outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A

logic high input ’data bit’ turns the respective output channel ON, a logic low ’data bit’ turns

it OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high

transition of CS transfers the serial data input bits to the output control buffer.

The input data consist of two bytes- a control byte and a data byte. The control byte is

used to program the device, to operate it in a certain. The eight data bits contain the input

information for the eight channels, and are high active.

4.1.1 Parallel Control for Channel 1 to 4

In addition to the serial control of the outputs it is possible to control channel 1 to 4 directly

in parallel for PWM applications.

A Boolean AND operation is performed on each of the parallel inputs and respective SPI

data bits, in order to determine the states of the respective outputs.

The parallel inputs are high or low active depending on the PRG pin. If the parallel input

pins are not connected (independent of high or low activity) it is guaranteed that the out-

puts 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not con-

nected.

PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active

PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.

The AND operation implies that the output can be switched off by the SPI data bits, even if

the corresponding parallel input is in the ON state.

⇒ SPI Priority for OFF-state

This also implies that the serial input data

bit can only switch the output channel ON if

the corresponding parallel input is in the

ON state.

&Output

Driver

IN 1...4

Serial Input,

data bits 0...3

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Due to the AND operation the

respective serial data bits must

be programmed to high level to

enable parallel control.

Figure 8 shows the serial data

transfer. Channel 5 to 8 are

programmed off, channel 1 to 4

on.

Figure 9 shows the parallel

control of channel 1 to 4 with

the software tool of the evalua-

tion board. Frequency and

Duty Cycle are adjustable. In

practice a µC-Port drives the

four inputs to react in real time

on different events.

Figure 10 shows the output

voltages of channel 1 to 4 dur-

ing parallel control with inductive

loads. The output voltage in-

creases after shut off until the

internal clamp gets active.

SCLK

Control Byte

Ch 8-5 off Ch 4-1 on

Figure 8 Data bits 0 to 3 are programmed high to

enable the parallel control for channel 1 to 4.

Figure 9 Parallel control via software tool

Figure 10 Output voltages of channel 1 to 4

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4.1.2 Serial control of the outputs

As mentioned above, the serial input byte consists of a control byte and a data byte. Via

the control word, the specific mode of the device is programmable.

MSB LSB

44344214434421Bits DataBits Control

DDDDDDDDCCCCCCCC : Serial input byte

Two specific control words are recognised (for TLE 6230 GP), having the following func-

tions:

No. Serial Input Byte Function

1 LLLL LLLL XXXX XXXX Only ’Full Diagnosis’ performed. No change to output

states.

2 HHHHHHHH DDDDDDDD IN1...4 and serial data bits ’AND’ed. ’Full Diagnosis’

performed.

Note: ’X’ means ’don’t care’, because this bit will be ignored

’D’ represents the data bit, either being H (=ON) or L (=OFF)

1. LLLLLLLL XXXXXXXX - Diagnosis only

By clocking in this control byte, it is possible to get pure diagnostic information (two bits

per channel) in accordance with the diagnosis chapter. The data bits are ignored, so that

the state of the outputs are not influenced. This command is only active once unless the

next control command is again "Diagnosis only". ⇒ Diagnostic information can be read out

at any time with no change of the switching conditions.

2. HHHHHHHH DDDDDDDD - AND operation, and ‘full diagnosis’

With HHHHHHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with

the corresponding data bits. Full diagnosis (2 bits per channel) is performed.

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4.2 Diagnostics

As mentioned previously, the TLE 62x0 GP devices provide on-board diagnostics to iden-

tify load problems for detailed fault detection. The four operation conditions that can be

detected are

• normal function

• overload/short to battery/overtemperature

• open load

• short to ground

As soon as an error occurs, the error information is latched into the diagnosis register and

a falling edge is generated at theFAULT pin.

4.2.1 Diagnostic via FAULT - pin

The general fault pin (open drain) shows a high to low transition as soon as an error oc-

curs for any one of the channels. This fault indication can be used to generate a µ C inter-

rupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication.

This saves processor time compared to a cyclic reading of the SO information.

For definite fault detection, an error must exist longer than td(fault) = 100 µ s (typ.). This fault

delay time is necessary to filter spikes, transitions, ... in order to avoid false error detec-

tion. Figure 11 shows an arising open load condition at channel 1. The error is detected

and latched, when it lasts longer than 100 µs. The previous oscillations - generated by a

bouncing contact – are filtered and not detected. The arrow shows the real beginning of

the open load condition.

VDS1

FAULT

Figure 11 Fault detection via FAULT pin

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Figure 12 shows the FAULT- signal during the occurrence of an open load condition

(arrow) and the CS low to high transition. After the fault delay time td(fault), the FAULT-

signal transits to low until CS rising edge. The chip select low to high transition clears all

error register and resets the FAULT- signal to high. The error is still present and is latched

in the fault register. The FAULT- signal again goes to low. Remark:

The SO line shows the

status information which

was valid at CS falling

edge. At that time there

was no fault condition,

so normal function for all

channels was trans-

ferred into the shift regis-

ter. The open load con-

dition for channel 1 can

be clocked out with the

next CS cycle even

when it disappears in the

meantime.

⇒ A new error over-

writes the old error re-

port but normal function

can’t overwrite any exist-

ing error. On ly the rising

edge of CS resets the

fault register.

4.2.2 Diagnostics via SO line

The FAULT line indicates the occurrence of an error. For a detailed analysis – under re-

spect of emissions levels - the system microcontroller needs to know, which channel

(load) is eff e cted and what kind of error has occurred. This detailed diagnostic information

is performed by the serial data output (SO) line according to Figure 13.

Diagnostic Serial Data O ut SO

HH Normal function

HL Overload, Shorted Load or Overtemperature

LH Open Load

LL Shorted to Gr ound

Ch.8 Ch.7 Ch.6 Ch.5

15 14 13 12 11 10 9 8 - - - - -

Figure 13 Two bits per channel diagnostic feedback

VDS1

FAULT

Figure 12

Fault detection via FAULT pin during CS rising edge

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With the falling edge of CS the diagnostic status information is transferred into the shift

ceives a LOW signal, all diagnosis bits can be shifted out serially. The rising edge of CS

will reset all error registers. Figure 14 shows the TLE 6230 GP controlled by the software

tool of the evaluation

board. The oscillogram

shows the generated

signals CS, SCLK, SI

and the SO-response of

the device. The SO-line

indicates normal function

for all channels and is tri-

stated before and after

CS cycle.

The control byte is pro-

grammed to FFhex, i.e.

AND operation and full

diagnosis is performed.

Due to the AND opera-

tion the parallel inputs

must be set to high

Figure 14 Oscillogram and software evaluation of serial control and diagnosis

SCLK

3-state

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(PRG-pin = high assumed) to enable the serial control for channel 1 to 4. The program

illustrates SI and SO and the state of the parallel inputs. For every channel normal func-

tion is recognised.

Detection of different errors

Figure 15 shows the detec-

tion of different fault condi-

tions. The input pattern is the

same like before but only

channel 1, 4 and 7 operate

with normal function.

Channel 8, 6: open load

Channel 5, 3: overload

Channel 2:short to ground

These errors are detected

and displayed accordingly.

Figure 15 Oscillogram and software display of different errors

SCLK

L H H H L H H L H H H L L L H H

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Diagnosis only

To check the diagnostic information of all channels with no change of its state, ”diagnosis

only” can be programmed as control word. Then all data bits will be ignored, i.e. the state

of channels 5 to 8 is

not influenced, chan-

nels 1 to 4 can con-

tinue in PWM-mode

depending on the

parallel control inputs.

Figure 16 illustrates

this operation mode.

The control byte is

programmed to 00hex.

The visible data bits

will be ignored.

Figure 16 Oscillogram and software display with diagnosis only command

control byte set to 00hex

SCLK

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5 Thermal and Power Consi der ations

The TLE 62x0 G family has demonstrated its effectiveness in serial data transfer and

driving various types loads, serial as well as parallel. The thermal and power considera-

tions are also of interest. The devices are available in surface-mount Power SO packages

to reduce thermal resistance when mounted to a copper-clad circuit board. Using 6 cm2

copper area a thermal resistance RthJA of 35 K/W can be achieved.

The maximum power dissipation for the device in this example is determined as follows:

Assume a maximum ambient temperature (TA) of 125 °C. Then with the maximum junc-

tion temperature (TJ) of 150 °C:

PD = (TJ- TA)/RthJA = 25/35 = 0.714 W for the device.

If the devices are mounted on Isolated Metal Substrate (IMS) a thermal resistance of 7 to

10 K/W can be achieved.

PD = (TJ- TA)/RthJA = 25/7 = 3.5 W for the device

Power SO 36 mounted on IMS

IMS

RthJA = 7 - 10 K/W

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6 Engine Management Application

Figure 17 shows the TLE 6230 GP in combination with the TLE 6240 GP (16-fold switch)

for relays and general purpose loads and the TLE 6220 GP (quad switch) to drive the in-

jector valves. This arrangement covers the numerous loads to be driven in a modern En-

gine Management/Powertrain system. From 28 channels in sum 16 can be controlled di-

rect in parallel for PWM applications.

7 Conclusion

The TLE 62x0 GP family are integrated multiple channel low-side switches which combine

both; power and logic in a single package. In addition, the devices feature on-board fault

diagnostics for detailed error detection (2 bit per channel) to reduce down time and in-

crease system reliability. The thermally enhanced power package increases the power

capability of the devices and the ”construction set” (4/8/16-fold) provides m o re flexibility f o r

design engineers to incorporate the TLE 6220, 6230, 6240 GP into their system solution.

CLK

MTSR

MRST

CLK

P x.y

P x.1-4

P x.y

P x.1-4

µC

C167

4 PWM

Channels

4 PWM

Channels

Injector 1

Injector 2

Injector 3

Injector 4

TLE

6220 GP

Quad

TLE

6230 GP

Octal

CLK

8 PWM

Channels

TLE

6240 GP

16-fold

P x.y

P x.1-8

Canister purge valve

Fuel pump (relay)

Engine speed output

Throttle position output

Exhaust gas recirculation valve

Secondary air valve

climate control (relay)

Alternator load (relay)

Ma in rela y

Malfunction indicator lamp

Cooling fan (relay)

Start relay

Figure 17 Engine Management Application with the TLE 6220/6230/6240 GP