Digitally Programmable Delay Units scenes: pou-13256F (8-Bit) TTL Interfaced Features: g Input & output TTL buffered m 8-BIT TTL programmable delay line m Two (2) separate outputs; inverting & non-inverting mg Completely interfaced m Compact & low profile Specifications: w@ Delay variation: Monotonic in one direction. @ Programmed delay tolerance: +5% or 2 ns whichever ts greater. a Inherent delay (Too): 15 ns on pin 6 18 ns on pind a Propagation delay: Address to output (Tsua) 12 ns typ. Enable to output (TsuE) 12 ns typ. m Power dissipation: .95 w max. uw Supply voltage: 5 Vdc + 5%, m Operating temperature: 0-70'C. mw Temperature coefficient: 100 PPM/C. a DOC parameters: See TTL-Fast Schottky Logic Table on Page 6. typical Test Conditions: g Input pulse-width: 2150% of Max. delay. a Input pulse spacing: 23 times of Max. delay. a Input pulse voltage: TTL logic. mg Measurements taken @ Ja= 25C; Vcc = 5V. = Mee Leary [~ ADRESS | Vp sas? at = 1.800 eon we ew 2h 484 42h 41] 35] 36} 33} 30] ss] I 1-506 2 Vee qn tedoey a ! 1.400 ee I i 1.300 i: | - _ 5 ouT 75 TYP oo " DS DELAY ip on O75 TYP ae 600 - ; ~ so ] oo tieatl | NETWORK ls | D [or SEa4 Al Pf tle S8K8 | Saeco tore . 2.450 | TRUTH TABLE Address (Bit No.) 68)}7,6/5 |4 4,3 | 2 [1 | Enable | Delay Out (E,) O;OTOFO]oOFOTOTO 0 Ty O;o;ToT;foy;,ofroyo}t 0 T, oloftololotlotito 0 T, incremental Delay Total Programmed olololtolololila 0 T; Part No. Per Step (ns) Delay (ns) olololololy oto 0 T PDU-13256F-.5 St 3 1275 olololalol: 1 1 0 r PDU-13256F-1 14 5 255 olololols ololo 0 os PDU-13256F-2 24 6 510 8 PDU-13256F-3 A o7To};o;]o] 1 1 1 1 0 Tis 2s ze PDU-13256F-4 4 2410 1,020 clololi+afolotole 0 Tye PDU-13256F-5 5 16 1,275 olololitsata]ad3 0 Toy PDU-13256F-6 6 415 1,536 ololi ololotolo 0 Tro PDU-13256F-7 7.215 1,785 Oo] 0O]1 1 1 1 1 1 0 To PDU-13256F-8 8 20 2,040 PDU-13256F-9 9 20 2,295 0 1 o;O0O;oTO]O; 0 0 To PDU-13256F-10 10 20 2,550 0 1 1 1 1 1 1 1 0 Tyo7 1 Oo7OT;TO];]OTFTOTOTO 0 Tro 1 1 1 1 1 1 4 1 0 Toss NOTE: 1. Forthe sake of simplicity all 256 programmable steps are not shown in this truth table 0 q ) ) o 6 0 6 1 1 2. After Bit 6, the incremental delay tolerance is 5% of 0 Logic 0 1 Logic 1 0 Dont care. Programmed delay Ty Reference or inherent delay of unit. T, T,5, Multiplier of incremental delay. 3 Mt. Prospect Avenue, Clifton. New Jersey 07013 @ (201) 56 773-2299 m FAX (201) 773-9672