CY7C024AV
CY7C025AV
CY7C026AV
3.3 V, 4K/8K/16K × 16 Dual-Port
Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06052 Rev. *T Revised August 1, 2017
3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM
Features
■True dual-ported memory cells which enable simultaneous
access of the same memory location
■4, 8 or 16K × 16 organization
(CY7C024AV/025AV/026AV)
■0.35 micron CMOS for optimum speed and power
■High speed access: 20 ns and 25 ns
■Low operating power
❐Active: ICC = 115 mA (typical)
❐Standby: ISB3 = 10 A (typical)
■Fully asynchronous operation
■Automatic power down
■Expandable data bus to 32 bits or more using Master and Slave
chip select when using more than one device
■On chip arbitration logic
■Semaphores included to permit software handshaking
between ports
■INT flag for port-to-port communication
■Separate upper byte and lower byte control
■Pin select for Master or Slave (M/S)
■Commercial and industrial temperature ranges
■Available in 100-pin Pb-free TQFP and 100-pin TQFP
Functional Description
The CY7C024AV/025AV/026AV consist of an array of 4K, 8K, and
16K words of 16 bits each of dual-port RAM cells, IO and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory.
To handle simultaneous writes and reads to the same location, a
BUSY pin is provided on each port. Two Interrupt (INT) pins can be
used for port to port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin, the
devices can function as a master (BUSY pins are outputs) or as a
slave (BUSY pins are inputs). They also have an automatic power
down feature controlled by CE. Each port has its own output enable
control (OE), which enables data to be read from the device.
For a complete list of related resources, click here.
Selection Guide
Parameter CY7C024AV/025AV/026AV
-20
CY7C024AV/025AV/026AV
-25 Unit
Maximum Access Time 20 25 ns
Typical Operating Current 120 115 mA
Typical Standby Current for ISB1
(Both ports TTL Level)
35 30 mA
Typical Standby Current for ISB3
(Both ports CMOS Level)
10 10 A
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 2 of 24
R/W
L
OE
L
IO
8L
–IO
15L
IO
Control
Address
Decode
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
BUSY
L
IO
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
IO
0L
–IO
7L
R/W
R
OE
R
IO
8L
– IO
15R
CE
R
UB
R
LB
R
IO
0L
– IO
7R
UB
L
LB
L
A
0L
–A
11/1213L
True Dual-Ported
RAM Array
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode A
0R
–A
11/12/13R
[1] [1]
[2] [2]
[4] [4]
12/13/14
8
8
12/13/14
8
8
12/13/14 12/13/14
[3]
[3]
[3]
[3]
Logic Block Diagram
Notes
1. IO8–IO15 for × 16 devices
2. IO0–IO7 for × 16 devices
3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 3 of 24
Contents
Pin Configurations ........................................................... 4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Write Operation ...........................................................6
Read Operation ........................................................... 7
Interrupts ..................................................................... 7
Busy ............................................................................7
Master/Slave ...............................................................7
Semaphore Operation ................................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics .................................................9
Capacitance .................................................................... 10
AC Test Loads and Waveforms .....................................10
Data Retention Mode ......................................................10
Timing .............................................................................. 10
Switching Characteristics ..............................................11
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 19
4K × 16 3.3 V Asynchronous Dual-Port SRAM ......... 19
8K × 16 3.3 V Asynchronous Dual-Port SRAM ......... 19
16K × 16 3.3 V Asynchronous Dual-Port SRAM ....... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 4 of 24
Pin Configurations
Figure 1. 100-pin TQFP pinout (Top View)
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A5L
A4L
INT
L
A2L
A0L
BUSY
L
GND
INT
R
A0R
A1L
NC
NC
NC
NC
IO 10L
IO 11L
IO 15L
VCC
GND
IO 1R
IO 2R
VCC
9091
A3L
M/S
BUSY
R
IO 14L
GND
IO 12L
IO 13L
A1R
A2R
A3R
A4R
NC
NC
NC
NC
IO 3R
IO 4R
IO 5R
IO 6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
IO 9L
IO 8L
IO 7L
IO 6L
IO 5L
IO 4L
IO 3L
IO
2L
GND
IO 1L
IO 0L
OEL
SEML
V
CC
CEL
UBL
LBL
NC
A11L
A10L
A9L
A8L
A7L
A6L
IO 0R
IO 7R
IO
8R
IO
9R
IO
10R
IO 11R
IO 12R
IO 13R
IO 14R
GND
IO
15R
ŒR
R\WR
GND
SEMR
CER
UBR
LBR
NC
A
11R
A10R
A
9R
A
8R
A
7R
A6R
A5R
CY7C024AV (4K × 16)
R/
W
L
[5]
[6]
CY7C025AV (8K × 16)
Notes
5. A12L on the CY7C025AV.
6. A12R on the CY7C025AV.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 5 of 24
Figure 2. 100-pin TQFP pinout (Top View)
Pin Configurations (continued)
IO
IO
IO
IO
IO
IO
IO
IO
G
IO
O
R
G
SE
C
U
N
A
A
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
NC
A6L
A5L
A4L
INT
L
A2L
A0L
GND
M/
S
A0R
A1R
A1L
A3L
BUSY
R
INT
R
A2R
A3R
A4R
A5R
NC
NC
NC
BUSY
L
58
57
56
55
54
53
52
51
CY7C026AV (16K × 16)
NC
NC
NC
NC
IO10L
IO11L
IO15L
IO13L
IO14L
GND
IO0R
VCC
IO3R
GND
IO12L
IO1R
IO2R
IO4R
IO5R
IO6R
NC
NC
NC
NC
VCC
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
IO9L
IO8L
IO7L
IO6L
IO5L
IO4L
IO0L
IO2L
IO1L
VCC
R/
WL
UB
L
LB
L
GND
IO3L
SEM
L
CE
L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
OE
L
34 35 36 424139 403837 43 44 45 5048 494746
A6R
A7R
A8R
A9R
A10R
A11R
CE
R
A13R
UB
R
GND
R/
WR
GND
IO14R
LB
R
A12R
OE
R
IO15R
IO13R
IO12R
IO11R
IO10R
IO9R
IO8R
IO7R
SEM
R
3332313029282726
Pin Definitions
Left Port Right Port Description
CELCERChip Enable
R/WLR/WRRead and Write Enable
OELOEROutput Enable
A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K)
IO0L–IO15L IO0R–IO15R Data Bus Input and Output
SEMLSEMRSemaphore Enable
UBLUBRUpper Byte Select (IO8–IO15 for × 16 devices)
LBLLBRLower Byte Select (IO0–IO7 for × 16 devices)
INTLINTRInterrupt Flag
BUSYLBUSYRBusy Flag
M/S Master or Slave Select
VCC Power
GND Ground
NC No Connect
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 6 of 24
Functional Overview
The CY7C024AV/025AV/026AV are low power CMOS 4K, 8K, and
16K × 16 dual port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory. The devices can be used as standalone
16-bit dual port static RAMs or multiple devices can be combined to
function as a 32-bit or wider master and slave dual port static RAM.
An M/S pin is provided for implementing 32-bit or wider memory
applications. It does not need separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual port video and graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared latches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE) pin.
The CY7C024AV/025AV/026AV are available in 100-pin Pb-free
Thin Quad Flat Pack (TQFP) and 100-pin TQFP.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of RW to guarantee a valid write. A write operation is controlled
by either the RW pin (see Figure 7 on page 14) or the CE pin (see
Figure 8 on page 14). Required inputs for non-contention
operations are summarized in Ta b l e 1.
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the data
read is not deterministic. Data is valid on the port tDDD after the
data is presented on the other port.
Table 1. Non-Contending Read/Write
Inputs Outputs Operation
CE R/W OE UB LB SEM IO8–IO15 IO0–IO7
H X X X X H High Z High Z Deselected: Power Down
X X X H H H High Z High Z Deselected: Power Down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write DIN0 into Semaphore Flag
X X H H L Data In Data In Write DIN0 into Semaphore Flag
L X X L X L Not Allowed
L X X X L L Not Allowed
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 7 of 24
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user wants to access a semaphore flag, then the
SEM pin and OE must be asserted.
Interrupts
The upper two memory locations are for message passing. The
highest memory location (FFF for the CY7C024AV, 1FFF for the
CY7C025AV, 3FFF for the CY7C026AV) is the mailbox for the
right port and the second highest memory location (FFE for the
CY7C024AV, 1FFE for the CY7C025AV, 3FFE for the
CY7C026AV) is the mailbox for the left port. When one port
writes to the other port’s mailbox, an interrupt is generated to the
owner. The interrupt is reset when the owner reads the contents
of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Busy
The CY7C024AV/025AV/026AV provide on-chip arbitration to
resolve simultaneous memory location access (contention). If both
ports’ CEs are asserted and an address match occurs within tPS of
each other, the busy logic determines which port has access. If tPS
is violated, one port definitely gains permission to the location, but it
is not predictable which port gets that permission. BUSY is asserted
tBLA after an address match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin helps to expand the word width by configuring the
device as a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This enables the
device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin enables the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) [7]
Left Port Right Port
Function R/WLCELOELA0L–13LINTLR/WRCEROERA0R–13R INTR
Set Right INTR Flag L L X FFF [8] XXXX X L
[9]
Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H[10]
Set Left INTL Flag XXX X L
[10] L L X FFE (or 1/3FFE) X
Reset Left INTL Flag X L L FFE [8] H[9] XXXXX
Notes
7. See Functional Overview on page 6 for specific highest memory locations by device.
8. See Functional Overview on page 6 for specific addresses by device.
9. If BUSYL = L, then no change.
10. If BUSYR = L, then no change.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 8 of 24
Semaphore Operation
The CY7C024AV/025AV/026AV provide eight semaphore
latches, which are separate from the dual port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for tSOP before attempting to read the semaphore.
The semaphore value is available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource.
Otherwise (reads a one), it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and RW are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Tab le 3 shows sample semaphore opera-
tions.
When reading a semaphore, all 16 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one of them. But there is no guarantee which side
controls the semaphore.
Table 3. Semaphore Operation Example
Function IO0–IO15 Left IO0–IO15 Right Status
No action 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 9 of 24
Maximum Ratings
Exceeding maximum ratings [11] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State .................................... –0.5 V to VCC + 0.5 V
DC Input Voltage [12] ........................... –0.5 V to VCC + 0.5 V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ........................................ > 2001 V
Latch-up Current ................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0 °C to +70 °C 3.3 V 300 mV
Industrial [13] –40 °C to +85 °C 3.3 V 300 mV
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C024AV/025AV/026AV
Unit-20 -25
Min Typ Max Min Typ Max
VOH Output HIGH Voltage (VCC = Min,
IOH = –4.0 mA)
2.4– –2.4– –V
VOL Output LOW Voltage (VCC = Min,
IOH = +4.0 mA)
– –0.4– –0.4V
VIH Input HIGH Voltage 2.0 – – 2.0 – – V
VIL Input LOW Voltage –0.3 [14] –0.8 –0.8V
IOZ Output Leakage Current –10 – 10 –10 – 10 A
IIX Input Leakage Current –10 – 10 –10 – 10 A
ICC Operating Current
(VCC = Max., IOUT = 0 mA)
Outputs Disabled
Commercial – 120 175 – 115 165 mA
Industrial [13] – 135 185 mA
ISB1 Standby Current
(Both Ports TTL Level)
CEL & CER VIH, f = fMAX
Commercial 35 45 30 40 mA
Industrial [13] –4050mA
ISB2 Standby Current
(One Port TTL Level)
CEL | CER VIH, f = fMAX
Commercial 75 110 65 95 mA
Industrial [13] –75105mA
ISB3 Standby Current
(Both Ports CMOS Level)
CEL & CER VCC 0.2 V, f = 0
Commercial 10 500 10 500 A
Industrial [13] –10500A
ISB4 Standby Current
(One Port CMOS Level)
CEL | CER VIH, f = fMAX [15]
Commercial 70 95 60 80 mA
Industrial [13] –7090mA
Notes
11. The voltage on any input or IO pin cannot exceed the power pin during power up.
12. Pulse width < 20 ns.
13. Industrial parts are available in CY7C024AV, CY7C025AV & CY7C026AV.
14. VIL > –1.5V for pulse width less than 10ns.
15. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 10 of 24
Data Retention Mode
The CY7C024AV/025AV/026AV are designed for battery backup.
Data retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70 percent of VCC
during the power up and power down transitions.
3. The RAM can begin operation > tRC after VCC reaches the
minimum operating voltage (3.0 V).
Capacitance
Parameter [16] Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz, VCC = 3.3 V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.0 V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 590
3.3 V
OUTPUT
R2 = 435
C= 30pF
VTH = 1.4 V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1 = 590
R2 = 435
3.3 V
OUTPUT
C= 5pF
RTH = 250
including scope and jig)
(Used for tLZ, tHZ, tHZWE, and tLZWE
Timing
Parameter Test Conditions [17] Max Unit
ICCDR1 at VCCDR = 2 V 50 A
Notes
16. Tested initially and after any design or process changes that may affect these parameters.
17. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 11 of 24
Switching Characteristics
Over the Operating Range
Parameter [18] Description
CY7C024AV/CY7C025AV/CY7C026AV
Unit-20 -25
Min Max Min Max
Read Cycle
tRC Read Cycle Time 20 –25 –ns
tAA Address to Data Valid –20 –25 ns
tOHA Output Hold From Address Change 3 – 3 – ns
tACE[19] CE LOW to Data Valid –20 –25 ns
tDOE OE LOW to Data Valid –12 –13 ns
tLZOE[20, 21, 22] OE Low to Low Z 3 – 3 – ns
tHZOE[20, 21, 22] OE HIGH to High Z –12 –15 ns
tLZCE[20, 21, 22] CE LOW to Low Z 3 – 3 – ns
tHZCE[20, 21, 22] CE HIGH to High Z –12 –15 ns
tPU[22] CE LOW to Power Up 0 – 0 – ns
tPD[22] CE HIGH to Power Down –20 –25 ns
tABE[19] Byte Enable Access Time –20 –25 ns
Write Cycle
tWC Write Cycle Time 20 –25 –ns
tSCE[19] CE LOW to Write End 15 –20 –ns
tAW Address Valid to Write End 15 –20 –ns
tHA Address Hold From Write End 0 – 0 – ns
tSA[19] Address Setup to Write Start 0 – 0 – ns
tPWE Write Pulse Width 15 –20 –ns
tSD Data Setup to Write End 15 –15 –ns
tHD Data Hold from Write End 0 – 0 – ns
tHZWE[21, 22] R/W LOW to High Z –12 –15 ns
tLZWE[21, 22] R/W HIGH to Low Z 3 – 0 – ns
tWDD[23] Write Pulse to Data Delay –45 –50 ns
tDDD[23] Write Data Valid to Read Data Valid –30 –35 ns
Notes
18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
19. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tACE/tSCE time.
20. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
21. Test conditions used are Load 3.
22. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 16.
23. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 16.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 12 of 24
Busy Timing [24]
tBLA BUSY LOW from Address Match –20 –20 ns
tBHA BUSY HIGH from Address Mismatch –20 –20 ns
tBLC BUSY LOW from CE LOW –20 –20 ns
tBHC BUSY HIGH from CE HIGH –17 –17 ns
tPS Port Setup for Priority 5 – 5 – ns
tWB R/W HIGH after BUSY (Slave) 0 – 0 – ns
tWH R/W HIGH after BUSY HIGH (Slave) 15 –17 –ns
tBDD[25] BUSY HIGH to Data Valid –20 –25 ns
Interrupt Timing [24]
tINS INT Set Time –20 –20 ns
tINR INT Reset Time –20 –20 ns
Semaphore Timing
tSOP SEM Flag Update Pulse (OE or SEM)10 –12 –ns
tSWRD SEM Flag Write to Read Time 5 – 5 – ns
tSPS SEM Flag Contention Window 5 – 5 – ns
tSAA SEM Address Access Time –20 –25 ns
Switching Characteristics (continued)
Over the Operating Range
Parameter [18] Description
CY7C024AV/CY7C025AV/CY7C026AV
Unit-20 -25
Min Max Min Max
Notes
24. Test conditions used are Load 2.
25. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 13 of 24
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [26, 27, 28]
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [26, 29, 30]
Figure 6. Read Cycle No. 3 (Either Port) [26, 28, 29, 30]
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
OE
CE and
LB or UB
CURRENT
UB or LB
DATA OUT
tRC
ADDRESS
tAA tOHA
CE
tLZCE
tABE
tHZCE
tHZCE
tACE
tLZCE
Notes
26. R/W is HIGH for read cycles.
27. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
28. OE = VIL.
29. Address valid prior to or coincident with CE transition LOW.
30. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 14 of 24
Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [31, 32, 33, 34]
Figure 8. Write Cycle No. 2 (CE Controlled Timing) [31, 32, 33, 39]
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
[37]
[37]
[34]
[35, 36]
NOTE 38 NOTE 38
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
[35, 36]
Notes
31. R/W or CE must be HIGH during all address transitions.
32. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
33. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
34. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to enable the IO drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified tPWE.
35. To access RAM, CE = VIL, SEM = VIH.
36. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
37. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
38. During this period, the IO pins are in the output state, and input signals must not be applied.
39. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 15 of 24
Figure 9. Semaphore Read after Write Timing, either side [40]
Figure 10. Timing Diagram of Semaphore Contention [41, 42, 43]
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS VALID ADRESS
tHD
DATAIN VALID DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
IO 0
SEM
A0–A 2
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEM R
Notes
40. CE = HIGH for the duration of the above timing (both write and read cycle).
41. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH.
42. Semaphores are reset (available to both ports) at cycle start.
43. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 16 of 24
Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [44]
Figure 12. Write Timing with Busy Input (M/S = LOW)
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
tPWE
R/W
BUSY
tWB tWH
Note
44. CEL = CER = LOW.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 17 of 24
Figure 13. Busy Timing Diagram No.1 (CE Arbitration) [45]
Figure 14. Busy Timing Diagram No.2 (Address Arbitration) [45]
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValid First:
ADDRESS L,R
BUSY
R
CEL
CER
BUSYL
CER
CE L
ADDRESSL,R
CELValid First
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY L
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
Left Address Valid First:
Note
45. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 18 of 24
Figure 15. Interrupt Timing Diagram
Switching Waveforms (continued)
WRITE FFF (OR 1/3FFF)
tWC
Right Side Clears INTR:
tHA
READ FFF
tRC
tINR
WRITE FFE (OR 1/3FFE)
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INT L:
READ FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/WL
CE L
INTR
tINS
tHA
tINS
(OR 1/3FFF)
(OR 1/3FFE)
[46]
[47]
[47]
[47]
[46]
[47]
Notes
46. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
47. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 19 of 24
Ordering Information
Ordering Code Definitions
4K × 16 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
20 CY7C024AV-20AXC 51-85048 100-pin TQFP (Pb-free) Commercial
CY7C024AV-20AXI 51-85048 100-pin TQFP (Pb-free) Industrial
25 CY7C024AV-25AXC 51-85048 100-pin TQFP (Pb-free) Commercial
CY7C024AV-25AXI 51-85048 100-pin TQFP (Pb-free) Industrial
8K × 16 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
20 CY7C025AV-20AXC 51-85048 100-pin TQFP (Pb-free) Commercial
25 CY7C025AV-25AXC 51-85048 100-pin TQFP (Pb-free) Commercial
CY7C025AV-25AXI 51-85048 100-pin TQFP (Pb-free) Industrial
16K × 16 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
20 CY7C026AV-20AXC 51-85048 100-pin TQFP (Pb-free) Commercial
25 CY7C026AV-25AXC 51-85048 100-pin TQFP (Pb-free)
CY7C026AV-25AXI 51-85048 100-pin TQFP (Pb-free) Industrial
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type:
A = 100-pin TQFP
Speed Grade: XX = 20 or 25
20 = 20 ns; 25 = 25 ns
AV = 3.3 V
Depth: X = 4 or 5 or 6
4 = 4K; 5 = 8K; 6 = 16K
Width: 02 = × 16
Technology Code: C = CMOS
Marketing Code: 7 = Dual Port SRAM
Company ID: CY = Cypress
CCY 02 X - XX XX XAV7
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 20 of 24
Package Diagram
Figure 16. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *J
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 21 of 24
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 22 of 24
Document History Page
Document Title: CY7C024AV/CY7C025AV/CY7C026AV, 3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM
Document Number: 38-06052
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 110204 SZV 11/11/2001 Change from Spec number: 38-00838 to 38-06052.
*A 122302 RBI 12/27/2002 Updated Maximum Ratings:
Added Note 11 and referred the same note in maximum ratings.
*B 128958 JFU 09/03/2003 Updated Ordering Information:
Added CY7C025AV-25AI.
*C 237622 YDT 06/25/2004 Updated Features:
Removed “Pin-compatible and functionally equivalent to IDT70V24, 70V25,
and 7V0261”.
*D 241968 WWZ 07/16/2004 Updated Ordering Information:
Added CY7C024AV-25AI.
*E 276451 SPN 10/12/2004 Updated Ordering Information:
Updated 16K × 16 3.3 V Asynchronous Dual-Port SRAM:
Replaced “× 18” with “× 16” in heading (for 026AV part numbers).
*F 279452 RUY 11/11/2004 Updated Pin Configurations:
Updated Figure 2:
Replaced A113L with A13L (for CY7C026AV pin list).
Updated Electrical Characteristics:
Added minimum value of VIL parameter (0.3 V)
Added Note 14 and referred the same note in minimum value of VIL parameter.
Updated Ordering Information:
Added Pb-free part numbers.
*G 373580 RUY 06/07/2005 Updated Ordering Information:
Replaced CY7C024AC-25AXC with CY7C024AV-25AXC.
*H 380476 PCX 06/15/2005 Updated Ordering Information:
Added CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI,
CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI.
*I 2543577 NXR /
AESA
07/25/2008 Updated Switching Waveforms:
Updated Note 31 (Replaced “R/W must be HIGH during all address transitions”
with “R/W or CE must be HIGH during all address transitions”).
*J 2623540 VKN /
PYRS
12/17/2008 Added CY7C024BV part related information in all instances across the
document.
*K 2896038 RAME 03/19/2010 Updated Ordering Information (Removed inactive parts).
Updated Package Diagram.
*L 3110406 ADMU 12/14/2010 Added Ordering Code Definitions under Ordering Information.
*M 3210221 ADMU 03/30/2011 Updated Package Diagram (spec 51-85048 (Changed revision from *D to *E)).
Updated Ordering Information (Removed part CY7C025AV-25AC from
Ordering Information table).
*N 3343888 ADMU 08/12/2011 Updated Document Title to read as “CY7C024AV/024BV/025AV/026AV, 3.3 V
4K/8K/16K × 16 Dual-Port Static RAM”.
Updated Features (Removed CY7C0241/251 and CY7C036 information).
Updated Functional Description (Removed CY7C0241/251 and CY7C036
information).
Updated Selection Guide (Removed CY7C0241/251 and CY7C036
information).
Updated Pin Configurations (Removed CY7C0241/251 and CY7C036
information).
Updated Pin Definitions.
CY7C024AV
CY7C025AV
CY7C026AV
Document Number: 38-06052 Rev. *T Page 23 of 24
*N (cont.) 3343888 ADMU 08/12/2011 Updated Functional Overview (Removed CY7C0241/251 and CY7C036
information).
Updated Electrical Characteristics (Removed CY7C0241/251 and CY7C036
information).
Updated Switching Characteristics (Removed CY7C0241/251 and CY7C036
information).
Added Acronyms and Units of Measure.
Updated to new template.
*O 3403638 ADMU 10/13/2011 Updated Ordering Information (Removed pruned part CY7C024BV-15AXI).
*P 3698952 SMCH 07/31/2012 Updated Title to read as “CY7C024AV/025AV/026AV, 3.3 V 4K/8K/16K × 16
Dual-Port Static RAM”.
Updated Features (Removed CY7C024BV related information, removed 15 ns
from the High speed access, removed the Note “CY7C024AV and CY7C024BV
are functionally identical.” and its reference).
Updated Functional Description (Removed CY7C024BV related information).
Updated Selection Guide (Removed CY7C024BV related information).
Updated Pin Configurations (Removed CY7C024BV related information).
Updated Functional Overview (Removed CY7C024BV related information).
Updated Electrical Characteristics (Removed CY7C024BV related
information).
Updated Switching Characteristics (Removed CY7C024BV related
information).
Updated Data Retention Mode (Removed CY7C024BV related information).
Updated Ordering Information (Removed pruned part CY7C026AV-20AXC).
Updated Package Diagram (spec 51-85048 (Changed revision from *E to *G)).
*Q 4112664 SMCH 09/03/2013 Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85048 – Changed revision from *G to *H.
Updated to new template.
Completing Sunset Review.
*R 4592640 VINI 12/11/2014 Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Package Diagram:
spec 51-85048 – Changed revision from *H to *I.
*S 5439053 NILE 09/16/2016 Updated Package Diagram:
spec 51-85048 – Changed revision from *I to *J.
Updated to new template.
Completing Sunset Review.
*T 5840744 NILE 08/01/2017 Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C024AV/CY7C025AV/CY7C026AV, 3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM
Document Number: 38-06052
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 38-06052 Rev. *T Revised August 1, 2017 Page 24 of 24
CY7C024AV
CY7C025AV
CY7C026AV
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including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
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