LC2MOS Quad SPST Switches
ADG441/ADG442/ADG444
Rev. A
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
FEATURES
44 V supply maximum ratings
VSS to VDD analog signal range
Low on resistance (<70 Ω)
Low ∆RON (9 Ω max)
Low RON match (3 Ω max)
Low power dissipation
Fast switching times
tON < 110 ns
tOFF < 60 ns
Low leakage currents (3 nA max)
Low charge injection (6 pC max)
Break-before-make switching action
Latch-up proof A grade
Plug-in upgrade for DG201A/ADG201A, DG202A/ADG202A,
DG211/ADG211A
Plug-in replacement for DG441/DG442/DG444
APPLICATIONS
Audio and video switching
Automatic test equipment
Precision data acquisition
Battery-powered systems
Sample-and-hold systems
Communication systems
GENERAL DESCRIPTION
The ADG441, ADG442, and ADG444 are monolithic CMOS
devices that comprise of four independently selectable switches.
They are designed on an enhanced LC2MOS process that
provides low power dissipation yet gives high switching speed
and low on resistance.
The on resistance profile is very flat over the full analog input
range, which ensures good linearity and low distortion when
switching audio signals. High switching speed also makes the
parts suitable for video signal switching. CMOS construction
ensures ultralow power dissipation, making the parts ideally
suited for portable and battery-powered instruments. The
ADG441, ADG442, and ADG444 contain four independent
SPST switches. Each switch of the ADG441 and ADG444 turns
on when a logic low is applied to the appropriate control input.
The ADG442 switches are turned on with logic high on the
appropriate control input. The ADG441 and ADG444 switches
FUNCTIONAL BLOCK DIAGRAM
05233-001
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
ADG441
ADG444 ADG442
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
differ in that the ADG444 requires a 5 V logic power supply
that is applied to the VL pin. The ADG441 and ADG442 do not
have a VL pin, the logic power supply is generated internally by
an on-chip voltage generator.
Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the power
supplies. In the OFF condition, signal levels up to the supplies
are blocked. All switches exhibit break-before-make switching
action for use in multiplexer applications. Inherent in the
design is the low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1. Extended signal range. The ADG441A/ADG442A/
ADG444A are fabricated on an enhanced LC2MOS, trench-
isolated process, giving an increased signal range that
extends to the supply rails.
2. Low power dissipation.
3. Low RON.
4. Trench isolation guards against latch-up for A grade parts. A
dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.
5. Break-before-make switching. This prevents channel
shorting when the switches are configured as a multiplexer.
6. Single-supply operation. For applications where the analog
signal is unipolar, the ADG441/ADG442/ADG444 can be
operated from a single-rail power supply. The parts are fully
specified with a single 12 V power supply.
ADG441/ADG442/ADG444
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Test Circ uits ........................................................................................9
Ter mi no lo g y .................................................................................... 11
Trench Isolat ion .............................................................................. 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
5/05—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Deleted CERDIP Package and T Grade ..........................Universal
Changes to Features and Product Highlights ............................... 1
Changes to Test Conditions in Table 2 .......................................... 4
Changes to Figure 11........................................................................ 8
Changes to Trench Isolation Section ........................................... 12
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 14
4/94–Revision 0: Initial Version
ADG441/ADG442/ADG444
Rev. A | Page 3 of 16
SPECIFICATIONS
DUAL SUPPLY1
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted.
Table 1.
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
RON 40 Ω typ VD = ±8.5 V, IS = −10 mA
70 85 Ω max VDD = +13.5 V, VSS = −13.5 V
∆RON 4 Ω typ −8.5 V ≤ VD ≤ +8.5 V
9 Ω max
RON Match 1 Ω typ VD = 0 V, IS = −10 mA
3 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source OFF Leakage IS (OFF) ±0.01 nA typ VD = ±15.5 V, VS = ∓15.5 V
±0.5 ±3 nA max See Figure 15
Drain OFF Leakage ID (OFF) ±0.01 nA typ VD = ±15.5 V, VS = ∓15.5 V
±0.5 ±3 nA max See Figure 15
Channel ON Leakage ID, IS (ON) ±0.08 nA typ VS = VD = ±15.5 V
±0.5 ±3 nA max See Figure 16
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±0.00001 µA typ VIN = VINL or VINH
±0.5 µA max
DYNAMIC CHARACTERISTICS2
tON 85 ns typ RL = 1 kΩ, CL = 35 pF;
110 170 ns max VS = ±10 V; see Figure 17
tOFF 45 ns typ RL = 1 kΩ, CL = 35 pF;
60 80 ns max VS = ±10 V; see Figure 17
tOPEN 30 ns typ RL = 1 kΩ, CL = 35 pF;
Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
6 pC max VDD = +15 V, VSS = –15 V; see Figure 18
OFF Isolation 60 dB typ RL = 50 Ω, CL = 5 pF; f = 1 MHz; see Figure 19
Channel-to-Channel Crosstalk 100 dB typ RL = 50 Ω, CL = 5 pF; f= 1 MHz; see Figure 20
CS (OFF) 4 pF typ f = 1 MHz
CD (OFF) 4 pF typ f = 1 MHz
CD, CS (ON) 16 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD Digital Inputs = 0 V or 5 V
ADG441/ADG442 80 µA max
ADG444 0.001 µA typ
1 2.5 µA max
ISS 0.0001 µA typ
1 2.5 µA max
IL (ADG444 Only) 0.001 µA typ VL = 5.5 V
1 2.5 µA max
1 Temperature range is: B Version: −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
ADG441/ADG442/ADG444
Rev. A | Page 4 of 16
SINGLE SUPPLY1
VDD = +12 V ± 10%, VSS = 0 V, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted.
Table 2.
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
RON 70 Ω typ VD = +3 V, +8 V, IS = −5 mA
110 130 Ω max VDD = 10.8 V
∆RON 4 Ω typ 3 V ≤ VD ≤ 8 V
9 Ω max
RON Match 1 Ω typ VD = +6 V, IS = −5 mA
3 Ω max
LEAKAGE CURRENT VDD = 13.2 V
Source OFF Leakage IS (OFF) ±0.01 nA typ VD = 12.2 V/1 V, VS = 1 V/12.2 V
±0.5 ±3 nA max See Figure 15
Drain OFF Leakage ID (OFF) ±0.01 nA typ VD = 12.2 V/1 V, VS = 1 V/12.2 V
±0.5 ±3 nA max See Figure 15
Channel ON Leakage ID, IS (ON) ±0.08 nA typ VS = VD = 12.2 V/1 V
±0.5 ±3 nA max Figure 16
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±0.00001 µA typ VIN = VINL or VINH
±0.5 µA max
DYNAMIC CHARACTERISTICS2
tON 105 ns typ RL = 1 kΩ, CL = 35 pF
150 220 ns max VS = 8 V; Figure 17
tOFF 40 ns typ RL = 1 kΩ, CL = 35 pF
60 100 ns max VS = 8 V; Figure 17
tOPEN 50 ns typ RL = 1 kΩ, CL = 35 pF
Charge Injection 2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF
6 pC max VDD = 12 V, VSS = 0 V; see Figure 18
OFF Isolation 60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 19
Channel-to-Channel Crosstalk 100 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
CS (OFF) 7 pF typ f = 1 MHz
CD (OFF) 10 pF typ f = 1 MHz
CD, CS (ON) 16 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD Digital Inputs = 0 V or 5 V
ADG441/ADG442 80 µA max
ADG444 0.001 µA typ
1 2.5 µA max
IL (ADG444 Only) 0.001 µA typ VL = 5.5 V
1 2.5 µA max
1 Temperature range is: B Version: −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
ADG441/ADG442/ADG444
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 44 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
VL to GND −0.3 V to VDD + 0.3 V
Analog, Digital Inputs VSS − 2 V to VDD + 2 V or 30 mA, Whichever Occurs First
Continuous Current, S or D 30 mA
Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) 100 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature, Soldering (10 sec) 300°C
Plastic Package, Power Dissipation 470 mW
θJA, Thermal Impedance 177°C/W
Lead Temperature, Soldering (10 sec) 260°C
SOIC Package, Power Dissipation 600 mW
θJA, Thermal Impedance 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum
rating may be applied at any one time.
Table 4. Truth Table
ADG441/ADG444 IN ADG442 IN Switch Condition
0 1 ON
1 0 OFF
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADG441/ADG442/ADG444
Rev. A | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
1
D1
2
S1
3
V
SS 4
IN2
16
D2
15
S2
14
V
DD
13
G
ND
5
NC
12
S4
6
S3
11
D4
7
D3
10
IN4
8
IN3
9
NC = NO CONNECT
ADG441
ADG442
TOP VIEW
(Not to Scale)
05233-002
Figure 2. ADG441/ADG442 (DIP/SOIC)
IN1
1
D1
2
S1
3
V
SS 4
IN2
16
D2
15
S2
14
V
DD
13
G
ND
5
V
L
12
S4
6
S3
11
D4
7
D3
10
IN4
8
IN3
9
ADG444
TOP VIEW
(Not to Scale)
05233-003
Figure 3. ADG444 (DIP/SOIC)
Table 5. ADG441/ADG442 Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 9, 16 IN1 to IN4 Logic Control Input.
2, 7, 10, 15 D1 to D4 Drain Terminal. May be
an input or output.
3, 6, 11, 14 S1 to S4 Source Terminal. May be
an input or output.
4 VSS Most Negative Power Supply
Potential in Dual Supplies. In
single-supply applications,
it may be connected to ground.
5 GND Ground (0 V) Reference.
12 NC No Connect.
13 VDD Most Positive Power Supply Potential.
Table 6. ADG444 Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 9, 16 IN1 to IN4 Logic Control Input.
2, 7, 10, 15 D1 to D4 Drain Terminal. May be
an input or output.
3, 6, 11, 14 S1 to S4 Source Terminal. May be
an input or output.
4 VSS Most Negative Power Supply
Potential in Dual Supplies. In
single-supply applications,
it may be connected to ground.
5 GND Ground (0 V) Reference.
12 VLLogic Power Supply (5 V).
13 VDD Most Positive Power Supply Potential.
ADG441/ADG442/ADG444
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
05233-005
V
D
(V
S
) (V) 15–15 –10 –5 0 5 10
R
ON
(Ω)
100
80
60
40
20
V
DD
= +5V
V
SS
= –5V
V
DD
= +15V
V
SS
= –15V
V
DD
= +10V
V
SS
= –10V
V
DD
= +12V
V
SS
= –12V
T
A
= 25°C
Figure 4. RON as a Function of VD (VS): Dual Supply
05233-006
TA = 25°C
VDD = 5V
VSS = 0V
VDD = 15V
VSS = 0V
VDD = 12V
VSS = 0V
VDD = 10V
VSS = 0V
VD (VS) (V) 15036912
RON (Ω)
170
110
130
150
70
90
50
30
10
Figure 5. RON as a Function of VD (VS): Single Supply
05233-007
VD (VS) (V) 15–15 –10 –5 0 5 10
RON (Ω)
100
80
60
40
20
VDD = +15V
VSS = –15V
125°C
25°C
85°C
Figure 6. RON as a Function of VD (VS) for Different Temperatures
05233-008
VS (VD) (V) 15–15 –10 –5 0 5 10
VDD = +15V
VSS = –15V
TA = 25°C
LEAKAGE CURRENT (nA)
0.02
0.01
0
–0.01
–0.02
ID (ON)
ID (OFF)
IS (OFF)
Figure 7. Leakage Currents as a Function of VS (VD)
05233-009
FREQUENCY (Hz) 10M1k 10k 100k 1M
dB
120
100
110
70
80
90
60
50
V
DD
= +15V
V
SS
= –15V
CROSSTALK
OFF ISOLATION
Figure 8. Crosstalk and Off Isolation vs. Frequency
05233-010
V
D
(V
S
) (V) 120246810
R
ON
(
Ω
)
120
100
60
80
40
20
125°C
25°C 85°C
V
DD
= 12V
V
SS
= 0V
Figure 9. RON as a Function of VD (VS) for Different Temperatures
ADG441/ADG442/ADG444
Rev. A | Page 8 of 16
05233-011
V
S
, V
D
(V) 120246810
LEAKAGE CURRENT (nA)
0.010
0.005
0
–0.005
–0.010
I
D
(OFF)
I
S
(OFF)
I
D
(ON)
V
DD
= 12V
V
SS
= 0V
T
A
= 25°C
Figure 10. Leakage Currents as a Function of VS (VD)
05233-012
V
S
(V) 15–15–12–9–6–3036912
CHARGE INJECTION (pC)
40
20
10
30
0
–20
–30
–10
–40
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
V
DD
= 12V
V
SS
= 0V
Figure 11. Charge Injection vs. Source Voltage
05233-013
SUPPLY VOLTAGE (V) ±20±10 ±12 ±14 ±16 ±18
V
IN
= 8V
t
ON
t
OFF
t (ns)
120
100
80
60
40
Figure 12. Switching Time vs. Bipolar Supply
05233-014
SUPPLY VOLTAGE (V) 20810 1412 16 18
t (ns)
160
140
120
100
80
60
40
20
V
IN
= 8V
t
ON
t
OFF
Figure 13. Switching Time vs. Single Supply
ADG441/ADG442/ADG444
Rev. A | Page 9 of 16
TEST CIRCUITS
SD
R
ON
= V
1
/I
DS
V
S
V1
I
DS
05233-015
Figure 14. On Resistance
SD
V
S
V
D
A
A
I
S
(OFF) I
D
(OFF)
05233-016
Figure 15. Off Leakage
SD
VSVD
A
ID (ON)
05233-017
Figure 16. On Leakage
SD
V
S
V
OUT
IN
V
SS
GND
V
L
V
DD
–15V
+15V +5V
C
L
35pF
R
L
1kΩ
3V
50%
50% 50%
90%90%
50%
ADG441/ADG444
ADG442
V
IN
V
IN
V
OUT
3V
tON tOFF
05233-018
0.1µF
0.1µF0.1µF
Figure 17. Switching Times
SD
V
S
V
OUT
IN
R
S
V
SS
GND
V
L
V
DD
–15V
+15V +5V
C
L
1nF
3V
V
IN
V
OUT
Q
INJ
= C
L
×∆V
OUT
∆V
OUT
05233-019
Figure 18. Charge Injection
ADG441/ADG442/ADG444
Rev. A | Page 10 of 16
SD
V
S
V
OUT
IN
V
SS
GND
V
SS
V
DD
–15V
+15V +5V
R
L
50Ω
0.1µF
0.1µF0.1µF
V
IN
05233-021
Figure 19. Off Isolation
SD
V
S
NC
V
SS
GND
V
SS
V
DD
–15V
+15V +5V
50Ω
0.1µF
0.1µF0.1µF
V
IN1
V
IN2
V
OUT
05233-022
R
L
50Ω
CHANNEL-TO-CHANNEL CROSSTALK = 20× LOG |V
S
/V
OUT
|
Figure 20. Channel-to-Channel Crosstalk
ADG441/ADG442/ADG444
Rev. A | Page 11 of 16
TERMINOLOGY
RON
Ohmic resistance between D and S.
RON Match
Difference between the RON of any two channels.
IS (OFF)
Source leakage current with the switch OFF.
ID (OFF)
Drain leakage current with the switch OFF.
ID, IS (ON)
Channel leakage current with the switch ON.
VD (VS)
Analog voltage on Terminals D, S.
CS (OFF)
OFF switch source capacitance.
CD (OFF)
OFF switch drain capacitance.
CD, CS (ON)
ON switch capacitance.
tON
Delay between applying the digital control input and the output
switching on.
tOFF
Delay between applying the digital control input and the output
switching off.
tOPEN
Break-before-make delay when switches are configured as a
multiplexer.
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an OFF switch.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ADG441/ADG442/ADG444
Rev. A | Page 12 of 16
TRENCH ISOLATION
In the ADG441A, ADG442A, and ADG444A, an insulating
oxide layer (trench) is placed between the NMOS and the
PMOS transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated
switches, are eliminated, and the result is a completely latch-up
proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
05233-004
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
TRENCH
P-WELL N-WELL
LOCO
NMOS PMOS
Figure 21. Trench Isolation
ADG441/ADG442/ADG444
Rev. A | Page 13 of 16
OUTLINE DIMENSIONS
16
18
9
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.015 (0.38)
MIN
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.785 (19.94)
0.765 (19.43)
0.745 (18.92)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AC
Figure 22. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AC
16 9
8
1
4.00 (0.1575)
3.80 (0.1496)
10.00 (0.3937)
9.80 (0.3858)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2283)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8°
0°
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
× 45°
Figure 23. 16-Lead Standard Small Outline Package [SOIC]
(R-16)
Dimensions shown in millimeters and (inches)
ADG441/ADG442/ADG444
Rev. A | Page 14 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG441BN −40°C to +85°C 16-Lead Plastic Dual In-Line Package (PDIP) N-16
ADG441BR −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG441BR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG441BRZ1−40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG441BRZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG441BCHIPS DIE
ADG441ABCHIPS2 DIE
ADG441ABN2 −40°C to +85°C 16-Lead Plastic Dual In-Line Package (PDIP) N-16
ADG441ABR2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG441ABR-REEL2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG441ABRZ-REEL1, 2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442BN −40°C to +85°C 16-Lead Plastic Dual In-Line Package (PDIP) N-16
ADG442BR −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442BR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442BRZ1 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442BRZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442ABN2 −40°C to +85°C 16-Lead Plastic Dual In-Line Package (PDIP) N-16
ADG442ABR2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442ABR-REEL2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442ABRZ1, 2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG442ABRZ-REEL1, 2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444BN −40°C to +85°C 16-Lead Plastic Dual In-Line Package (PDIP) N-16
ADG444BR −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444BR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444BRZ1 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444BRZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444ABN2 −40°C to +85°C 16-Lead Plastic Dual In-Line Package (PDIP) N-16
ADG444ABR2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444ABR-REEL2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444ABRZ1, 2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
ADG444ABRZ-REEL1, 2 −40°C to +85°C 16-Lead Standard Small Outline Package (SOIC) R-16
1 Z = Pb-free part.
2 A = Trench isolated.
ADG441/ADG442/ADG444
Rev. A | Page 15 of 16
NOTES
ADG441/ADG442/ADG444
Rev. A | Page 16 of 16
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00396–0–5/05(A)
