SY56011R
Low Voltage 1.2V/1.8V/2.5V CML 1:2
Fanout Buffer 6.4G bps with E qualization
Preliminary
Precision Edge is a registered tradem ark of Micrel, Inc.
QFN and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 2008
M9999-070208-A
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General Description
The SY56011R is a fully differential, low voltage
1.2V/1.8V/2.5V CML 1:2 Fanout Buffer with input
equalization. The SY56011R can process clock signals
as fast as 4.5 GHz or data patterns up to 6.4Gbps.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that interfaces to CML
differential signals, without any level-shifting or
termination resistor networks in the signal path. The
differential input can also accept AC-coupled LVPECL
and LVDS signals. Input voltages as small as 200mV
(400mVpp) are applied before the 9”, 18” or 27” FR4
transmission line. For AC-coupled input interface
applications, an internal voltage reference is provided to
bias the VT pin. The outputs are CML, with extremely
fast rise/fall times guaranteed to be less than 80ps.
The SY56011R operates from a 2.5V ±5% core supply
and a 1.2V, 1.8V or 2.5V ±5% output supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY56011R is part of Micrel’s
high-speed, Precision Edge® produc t line.
Datasheets and support doc um entation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
1.2V/1.8V/2.5V CML 1:2 Fanout Buffer
Equalizes 9, 18, 27 inches of FR4
Guaranteed AC performance over temperature and
voltage:
DC-to > 6.4Gbps Data throughput
DC-to > 4.5GHz Clock throughput
<280ps propagation delay (IN-to-Q)
<15ps withi n-device skew
<80ps rise/fall times
Ultra-low jitter design
<1psRMS random jitter
High-speed CML outputs
2.5V ±5% VCC , 1.2/1.8 V/2. 5V ±5% VCCO power supply
operation
Industrial temperature range: 40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
Applications
Data Distribution:
SONET clock and data distribution
Fiber Channel clock and data distribution
Gigabit Ether net c lock and data distribut ion
Markets
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Metro area network equipment
Micrel, Inc.
SY56011R
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Ordering Information(1)
Part Number Package
Type Operating
Range Package Marking Lead
Finish
SY56011RMG QFN-16 Industrial R011 with Pb-Free
bar-line indicator NiPdAu
Pb-Free
SY56011RMGTR
(2)
QFN-16 Industrial R011 with Pb-Free
bar-line indicator NiPdAu
Pb-Free
Notes:
1. Contact f act ory for die availabi lit y. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Truth Table
EQ Equalization FR4 6mil Stripline
LOW 9”
FLOAT 18”
HIGH 27”
Micrel, Inc.
SY56011R
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Pin Description
Pin Number Pin Name Pin Function
1,2
IN, /IN
Differential Input: Signals as small as 200mV VPK (400mVPP) applied to the input of 9, 18 or
27 inches 6mil FR4 stripline transmission line are then terminated with this differential input.
Each input pin internally terminates with 50Ω to the VT pin.
3
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. An
internal high impedance resistor divider biases VT to allow input AC-coupling. For AC-
coupling, bypass VT with 0.1µF low ESR capacitor to VCC. See “Interface Applications”
subsection and Figure 2a.
6 EQ Three level input for equalization control. High, float, low.
7 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC
pins as possible. Supplies input and core circuitry.
8,13 VCCO Output Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCCO pins as
possible. Supplies the output buffers.
14 GND,
Exposed pad Ground: Exposed pad must be connected to a ground plane that is the same potential as the
ground pins.
12,11
10,9 Q0, /Q0
Q1, /Q1 CML Differential Output Pairs: Differential buffered copy of the input signal. The output swing
is typically 390mV. See “Interface Applications” subsection for termination information.
4,5,15,16 NC No connect pins
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... 0.5V to +3.0V
Supply Voltage (VCCO) ............................. –0.5V to +3.0V
VCC - VCCO ............................................................... <1.8V
VCCO - VCC ............................................................... <0.5V
Input Voltage (VIN) ....................................... 0.5V to VCC
CML Output Voltage (VOUT) ......................... 0.6V to 3.0V
Current (VT)
Source or sink on VT pin ............................. ±100mA
Input Current
Source or sink Current on (IN, /IN) ................ ±50mA
Maximum operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (Ts) .................... 65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC) .......................... 2.375V to 2.625V
(VCCO) .......................... 1.14V to 2.625V
Ambient Temperature (TA) ................... 40°C to +85°C
Package Thermal Resistance(3)
QFN
Still-air (θJA) .................................................. 75°C/W
Junction-to-board (ψJB) ................................ 33°C/W
DC Electrical Characteristics(4)
TA = 40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC
Power Supply Voltage Range VCC
VCCO
VCCO
VCCO
2.375
1.14
1.7
2.375
2.5
1.2
1.8
2.5
2.625
1.26
1.9
2.625
V
V
V
V
ICC Power Supply Current Max. V CC 54 75 mA
ICCO Power Supply Current No Load. VCCO 32 42 mA
RIN Input Resistance
(IN-to-VT, /IN-to-VT ) 45 50 55
RDIFF_IN Differential Input Resistance
(IN-to-/IN) 90 100 110
VIH Input HIGH Voltage
(IN, /IN) IN, /IN 1.42 VCC V
VIL Input LO W Voltage
(IN, /IN) IN, /IN
1.22V = 1.7-0.475 1.22 VIH0.2 V
VIN Input Voltage Swing
(IN, /IN) See Figure 3a, Note 5, applied to
input of transmiss ion line. 0.2 1.0 V
VDIFF_IN Differential Input Voltage Swing
(|IN - /IN|) See Figure 3b, Note 5, applied to
input of transmission line. 0.4 2.0 V
VT_IN Voltage from Input to VT 1.28 V
Notes:
1. Permanent device dam age may occur if absolute maximum rati ngs are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed i n the operational secti ons of this data sheet. E xposure to absol ut e maximum ratings conditi ons f or
extended periods may aff ect device reliabi l i t y.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resist ance assumes exposed pad is sol dered (or equivalent) t o the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air num ber, unless otherwise s tated.
4. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
5. VIH( max) is specified when VT i s floating.
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CML Outputs DC Electrical Characteristics(6)
VCCO = 1.14V to 1.26V RL = 50Ω to VCCO,
VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50Ω to VCCO or 100Ω across the outputs.
VCC = 2.375V to 2.625V; TA = 40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage RL = 50Ω to VCCO VCC-0.020 VCC-0.010 VCC V
VOUT Output Voltage Swing See Figure 3a 300 390 475 mV
VDIFF_OUT Differ ential Output Voltage Swing See Figure 3b 600 780 950 mV
ROUT Output Source Impedance 45 50 55
Three Level EQ Input DC Electrical Characteristics(6)
VCC = 2.375V to 2.625V; TA = 40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage VCC-0.3 V
VIL Input LO W Voltage 0 VEE+0.3 V
IIH Input HIGH Current VIH = VCC 400 uA
IIL Input LO W Current VIL = GND -480 uA
Note:
6. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
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AC Electrical Characteristics
VCCO = 1.14V to 1.26V RL = 50Ω to VCCO,
VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50Ω to VCCO or 100Ω across the outputs,
VCC = 2.375V to 2.625V; TA = 40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Frequency NRZ Data 6.4 Gbps
VOUT > 200mV Clock 4.5 GHz
tPD Propagation Delay IN-to-Q
Note 7, Fig ur e 1 100 180 280 ps
tSkew Within Device Skew Note 8 3 15 ps
Part-to-Part Skew Note 9 100 ps
tJitter Random Jitter Note 10 1 psRMS
tr tf Output Rise/Fall Time
(20% to 80%) At full output swing. 20 50 80 ps
Notes:
7. Propagati on del ay is measured with no attenuati ng transmi ss i on line connected t o the input.
8. Within-dev ice skew is measured across all outputs under identic al input transiti on, t em perature and power supply.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
10. Random jitt er is measured with a K28.7 pattern, measured at ≤ fMAX.
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Interface Applications
For Input Interface Applications see Figures 4a-e and
for CML Output Termination, see Figures 5a-d.
CML Output Termination with VCCO 1.2 V
For VCCO of 1.2V, Figure 5a, terminate the output
with 50 Ohms to 1.2V, not 100 ohms differentially
across the outputs . If AC -coup lin g is us ed, F i gure 5 d,
terminate into 50 ohms to 1.2V before the coupling
capacitor a nd then connect to a high value resis tor to
a referenc e volt ag e. Any unused ou tput p air ne eds to
be terminated, do not leave floating.
CML Output Termination with VCCO 1.8 V
For VCCO of 1.8V, Figure 5a and Figure 5b,
terminate either with 50 ohms to 1.8V or 100 ohms
differentially across the outputs. AC- or DC-coupling
is f ine. For bes t si gnal integ rit y, term inate an y unused
output pairs.
Input Termination
1.8V CML dri ver: T erminat e input with VT tied to 1. 8V.
Don’t term inate 100 ohms differ entially.
2.5V CML driver: Terminate input with either VT tied
to 2.5V or 100 ohms differentially.
The input cannot be DC-coupled from a 1.2V CML
driver.
Timing Diagrams
Figure 1. Propagation Delay
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Typical Characteris tics
VCC = 2.5, VCCO = 1.2V, GND = 0V, VIN = 400mV, RL = 50Ω to 1.2V, Data Pattern: 223-1, TA = 25°C, unless otherwise
stated.
SY56011R
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Input and Output Stage
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified CML Output Buffer
Single-Ended and Differential Swings
Figure 3a. Single-Ended Swing
Figure 3b. Differential Swing
SY56011R
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Input Interface Applications
Figure 4a. CML Interface
100Ω Differential
(DC-Coupled, 2.5V)
Figure 4b. CML Interface
50Ω to VCC
(DC-Coupled, 1.8V, 2.5V)
Figure 4c. CML Interface
(AC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
(AC-Coupled)
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CML Output Termination
Figure 5a. 1.2V or 1.8V CML DC-Coupled Termination
Figure 5b. 1.8V CML DC-Coupled Termination
Figure 5c. CML AC-Coupled Termination
VCCO 1.8V Only
Figure 5d. CML AC-Coupled Termination
VCCO 1.2V Only
Related Product and Support Documents
Part Number Function Datasheet Link
HBW Solutions New Products and Termination Application Notes http://www.micrel.com/page.do?page=/product-
info/as/HBWsolutions.shtml
SY56011R
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Package Information
16-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-10 00 WEB http://ww w .micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is
assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification t o the customer.
Micrel Products are not designed or authorized for use as components in life support applianc es, devic es or syst ems where malfunction of a
product can reasonably be expected to result i n personal i nj ury. Lif e support devices or systems are devices or systems that (a) are intended for
surgical implant int o the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury
to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchas er’s own risk and
Purchaser agrees to fully indem nify Micrel f or any damages resulting from such use or sale.
© 2008 Micrel, Incorporated.