ISSI IS64C1024L (R) ADVANCED INFORMATION JANUARY 2003 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES DESCRIPTION * High-speed access time: 15 ns * Low active and standby power * Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 5V (10%) power supply * Temperature offerings: Option A1: -40oC to +85oC Option A2: -40oC to +105oC Option A3: -40oC to +125oC The ISSI IS64C1024L is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAMs. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS64C1024L is available in the following 32-pin packages: 300-mil and 400-mil SOJ, and TSOP (Type I, 8x20). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 x 2048 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT 1024 BLK.eps Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 1 ISSI IS64C1024L PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type 1) (T) NC 1 32 VDD A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A11 A9 A8 A13 WE CE2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (R) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output VDD Power GND Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write 2 WE CE1 CE2 OE X X H H L H X L L L X L H H H X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 ISSI IS64C1024L (R) ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.5 to +7.0 -65 to +150 1.5 Unit V C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Options A1 Ambient Temperature -40C to +85C IS64C1024L 4.5V - 5.5V A2 -40C to +105C 4.5V - 5.5V A3 -40C to +125C 4.5V - 5.5V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = -4.0 mA 2.4 -- V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA -- 0.4 V VIH Input HIGH Voltage 2.2 VDD + 0.5 V -0.3 0.8 V (1) VIL Input LOW Voltage ILI Input Leakage GND VIN VDD -- -5 -- 5 A ILO Output Leakage GND VOUT VDD Outputs Disabled -- -5 -- 5 A Note: 1. VIL = -3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 3 ISSI IS64C1024L (R) POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Options -15 ns Min. Max. Symbol Parameter Test Conditions Unit ICC1 VDD Operating Supply Current VDD = VDD MAX., CE = VIL IOUT = 0 mA, f = 0 A1 A2 A3 -- -- -- 90 95 100 mA ICC2 VDD Dynamic Operating Supply Current VDD = VDD MAX., CE = VIL IOUT = 0 mA, f = fMAX A1 A2 A3 -- -- -- 150 155 160 mA ISB1 TTL Standby Current (TTL Inputs) VDD = VDD MAX, VIN = VIH or VIL CE1 VIH, f = 0 or CE2 VIL, f = 0 A1 A2 A3 -- -- -- 30 40 45 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = VDD MAX., CE1 VDD - 0.2V, CE2 0.2V VIN VDD - 0.2V, or VIN 0.2V, f = 0 A1 A2 A3 -- -- -- 1.0 2 3 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 5 pF VOUT = 0V 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 5.0V. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 ISSI IS64C1024L AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 480 5V 5V OUTPUT OUTPUT 30 pF Including jig and scope 255 5 pF Including jig and scope 255 Figure 2 Figure 1 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -15 ns Symbol Parameter Min. Max. Unit tRC Read Cycle Time 15 -- ns tAA Address Access Time -- 15 ns tOHA Output Hold Time 2 -- ns tACE1 CE1 Access Time -- 15 ns tACE2 CE2 Access Time -- 15 ns tDOE OE Access Time -- 7 ns OE to Low-Z Output 0 -- ns tHZOE OE to High-Z Output 0 6 ns tLZCE1(3) CE1 to Low-Z Output 2 -- ns tLZCE2(3) CE2 to Low-Z Output 2 -- ns tHZCE CE1 or CE2 to High-Z Output 0 8 ns tPU CE1 or CE2 to Power-Up 0 -- ns tPD(4) CE1 or CE2 to Power-Down -- 12 ns tLZOE (3) (3) (3) (4) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 5 (R) ISSI IS64C1024L (R) AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE1 CE2 t LZCE1 t LZCE2 DOUT t ACE1 t ACE2 HIGH-Z t HZCE1 t HZCE2 DATA VALID CE2_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 ISSI IS64C1024L (R) WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) Symbol Parameter -15 ns Min. Max. Unit tWC Write Cycle Time 15 -- ns tSCE1 CE1 to Write End 12 -- ns tSCE2 CE2 to Write End 12 -- ns tAW Address Setup Time to Write End 12 -- ns tHA Address Hold from Write End 0 -- ns Address Setup Time 0 -- ns tPWE WE Pulse Width 12 -- ns tSD Data Setup to Write End 10 -- ns tHD Data Hold from Write End 0 -- ns tHZWE(5) WE LOW to High-Z Output -- 7 ns tLZWE WE HIGH to Low-Z Output 2 -- ns tSA (4) (5) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with OE HIGH. 4. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 7 ISSI IS64C1024L (R) AC WAVEFORMS WRITE CYCLE NO. 1 (CE CONTROLLED, OE IS HIGH OR LOW) (1 ) t WC VALID ADDRESS ADDRESS t SCE1 t SCE2 t SA t HA CE1 CE2 t AW t PWE1 t PWE2 WE t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE2_WR1.eps WRITE CYCLE NO. 2 (OE IS HIGH DURING WRITE CYCLE) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE1 LOW HIGH CE2 t AW t PWE1 WE t HZWE t SA DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 ISSI IS64C1024L WRITE CYCLE NO. 3 (OE IS LOW DURING WRITE CYCLE) (1) t WC ADDRESS VALID ADDRESS OE LOW CE1 LOW t HA HIGH CE2 t AW t PWE2 WE t SA DOUT t HZWE DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR3.eps Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03 9 (R) ISSI IS64C1024L (R) IS64C1024L LOW POWER VERSION ORDERING INFORMATION Temperature Range (A1): -40C to +85C Speed (ns) 15 Order Part No. Package IS64C1024L-15JA1 IS64C1024L-15KA1 IS64C1024L-15TA1 300-mil Plastic SOJ 400-mil Plastic SOJ TSOP (Type I) Temperature Range (A2): -40C to +105C Speed (ns) 15 Order Part No. Package IS64C1024L-15JA2 IS64C1024L-15KA2 IS64C1024L-15TA2 300-mil Plastic SOJ 400-mil Plastic SOJ TSOP (Type I) Temperature Range (A3): -40C to +125C Speed (ns) 15 10 Order Part No. Package IS64C1024L-15JA3 IS64C1024L-15KA3 IS64C1024L-15TA3 300-mil Plastic SOJ 400-mil Plastic SOJ TSOP (Type I) Integrated Silicon Solution, Inc. -- 1-800-379-4774 Advanced Information Rev. 00A 01/22/03