74VHCT00A Quad 2-Input NAND Gate Features General Description High speed: tPD = 5.0ns (Typ.) at TA = 25C High noise immunity: VIH = 2.0V, VIL = 0.8V The VHCT00A is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages, including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and outputs Low noise: VOLP = 0.8V (Max.) Low power dissipation: ICC = 2A (Max.) at TA = 25C Pin and function compatible with 74HCT00 Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC = 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Ordering Information Order Number Package Number Package Description 74VHCT00AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHCT00ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT00AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 74VHCT00A -- Quad 2-Input NAND Gate December 2007 Logic Symbol Pin Description Truth Table Pin Names Description An, Bn Inputs On Outputs (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 A B O L L H L H H H L H H H L www.fairchildsemi.com 2 74VHCT00A -- Quad 2-Input NAND Gate Connection Diagram Symbol Parameter Rating VCC Supply Voltage -0.5V to +7.0V VIN DC Input Voltage -0.5V to +7.0V VOUT DC Output Voltage Note 1 -0.5V to VCC + 0.5V Note 2 -0.5V to 7.0V IIK Input Diode Current -20mA IOK Output Diode Current(3) 20mA IOUT DC Output Current 25mA ICC DC VCC / GND Current TSTG TL 50mA Storage Temperature -65C to +150C Lead Temperature (Soldering, 10 seconds) 260C Recommended Operating Conditions(4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Rating 4.5V to +5.5V 0V to +5.5V Output Voltage Note 1 0V to VCC Note 2 0V to 5.5V TOPR Operating Temperature -40C to +85C t r, t f Input Rise and Fall Time, VCC = 5.0V 0.5V 0ns/V 20ns/V Notes: 1. HIGH or LOW state. IOUT absolute maximum rating must be observed. 2. VCC = 0V. 3. VOUT < GND, VOUT > VCC (Outputs Active). 4. Unused inputs must be held HIGH or LOW. They may not float. (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 3 74VHCT00A -- Quad 2-Input NAND Gate Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = -40C to +85C TA = 25C Symbol Parameter VCC (V) Conditions Min. Typ. Max. Min. Max. Units VIH HIGH Level Input Voltage 4.5 2.0 5.5 2.0 VIL LOW Level Input Voltage 4.5 0.8 0.8 5.5 0.8 0.8 HIGH Level Output Voltage 4.5 LOW Level Output Voltage 4.5 VOH VOL VIN = VIH or VIL IOH = -50A 4.40 IOH = -8mA 3.94 VIN = VIH or VIL IOL = 50A 2.0 V 2.0 4.50 4.40 V V 3.80 0.0 0.1 IOL = 8mA 0.1 V 0.36 0.44 0 - 5.5 VIN = 5.5V or GND 0.1 1.0 A Quiescent Supply Current 5.5 VIN = VCC or GND 2.0 20.0 A ICCT Maximum ICC / Input 5.5 VIN = 3.4V, Other Inputs = VCC or GND 1.35 1.50 mA IOFF Output Leakage Current (Power Down State) 0.0 VOUT = 5.5V 0.5 5.0 A IIN Input Leakage Current ICC Noise Characteristics TA = 25C Symbol Parameter Conditions VCC (V) Typ. Limit Units CL = 50pF 5.0 0.4 0.8 V CL = 50pF 5.0 -0.4 -0.8 V Minimum HIGH Level Dynamic Input Voltage CL = 50pF 5.0 2.0 V Maximum LOW Level Dynamic Input Voltage CL = 50pF 5.0 0.8 V (5) Quiet Output Maximum Dynamic VOL (5) Quiet Output Minimum Dynamic VOL (5) VILD(5) VOLP VOLV VIHD Note: 5. Parameter guaranteed by design. AC Electrical Characteristics TA = -40C to +85C TA = 25C Symbol Parameter VCC (V) Max. Min. Max. Units CL = 15pF 5.0 6.9 1.0 8.0 ns CL = 50pF 5.5 7.9 1.0 9.0 4 10 tPLH, tPHL Propagation Delay CIN Input Capacitance VCC = Open Power Dissipation Capacitance (6) CPD 5.0 0.5 Typ. Conditions Min. 10 17 pF pF Note: 6. CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (Opr.) = CPD * VCC * fIN + ICC / 4 (per gate) (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 4 74VHCT00A -- Quad 2-Input NAND Gate DC Electrical Characteristics 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45 0.25 R0.10 R0.10 8 0 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 5 74VHCT00A -- Quad 2-Input NAND Gate Physical Dimensions 74VHCT00A -- Quad 2-Input NAND Gate Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 6 74VHCT00A -- Quad 2-Input NAND Gate Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00 TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 7 ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM PDP-SPMTM SyncFETTM (R) Power220(R) (R) Power247 The Power Franchise(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) TinyBoostTM Programmable Active DroopTM TinyBuckTM (R) QFET TinyLogic(R) QSTM TINYOPTOTM QT OptoelectronicsTM TinyPowerTM (R) Quiet SeriesTM TinyPWMTM RapidConfigureTM TinyWireTM Fairchild(R) SMART STARTTM Fairchild Semiconductor(R) SerDesTM (R) SPM FACT Quiet SeriesTM UHC(R) STEALTHTM FACT(R) Ultra FRFETTM SuperFETTM FAST(R) UniFETTM SuperSOTTM-3 FastvCoreTM VCXTM (R) (R)* SuperSOTTM-6 FlashWriter SuperSOTTM-8 * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 (c)1997 Fairchild Semiconductor Corporation 74VHCT00A Rev. 1.4.0 www.fairchildsemi.com 8 74VHCT00A -- Quad 2-Input NAND Gate TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.