74VHCT00AMX - Fairchild Semiconductor Corporation

74VHCT00A — Quad 2-Input NAND Gate

74VHCT00A Rev. 1.4.0

December 2007

74VHCT00A

Quad 2-Input NAND Gate

Features

■

High speed: t

5.0ns (Typ.) at T

25°C

■

High noise immunity: V

2.0V, V

0.8V

■

Power down protection is provided on all inputs and

outputs

■

Low noise: V

OLP

0.8V (Max.)

■

Low power dissipation: I

2A (Max.) at T

25°C

■

Pin and function compatible with 74HCT00

General Description

The VHCT00A is an advanced high-speed CMOS

2-Input NAND Gate fabricated with silicon gate CMOS

technology. It achieves the high-speed operation similar

to equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. The internal circuit is

composed of 3 stages, including buffer output, which

provide high noise immunity and stable output.

Protection circuits ensure that 0V to 7V can be applied to

the input pins without regard to the supply voltage and to

the output pins with V

0V. These circuits prevent

device destruction due to mismatched supply and input/

output voltages. This device can be used to interface 3V

to 5V systems and two supply systems such as battery

backup.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74VHCT00AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012,

0.150" Narrow

74VHCT00ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHCT00AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHCT00A Rev. 1.4.0 2

74VHCT00A — Quad 2-Input NAND Gate

Connection Diagram

Pin Description

Logic Symbol

Truth Table

Pin Names Description

, B

Inputs

Outputs

ABO

LLH

LHH

HLH

HHL

74VHCT00A Rev. 1.4.0 3

74VHCT00A — Quad 2-Input NAND Gate

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

(4)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Notes:

1. HIGH or LOW state. I

OUT

absolute maximum rating must be observed.

2. V

0V.

3. V

OUT

GND, V

OUT

(Outputs Active).

4. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

Supply Voltage –0.5V to +7.0V

DC Input Voltage –0.5V to +7.0V

OUT

DC Output Voltage

Note 1

Note 2

–0.5V to V

+ 0.5V

–0.5V to 7.0V

Input Diode Current –20mA

Output Diode Current

(3)

±20mA

OUT

DC Output Current ±25mA

DC V

/ GND Current ±50mA

STG

Storage Temperature –65°C to +150°C

Lead Temperature (Soldering, 10 seconds) 260°C

Symbol Parameter Rating

Supply Voltage 4.5V to +5.5V

Input Voltage 0V to +5.5V

OUT

Output Voltage

Note 1

Note 2

0V to V

0V to 5.5V

OPR

Operating Temperature –40°C to +85°C

, t

Input Rise and Fall Time, V

5.0V ±0.5V 0ns/V

∼

20ns/V

74VHCT00A Rev. 1.4.0 4

74VHCT00A — Quad 2-Input NAND Gate

DC Electrical Characteristics

Noise Characteristics

Note:

5. Parameter guaranteed by design.

AC Electrical Characteristics

Note:

6. C

is defined as the value of the internal equivalent capacitance, which is calculated from the operating

current consumption without load. Average operating current can be obtained from the equation:

(Opr.)

• V

• f

+ I

/ 4 (per gate)

Symbol Parameter V

(V) Conditions

25°C

–40°C

to +85°C

UnitsMin. Typ. Max. Min. Max.

HIGH Level Input

Voltage

4.5 2.0 2.0 V

5.5 2.0 2.0

LOW Level Input

Voltage

4.5 0.8 0.8 V

5.5 0.8 0.8

HIGH Level Output

Voltage

4.5 V

or V

–50µA 4.40 4.50 4.40 V

–8mA 3.94 3.80

LOW Level Output

Voltage

4.5 V

or V

50µA 0.0 0.1 0.1 V

8mA 0.36 0.44

Input Leakage

Current

0 – 5.5 V

5.5V or GND ±0.1 ±1.0 µA

Quiescent Supply

Current

5.5 V

or GND 2.0 20.0 µA

CCT

Maximum I

/ Input 5.5 V

3.4V, Other

Inputs

or GND

1.35 1.50 mA

OFF

Output Leakage

Current (Power

Down State)

0.0 V

OUT

5.5V 0.5 5.0 µA

Symbol Parameter Conditions V

(V)

25°C

UnitsTyp. Limit

OLP(5)

Quiet Output Maximum Dynamic V

50pF 5.0 0.4 0.8 V

VOLV(5) Quiet Output Minimum Dynamic VOL CL = 50pF 5.0 –0.4 –0.8 V

VIHD(5) Minimum HIGH Level Dynamic Input Voltage CL = 50pF 5.0 2.0 V

VILD(5) Maximum LOW Level Dynamic Input Voltage CL = 50pF 5.0 0.8 V

Symbol Parameter VCC (V) Conditions

TA = 25°C

TA = –40°C

to +85°C

UnitsMin. Typ. Max. Min. Max.

tPLH, tPHL Propagation Delay 5.0 ± 0.5 CL = 15pF 5.0 6.9 1.0 8.0 ns

CL = 50pF 5.5 7.9 1.0 9.0

CIN Input Capacitance VCC = Open 4 10 10 pF

CPD Power Dissipation

Capacitance

(6) 17 pF

74VHCT00A Rev. 1.4.0 5

74VHCT00A — Quad 2-Input NAND Gate

Physical Dimensions

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45°

0.10

BC A

14 B

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00 4.00

3.80

(0.33)

1.27 0.51

0.35

1.75 MAX

1.50

1.25 0.25

0.10 0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

74VHCT00A Rev. 1.4.0 6

74VHCT00A — Quad 2-Input NAND Gate

Physical Dimensions (Continued)

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74VHCT00A Rev. 1.4.0 7

74VHCT00A — Quad 2-Input NAND Gate

Physical Dimensions (Continued)

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°TOP & BOTTO

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

74VHCT00A Rev. 1.4.0 8

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™

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OPTOPLANAR®

PDP-SPM™

Power220®

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Programmable Active Droop™

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Form

First Production

ative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I32

74VHCT00A — Quad 2-Input NAND Gate