© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0 1Publication Order Number:
TCP−5012UB/D
TCP-5012UB
1.2 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 1.2 pF ultra−high tuning PTICs are available as wafer-level chip
scale packages (WLCSP).
Key Features
•Ultra−High Tuning Range(5:1) and Operation up to 24 V
•Usable Frequency Range: from 700 MHz to 2.7 GHz
•High Quality Factor (Q) for Low Loss
•High Power Handling Capability
•Compatible with PTIC Control ICs from ON Semiconductor
•These devices are Pb−Free and RoHS Compliant
Typical Applications
•Multi-band, Multi-standard, Advanced and Simple Mobile Phones
•Tunable Antenna Matching Networks
•Tunable RF Filters
•Active Antennas
MARKING DIAGRAM
Device Package Shipping†
ORDERING INFORMATION
www.onsemi.com
TCP−5012UB−DT WLCSP6
(Pb−Free) 4000 Units /
7” Tape & Reel
WLCSP6
1.097x0.622
CASE 567NZ
FUNCTIONAL BLOCK DIAGRAM
PTIC Functional Block Diagram
PTIC
Bias
RF1 RF2
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer t o our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
A = Specific Device Code
Y = Year
W = Work Week
AYW
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3
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 2. PERFORMANCE DATA
Parameter Min Typ Max Unit
Operating Bias Voltage 1.0 24 V
Capacitance (Vbias = 2 V) 1.092 1.20 1.308 pF
Capacitance (Vbias = 24 V) 0.235 0.258 0.281 pF
Tuning Range (1 V - 24 V) 4.80 5.25 6.00
Tuning Range (2 V - 24 V) 4.20 4.65 5.30
Leakage Current (Vbias = 24 V) 0.1 mA
Operating Frequency 700 2700 MHz
Quality Factor @ 700 MHz, 2 V (Note 5) 55
Quality Factor @ 700 MHz, 24 V (Note 5) 75
Quality Factor @ 2.4 GHz, 2 V (Note 5) 35
Quality Factor @ 2.4 GHz, 24 V (Note 5) 35
IP3 (Vbias = 2 V) (Notes 1, 3 and 5) 70 dBm
IP3 (Vbias = 24 V) (Notes 1, 3 and 5) 80 dBm
2nd Harmonic (Vbias = 2 V) (Notes 2, 3 and 5) -65 dBm
2nd Harmonic (Vbias = 24 V) (Notes 2, 3 and 5) -75 dBm
3rd Harmonic (Vbias = 2 V) (Notes 2, 3 and 5) -45 dBm
3rd Harmonic (Vbias = 24 V) (Notes 2, 3 and 5) -75 dBm
Average Transition Time (Cmin ³ Cmax) (Note 4
and 5) 66 ms
Average Transition Time (Cmax ³ Cmin) (Note 4
and 5) 48 ms
1. f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone
2. 850 MHz, Pin +34 dBm
3. IP3 and Harmonics are measured in the shunt configuration in a 50 W environment
4. RFIN and RFOUT are both connected to DC ground
5. Sample testing only. Average Transition Time for all start and stop voltage combinations between 2 V and 24 V is 50 ms.
TCP−5012UB
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4
Representative performance data at 255C for 1.2 pF WLCSP Package
Figure 2. Capacitance Figure 3. Harmonic Power*
Figure 4. IP3*
Figure 5. Q*
*Data shown is representative only.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Input Power +40 dBm
Bias Voltage +30 (Note 6) V
Operating Temperature Range −30 to +85 °C
Storage Temperature Range −55 to +125 °C
ESD − Human Body Model Class 1B JEDEC HBM Standard (Note 7)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
6. WLCSP: Recommended Bias Voltage not to exceed 24 V.
7. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse.
TCP−5012UB
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5
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1B sensitive.
The proper ESD handling procedures should be used.
Mounting
The WLCSP PTIC is fabricated for Flip Chip solder
mounting. Connectivity to the RF and Bias terminations on
the PTIC die is established through SAC305 solder balls
with 90 mm nominal height (65 mm to 115 mm height
variation). The PTIC die is RoHS-compliant and compatible
with lead-free soldering profile.
Molding
The PTIC die is compatible for over-molding or
under-fill. Figure 6. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
Figure 7. PTIC Orientation Functional Block
Diagram
Bias
RF ANT
RF1
(PTIC Pad)
RF2
(PTIC Pad)
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6
PART NUMBER DEFINITION
Table 4. PART NUMBERS
Part Number
Capacitance Marking
Package*
2 V 24 V Device ID Trace Code
TCP−5012UB−DT 1.20 0.258 A YW** 6−bump WLCSP
*See PTIC package dimensions on following page.
**Refer to table below (Table 5) for YW trace code.
For information on device numbering and ordering codes, please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
Table 5. Two Digits Year and Work Week Date coding (YW) − In Process Product / Traceability Date Code Marking
Code Term Definition
YW Year and
Work Week
Two−character Alpha Code. Example: 2005, workweek 10 = GJ
YEAR WORK
WEEK CODE YEAR WORK
WEEK CODE YEAR WORK
WEEK CODE
2003 1
26
27
52
CA
CZ
DA
DZ
2004 1
26
27
52
EA
EZ
FA
FZ
2005 1
26
27
52
GA
GZ
HA
HZ
2006 1
26
27
52
IA
IZ
JA
JZ
2007 1
26
27
52
KA
KZ
LA
LZ
2008 1
26
27
52
MA
MZ
NA
NZ
2009 1
26
27
52
PA
PZ
RA
RZ
2010 1
26
27
52
SA
SZ
TA
TZ
2011 1
26
27
52
UA
UZ
VA
VZ
2012 1
26
27
52
WA
WZ
XA
XZ
2013 1
26
27
52
YA
YZ
ZA
ZZ
2014 1
26
27
52
AA
AZ
BA
BZ
2015 1
26
27
52
CA
CZ
DA
DZ
2016 1
26
27
52
EA
EZ
FA
FZ
2017 1
26
27
52
GA
GZ
HA
HZ
For dates outside of the table: the first character of the code is incremented at the start of workweek 01 and workweek 27
each year. The second character begins with “A” in workweek 01 of each year and increments weekly. “A” follows “Z” to make
the code continuous.
ParaScan is a trademark of Paratek Microwave, Inc.
WLCSP6, 1.097x0.622
CASE 567NZ
ISSUE A
DATE 27 SEP 2016
SEATING
PLANE
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. BACKSIDE TAPE APPLIED TO IMPROVE
PIN 1 MARKING.
2X
DIM
A
MIN NOM
0.295
MILLIMETERS
A1
A3 0.025 REF
b1 0.075 0.100
e0.40 BSC
0.335
È
È
E
D
A B
PIN A1
REFERENCE
0.05 C
C
B
A
0.06 C
A1 C
0.065 0.090
SCALE 4:1
0.05 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 3
e
12
b0.125 0.150
A
DETAIL A
DETAIL A
A0.05 BC
0.03 C
6X b
6X b1
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
PACKAGE
OUTLINE
A1
0.20
6X
0.40
0.40
PITCH
DETAIL C
DETAIL C
NOTE 4
TAPE
e
e/2
D1.047 1.097
E0.572 0.622
MAX
0.125
0.375
0.115
0.175
1.147
0.672
A3
X = Specific Device Code
Y = Year
W = Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
XYW
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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