HN58C256A Series
HN58C257A Series
256k EEPROM (32-kword × 8-bit)
Ready/Busy and RES function (HN58C257A)
REJ03C0148-0600Z
Rev. 6.00
Oct. 26. 2006
Description
Renesas Technology's HN58C256A and HN58C257A are electrically erasable and programmable ROMs
organized as 32768-word × 8-bit. They have realized high speed low power consumption and high reliability
by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
• Single 5 V supply: 5 V ±10%
• Access time: 85 ns/100 ns (max)
• Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic byte wr ite: 10 ms max
• Automatic page write (64 bytes): 10 ms max
• Ready/Busy (only the HN58C257A series)
• Data polling and Toggle bit
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 105 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin (only the HN58C257A series)
• Industrial versions (Temperatur range: −20 to 85°C and – 40 to 85°C) are also available.
• There are also lead free products.
Rev.6.00, Oct. 26.2006, page 1 of 24
HN58C256A Series, HN58C257A Series
Ordering Information
Type No. Access time Package
HN58C256AP-85
HN58C256AP-10
85 ns
100 ns
600 mil 28-pin plastic DIP
PRDP0028AB-A
(DP-28)
HN58C256AFP-85
HN58C256AFP-10
85 ns
100 ns
400 mil 28-pin plastic SOP
PRSP0028DC-A
(FP-28D)
HN58C256AT-85
HN58C256AT-10
85 ns
100 ns
28-pin plastic TSOP
PTSA0028ZB-A
(TFP-28DB)
HN58C257AT-85
HN58C257AT-10
85 ns
100 ns
32-pin plastic TSOP
PTSA0032KD-A
(TFP-32DA)
HN58C256AP-85E
HN58C256AP-10E
85 ns
100 ns
600 mil 28-pin plastic DIP
PRDP0028AB-A
(DP-28V)
Lead free
HN58C256AFP-85E
HN58C256AFP-10E
85 ns
100 ns
400 mil 28-pin plastic SOP
PRSP0028DC-A
(FP-28DV)
Lead free
HN58C256AT-85E
HN58C256AT-10E
85 ns
100 ns
28-pin plastic TSOP
PTSA0028ZB-A
(TFP-28DBV)
Lead free
HN58C257AT-85E
HN58C257AT-10E
85 ns
100 ns
32-pin plastic TSOP
PTSA0032KD-A
(TFP-32DAV)
Lead free
Rev.6.00, Oct. 26.2006, page 2 of 24
HN58C256A Series, HN58C257A Series
Pin Arrangement
HN58C256AP/AFP Series HN58C256AT Series
HN58C257AT Series
(Top view)
(Top view)
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
16
15
14
13
12
11
10
9
8
7
6
5
4
3
31
32
2
1
NC
NC
RES
RDY/Busy
Rev.6.00, Oct. 26.2006, page 3 of 24
HN58C256A Series, HN58C257A Series
Pin Description
Pin name Function
A0 to A14 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy*1 Ready busy
RES*1 Reset
NC No connection
Note: 1. This function is supported by only the HN58C257A series.
Block Diagram
Note: 1. This function is supported by only the HN58C257A series.
V
V
OE
CE
A5
A0
A6
A14
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/Busy
RES
*
1
*
1
*
1
to
to
to
Rev.6.00, Oct. 26.2006, page 4 of 24
HN58C256A Series, HN58C257A Series
Operation Table
Operation CE OE WE RES*3 RDY/Busy*3 I/O
Read VIL V
IL V
IH V
H*1 High-Z Dout
Standby VIH ×*2 × × High-Z High-Z
Write VIL V
IH V
IL V
H High-Z to VOL Din
Deselect VIL V
IH V
IH V
H High-Z High-Z
Write inhibit × × V
IH ×  
× V
IL × ×
Data polling VIL V
IL V
IH V
H V
OL Dout (I/O7)
Program reset × × × V
IL High-Z High-Z
Notes: 1. Refer to the recommended DC operating condition.
2. × : Don’t care
3. This function is supported by only the HN58C257A series.
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage rerative to VSS V
CC −0.6 to +7.0 V
Input voltage rerative to VSS Vin −0.5*1 to +7.0*3 V
Operationg temperature range*2 Topr 0 to +70 °C
Storage temperature range Tstg −55 to +125 °C
Notes: 1. Vin min = −3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
3. Should not exceed VCC + 1 V.
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
V
SS 0 0 0 V
Input voltage VIL −0.3*1 0.8 V
V
IH 2.2 V
CC + 0.3*2 V
V
H*3 V
CC −0.5 V
CC + 1.0 V
Operating temperature Topr 0 +70 °C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.
2. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.
3. This function is supported by only the HN58C257A series.
Rev.6.00, Oct. 26.2006, page 5 of 24
HN58C256A Series, HN58C257A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ±10%)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI   2*1 µA VCC = 5.5 V, Vin = 5.5 V
Output leakage current ILO 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V
Standby VCC current ICC1 20 µA CE = VCC
I
CC2 1 mA CE = VIH
Operating VCC current ICC3 12 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 5.5 V
30 mA Iout = 0 mA, Duty = 100%,
Cycle = 85 ns, VCC = 5.5 V
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH 2.4 V IOH = −400 µA
Note: 1. ILI on RES = 100 µA max (only the HN58C257A series)
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1 Cin 6 pF Vin = 0 V
Output capacitance*1 Cout 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
Rev.6.00, Oct. 26.2006, page 6 of 24
HN58C256A Series, HN58C257A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V±10%)
Test Conditions
• Input pulse levels: 0.4 V to 3.0 V, 0 V to VCC (RES pin*2)
• Input rise and fall time: ≤ 5 ns
• Input timing reference levels: 0.8, 2.0 V
• Output load: 1TTL Gate +100 pF
• Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58C256A/HN58C257A
-85 -10
Parameter Symbol Min Max Min Max Unit Test conditions
Address to output delay tACC 85 100 ns CE = OE = VIL,
WE = VIH
CE to output delay tCE 85 100 ns OE = VIL, WE = VIH
OE to output delay tOE 10 40 10 50 ns CE = VIL, WE = VIH
Address to output hold tOH 0 0 ns CE = OE = VIL,
WE = VIH
OE (CE) high to output float*1 t
DF 0 40 0 40 ns CE = VIL, WE = VIH
RES low to output float*1, 2 t
DFR 0 350 0 350 ns CE = OE = VIL,
WE = VIH
RES to output delay*2 t
RR 0 450 0 450 ns CE = OE = VIL,
WE = VIH
Rev.6.00, Oct. 26.2006, page 7 of 24
HN58C256A Series, HN58C257A Series
Write Cycle
Parameter Symbol Min*3 Typ Max Unit Test conditions
Address setup time tAS 0 ns
Address hold time tAH 50 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time tOES 0 ns
OE hold time tOEH 0 ns
Data setup time tDS 50 ns
Data hold time tDH 0 ns
WE pulse width (WE controlled) tWP 100 ns
CE pulse width (CE controlled) tCW 100 ns
Data latch time tDL 50 ns
Byte load cycle tBLC 0.2 30 µs
Byte load window tBL 100 — µs
Write cycle time tWC 10*4 ms
Time to device busy tDB 120 ns
Write start time tDW 0*5 ns
Reset protect time*2 t
RP 100 µs
Reset high time*2, 6 t
RES 1 µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. This function is supported by only the HN58C257A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy (only the HN58C257A
series) are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy (only the
HN58C257A series) are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A14 are page address and these addresses are latched at the first falling edge of WE.
8. A6 through A14 are page address and these addresses are latched at the first falling edge of CE.
9. See AC read characteristics.
Rev.6.00, Oct. 26.2006, page 8 of 24
HN58C256A Series, HN58C257A Series
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
tACC
tCE
tOE
tOH
tDF
tRR
tDFR
RES *2
Rev.6.00, Oct. 26.2006, page 9 of 24
HN58C256A Series, HN58C257A Series
Byte Write Timing Waveform (1) (WE Controlled)
Address
CE
WE
OE
Din
RDY/Busy *2
tWC
tCH
tAH
tCS
tAS tWP
tOEH
tBL
tOES
tDS tDH
tDB
tRP
RES *2
VCC
tRES
High-Z High-Z
tDW
Rev.6.00, Oct. 26.2006, page 10 of 24
HN58C256A Series, HN58C257A Series
Byte Write Timing Waveform (2) (CE Controlled)
Address
CE
WE
OE
Din
RDY/Busy *
2
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES *
2
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z High-Z
Rev.6.00, Oct. 26.2006, page 11 of 24
HN58C256A Series, HN58C257A Series
Page Write Timing Waveform (1) (WE Controlled)
Address
A0 to A14
WE
CE
OE
Din
RDY/Busy *2
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES *2
VCC
tCH
tCS
tWP
tDL tBLC
tDS
tDW
High-Z High-Z
*7
Rev.6.00, Oct. 26.2006, page 12 of 24
HN58C256A Series, HN58C257A Series
Page Write Timing Waveform (2) (CE Controlled)
Address
A0 to A14
WE
CE
OE
Din
RDY/Busy *2
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES *2
VCC
tWH
tWS
tCW
tDL tBLC
tDS
tDW
High-Z High-Z
*8
Rev.6.00, Oct. 26.2006, page 13 of 24
HN58C256A Series, HN58C257A Series
Data Polling Timing Waveform
t
CE
t
OEH
t
WC
t
DW
t
OES
Address
CE
WE
OE
I/O7
t
OE
Din X
An An
Dout XDout X
*9
*9
An
Rev.6.00, Oct. 26.2006, page 14 of 24
HN58C256A Series, HN58C257A Series
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.
Toggle bit Waveform
Notes: 1. I/O6 beginning state is "1".
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
WE
t
OES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1 *2 *2
Address
*3
*3
*4
Din
Rev.6.00, Oct. 26.2006, page 15 of 24
HN58C256A Series, HN58C257A Series
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data
5555
AA
2AAA
55
5555
A0
t
BLC
t
WC
CC
Write address
Write data
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
20
Software Data Protection Timing Waveform (2) (in non-protection mode)
Rev.6.00, Oct. 26.2006, page 16 of 24
HN58C256A Series, HN58C257A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.
RDY/Busy Signal (only the HN58C257A series)
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle,
the RDY/Busy signal changes state to high impedance.
RES Signal (only the HN58C257A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn't provide
a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit Read inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
Rev.6.00, Oct. 26.2006, page 17 of 24
HN58C256A Series, HN58C257A Series
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming
(1% cumulative failure rate). The data reten tion time is more than 10 years when a device is page-
programmed less than 104 cycles.
Data Protection
To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns
or less.
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the
control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
Rev.6.00, Oct. 26.2006, page 18 of 24
HN58C256A Series, HN58C257A Series
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET
signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
2.1 Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the
table below.
CE VCC × ×
OE × V
SS ×
WE × × V
CC
V
CC
RES
WE
or CE 100 µs min 10 ms min
1 µs min
Program inhibit Program inhibit
×: Don’t care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
2.2 Protection by RES (only the HN58C257A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept VSS level during VCC on/off.
The EEPROM breaks off programming operation when RES becomes low, programming operation
doesn’t finish correctly in case that RES falls low during programming operation. RES should be
kept high for 10 ms after the last data input.
Rev.6.00, Oct. 26.2006, page 19 of 24
HN58C256A Series, HN58C257A Series
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The
SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3
bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write
data.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
5555
↓
2AAA
↓
5555
↓
Write address Normal data input
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
5555
↓
2AAA
↓
5555
↓
5555
↓
2AAA
↓
5555
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be w ritten.
The software data protection is not enabled at the shipment.
Note: There are some differences between Renesas Technology’s and other company’s for enable/disable
sequence of software data protection. If there are any questions , please contact with Renesas
Technology’s sales offices.
Rev.6.00, Oct. 26.2006, page 20 of 24
HN58C256A Series, HN58C257A Series
Package Dimensions
HN58C256AP Series (PRDP0028AB-A / Previous Code: DP-28, DP-28V)
15.24
MaxNomMin
Dimension in Millimeters
Symbol
Reference
35.6
13.4
5.70
A1
Z
b3
D
E
A
bp
c
θ
e
L
e1
0.51
0.58
1.2
0.20 0.25 0.36
2.29 2.54 2.79
0° 15°
36.5
14.6
0.38 0.48
1.9
2.54
1528
141
3
1
p
1
ce
Z
L A
A
b
b
E
D
e
θ
P-DIP28-13.4x35.6-2.54 4.6g
MASS[Typ.]
DP-28/DP-28VPRDP0028AB-A
RENESAS CodeJEITA Package Code Previous Code
Rev.6.00, Oct. 26.2006, page 21 of 24
HN58C256A Series, HN58C257A Series
Package Dimensions (cont.)
HN58C256AFP Series (PRSP0028DC-A / Previous Code: FP-28D, FP-28DV)
F
*1
*2
p
Mx
y
1
E
Index mark
14
28 15
A
Z
H
E
D
b
1
1
p
Terminal cross section
c
b
b
c
1
1
Detail F
A
L
L
θ
A
L
e
c
1
b
1
D
E
A
2
b
p
c
θ
x
y
H
E
Z
L
1
18.3
1.7
0.20
0° 8°
11.8
0.12 0.17 0.22
0.38
0.48
0.10 0.20 0.30
8.4
0.15
0.8 1.0 1.2
2.50
Reference
Symbol
Dimension in Millimeters
Min Nom Max
18.8
A
1
0.32 0.40
12.111.5
1.27
0.15
1.12
NOTE)
1. DIMENSION"*1"
DOES NOT INCLUDE MOLD FLASH.
2. DIMENSION"*2"DOES NOT
INCLUDE TRIM OFFSET.
e
P-SOP28-8.4x18.3-1.27 0.7g
MASS[Typ.]
FP-28DPRSP0028DC-A
RENESAS CodeJEITA Package Code Previous Code
Rev.6.00, Oct. 26.2006, page 22 of 24
HN58C256A Series, HN58C257A Series
Package Dimensions (cont.)
HN58C256AT Series (PTSA0028ZB-A / Previous Code: TFP-28DB, TFP-28DBV)
0.45
0.10
0.55
13.10 13.70
0.220.14
A
1
8.20
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.20
0.600.500.40
0.15
8.00
0.200.130.05
0.30
0.20
0.220.170.12
13.40
5°0°
0.10
0.80
11.80
L
1
Z
H
D
y
x
θ
c
b
p
A
2
E
D
b
1
c
1
e
L
A
NOTE)
1. DIMENSION"*1"AND"*2(Nom)"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
*1
*3
D
p
1
Mx
y
14
28
15
Index mark
*2
e
Zb
A
E
H
D
1
1
p
Terminal cross section
c
b
b
c
1
1
Detail F
L
L
A
θ
P-TSOP(1)28-8x11.8-0.55 0.23g
MASS[Typ.]
TFP-28DB/TFP-28DBV
PTSA0028ZB-A
RENESAS CodeJEITA Package Code Previous Code
Rev.6.00, Oct. 26.2006, page 23 of 24
HN58C256A Series, HN58C257A Series
Rev.6.00, Oct. 26.2006, page 24 of 24
Package Dimensions (cont.)
HN58C257AT Series (PTSA0032KD-A / Previous Code: TFP-32DA, TFP-32DAV)
Index mark
17
32
16
y
xM
1
p
D
*2
*1
F
D
H
E
A
b
Z
e
Terminal cross section
p
1
1
c
b
b
c
Detail F
1
1
A
L
L
θ
A
L
e
c
1
b
1
D
E
A
2
b
p
c
θ
x
y
H
D
Z
L
1
12.40
0.80
0.08
0° 5°
14.00
0.12 0.17 0.22
0.20
0.30
0.080.130.18
8.00
0.125
0.40 0.50 0.60
1.20
Reference
Symbol
Dimension in Millimeters
Min Nom Max
8.20
A
1
0.14 0.22
14.2013.80
0.50
0.10
0.45
NOTE)
1. DIMENSION"*1"DOES NOT
INCLUDE MOLD FLASH.
2. DIMENSION"*2"DOES NOT
INCLUDE TRIM OFFSET.
P-TSOP(1)32-8x12.4-0.50 0.26g
MASS[Typ.]
TFP-32DA/TFP-32DAV
PTSA0032KD-A
RENESAS CodeJEITA Package Code Previous Code
Revision History HN58C256A/HN58C257A Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.0 Jun. 19. 1995 Initial issue
1.0 May. 17. 1996
4
4
5
6
Change of format
Absolute Maximun Ratings
Addition of note 4
Recommended DC Operating Conditions
VIH (min): 3.0 V to 2.2 V
DC Characteristics
VOH (min): VCC × 0.8 V to 2.4 V
AC Characteristics
Input pulse levels: 0 V to 3.0 V to 0.4 V to 3.0 V
Data Polling Timing Waveform
Addition of note 1
Toggle bit Waveform
Addition of note 4
2.0 Feb. 27. 1997 4
16
Recommended DC Operating Conditions
VIL (max): 0.6 V to 0.8 V
Functional Description
Data Protection 3: Addition of note
3.0 May. 20. 1997 16 Functional Description
Data Protection 3: Change of Description
4.0 Oct. 24. 1997 8 Timing Waveforms
Read Timing Waveform: Correct error
5.00 Nov. 17. 2003
2
20-23
Change format issued by Renesas Technology Corp.
Ordering Information
Addition of HN58C256AFP-85E, HN58C256AFP-10E, HN58C256AT-85E,
HN58C256AT-10E, HN58C257AT-85E, HN58C257AT-10E
Package Dimensions
FP-28D to FP-28D, FP-28DV
TFP-28DB to TFP-28DB, TFP-28DBV
TFP-32DA to TFP-32DA, TFP-32DAV
6.00 Oct. 26, 2006 2 Ordering Information
Addition of HN58C256AP-85E, HN58C256AP-10E
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
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© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company nam e remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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Renesas Electronics products are not subject to radiation resistance design. Pl ease be sure to implemen t safety measures to
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