TOSHIBA TC4027BP/BF/BFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4027BP, TC4027BF, TC4027BFN (Note) The JEDEC SOP (FN) is not available in TC4027B DUAL J-K MASTER--SLAVE FLIP FLOP Japan. TC4027B is J-K master-slave flip-flop having RESET and SET functions. In the case of J-K made, when the clock input is given with both RESET and SET at L, the output changes at rising 16 edge of the clock according to the states of J and K. When SET input is placed at H, and RESET input is a P (DIP 16-P-300-2.54A) placed at L, outputs become Q=H, and Q=L, Weight : 1.00g (Typ.) When RESET input is placed at H, and SET input is placed at L, outputs become Q=L, and Q=H. ae When both of RESET input and SET input are at H, 16 EE 16 outputs become Q=H and Q=H. 1 1 F (SOP16-P-300-1.27) FN (SOL16-P-150-1.27) Weight : 0.18g (Typ.) Weight : 0.13g (Typ.) MAXIMUM RATINGS PIN ASSIGNMENT CHARACTERISTIC SYMBOL RATING UNIT oe, DC Supply Voltage Voo | Vsg0.5~Vss+20 | V aiff 16 Von Input Voltage Vin | Vsg-0.5~Vpp +0.5 | V a 20 15 2 Output Voltage Vout | Vss-0.5~Vpp +0.5 | V clock! 3 [J 14 @ DC Input Current ly +10 mA RESET 4 [ f] 13 cLock2 Power Dissipation Pp 300 (DIP) / 180 (SOIC) | mW K1 5 i ] 12 RESET2 Operating Temperature Range 9 p Topr -40~85 Cc HN 6 : 5 1 K2 Storage Temperature _ eRe SET1 7 10 J2 Vss_ 8 o rT] 9 SET2 LOGIC DIAGRAM (TOP VIEW) 1/2 TC4027B BLOCK DIAGRAM RESET 775 SET 7/9 7 9 K 5/11 | | , 6/0 5 5 6 J Qr 1 10 J Qr 15 3 CK 13 7CK 5K Q--2 111K QP 14 R R CLOCK as Pe cL | | cL 4 12 961001EBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. 1997-12-11 1/7TOSHIBA TRUTH TABLE TC4027BP/BF/BFN INPUTS OUTPUTS RESET SET J K |CLOCKA] Qna1 | Qnat L H * * * H L H L * * * L H H H * * * H H L L L L ft Qne Qns L L L H f L H L L H L fF H L L L H H a Qn Qne L L * % L Qn+ On ct : Dont Care : Level Change :No Change : Change 961001EBA2' @ The products described in this document are subject to foreign exchange and foreign trade control laws. otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or 1997-12-11 2/7TOSHIBA TC4027BP/BF/BFN RECOMMENDED OPERATING CONDITIONS (Vss = OV) CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT DC Supply Voltage Vop 3 18 Vv Input Voltage Vin 0 _ Vop V STATIC ELECTRICAL CHARACTERISTICS (Vss = OV) SYM- 40C 25C 85C CHARACTERISTIC |3G) | TEST CONDITION [Voo UNIT (vy | MIN. | MAX. | MIN. | TYP. | MAX. | MIN. | MAX. 5] 495| | 495/500] | 495| ae te : Vou poutl _ 70 200 . tru 10 _ 35 100 (Low to High) 15 _ 30 80 Output Transition Time > _ 70 200 . tru 10 _ 35 100 (High to Low) 15 _ 30 80 5 150 300 ns Propagation Delay Time tou 10 7 75 130 (CLOCK -Q, Q) toHL 15 _ 60 90 . . 12 Propagation Delay Time tou 1 0 30 (SET, RESET - Q, Q) tox 15 _ AS 90 5 3.5 8 _ Max. Clock Frequency fe 10 8.0 16 MHz 15 12.0 20 _ 5 Max. Clock Input Rise Time | tre, ae 1 No L Max. Clock Input Fall Time | tic, ts Limit us Min. Pulse Width t 1 i ee "0 (SET, RESET) w 15 7 35 50 ns 5 _ 60 140 Min. Clock Pulse Width tw 10 35 60 15 _ 25 40 _ 14 Min. Setup Time t 1 6 0 (J, K- CLOCK) * 15 5 35 Min. Hold Time > a a 40 ty 10 _ 50 ns (J, K - CLOCK) 15 35 Min. Removal Time t 1 a a 0 (SET, RESET - CLOCK) mm 15 15 Input Capacitance Cin _ 5 7.5 pF 1997-12-11 4/7TOSHIBA TC4027BP/BF/BFN WAVEFORMS FOR MEASUREMENT OF DYNAMIC CHARACTERISTICS WAVEFORM 1 20ns 20ns 7 90% \ 90% CLOCK 50% 50% / A 10% k 10% Q 50% 50% tpoLH tpHL WAVEFORM 2 20ns 20ns / 3 90% f 90% SET 50% \ / / L 10% + 10% 20ns 20ns | } 90% 5 90% RESET iv 50% \ YM 10% k 10% trLH true F 90% *, | 90% Q 50% 50% 10% K_10% _| toLH tpHL WAVEFORM 3 20ns 20ns | 90% 90% I,K 50% \ 10% x 10% tsu jt _, | 20ns 20ns 5 90% 90% CLOCK JF 50% \ / 10% K_10% TTLH TTHL 0 US 10% F 90% \ 90% K_10% 1997-12-11 5/7TOSHIBA TC4027BP/BF/BFN DIP 16PIN OUTLINE DRAWING (DIP16-P-300-2.54A) Unit in mm 16 8 eee % Py od) ee) 0 ! z & ne] 3 FP wy 1 8 == 19.75MAX 19.2540.2 0.95+0.1 u z 3] 0.735TYP | | 1.440.1 | 0.540.1 FI0.25 2.54 Weight : 1.00g (Typ.) SOP 16PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300-1.27) Unit in mm 16 9 ; BEBRARAEA Ny 9 = s| i > | toad oo HHA HAHAHA 4 1 8 o.7osTvP| | |_| 0.4310.1 Pere 55 Gy 27] 1 | 10.8MAX 10.340.2 ol FA = Coe ef 2 sar Lt 710.1 eT So | 0,820.2 Weight : 0.18g (Typ.) 1997-12-11 6/7TOSHIBA SOP 16PIN (150mil BODY) OUTLINE DRAWING (SOL16-P-150 -1.27) TC4027BP/BF/BFN Unit in mm Weight : 0.13g (Typ.) 0.505T YP (Note) This package is not available in Japan. 16 9 AAA AAA A 3.940.1 6.040.2 9.9+0.1 1 A BE AHO i 8 0.4240.07 era aEGy [ 710.1] : 1.37540.2 0.15345 0.17540.075 | 0.740.3 1997-12-11 TT