Preliminary W26B021 128K x 16 CMOS STATIC RAM GENERAL DESCRIPTION The W26B021 is a normal speed, very low-power CMOS static RAM organized as 131,072 x 16 bits that operates on a wide voltage range from 2.2V to 3.6V power supply. The W26B021T-LL, W26B021T-LE and W26B021T-LI, can meet the requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * * * * * * Low power consumption Access time: 70, 100 nS 2.2V to 3.6V supply voltage Fully static operation All inputs and outputs directly TTL compatible Three-state outputs * Battery back-up operation capability Data retention voltage: 1.5V (min.) Data byte control - #LB (I/O1 - I/O8), #UB (I/O9 - I/O16) * Available packages: 48-pin TSOP * * BLOCK DIAGRAM PIN CONFIGURATION CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A4 A3 A15 A14 A16 A1 A2 A0 1024 ROWS D E C O D E R 128 X 16 COLUMNS A13 A15 A14 A13 A12 A11 A10 A9 A8 NC NC #WE CS2 NC #UB #LB NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 V DD I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 #OE VSS #CS1 A0 I/O1 : I/O16 I/O CKT. COLUMN DECODER DATA CNTRL. CLK GEN. A7 A6 A5 A8 A9 A10 A11 A12 #WE #CS #UB #LB #OE PIN DESCRIPTION SYMBOL A0 - A16 I/O1 - I/O16 #CS1 CS2 #WE #LB #UB #OE VDD VSS NC -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input 1, Low Active Chip Select Input 2, High Active Write Enable Input Lower byte select Upper byte select Output Enable Input Power Supply Ground No Connection Publication Release Date: April 19, 2002 Revision A1 Preliminary W26B021 TRUTH TABLE I/O1 - I/O8 I/O9 - I/O16 VDD CURRENT Not Selected High Z High Z ISB, ISB1 X Not Selected High Z High Z ISB, ISB1 H H Not Selected High Z High Z ISB, ISB1 H X X Output Disable High Z High Z IDD L H L L 2 Bytes Read DOUT DOUT IDD H L H L H Lower Byte Read DOUT High Z IDD L H L H H L Upper Byte Read High Z DOUT IDD L H X L L L 2 Bytes Write DIN DIN IDD L H X L L H Lower Byte Write DIN High Z IDD L H X L H L Upper Byte Write High Z DIN IDD #CS1 CS2 #OE #WE #LB #UB H X X X X X X L X X X X X X X L H H L H L MODE -2- Preliminary W26B021 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +4.6 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C LL 0 to 70 C LE -20 to 85 C LI -40 to 85 C Supply Voltage to VSS Potential Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VSS = 0V; TA (C) = 0 to 70 for LL, -20 to 85 for LE, -40 to 85 for LI) PARAMETER SYM. W26B021 TEST CONDITIONS MIN. MAX. UNIT Operating Power Voltage VDD - 2.2 3.6 V Input Low Voltage VIL - -0.3 +0.4 V Input High Voltage VIH VDD = 2.7V to 3.6V +2.4 VDD +0.4 VDD = 2.2V to 2.7V +2.0 VDD +0.3 Input Leakage Current ILI VIN = VSS to VDD -1 +1 A Output Leakage Current ILO VI/O = VSS to VDD; #CS1 = VIH (min.) or CS2 = VIL (max.) or #OE = VIH (min.) or #WE = VIL (max.) -1 +1 A Output Low Voltage VOL IOL = +1.0 mA, VDD = 2.7V to 3.6V - 0.4 IOL = +1.0 mA, VDD = 2.2V to 2.7V - 0.4 Output High Voltage VOH IOH = -0.5 mA, VDD = 2.7V to 3.6V 2.4 - IOH = -0.5 mA, VDD = 2.2V to 2.7V 1.8 - Operating Power Supply Current IDD #CS1 = VIL (max.) and CS2 = VIH (min.), I/O = 0 mA; Cycle = min. Duty = 100% - 20 mA ISB #CS1 = VIH (min.) or CS2 = VIL (max.) - 0.3 mA ISB1 #CS1 VDD -0.2V, CS2 VDD -0.2V or #CS1 0.2V, CS2 0.2V - 5 A Standby Power Supply Current -3- V V V Publication Release Date: April 19, 2002 Revision A1 Preliminary W26B021 CAPACITANCE (TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 8 pF Input/Output Capacitance CI/O VOUT = 0V 10 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 5 pF Including Jig and Scope 100 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0V 90% 10% 0V 90% 10% 5 nS 5 nS -4- Preliminary W26B021 AC Characteristics, continued (VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI) Read Cycle PARAMETER SYM. W26B021-70 W26B021-10 MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 100 - nS Address Access Time TAA - 70 - 100 nS Chip Select Access Time TACS - 70 - 100 nS Output Enable to Output Valid TAOE - 35 - 50 nS #UB, #LB Access Tim TBA - 70 - 100 nS Chip Selection to Output in Low Z TCLZ* 10 - 10 - nS Output Enable to Output in Low Z TOLZ* 5 - 5 - nS #UB, #LB Enable to Output in Low Z TBLZ* 5 - 5 - nS Chip Deselection to Output in High Z TCHZ* - 30 - 35 nS Output Disable to Output in High Z TOHZ* - 30 - 35 nS #UB, #LB Disable to Output in High Z TBHZ* - 30 - 35 nS Output Hold from Address Change TOH 10 - 10 - nS These parameters are sampled but not 100% tested Write Cycle PARAMETER SYM. W26B021-70 W26B021-10 MIN. MAX. MIN. MAX. UNIT Write Cycle Time TWC 70 - 100 - nS Chip Selection to End of Write TCW 60 - 80 - nS Address Valid to End of Write TAW 60 - 80 - nS #UB, #LB Select to End of Write TBW 60 - 80 - nS Address Setup Time TAS 0 - 0 - nS Write Pulse Width TWP 55 - 60 - nS TWR 0 - 0 - nS Data Valid to End of Write TDW 40 - 40 - nS Data Hold from End of Write TDH 0 - 0 - nS Write to Output in High Z TWHZ* - 30 - 35 nS Output Disable to Output in High Z TOHZ* - 30 - 35 nS Output Active from End of Write TOW 5 - 5 - nS Write Recovery Time #CS1, CS2, #WE These parameters are sampled but not 100% tested -5- Publication Release Date: April 19, 2002 Revision A1 Preliminary W26B021 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH D OUT Read Cycle 2 (Chip Select Controlled, #OE = VIL, #WE= VIH) TRC Address #CS1 CS2 TACS TCHZ TCLZ #OE TOLZ TAOE TOHZ TBA #UB / #LB TBHZ HIGH-Z TBLZ HIGH-Z D OUT -6- Preliminary W26B021 Timing Waveforms, continued Read Cycle 3 (Output Enable Controlled) T RC C Address T AA #OE T OH T AOE T OLZ #CS1 CS2 T ACS T CHZ T OHZ T CLZ D OUT Write Cycle 1 (#OE Clock) T WC Address TWR #OE TCW #CS1 CS2 TBW #UB/#LB TAW TWP #WE TAS D OUT TDW TDH D IN -7- Publication Release Date: April 19, 2002 Revision A1 Preliminary W26B021 Timing Waveforms, continued Write Cycle 2 (#OE = VIL Fixed) TWC Address TCW TWR #CS1 CS2 TBW #UB/#LB TAW #WE TWP TAS TWHZ (1, 4) TOH TOW (2) (3) D OUT TDW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -8- Preliminary W26B021 DATA RETENTION CHARACTERISTICS (TA (C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 1.5 - - V VDD for Data Retention VDR #CS1 VDD-0.2V or CS2 0.2V Data Retention Current IDDDR #CS1 VDD -0.2V or CS2 0.2V, VDD = 3.0V - - 5 A Chip Deselect to Data Retention Time TCDR See data retention waveform 0 - - nS Operation Recovery Time TR TRC* - - nS * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 x V DD > 1.5V VDR = TCDR #CS1 CS2 0.9 x V DD TR > V DD - 0.2V #CS1 = CS2 < = 0.2V -9- Publication Release Date: April 19, 2002 Revision A1 Preliminary W26B021 ORDERING INFORMATION ACCESS TIME OPERATING VOLTAGE (V) OPERATING TEMPERATURE (nS) STANDBY CURRENT (A) (C) W26B021T70LL 70 3V/5 A 0 to 70 48L TSOP-I W26B021T70LE 70 3V/5 A -20 to 85 48L TSOP-I W26B021T70LI 70 3V/5 A -40 to 85 48L TSOP-I W26B021T10LL 70 3V/5 A 0 to 70 48L TSOP-I W26B021T10LE 100 3V/5 A -20 to 85 48L TSOP-I W26B021T10LI 100 3V/5 A -40 to 85 48L TSOP-I PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 10 - Preliminary W26B021 PACKAGE DIMENSION TSOP48 48-Pin Standard Thin Small Outline Package (measured in millimeters) MILLIMETER INCH SYMBOL Min. Nom. Max. - 11 - Min. Nom. Max. Publication Release Date: April 19, 2002 Revision A1 Preliminary W26B021 VERSION HISTORY VERSION A1 DATE PAGE Apr. 19, 2002 - DESCRIPTION Initial Issued Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 12 -