ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 1 of 18
Member of the Family
Applications
• Low voltage, high density systems with
Interm ediate Bus Ar c hitec tur es (IBA)
• Point-of-load regulators for high performance DSP,
FPGA, AS IC , and microprocessor applications
• Desktops, servers, and portable computing
• Broadban d, net work ing, opt ic al, and
communications systems
• Active memory bus terminators
Benefits
• Integrates digital power conversion with intelligent
power management
• Eliminates the need for external power
management components and communication bus
• Completely programmable via pin strapping and
external R and C
• One part that covers all applications
• Reduces board space, system cost and
complexity, and time to market
Features
• RoHS lead free and lead-solder-exempt products are
available
• Wide input voltage range: 3V–14V
• High continuous output current: 7A
• Wide programmable output voltage range: 0.5V–5.5V
• Active digital current share
• Output voltage margining
• Overcurrent and overtemperature protections
• Overvoltage and under volt age pr otec ti ons, and Po wer
Good signal tracking the output voltage setpoint
• Programmable power-up delay
• Tracking during turn-on and turn-off with guaranteed
slew rates
• Sequenced and cascaded modes of operation
• Single-wire line for frequency synchronization
between multiple POLs
• Programmable interleave
• Programmable feedback loop compensation
• Enable control with programmable polarity
• Flexible fault management and propagation
• Start-up into the load pre-biased up to 100%
• Full rated current sink
• Real time current and temperature measurements,
monitoring, and reporting
• Small footprint SMT package: 12.5x22mm
• Low profile of 6.5mm
• Compatible with conventional pick-and-place
equipment
• Wide industrial operating temperature range
• UL 60950-1/CS A 22.2 No. 60950-1-07 Second
Edition, IEC 60950-1: 2005, and EN 60950-1:2006
Description
Power-One’s point-of-load converters are recommended for use with regulated bus converters in an Intermediate
Bus Arc hitecture (IBA) . The ZY1207 is an int elligent, f ully programm able step-down p oint-of-load DC -DC module
integrating digital power conversion and intelligent power management. The ZY1207 completely eliminates the
need for external components for sequencing, tracking, protection, monitoring, and reporting. Performance
parameters of the ZY1207 are programmable by pin strapping and external resistor and capacitor and can be
changed by a user at any time during product development and service without a need for a communication bus.
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 2 of 18
Reference Documents
No-BusTM POL Converters. Z-1000 Series Application Note
Z-One® POL Converters. Eutectic Solder Process Application Note
Z-One® POL Converters. Lead-Free Process Application Note
1. Orderin g Information
ZY 12 07 x y – zz
Product
family:
Z-One
Module
Series:
No-Bus
POL
Converter
Output
Current:
7A
Output voltage setpoint
accuracy:
No suffix – 1.5% or 35mV,
whichever is greater.
H1 – 1.5% or 20mV,
whichever is greater
RoHS compliance:
No suffix - RoHS
compliant with Pb
solder exemption2
G - RoHS compliant
for all six substances
Dash
Packaging Option3:
T1 – 500 pcs T&R
T2 – 100 pcs T&R
T3 – 50pcs T&R
Q1 – 1pc sample for
evaluation only
K1 – 1pc mounted on
the evaluation board4
______________________________________
1 Contact factory f or availabil i t y.
2 The solder exemption ref ers to all the rest rict ed materials except lead in solder. These materials are Cadmi um (Cd), Hexavalent chrom ium
(Cr6+), Mercury (Hg), P ol ybromi nated biphenyl s (PBB), Polybrominated diphenylethers (P B DE), and Lead (Pb) used anywhere except in
solder.
3 Packaging opti on is used only for ordering and not included in the part number printed on the POL converter label.
4 The evaluation board is avail abl e in only one configurati on: ZY 1207-K1.
Example: ZY1207HG-T2: A 100-peices reel of RoH S compliant POL converter s with the output voltage setpoint
of 1.5% or 20mV, whichever is greater. Each POL converter is labeled ZY1207HG.
2. A b solute Maximum Ratings
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-
term reliability, and cause permanent damage to the POL converter.
Parameter Conditions/Description Min Max Units
Operating Temperature Controller Case Temperature -40 105 °C
Input Voltage 250ms Transient 15 VDC
Output Current (See Output Current Derating Curves) -7 7 ADC
3. Environmental and Mechanic al Specifications
Parameter Conditions/Description Min Nom Max Units
Ambient Temperature Range -40 85 °C
Storage Temperature (Ts) -55 125 °C
Weight 8 grams
MTBF Calculated Per Telcordia Technologies SR-332 6.24 MHrs
Peak Reflow Temperature ZY1207
ZY1207G
245
220
260
°C
°
C
Lead Plating ZY1207 and ZY1207G
100% Matte Tin or
1.5µm Ag over 1.5µm Ni
Moisture Sensitivity Level
ZY1207
ZY1207G
2
3
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 3 of 18
4. Electrical Specifications
Specifications apply at the input voltage from 3V to 14V, o utp ut loa d from 0 to 7A, ambient temperature from -40°C
to 85°C, output capacitance consisting of 110µF ceramic and 220µF tantalum, and default performance
parameters settings unless otherwise noted.
4.1 Input Specifications
Parameter Conditions/Description Min Nom Max Units
Input voltage (VIN) At VIN<4.75V, VLDO pin needs to be
connected to an external voltage source
higher than 4.75V 3 14 VDC
Input Current (at no load) VIN≥4.75V, VLDO pin connected to VIN 50 mADC
Undervoltage Lockout (VLDO
connected to VIN) Ramping Up
Ramping Down 4.00
3.9 VDC
VDC
Undervoltage Lockout (VLDO
connected to VAUX=5V) Ramping Up
Ramping Down 2.8
2.7 VDC
VDC
External Low Voltage Supply Connect to VLDO pin when VIN<4.75V 4.75 14 VDC
VLDO Input Current Current drawn from the external low
voltage supply at VLDO=5V 50 mADC
4.2 Output Specifications
Parameter Conditions/Description Min Nom Max Units
Output Current (IOUT) VIN MIN to VIN MAX -71 7 ADC
Output Voltage Range (VOUT)
Programmable2
0.5
with a resistor between
TRIM and REF pins
Default (no resistor)
0.5
5.5
VDC
VDC
Output Voltage Setpoint
Accuracy3VIN=12V, IOUT=0.5*IOUT MAX, room
temperature See Ordering Information
Line Regulation3 VIN MIN to VIN MAX ±0.2 %VOUT
Load Regulation3 0 to IOUT MAX ±0.2 %VOUT
Dynamic Regulation
Peak Deviation
Peak Deviation
Settling Time
Slew rate 1A/µs, 50-75% load step,
VIN≥5V
VIN=3.3V
to 10% of peak deviation
75
100
30
mV
mV
µ
s
Output Voltage Peak-to-Peak
Ripple and Noise
BW=20MHz
Full Load
VIN=5.0V, VOUT≤2.5V
VIN=5.0V, VOUT>2.5V
VIN=12V, VOUT≤2.5V
VIN=12V, VOUT>2.5V
15
25
25
40
mV
mV
mV
mV
Temperature Coefficient VIN=12V, IOUT=0.5*IOU T MAX 50 ppm/°C
Switching Frequency 450 500 550 kHz
1 At the negative output current (bus terminator mode) efficiency of the ZY1207 degrades resulting in increased internal power dissipation.
Therefore maximum allowable negative current under specific conditions is 20% lower than the current determined from the derating curves
shown in paragraph 5.5.
2 ZY1207 is a step-down converter, thus the output volt age is always lower than the input voltage as show in Figure 1.
3 Digital PW M has an inherent quantization uncert ai nt y of ±6.25mV that is not included in the specif i ed static regulati on parameters.
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 4 of 18
Figure 1. Output Voltage as a Function of Input Voltage and Output Current
4.3 Protection Specifications
Parameter Conditions/Description Min Nom Max Units
Output Overcurrent Protection
Type Non-Latching, 130ms period
Threshold 140 %IOUT
Threshold Accuracy -25 25 %IOCP.SET
Output Overvoltage Protection
Type Latching
Threshold Follows the output voltage setpoint 1301 %VO.SET
Threshold Accuracy Measured at VO.SET=2.5V -2 2 %VOVP.SET
Delay From instant when threshold is exceeded until
the turn-off co mm and is gener ated 6 μs
Output Undervoltage Protection
Type Non-Latching, 130ms period
Threshold Follows the output voltage setpoint 75 %VO.SET
Threshold Accuracy Measured at VO.SET=2.5V -2 2 %VUVP.SET
Delay From inst ant when threshold is exceeded until
the turn-off co mm and is gener ated 6 μs
5.0
4.0
3.0
2.0
1.0
V
OUT
[V]
14.0
12.0
10.0
8.0
6.0
2.0
4.0
Min Load 0.2A
V
IN
[V]
3.0
3.3
5.5
2.5
5.5
4.5
3.5
1.5
0.5
6.25
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 5 of 18
Overtemperature Protection
Type Non-Latching, 130ms period
Turn Off Threshold Temperature is increasing 120 °C
Turn On Threshold
Temperature is decreasing after module was
shut down by OTP
110 °C
Threshold Accuracy -5 5 °C
Delay From instant when threshold is exceeded until
the turn-off co mm and is gener ated
6 μs
Power Good Signal (PGOOD pin)
Logic
V
OUT
is inside the PG window and stable
VOUT is outside of the PG window or ramping
up/down
High
Low
N/A
Lower Threshold Follows the output voltage setpoint 90 %VO.SET
Upper Threshold Follows the output voltage setpoint 110 %VO.SET
Delay From instant when threshold is exceeded until
status of PG signal changes
6 μs
Threshold Accuracy Measured at VO.SET=2.5V -2 2 %VO.SET
___________________
1 Minimum OVP threshold is 1 .0V
4.4 Feature Specifications
Parameter Conditions/Description Min Nom Max Units
Current Sha re (CS pin)
Type Active, Single Line
Maximum Number of Modules
Connected in Parall el IOUT MIN=0 4
Current Share Accuracy IOUT MIN≥20%*IOUT NOM ±20 %IOUT
Interleave (IM and INTL2…INTL4 pins)
Interleav e (Pha se Lag)
Programmable via INTL2…INTL4 pins in
45
°
steps
0
315
degree
Sequencing (DELAY pin)
Power-Up Delay
Programmab le by capacit or co nnec ted to
DELAY pin
210
ms
Default: CDELAY=0 0 ms
Tracking
Rising Slew Rate Proportional to SYNC frequency 0.1 V/ms
Falling Slew Rate Proportional to SYNC frequency -0.5 V/ms
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 6 of 18
Enable (EN and ENP pins)
EN Pin Polarity
ENP pin is pulled low
ENP pin is open
Negative (enables the output when EN pin is
pulled low)
Positive (enables the output when EN pin is
open or pulled high)
EN High Threshold 2.3 VDC
EN Low Threshold 1.0 VDC
Open Circuit Voltage EN and ENP 3.3 VDC
Turn-On Delay
From EN pin changing state to V
OUT
starting to ramp up
0 ms
Turn-Off Delay
From EN pin changing state to V
OUT
reaching 0V
11 ms
Feedback Loop Compensation (CCA0…CCA2 pins)
CCA=7 (default)
Recommended VIN range
8
12
14
VDC
Recommended C
OUT
/ESR range,
combination of ceramic+ tantalum
50/5 +
220/40
100/5 +
470/40
400/5 +
2000/20
µF/mΩ
µF/mΩ
CCA=6
Recommended VIN range
8
12
14
VDC
Recommended C
OUT
range, ta ntalu m
Recommended ESR range, tantalum
440
40
880
25
10,000
10
µF
mΩ
CCA=5 Recommended VIN range 8 12 14 VDC
Recommended COUT/ESR range, ceramic
100/5
220/5
400/5
µF/mΩ
CCA=3 or CCA=4
Recommended VIN range
3
5
5.5
VDC
Recommended C
OUT
/ESR range,
combinatio n of cerami c + tantalum
50/5 +
220/40
100/5 +
470/40
200/5 +
880/40
µF/mΩ
µF/mΩ
CCA=2 Recommended VIN range 3 5 5.5 VDC
Recommended COUT/ESR range, tantalum
100/25
440/20
1,000/10
µF/mΩ
CCA=1
Recommended VIN range
3
5
5.5
VDC
Recommended COUT/ESR range, ceramic 100/5 220/5 400/5 µF/mΩ
CCA=0 Recommended VIN range 6 11 VDC
Recommended COUT/ESR range,
combinatio n of cerami c+ tantalum
50/5 +
220/40
100/5 +
470/40
200/5 +
880/40
µF/mΩ
µF/mΩ
Output Current Monitoring (CS pin)
Output Current Monitoring
Accuracy 20%*IOUT NOM < IOUT < IOUT NOM
VIN=12V -20 +20 %IOUT
Conversion Ratio
Duty Cycle of the negative pulse
correspon din g to 100% of nominal curr ent
70 %
Temperature Monitoring (TEMP pin)
Temperature Monitoring
Accuracy
Junction temperature of POL controller -5 +5 °C
Conversion Ratio Junction temperature from -40°C to 140°C 10 mV/°C
Monitoring Voltage Range Corresponds to -40°C to 140°C junction
temperature range
0.2 2 VDC
Output Impedance TEMP pin 6.4 kΩ
Remote Voltage Sense (+VS pin)
Voltage Drop Compensation Between +VS and VOUT 300 mV
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 7 of 18
4.5 Signal Specifications
Parameter Conditions/Description Min Nom Max Units
VDD Internal supply voltage 3.15 3.3 3.45 V
SYNC Line
ViL_s LOW level input voltage -0.5 0.3 x VDD V
ViH_s HIGH level input voltage 0.75 x
VDD
VDD + 0.5 V
Vhyst_s Hysteresis of input Schmitt trigger
0.25 x
VDD
0.45 x
VDD
V
IoL_s LO W level sink current V(SYNC)=0.5V 14 60 mA
Ipu_s Pull-up current source V(SYNC)=0V 300 1000 μA
Tr_s Maximum allowed rise time 10/90%VDD 300 ns
Cnode_s Added node capacit an ce 5 10 pF
Freq_s Clock frequency of external SYNC line 475 525 kHz
Tsynq Sync pulse duration 22 28
% of clock
cycle
T0 Data=0 pulse duration 72 78
% of clock
cycle
Inputs: INTL2…INTL4, CCA0…CCA2, EN, ENP, IM
Iup_x Pull-up current source V(X)=0 25 110 μA
ViL_x LOW level input voltage -0.5 0.3 x VDD V
ViH_x HIGH level input voltage 0.7 x VDD VDD+0.5 V
Vhyst_x Hysteresis of input Schmitt trigger 0.1 x VDD 0.3 x VDD V
RdnL_x
External pull down resistance
pin forced low
10 kOhm
Power Good and OK Inputs/Outputs
Iup_PG Pull-up current source V(PG)=0 25 110 μA
Iup_OK Pull-up current source V(OK)=0 175 725 μA
ViL_x LOW level input voltage -0.5 0.3 x VDD V
ViH_x HIGH level input voltage 0.7 x VDD VDD+0.5 V
Vhyst_x Hysteresis of input Schmitt trigger 0.1 x VDD 0.3 x VDD V
IoL_x LOW level sink current at 0.5V 4 20 mA
Current Sha re/Sense Bus
Iup_CS Pull-up current source at V(CS)=0V 0.84 3.10 mA
ViL_CS LOW level input voltage -0.5 0.3 x VDD V
ViH_CS HIGH level input voltage 0.75 x
VDD
VDD+0.5 V
Vhyst_CS Hysteresis of input Schmitt trigger
0.25 x
VDD
0.45 x
VDD
V
IoL_CS LOW level sink curren t V(CS)=0.5V 14 60 mA
Tr_CS Maxim um allowed rise time 10/90% VDD 100 ns
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 8 of 18
5. Typical Performance Characteristics
5.1 Efficiency Curves
55
60
65
70
75
80
85
90
95
0 1 2 3 4 5 6 7
O ut put Cur r ent , A
Eff i ci ency, %
Vo=0.5V Vo=1.2V Vo=2.5V
Figure 2. Efficiency vs. Load. Vin=3.3V
60
65
70
75
80
85
90
95
0 1 2 3 4 5 6 7
O ut put Cur r ent , A
Eff i ci ency, %
Vo=0.5V Vo=1.2V
Vo=2.5V Vo=3.3V
Figure 3. Efficiency vs. Load. Vin=5V
74
76
78
80
82
84
86
88
90
92
94
0 1 2 3 4 5 6 7
O ut put Cur r ent , A
Eff i ci ency, %
Vo=1.2V Vo=2.5V
Vo=3.3V Vo=5.0V
Figure 4. Efficiency vs. Load. Vin=9.6V
70
72
74
76
78
80
82
84
86
88
90
92
0 1 2 3 4 5 6 7
O ut put Cur r ent , A
Eff i ci ency, %
Vo=1.2V Vo=2.5V
Vo=3.3V Vo=5.0V
Figure 5. Efficiency vs. Load. Vin=12V
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 9 of 18
55
60
65
70
75
80
85
90
95
0.5 1.5 2.5 3.5 4.5 5.5
O ut put Volta ge, V
Eff i ci ency, %
Vin=5V Vin=3.3V
Vin=9.6V Vin=12V
Figure 6. Efficiency vs. Output Voltage, Iout=7A
50
55
60
65
70
75
80
85
90
345678910 11 12 13 14
I nput Vol tage, V
Eff i ci ency, %
Vo=0.5V Vo=1.2V Vo=2.5V
Figure 7. Efficiency vs. Input Voltage. Iout=7A
5.2 Turn-On Characteristics
Figure 8. Trackin g Turn -O n .
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
5.3 Turn-Off Characteri stics
Figure 9. Trackin g Turn -Off
Vin=12V, Ch1 – V1, C h2 – V2, Ch3 – V3
5.4 Transient Respon se
The pictures in Figure 10 - Figure 15 show the
deviatio n of the output volt age in response to the 50-
75-50% step load at 1.0A/μs. In all tests the POL
converters had 5x22μF ceramic capacitors and a
220μF tantalum capacitor connected across the
output pins. The speed of the transient response
was optimized by selecting appropriate CCA
settings.
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 10 of 18
Figure 10. Vin=12V, Vout=1 V. CCA=00
Figure 11. Vin=12V, Vout=2.5V. CCA=00
Figure 12. Vin=12V, Vout=5V, CCA=00
Figure 13. Vin=5V, Vout= 1V. CCA=03
Figure 14. Vin=5V, Vo u t = 2 .5V. CCA=03
Figure 15. Vin=3.3V, Vout=1 V. CCA=03
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 11 of 18
5.5 Thermal Derating Curves
3
3.5
4
4.5
5
5.5
6
6.5
7
45 55 65 75 85
Am bient Temperature, D egree C
Output C urrent, A
0LFM 100LFM 200LFM 400LFM 600LFM
Figure 16. Thermal Derating Curves. Vin=12V, Vout=5.0V
3
3.5
4
4.5
5
5.5
6
6.5
7
45 55 65 75 85
Am bient Temperature, D egree C
Output Current , A
0LFM 100LFM 200LFM 400LFM 600LFM
Figure 17. Thermal Derating Curves. Vin=14V, Vout=5.0V
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 12 of 18
6. Typical Application
POL1
22uF
220uF
TRIM
VREF
IM
INTL2
INTL3
INTL4
CCA0
CCA1
CCA2
ENP
EN
CS SYNC OK
PGOOD
DELAY
TEMP
4.7uF 4.7uF
POL4
22uF
220uF
TRIM
VREF
IM
INTL2
INTL3
INTL4
CCA0
CCA1
CCA2
ENP
EN
CS SYNC OK
PGOOD
DELAY
TEMP
4.7uF 4.7uF
POL3
22uF
220uF
TRIM
VREF
IM
INTL2
INTL3
INTL4
CCA0
CCA1
CCA2
ENP
EN
CS SYNC OK
PGOOD
DELAY
TEMP
4.7uF 4.7uF
POL2
22uF
220uF
VLDO
VIN
+VS
VOUT
PGND
TRIM
VREF
IM
INTL2
INTL3
INTL4
CCA0
CCA1
CCA2
ENP
EN
CS SYNC OK
PGOOD
DELAY
TEMP
4.7uF 4.7uF
47uF
IBV
Vo1
Vo2
Vo3
ENABLE
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
VIN
VIN
VIN
VIN
+VS
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
VLDO
VIN
VIN
VIN
VIN
VIN
VLDO
VIN
VIN
VIN
VIN
VIN
VLDO
VIN
VIN
VIN
VIN
VIN
+VS
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
+VS
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
47uF
47uF 47uF 47uF 47uF
47uF 47uF
PGND
PGND PGND
PGND
Figure 18. Complete Schematic of Application with Three Independent Outputs. Intermediate Bus Voltage is from 8V to 14V.
In this application four POL converters are configured to deliver three independent output voltages. POL1 and
POL2 are connected in parallel for increased output current. Output voltages are programm ed with the resistors
connected between TRIM and VREF pins of individual converters.
POL1 is configured as a master (IM and INTL0…INTL4 pins are grounded) and all other POL converters are
synchronized to the switching frequency of POL1. Interleave is programmed with pins INTL0…INTL4 to ensure
the lowest input and output noise. POL2 has 180° phase shift, POL 3 and POL4 have phase shifts of 270° and
90° respectively.
All converters are controlled by the common ENABLE signal. Turn-on and turn-off processes of the system are
illustrated by pictures in Figure 8 and Figure 9.
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 13 of 18
7. Pin Assignments and Description
Pin
Name Pin
No. Pin
Type Buffer
Type Pin Description Notes
VLDO 1 P Low Voltage Dropout
Connect to an external voltage source higher
than 4.75V, if VIN<4.75V. Connect to VIN, if
VIN≥4.75V
CCA0 2 I PU Compensation Coefficient Address
Bit 0
Tie to PGND for 0 or leave open for 1
CCA1 3 I PU
Compensation Coefficient Address
Bit 1
Tie to PGND for 0 or leave open for 1
CCA2 4 I PU Compensation Coefficient Address
Bit 2
Tie to PGND for 0 or leave op en for 1
TEMP 5 A Temperature Meas urement
Analog voltage proportional to junction
temperatur e of the contr oll er
ENP 6 I PU Enable Logic Selection Tie to PGND for Negative logic or leave open
for Positive logic
INTL2 7 I PU Interleav e Bit 2 Tie to PGND for 0 or leave open for 1
INTL3 8 I PU Interleav e Bit 3 Tie to PGND for 0 or leave open for 1
INTL4 9 I PU Interleav e Bit 4 Tie to PGND for 0 or leave open for 1
CS 10 I/O PU Current Share/Sense Connect to CS pin of other Z-POLs connected
in parallel
TRIM 11 A Output Voltage Trim
To program the output voltage, connect a
resistor between VREF and TRIM
PGOOD 12 I/O PU Power Good
SYNC 13 I/O PU Frequency Synchr oniz at ion Line
Connect to SYNC pin of other Z-POLs and/or
to an external clock generator
OK 14 I/O PU Fault Status
Connect to OK pin of other Z-1000 POLs.
Leave open, if not used
EN 15 I PU Enable Polarity is determined by ENP pin
VREF 16 A Voltage Reference
To program the output voltage, connect a
resistor between VREF and TRIM
IM 17 I PU Interleave Mode Tie to PGND for master or leave open to set
interleave by INTL0…INTL4 pins
DELAY 18 A Power-Up Delay
Connect a capacitor between the pin and
PGND to program the Power-Up delay. Leave
open for zero delay
VOUT 19-
23
P Output Voltage
+VS 24 I PU Positive Voltage Sense Connect to the positive point close to the load
PGND 25-
31
P Power Ground
VIN
32-
36
P Input Voltage
Legend: I=input, O=output, I/O=input/out put, P=power, A=anal og, P U=i nternal pul l -up
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 14 of 18
8. Pin and Feature Description
8.1 VLDO, Low Voltage Dropout
The input of the internal linear regulator. VVLDO
always needs to be greater than 4.75V for normal
operation of the POL converter.
8.2 IM, Interleave Mode
The inp ut with the int ernal pul l-up r esis tor. When the
pin is left floating, the phase lag of the POL converter
is set b y IN T L2…IN TL4 pin s. If the pin is pul led low,
the phase lag is set to 0°. Pulling all INTL pins and
the IM pin low configures a POL converter as a
master. The master determines the clock on the
SYNC line.
8.3 TEMP, Temperature Measurement
The voltage output of the internal temperature
sensor measuring junction temperature of the
controller IC. Voltage range from 0 to 2V
corresponds to the temperature range from -50°C to
150°C.
8.4 ENP, Enable Polarity
The input with the inter nal pull-up r es istor . When the
ENP pin is pulled low, the control logic of the EN
input is inverted.
8.5 DELAY, Power-Up Del ay
The input of the POR circuit with the internal pull-up
resistor. By connecting a capacitor between the pin
and PGND the power-up delay can be programmed.
8.6 CCA[0:2], Compensation Coefficient
Address
Inputs with i nternal pul l-ups to select one of 7 sets of
digital filter coefficients optimized for various
application conditions.
8.7 VREF, Voltage Reference
The output of the 2V internal voltage reference that
is used to program the output voltage of the POL
converter.
8.8 EN, En ab le
The input with the internal pull-up res istor. The POL
converter is turned off, when the pin is pulled low
(see ENP to inverse logic of the Enable function).
8.9 OK, Fault Status
The open drain input/output with the internal pull-up
resistor. The POL convert er pulls its OK p in lo w, if a
fault occurs. Pulling lo w th e OK input by an extern al
circuitry turns off the POL converter.
8.10 SYNC, Frequency Syn chronization Line
The bidir ectional input/ outp ut wit h the i nternal pull-up
resistor. If the POL converter is configured as a
master, the SYNC line propagates clock to other
POL converters. If the POL converter is configured
as a slave, the internal clock recovery circuit
synchronizes the POL converter to the clock of the
SYNC line.
8.11 PG, Power Good
The open drain input/output with the internal pull-up
resistor. T he pin is pu lled lo w by the POL convert er,
if the output volt age is outside of the window defined
by the Power Good High and Low thresholds.
Note: See the No-Bus Application Note for recommendations on
PG deglitching.
8.12 TRIM, Output Voltage Trim
The input of the TRIM comparator for the output
voltage programming.
The output voltage can be programmed by a single
resistor connected between VREF and TRIM pins.
Resistance of the trim resistor can be determined
from the equation below:
,
)5.5(20
OUT
OUT
TRIM VV
R−×
= kOhms
where VOUT is the desired output voltage in Volts.
If the RTRIM is open or the TRIM pin is shorted to
PGND, the VOUT=0.5V.
8.13 CS, Current Share/Sense Bus
The open drain digital input/output with the internal
pull-up resistor. The duty cycle of the d igi tal sig na l is
proportional to the output current of the POL
converter. External capacitive loading of the pin
shall be avoided.
8.14 INTL[2:4], Interleave Bits
Inputs with internal pull-up resistors. The encoded
number determines the phase lag of the POL
converter when the IM pin i s left floating. The phase
lag is equal to the number multiplied by 45°.
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 15 of 18
8.15 +VS
The positive voltage input of the POL converter
feedback loop.
9. A p p lication Information
9.1 Output Voltage Margining
Margining can be implemented either by changing
the trim voltage as described in the previous
paragraph or by changing the resistance between
the REF and TRIM pins.
Figure 19. Margining Configuration
In the schematic shown in Figure 19, the nominal
output voltage is set with the trim resistor RTRIM
calculated from the equation in the paragraph 8.12.
Resistors RUP and RDOWN are added to margin the
output voltage up and down respectively and
determined from the equations below.
∆
∆−×
×
+
×
=%%5
20
20 VV
R
R
R
R
TRIM
TRIM
TRIM
UP
, kΩ
( )
∆−
∆
×+= %100 %
20 V
V
RR TRIMDOWN , kΩ
where RTRIM is the val ue of the trim res istor in kΩ and
ΔV% is the absolute value of desired margining
expressed in percents of the nominal output voltage.
During normal operation the resistors are removed
from the circuit by the switches. The “Margining
Down” s witch is nor mally closed shor ting the resistor
RDOWN while the “Margining Up” switch is normally
open disconnecting the resistor RUP.
An alter nat ive c onf ig urat ion of the margining c irc u it is
shown in Figure 20. In this configuration both
switches are normally open that may be
advantageous in some implementations.
Figure 20. Alternative Margining Configuration
RUP and RDOWN for this configuration are determined
from the following equations:
∆
∆−×
×
+
×
=%%5
20
20 VV
R
R
R
R
TRIM
TRIM
TRIM
UP
, kΩ
∆
∆
−
×
+
×
=%%100
20
20 VV
R
R
R
TRIM
TRIM
DOWN
, kΩ
Caution: Noise inject ed into the TRIM node may affect accuracy
of the output voltage and stability of the POL
converter. A lways minim ize the PCB trace l ength from
the TRIM pin to external components to avoid noise
pickup.
Refer to No-BusTM POL Converters. Z-1000 Series
Application Note on www.power-one.com for more
application information on this and other product
features.
REF
TRIM
POL
PGND
R
DOWN
R
TRIM
Margining
Down Switch
(normally
closed)
Margining
Up Switch
(normally
open)
R
UP
REF
TRIM
POL
PGND
R
TRIM
R
DOWN
Margining
Down Switch
(normally
open)
Margining
Up Switch
(normally
open)
R
UP
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 16 of 18
10. Mechanical Drawings
All Dimensio ns are in mm
Tolerances:
0.5-10 ±0.1
10-100 ±0.2
Pin Coplanarity: 0.1 max
22.2 ±0.30
36
19
Pin 1
18
5.2
17.7
SMT PICKUP POINT
12.5 ±0.30
2.6
1
0.4
Figure 21. Top (Left) and Bottom Views
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 17 of 18
12
6.5±0.30
8.7
2.1
Figure 22. Side View
44±0.20
40.4±0.10
7.0
1.54
Section
Y , Y
Section
X , X
22.8±0.10 (Bo)
1.1 0.3
24
12.8
12.80 (Ao)
5°
5°
5°
Y
Y
X
X
1.00
Pin 1 indicating
Chamfer.
SMT PICKUP
POINT
DIRECTION OF FEED
Figure 23. Tape and Reel
ZY1207 7A No-Bus POL Da ta S he e t
3V to 14V Input • 0.5V to 5.5V Outp u t
ZD-00697 Rev. 2.1, 11-Oct-2011 www.power-one.com Page 18 of 18
22.20
10.40
1.00
12.50
2.60
Pin 1
0.60
2.00
118
19
36
(x 36)
Top View
Figure 24. Recommended PCB Pad Sizes
Figure 25. Recommended PCB La yout for Multilayer PCBs
Notes:
1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, int ended f or use in, or authorized for use as critical
components in life support systems, equipm ent us ed in hazardous environm ents , or nuclear c ontrol sys t ems without the express written
consent of the respective divisi onal presi dent of Power-One, I nc.
2. TECHNICAL REVISIO NS - The appearance of products, inc l udi ng safety agenc y certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
