July 1993
Revised April 1999
74VHC123A Dual Retriggerable Monostable Multivibrator
© 1999 Fairchild Semiconductor Corporation DS011621.prf www.fairchildsemi.com
74VHC123A
Dual Retriggerable Monostable Multivibrator
General Descript ion
The VHC123A is an advanced high speed CMOS
Monostable Multivibrator fabricated with silicon gate CMOS
technolo gy. It achie ves the high sp eed opera tion similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Each multivibrator features
both a negative, A, and a positive, B, transition triggered
input, e ither of wh ich can be used as an inhibit i nput. Also
included is a clear input that when taken low resets the
one-shot. The VHC123A can be triggered on the positive
transition of the clear while A is held low and B is held high.
The output pulse width is determined by the equation:
PW = (Rx)(Cx); where PW is in seconds, R is in ohms, and
C is in farads.
Limits for Rx and Cx are:
External capacitor, CxNo limit
External resisto r s, RxVCC = 2.0V, 5 kΩ min
VCC > 3.0V, 1 kΩ min
An input protection circuit ensures that 0 to 7V can be
applied to the inp ut pins with out regard to the sup ply volt-
age. This device can be used to interface 5V to 3V systems
and two sup ply systems such as battery ba ck up. This cir-
cuit pr eve nts dev ic e d estr uct ion due to m i sma tche d s upp l y
and input voltages.
Features
■High Spee d:
tPD = 8.1 ns (typ) at TA = 25°C
■Low Power Dissipation:
ICC = 4 µA (Max) at TA=25°C
■Active State: ICC = 600 µA (Max) at T A = 25°C
■High Noise Immunity: VNIH = VNIL = 28% VCC (min)
■Power down protection is provided on all inputs
■Pin and function compatible with 74HC123A
Ordering Code:
Surface m ount pa c k ages are als o available on Tape and Reel. Specify by appending the s uffix let te r “X” to the or dering co de.
Logic Symbol
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74VHC123AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC123ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC123AMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC123AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
www.fairchildsemi.com 2
74VHC123A
Pin Descriptions Truth Table
H = HIGH Voltage L ev el
= HIGH -t o-LOW Trans iti on
L = LOW Voltage Level
= LOW-to-HIGH Transition
X = Don’t Care
Block Diagrams
Note A: Cx, Rx, Dx are extern al C apaci to r, Resisto r, and Diode, res pectively.
Note B: Externa l cl am ping diode, Dx;
External cap ac it or is charg ed to VCC lev el in the wa it st at e, i. e. w hen no tri gger is applied.
If the supply voltage is turned off, Cx discharges m ainly through the inte rnal (p arasitic ) diode. If C x is suffici ently larg e and VCC drops ra pidly, there will be
some po ss ibilit y of dam agin g the I C throu gh in rush curre nt or latc h-up . If the capa citanc e of the supp ly vo ltag e filter is large enough and VCC d rops s low ly,
the in ru s h c urrent is automa tically limited and damage t o t he I C is av oided.
The ma ximum v alue o f fo rwar d curr ent thro ugh the p ar asitic dio de is ±2 0 mA. In the case of a large Cx, the limit of fall time of the supply voltage is deter-
mine d as f ollows:
tf ≥ (VCC −0.7) Cx/20 mA
(tf is the time between the su pply voltage turn off and the sup ply v olt age reaching 0.4 VCC)
In the event a system does not satisfy the above condition, an external clamping diode (Dx) is needed to protect the IC from rush current.
System Diagram
Pin Names Description
ATrigger Inputs (Negative Edge)
B Trigger Inputs (Positive Edge)
CLR Reset Inp uts
CxExternal Capacitor
RxExternal Resistor
Q, Q Outputs
Inputs Outputs Function
ABCLRQQ
HH
Output Enable
X L H L H Inhibit
H X H L H Inhibit
L
H
Output Enable
LH
Output Enable
XX L LHReset
3 www.fairchildsemi.com
74VHC123A
Tim ing Chart
Functional Description
1. Stand-by State
The external capacitor (Cx) is fully charged to VCC in
the Stand- by State. That mean s, before trigger ing, the
QP and QN transistor s which are connected to the Rx/
Cx node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage sup plies turn off. The total supply cu rrent
is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling signal;
and third, where the A input is LOW an d the B input is
HIGH, and the CLR input has a ris ing signal.
After a trig ger becomes effectiv e, comparators C1 and
C2 start operating, and QN is turned on. The external
capacitor discharges th rough QN. The voltage level at
the Rx/Cx no de drop s. If the Rx/Cx vo ltag e leve l f alls to
the internal reference voltage VrefL, the output of C1
becomes LOW. The flip-flo p is then reset an d QN turns
off. At that moment C1 s tops but C2 conti nues operat-
ing.
Aft er QN tu rns off, the voltage at the Rx/Cx nod e starts
rising at a rate determined by the time constant of
external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes HIGH, following
some delay time o f the inter nal F/F a nd gates. It stays
HIGH even if the vol tage of Rx/Cx changes from fa lling
to rising. When Rx/Cx reaches the internal reference
voltage V refH, the output of C2 becomes L OW, the out-
put Q goes LOW and C2 stops its operation. That
means, after triggering, when the voltage level of the
Rx/Cx node reaches VrefH, the IC returns to its
MONOSTABLE state.
With large values of Cx and Rx, and ignoring the dis-
charge ti me of the capacitor a nd internal dela ys of the
IC, the width of the output pulse, tW (OUT), is as fol-
lows:
tW (OUT) = 1.0 Cx Rx
3. Retrigg er ope ration (74V HC 12 3A )
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging Cx. The voltage level of the Rx/Cx
node then falls to VrefL level again. Therefore the Q
output stays HIGH if the next trigger comes in before
the time period set by Cx and Rx.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The mi nimum tim e for a tr igge r to be effecti ve 2nd trig-
ger, tRR (Min), depends on VCC and Cx.
4. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q out-
put is held LOW and the trigger control F/F is reset.
Also, Qp turns on and Cx is charged rapidly to V CC.
This means if CLR is set LO W, the IC goes into a wa it
state.
www.fairchildsemi.com 4
74VHC123A
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions (Note 2)
Note 1: Absolute maximum ratings are values beyond which the device
may be da maged or ha ve its useful li fe impaire d. The datab ook specific a-
tions should be met, without exception, to ensure that the system design is
reliable over its pow er supply, temperatur e, and output/inpu t loading va ri-
ables. F airchil d does not recommended opera tio n outsid e data book spec i-
fications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
Note 3: T he maxim um allo wable valu es of Cx and Rx ar e a f unc tion of the
leakage of capacitor Cx, the leakage of the device, and leakage due to
board layout and surface resistance. Susceptibility to externally induced
noise signals may occur f or R x> 1MΩ.
DC Electrical Characteristics
Note 4: Per Circuit
Supply Voltage (VCC)−0.5V to +7.0V
DC Input Voltage (VIN)−0.5V to +7.0V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Input Diode Current (IIK)−20 mA
Output Diode Current (IOK)±20 mA
DC Output Current (IOUT)±25 mA
DC VCC/Current (ICC)±50 mA
Storage Temperature (TSTG)−65°C to 150°C
Lead Temperature (TL)
Sol dering, 10 seconds 260°C
Supply Voltage (VCC) 2.0V to +5.5V
Input Voltage (VIN)0V to +5.5V
Output Voltage (VOUT) 0V to VCC
Operating Temperature
(Topr)−40° to +85°C
Input Rise and Fall Time (tr, tf)
(CLR only)
VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V
VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V
External Capacitor - CxNo Limitation (Note 3) F
External Resistor - Rx>5 kΩ (Note 3) (VCC = 2.0V)
>1 kΩ (Note 3) (VCC > 3.0 V)
Symbol Parameter VCC
(V)
TA = 25°CT
A = −40° to 85°CUnits Conditions
Min Typ Max Min Max
VIH HIGH Level 2.0 1.50 1.50 V
Input Voltage 3.0 − 5.5 0.7 VCC 0.7 VCC
VIL LOW Level 2.0 0.50 0.50 V
Input Voltage 3.0 − 5.5 0.3 VCC 0.3 VCC
VOH HIGH Level 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or VIL
4.5 4.4 4.5 4.4
3.0 2.58 2.48 VIOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
VOL LOW Level 2.0 0.0 0.1 0.1
V
VIN = VIH IOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 or VIL
4.5 0.0 0.1 0.1
3.0 0.36 0.44 IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAV
IN = 5.5V or GND
IIN Rx/Cx Terminal 5.5 ±0.25 ±2.50 µAV
IN = VCC or GND
Off-State Current
ICC Quiescent Supply Current 5.5 4.0 40.0 µAV
IN = VCC or GND
ICC Active—State 3.0 160 250 280 VIN = VCC or GND
(Note 4) 4.5 380 500 650 µAR
x/Cx = 0.5 VCC
Supply Current 5.5 560 750 975
5 www.fairchildsemi.com
74VHC123A
AC Electrical Characteristics (Note 5)
Note 5: R ef er t o Timing Char t.
Note 6: CPD is defined as th e v alue of th e intern al equivalent capa c it ance whic h is calculated fr om t he operating cu rrent consumptio n w it ho ut load. Avera ge
operati ng c urrent ca n be obtained by the equation :
ICC (opr.) = CPD*VCC*fIN+ ICC1*Duty/100 + ICC/2 (per Circuit)
ICC1: Active Supply Current
Duty:%
AC Operating Requirement (Note 7)
Note 7: R ef er t o Timing Char t.
Symbol Parameter VCC
(V)
TA = 25°CT
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
tPLH
tPHL Propagation Delay Time 3.3 ± 0.3 13.4 20.6 1.0 24.0 ns CL = 15 pF
(A, B–Q, Q)15.9 24.1 1.0 27.5 CL = 50 pF
5.0 ± 0.5 8.1 12.0 1.0 14.0 ns CL = 15 pF
9.6 14.0 1.0 16.0 CL = 50 pF
tPLH
tPHL Propagation Delay Time 3.3 ± 0.3 14.5 22.4 1.0 26.0 ns CL = 15 pF
(CLR Trigger—Q, Q \) 17.0 25.9 1.0 29.5 CL = 50 pF
5.0 ± 0.5 8.7 12.9 1.0 15.0 ns CL = 15 pF
10.2 14.9 1.0 17.0 CL = 50 pF
tPLH
tPHL Propagation Delay Time 3.3 ± 0.3 10.3 15.8 1.0 18.5 ns CL = 15 pF
(CLR—Q, Q)12.8 19.3 1.0 22.0 CL = 50 pF
5.0 ± 0.5 6.3 9.4 1.0 11.0 ns CL = 15 pF
7.8 11.4 1.0 13.0 CL = 50 pF
tWOUT Output Pulse Width 3.3 ± 0.3 160 240 300 ns CL = 50 pF Cx = 28 pF
5.0 ± 0.5 133 200 240 Rx = 2 kΩ
3.3 ± 0.3 90 100 110 90 110 µsCL = 50 pF Cx = 0.01 µF
5.0 ± 0.5 90 100 110 90 110 Rx = 10 kΩ
3.3 ± 0.3 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF Cx = 0.1 µF
5.0 ± 0.5 0.9 1.0 1.1 0.9 1.1 Rx = 10 kΩ
∆tWOUT Output Pulse Width Error
Between Circuits ±1%
(In same Package)
CIN Input Capacitance 4 10 10 pF VCC = Open
CPD Power Dissipation 73 pF (Note 6)
Capacitance
Symbol Parameter VCC
(V)
TA = 25°CT
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
tW(L) Minimum Trigger 3.3 5.0 5.0 ns
tW(H) Pulse Width 5.0 5.0 5.0
tW(L) Minimum Clear 3.3 5.0 5.0 ns
Pulse Width 5.0 5.0 5.0
tRR Minimum 3.3 ± 0.3 60 ns Rx = 1 kΩ
Retrigger Time 5.0 ± 0.5 39 CX = 100 pF
3.3 1.5 µsR
x = 1 kΩ
5.0 1.2 CX = 0.01 µF
www.fairchildsemi.com 6
74VHC123A
Device Character istics
twout*Cx Cha ra cte ri sti cs (typ) tRR*VCC Characteristics (typ)
Output Pulse Width Constant K-Supply Voltage
(Typical) Input Equivalent Circuit
7 www.fairchildsemi.com
74VHC123A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com 8
74VHC123A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC123A Dual Retriggerable Monostable Multivibrator
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the labe l ing, can be re a-
sonably expected to result in a significant injury to the
user.
2. A critica l com ponent i n any compo nent o f a life s upp ort
device or system whose failure to perform can be rea-
sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
