M41T81MY6F - STMicroelectronics, Inc.

1/30June 2004

M41T81

Serial Access Real-Time Clock with Alarms

FEATURES SUMMARY

■2.0 TO 5.5V CLOCK OPERATING VOLTAGE

■COUNTERS FOR TENTHS/HUNDREDTHS

OF SECONDS, SECONDS, MINUTES,

HOURS, DAY, DATE, MONTH, YEAR, AND

CENTURY

■AUTOMATIC SWITCH-OVER AND

DESELECT CIRCUITRY

■SERIAL INTERFACE SUPPORTS I2C BUS

(400kHz PROTOCOL)

■PROGRAMMABLE ALARM AND

INTERRUPT FUNCTION (VALID EVEN

DURING BATTERY BACK-UP MODE)

■WATCHDOG TIMER

■POWER-DOWN TIME-STAMP (HT Bit)

■LOW OPERATING CURRENT OF 400µA

■BATTERY BACK-UP NOT RECOMMENDED

FOR 3.0V APPLICATIONS (CAPACITOR

BACK-UP ONLY)

■BATTERY OR SUPER-CAP BAC K-UP

■OPERATING TEMPERATURE OF –40 TO

85°C

■ULTRA-LOW BATTERY SUPPLY CURRENT

OF 1µA

■PACKAGE OPTIONS INCLUDE A 28-LEAD

OR 18-LEAD EMBEDDED CRYSTAL SOIC

Figure 1. Packages

SO8 (M)

8-pin SOIC

SOX28 (M X)*

28-pin (300mil) SOIC

with Embe dd ed Crystal

SOX18 (M Y)*

18-pin (300mil) SOIC

with Embe dd ed Crystal

M41T81

2/30

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 4. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. 18-pin, 300mil SOIC (MY) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Dual Package Connections (28-pin to 18-pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 9. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12.Alternative READ Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2. TIMEKEEPER® Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16.Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 17.Back-up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Square Wave Output Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3/30

M41T81

Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 19.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 21.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mechanical Data. . 25

Figure 22.SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline. 26

Table 15. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech. . 26

Figure 23.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline. 27

Table 16. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech. . 27

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

M41T81

4/30

SUMMARY D ESCRIPTION

The M41T81 Serial Access TIMEKEEPER®

SRAM is a low power Serial RTC with a built-in

32.768kHz oscillator (external crystal controlled).

Eight bytes of the SRAM (see Table 2., page 13)

are used for the clock/calendar function and are

config ured in bi nar y c ode d d ec ima l (B CD) fo rm at.

An additional 12 bytes of SRAM provide status/

control of Alarm, Watchdog and Square Wave

functions. Addresses and da ta ar e tra nsfer r ed se -

rially via a two line, bi-directional I2C interface. The

built-in address register is incremented automati-

cally after each WRITE or READ data byte.

The M41T81 has a built-in power sense circuit

which detects power failures and automatically

switches to the battery supply when a power fa il-

ure occurs. The energy needed to sustain the

SRAM and c loc k operati ons c an be suppl ied by a

small lithium button supply when a power failure

occurs.

Functio ns availab le to the user include a non-vol-

atile, time -o f-day cl oc k/cal en dar , Al ar m inter r upt s,

Watchdog Timer and programmable Square

Wave output. The eight clock address locations

contain t he ce ntury , yea r, month, date, day, hour,

minute, second and tenths/hundredths of a sec-

ond in 24 hour BCD format. Corrections for 28, 29

(leap year - valid until year 2100), 30 a nd 31 day

months are made automatically.

The M41T81 is supplied in either an 8-pin SOIC or

an 18-pin (MY) or 28-pin (MX), 300mil SOIC pack-

age which includes an embedded 32kHz crystal.

The 18-pin and 28-pin, embedded crystal SOIC re-

quires only a user-supplied battery to provide non-

volatile operation.

Figure 2. Logic Diagram

Note: 1. For SO8 package only.

Table 1. Signal Names

Note: 1. For SO8 package only.

SCL

VCC

M41T81

VSS

SDA

IRQ/FT/OUT/SQW

VBAT

XI(1)

XO(1)

AI04613

XI(1) Oscillator Input

XO(1) Oscillator Output

IRQ/OUT/

FT/SQW Interrupt / Output Driver / Frequency

Test / Square Wave (Open Drain)

SDA Serial Data Input/Output

SCL Serial Clock Input

VBAT Battery Supply Voltage

VCC Supply Voltage

VSS Ground

NC No Connect

NF No Function

5/30

M41T81

Figure 3. 8-pin SOIC (M) Connections

Figure 4. 28-pin, 300mil SOIC (MX)

Connections

Note: 1. No Connect ( NC) pin for 28-p in S OI C, but s ho uld be c on-

sidered to have indicated function in anticipation of re-

placement with 18-pin SOIC.

2. No Function (NF) pi ns should be t ied to VSS. Pins 1, 2, 3,

and 4 are internally shorted together.

Figure 5. 18-pin, 300mil SOIC (MY)

Connections

Note: 1. NF pins must be t ied to VSS. Pins 2 and 3, 16, an d 17 are

internally shorted together.

Figure 6. Dual Footprint Connections (28-pin to

18-pin)

Note: 1. Remove this jumper for SOX18.

1IRQ/FT/OUT/SQW

SDA

BAT

SCL

XI V

M41T81

AI04769

IRQ/FT/OUT/SQW

SCL

SDANC

VSS

VBAT SCL(1)

NF(2)

VCC

VCC(1)

M41T81

IRQ/FT/OUT/SQW(1)

SDA(1)

AI07805

NF(1)

SCL

SDA

VSS

VBAT

NF(1)

VCC

M41T81 IRQ/FT/OUT/SQW

NF(1)

AI07830

8(3)

6(1)

7(2)

9(4)

10(5)

11(6)

12(7)

13(8)

14(9)

(17)22

(16)21

(15)20

(14)19

(13)18

(12)17

(11)16

(10)15

(18)23

IRQ/FT/OUT/SQW

SCL

(1)

SDA

VSS

VBAT

VCC

M41T81MX

(SOX28)

M41T81MY

(SOX18)

AI09646

M41T81

6/30

Figure 7. Block Diagram

Note: 1. Open drain output

2. Square Wave f unction has the highest priority on IR Q /FT/OUT/SQW output.

3. VSO = VBAT – 0.5V (typ)

AI04616

REAL TIME CLOCK

CALENDAR

RTC W/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

FREQUENCY TEST

OUTPUT DRIVER

IRQ/FT/OUT/SQW(1,2)

INTERNAL

POWER

SQWE

AFE

SDA

SCL

VCC

COMPARE

I2C

INTERFACE

32KHz

OSCILLATOR

VBAT

CRYSTAL

VSO(3)

WRITE

PROTECT

OUT

7/30

M41T81

OPERATION

The M41T81 c lock opera tes as a slave dev ice on

the serial bus. Access is obtained by implementing

a start con dition fo llowed by the corr ect slave ad -

dress (D0h). The 20 bytes contained in the device

can then be accessed sequentially in the following

order:

1. Tenths/Hundredths of a Second Register

2. Seconds Register

3. Minutes Register

4. Century/Hours Register

5. Day Register

6. Date Register

7. Month Register

8. Year Register

9. Control Register

10. Watchdog Register

11 - 16. Alarm Registers

17 - 19. Reserved

20. Square Wave Register

The M41T81 clock continually monitors VCC for an

out-of-tolerance condition. Should VCC fall below

VSO, the dev ice ter mi nat es an ac ce ss i n p ro gr es s

and resets the device address counter. Inputs to

the device will not be recognized at this time to

prevent erroneous data from being written to the

device from a an out-of-tolerance system. The de-

vice also automatically switches over to the battery

and powers down into an ultra low current mode of

operation to conserve battery life. As system pow-

er returns and VCC rise s a bov e VSO, the battery is

disconnected, and the power supply is switched to

external VCC.

For more information on Battery Storage Life refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines must be connected to

a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the

bus is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

High, will be interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data line, from high to Low, while the clock is High,

defines the START condition.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition.

Data Valid. The state of the data line represents

valid data when after a start condition, the data line

is stable for the duration of the high period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condition

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte -wi de and eac h rec eiv er ac kn owl -

edges with a ninth bit.

By defin iti on a dev ice that gi ves ou t a me ss ag e i s

called “ transmitter,” the receiv ing device th at gets

the message is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by the master are called

“slaves.”

Acknowledge. Each byte of eight bits is followed

by one A ckn owledge Bit. Thi s Ack nowledg e Bit i s

a low level put on the bus by the receiver whereas

the master generates an extra acknowledge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA l ine durin g the ackn owledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receiver must sig-

nal an end of data to the slave transm itter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

M41T81

8/30

Figure 8. Serial Bus Data Transfer Sequence

Figure 9. Acknowledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

9/30

M41T81

READ Mode

In this mode the master reads the M41T81 slave

after setting the slave address (see Figure

11., page 10). F ollo wi ng t he W RIT E Mo de Co ntro l

Bit (R/W=0) and the Acknowledge Bit, the word

address 'An' is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transmitter. The address pointer is only

incremented on reception of an Acknowledge

Clock. The M41T81 slave transmitter will now

place the data byte at address An+1 on the bus,

the master receiver reads and acknowledges the

new byte and the address pointer is incremented

to “An+2.”

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condit io n to the slave tran sm itte r .

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). The update will resume due

to a Stop Condition or when the pointer increments

to any non-clock address (08h-13h).

Note: This is true both in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement-

ed whereby the master reads the M41T81 slave

without fir st writing to the (vol atile) address po int-

er. The first address that is read is the last one

stored in t he pointer (see F igure 12., page 10).

Figure 10. Slave Address Location

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

M41T81

10/30

Figure 11. READ Mode Sequence

Figure 12. Alternative READ Mode Sequence

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

11/30

M41T81

WRITE Mode

In this mode the master transmitter transmits to

the M41T81 slave receiver. Bus protocol is shown

in Figure 13., page 11. Following the START con-

dition and slave address, a logic '0' (R/W=0) is

placed on the bus and i ndica tes to the a ddres sed

device that word addres s “An” will fol low and is to

be written to the on-chip address pointer. The data

word to be written to the memory is strobed in next

and the interna l add ress poi nter is inc remen ted to

the next address location on the reception of an

acknowledge clock. The M41T81 slave receiver

will send an acknowledge clock to the master

transmitter after it has rece ived the s lave ad dress

see Figure 10., page 9 and again after it has re-

ceived the word address and each data byte.

Data Retention Mode

With valid VCC applied, the M41T81 can be ac-

cessed as des c ribed ab ov e wi th READ or WRIT E

Cycles. Should the supply voltage decay, the pow-

er input will be switched from the VCC pin to the

battery when V CC falls bel ow the B attery Ba ck-u p

Switchover Voltage (VSO). At this time the clock

registers will be maintained by the attached bat-

tery supp ly. On power -up, when VCC returns to a

nominal value, write protection continues for trec.

For a further , more detail ed review of li fetime cal-

culations, please see Application Note AN1012.

Figure 13. WRITE Mode Sequence

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

M41T81

12/30

CLOCK OPERATION

The 20-byte Register Map (see Table 2., page 13)

is used to both set th e clock a nd to rea d the date

and time from the clock, in a binary coded decimal

format. Tenth s/Hundr edths of S econds, S econd s,

Minutes, and Hours are contained within the first

four registers.

Note: The Tenths/Hund redth s of Seco nds cannot

be written t o any value other than “00.”

Bits D6 and D7 of Clock Register 03h (Century/

Hours Register) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or from '1' to '0' at the turn of the century (de-

pending upon its initial state). If CEB is set to a '0,'

CB will not toggle . Bits D0 throug h D2 of Registe r

04h contain the Day (day of week). Registers 05h,

06h, and 07h contain the Date (day of month),

Month and Years. The ninth clock register is the

Control Register (this is described in the Clock

Calibration section). Bit D7 of Register 01h con-

tains the STOP Bit (ST). Setting this bit to a '1' will

cause the oscillator to stop. If the device is expect-

ed to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduce cur-

rent drain. When reset to a '0' the oscillator restarts

within one seco nd.

The eight Clock Registers may be read one byte at

a time, or in a sequential block. Provision has been

made to assure that a clock update does not occur

while any of the eight clock addresses are being

read. If a clock address is being read, an update of

the clock r eg ister s will b e hal ted . T h is wi ll pr ev ent

a transition of data during the READ.

Power-down Time -Stamp

When a power fai lu re oc cu rs, th e HT Bit wi ll auto -

matically be set to a '1.' This will prevent the clock

from updating the TIMEKEEPER® registers, and

will allow the user to read the exact time of the

power-down event. Resetting the HT Bit to a '0' will

allow the clock to update the TIMEKEEPER regis-

ters with the current time. For more information,

see Applic ation Note AN1572.

TIMEKEEPER® Registers

The M41T81 offers 20 internal registers which

contain Clock, Alarm, Watchdog, Flag, Square

Wave and Control data. These registers are mem-

ory locations which contain external (user accessi-

ble) and internal copies of the data (usually

referred to as BiPORT™ TIMEKE EPER cells ). The

external copies are independent of internal func-

tions e xcept that the y are updated pe riodically by

the simultaneous transfer of the incremented inter-

nal copy. The internal divider (or clock) chain will

be reset upon the completion of a WRITE to any

clock address.

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). The update w ill resume ei-

ther due to a Stop Condition or when the pointer

increments to any non-clock address (08h-13h).

TIMEKEEPER and Alarm Registers store data in

BCD. Con trol, Watchdo g and Squar e Wave Reg -

isters store data in Binary Format.

13/30

M41T81

Table 2. TIMEKEEPER® Register Map

Keys: S = Sign Bit

FT = Frequency Test Bit

ST = Sto p Bit

0 = Must be set to '0'

BMB0-BMB4 = Watchdog Multiplier Bi ts

CEB = Century Enable Bit

CB = Century Bit

OUT = Outp u t level

ABE = Al arm in Battery Back-up Mode Enable Bit

AFE = Alarm Flag Enable Flag

RB0-RB1 = Watchdog Resolut i on Bits

RPT1-RPT5 = Alarm Repeat Mode Bits

WDF = Watchdog Flag (Read only)

AF = Alarm Flag (Read only )

SQWE = Square Wave Enable

RS0-RS3 = SQW Frequency

HT = Halt Update Bit

Addr Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 Seconds 0.01 Seconds Seconds 00-99

01h ST 10 Seconds Seconds Seconds 00-59

02h 0 10 Minutes Minutes Minutes 00-59

03h CEB CB 10 Hours Hours (24 Hour Format) Century/

Hours 0-1/00-23

04h 0 0 0 0 0 Day of Week Day 01-7

05h 0 0 10 Date Date: Day of Month Date 01-31

06h 0 0 0 10M Month Month 01-12

07h 10 Years Year Year 00-99

08h OUT FT S Calibration Control

09h 0 BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE SQWE ABE Al 10M Alarm Month Al Month 01-12

0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31

0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23

0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59

0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59

0FhWDFAF000000 Flags

10h00000000Reserved

11h00000000Reserved

12h00000000Reserved

13h RS3 RS2 RS1 RS0 0 0 0 0 SQW

M41T81

14/30

Calibrating the Clock

The M41T81 is driven by a quartz controlled oscil-

lator with a nominal frequency of 32,768Hz. The

devices are tested not exceed –25 to +45 ppm

(parts per million) oscillator frequency error at

25oC, which equates to about +1.9 to –1.1 minutes

per month (see Figure 14., page 15). When the

Calibratio n circuit is properly employed, acc uracy

improves to better than ±2 ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature. The M41T81 design employs periodic

counter correction. The calibration circuit adds o r

subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure

15., page 15. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into the five Calibration Bits found

in the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Control Register 08h. These

bits ca n be set to represent a ny value betw een 0

and 31 in bina ry for m. Bit D5 is a Si gn B it; '1' in di -

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. Th e firs t 62 min ute s in the cycle m ay, onc e

per minut e, have one second e ither shorten ed by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125 ,829,120 actual oscilla tor cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register (see Figure

15., page 15). Assuming that the oscillator is run-

ning at exactly 32,768Hz, each of the 31 incre-

ments in the Calibration byte would represent

+10.7 or –5.35 seconds per month which corre-

sponds to a total range of +5.5 or –2.75 minutes

per month.

Two methods are available for ascertaining how

much calibration a given M41T81 may require.

The first involves setting the clock, letting it run for

a month and comparing it to a known accurate ref-

erence and recording deviation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934, “TIMEKEEP-

ER® CALIBRATION.” This allows the designer to

give the en d user the abili ty to calibrat e the clock

as the environment requires, even if the final prod-

uct is packaged in a non-user serviceable enclo-

sure. The designer could provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT/OUT/SQW pin. The pin will toggle at

512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the

Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm

Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the

Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0'

and the Watchdog Register (09h = 0) is reset.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (XX001010) to be

loaded into the Calibration Byte for correction.

Note that setting or changi ng the Cali bration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT/OUT/SQW pin is an open drain output

which requ ires a pull - up res is tor to V CC for pr ope r

operation. A 500-10k resistor is recommended in

order to control the rise time. The FT Bit is cleared

on power-down.

15/30

M41T81

Figure 14. Crystal Accuracy Across Temperature

Figure 15. Clock Calibration

AI07888

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

= –0.036 ppm/°C2 ± 0.006 ppm/°C2

∆F= K x (T – TO)2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41T81

16/30

Setting Alarm Clock Registers

Address loc ati on s 0A h- 0E h contai n the al ar m set -

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M41T81 is in the bat-

tery back- up mo de to s erve as a sy stem wak e-up

call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Table 3., page 17 shows the possible

configurations. Codes not listed in the table default

to the once per second mode to quickly alert the

user of an incorrect alarm setting.

When the clock information matches the alarm

clock s ett ing s based on the m atc h cr iter ia de fin ed

by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE

(Al arm Fla g Enab le) is also set (and S QWE is ' 0.') ,

the alarm condition activates the IRQ/FT/OUT/

SQW pin.

Note: If the address pointer is allowed to incre-

ment to the Fl ag Register add ress, an alarm con-

dition will not cause the Interrupt/Flag to occur until

the address pointer is moved to a different ad-

dress. It should also be noted that if the last ad-

dress writ ten is th e “Alarm Seco nds,” the addres s

pointer will increment to the Flag address, causing

this situation to occur.

The IRQ/FT/OUT/SQW output is cleared by a

READ to the Flags Register as shown in Figure

16. A subsequent READ of the Flags Register is

necessa ry to s ee th at the valu e of the Ala rm Fl ag

has been reset to '0.'

The IRQ/FT/OUT/SQW pin can also be activated

in the battery back-up mode. The IRQ/FT/OUT/

SQW wil l go low if an al ar m o ccur s and both AB E

(Alarm in Battery Back-up Mode Enable) and AFE

are set. Figure 17 illustrates the back-up mode

alarm timing.

Figure 16. Alarm Interrupt Reset Waveform

Figure 17. Back-up Mode Alarm Waveform

IRQ/FT/OUT/SQW

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

AI04617

VCC

IRQ/FT/OUT/SQW

ABE and AFE Bits

AF Bit in Flags

HIGH-Z

VSO

trec

AI05663

17/30

M41T81

Table 3. Alarm Repeat Modes

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 09h.

Bits BMB4-BMB0 store a binary multiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00 = 1/16 second, 01 = 1/4 second,

10 = 1 second, and 11 = 4 seconds. The amount

of time-out is then determined to be the multiplica-

tion of the fiv e-bit multipl ier value with the r esolu-

tion. (For example: writing 00001110 in the

Watchdog Register = 3*1, or 3 seconds). If the

processor does not reset the timer within the spec-

ified period, the M41T81 sets the WDF (Watchdog

Flag) and generates a watchdog interrupt.

The watchdog timer can be reset by having the mi-

croprocessor perform a WRITE of the Watchdog

Should the watchdog timer time-out, a value of

00h needs to be writ ten to the Wa tchdo g Regi ste r

in order to clear the IRQ/FT/OUT/SQW pin. This

will also disable the watchdog function until it is

again programmed correctly. A READ of the Flags

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function is set, the fre-

quency test function is activated, and the SQWE

Bit is '0,' the watchdog function prevails and the

frequency test function is denied.

RPT5 RPT4 RPT3 RPT2 RPT1 Al arm Setting

1 1 1 1 1 Once per Second

1 1 1 1 0 Once per Minu te

1 1 1 0 0 Once per Hour

1 1 0 0 0 Once per Day

1 0 0 0 0 Once pe r Mon th

0 0 0 0 0 Once per Year

M41T81

18/30

Square Wave Output

The M41T81 offers the user a programmable

square wave function which is output on the SQW

pin. RS3-RS0 bits located in 13h establish the

square wave output frequency. These frequencies

are listed in Table 4. Once the selection of the

SQW frequency has been completed, the IRQ/FT/

OUT/SQW pin can be turned on and off under soft-

ware control with the Square Wave Enable Bit

(SQWE) located in Register 0Ah.

Table 4. Square Wave Output Frequency

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0000None-

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

19/30

M41T81

Century Bit

Bits D7 and D6 of Cloc k Register 03h co ntain the

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (de pending upon its initi al state). If

CEB is set to a '0,' CB will not toggle.

Output Driver Pin

When the FT Bit, AFE Bit, SQWE Bit, and Watch-

dog Register are not set, the IRQ/FT/OUT/SQW

pin becomes an output driver that reflects the con-

tents of D7 of the Control Register. In other words,

when D7 (OUT B it) an d D6 ( F T Bi t) of add ress lo -

cation 08h are a '0,' then the IRQ/FT/OUT/SQW

pin will be driven low.

Note: The IRQ/FT/OUT/SQW pin is an open drain

which requires an external pull-up resistor.

Preferred Initial Power-on Default

Upon initial application of power to the device, the

following register bits are set to a '0' state: Watch-

dog Register; AFE; ABE; SQWE; and FT. The fol-

lowing bits are set to a '1' state: ST; OUT; and HT

(see Table 5., page 19).

Table 5. Preferred Default Values

Note: 1. BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. UC = Unchanged

Condition ST HT Out FT AFE SQWE ABE WATCHDOG

Initial Power-up(2) 1110000 0

Subsequent Power-up (with battery

back-up)(3) UC 1 UC 0 UC UC UC 0

M41T81

20/30

MAXIMUM RATING

Stressing the dev ice above the ratin g lis ted in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of th e device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicro ele ctr o nic s S URE P ro gram an d other rel -

evant quality documents.

Table 6. Absolute Maximum Ratings

Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for

between 90 to 150 seconds).

2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C

for greater than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin whil e i n the Batter y Ba ck-up Mode

Sym Parameter Value Unit

TSTG Storag e Te mp era tu re (VCC Off, Oscillator Off) SOIC –55 to 125 °C

VCC Supply Voltage –0.3 to 7 V

TSLD(1,2) Lead Solder Temperature for 10 Seconds 260 °C

VIO Input or Output Voltages –0.3 to Vcc+0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

21/30

M41T81

DC AND AC PARA METERS

This section summarizes th e operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests perfo rmed under the Measure -

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 7. Operating and AC Measurement Conditions

Note: Output Hi-Z is defined as t he point where data is no longer driv en.

Figure 18. AC Measurement I/O Waveform

Table 8. Capacitance

Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.

2. At 25°C , f = 1MH z.

3. Outputs deselected.

Parameter M41T81

Supply Voltage (VCC)2.0 to 5.5V

Ambient Operating Temperature (TA)– 40 to 85 °C

Load Capacitance (CL)100pF

Input Rise and Fall Times ≤ 50ns

Input Pulse Voltages 0.2VCC to 0.8 VCC

Input and Output Timing Ref. Voltages 0.3VCC to 0.7 VCC

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 7 pF

COUT(3) Output Capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

M41T81

22/30

Tab le 9. DC Char acteristics

Note: 1. Valid for Ambient Operat ing Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where not ed).

2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equi valent) as t he battery supply.

3. After switchover (VSO), VBAT (min) can be 2.0V for crystal with RS = 40KΩ.

4. For rechargeable back-up, VBAT (max) may be considered VCC.

5. For IRQ/FT/OUT/SQW pin (Open Drain)

Table 10. Crystal Electrical Characteristics

Note: 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork

Type (thru-h ole) or the DMX-26S: 1TJ S125FH2 A212, (S MD) quart z cryst al fo r indust rial t emperat ure op eration s. KDS c an be con-

tacted at kouhou@kdsj.c o.jp or http://www.kdsj.co.jp for further information on this crystal type.

2. Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768kHz crystal of minimum trace

lengths and isolation from RF generat ing signals should be taken into account.

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Switch Freq = 400kHz 400 µA

ICC2 Supply Current (standby) SCL,SDA = VCC – 0.3V 100 µA

VIL Input Low Voltage –0.3 0.3VCC V

VIH Input High Voltage 0.7VCC VCC + 0.3 V

VOL Output Low Voltage IOL = 3.0mA 0.4 V

Output Low Voltage (Open Drain) (5) IOL = 10mA 0.4 V

Pull-up Supply Voltage (Open Drain) IRQ/OUT/FT/SQW 5.5 V

VBAT(2) Battery Supply Voltage 2.5(3) 33.5(4) V

IBAT Battery Supply Current TA = 25°C, VCC = 0V

Oscillator ON, VBAT = 3V 0.6 1 µA

Sym Parameter(1,2,3) Min Typ Max Units

fOResona nt Fre qu en cy 32.76 8 kHz

RSSeries Resistance 60 kΩ

CLLoad Capacitance 12.5 pF

23/30

M41T81

Figure 19. Power Down/Up Mode AC Waveforms

Table 11. Power Down/Up AC Characteristics

Note: 1. VCC fall time should not exceed 5mV/µs.

2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (excep t where noted).

Table 12. Power Down/Up Trip Points DC Characteristics

Note: 1. All voltages referenced to VSS.

2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (excep t where noted).

Symbol Parameter(1,2) Min Typ Max Unit

tPD SCL and SDA at VIH before Power Down 0nS

trec SCL and SDA at VIH after Power Up 10 µS

Sym Parameter(1,2) Min Typ Max Unit

VSO Battery Back-up Switchover Voltage VBAT – 0.80 VBAT – 0.50 VBAT – 0.30 V

AI00596

VCC

trec

tPD

VSO

SDA

SCL DON'T CARE

M41T81

24/30

Figure 20. Bus Timing Requirements Sequence

Table 13. AC Characteristics

Note: 1. Valid for Ambient Operat ing Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where not ed).

2. Transmitter must internally provide a hold time to brid ge the undefined region (300ns max) of the falling edge of SCL.

Sym Parameter(1) Min Typ Max Units

fSCL SCL Clo ck Freq ue ncy 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA START Conditi on Ho ld Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT(2) Data Setup Time 100 ns

tHD:DAT Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF Time the bus must be free before a new

transmission can start 1.3 µs

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

25/30

M41T81

PACKAGE MECHANICAL INFORMATION

Figure 21. SO8 – 8-lead Plastic Small Package Outline

Note: Drawing is not to scale.

Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

ddd 0.10 0.004

SO-A

ddd

LA1 α

h x 45˚

M41T81

26/30

Figure 22. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline

Note: Drawing is not to scale.

Table 15. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech.

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.44 2.69 0.096 0.106

A1 0.15 0.31 0.006 0.012

A2 2.29 2.39 0.090 0.094

B 0.41 0.51 0.016 0.020

C 0.20 0.31 0.008 0.012

D 11.61 11.56 11.66 0.457 0.455 0.459

ddd 0.10 0.004

E 7.57 7.67 0.298 0.302

e 1.27 – – 0.050 – –

H 10.16 10.52 0.400 0.414

L 0.51 0.81 0.020 0.032

α0° 8° 0° 8°

N18 18

10 18

SO-J

A1 LA1 α

h x 45°

AA2

ddd

27/30

M41T81

Figure 23. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline

Note: Drawing is not to scale.

Table 16. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech.

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.44 2.69 0.096 0.106

A1 0.15 0.31 0.006 0.012

A2 2.29 2.39 0.090 0.094

B 0.41 0.51 0.016 0.020

C 0.20 0.31 0.008 0.012

D 17.91 18.01 0.705 0.709

ddd 0.10 0.004

E 7.57 7.67 0.298 0.302

e 1.27 – – 0.050 – –

H 10.16 10.52 0.400 0.414

L 0.51 0.81 0.020 0.032

α0° 8° 0° 8°

N28 28

15 28

SO-E

A1 LA1 α

h x 45°

AA2

ddd

M41T81

28/30

PART NUMBERING

Table 17. Ordering Information Scheme

Note: 1. The SOX28 and SOX18 packages includ e an embedded 32,768Hz crystal.

For other options, or for more information on any aspect of this device, please contact the ST Sales Office

nearest you.

Example: M41T 81 M 6 E

Device Type

M41T

Supply Voltage and Write Protect Voltage

81 = VCC = 2.0 to 5.5V

Package

M = SO8

MX(1) = SOX28

MY(1) = SOX18

Temperature Range

6 = –40°C to 85°C

Shipping Method

For SO8:

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

For SOX28 and SOX18:

blank = Tubes

TR = Tape & Reel

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M41T81

REVISION HISTORY

Table 18. Document Revision History

M41T81, 41T81, T 81Serial, S erial, Seria l, Serial, Seri al, Serial, Se rial, Serial , Serial, Ser ial, Serial, Ser ial, Ser ial, Serial, Serial , Serial, Serial, Seri al, Seria l, Serial, Seri al,

Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,

Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-

cess, Access, Access, Ac cess, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, A ccess, Access,

Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-

cess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access , In te rfac e , In ter fa ce, I nte r-

face, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface,

Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Inter-

face, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface,

Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Inter-

face, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface,

Interface, Interface, Interface, Interface, Interface, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clo c k, Cl ock, RT C, RTC, RTC, RT C,

RTC, R TC , RT C, RT C, R TC, RT C, RTC, R TC, R TC, RTC , R TC, R TC, RTC , R TC, R TC, RTC , RTC, RT C, RTC , RT C, RT C, RTC , RT C, RT C, R TC , RT C, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, Programmable , Programmable, Progr ammable, Pro grammable, Progr ammable, Program mable, Pr ogrammable, Prog rammable, Program-

mable, Programm able, Programm able, Program mable, Pr ogrammable, Prog rammable, Progr ammable, Pr ogrammable, P rogrammabl e, Programmable, Programmab le,

Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Pro-

grammable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Program-

mable, Programm able, Programm able, Program mable, Pr ogrammable, Prog rammable, Progr ammable, Pr ogrammable, P rogrammabl e, Programmable, Programmab le,

Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable

Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm, Alarm, Alarm,

Alarm, Alar m, Alarm, Alarm, Alarm, Alarm, Al arm, Alarm, Alarm , Alarm, Alarm, A larm, Alarm, Alarm, A larm, Alarm, Alar m, Alarm, Alarm, Alarm, A larm, Alarm, Alar m,

Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Inter ru p t, In te rrupt, Int e rru p t, Interru p t, In ter-

rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,

Interru p t, Interr u p t, Interru p t, Interrupt, Interr u p t, Interr u p t, Interru pt, Interrupt, Inte rrupt, Interrupt, I n te rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, In-

terrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, In ter ru pt , In terr up t, In te rru p t, In te rru pt , In ter rup t, I nte r-

rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,

rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,

Watchdog, Watchdog, Watchdog , Watchdog, Watchdo g, Watchdog, Watchdog, Watchdog, Watc hdog, Wa tchdog, Wat chdog, Watchdog , Watc hdog, Watchdo g, Watch-

dog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,

Watchdog, Watchdog, Watchdog , Watchdog, Watchdo g, Watchdog, Watchdog, Watchdog, Watc hdog, Wa tchdog, Wat chdog, Watchdog , Watc hdog, Watchdo g, Watch-

dog, Watchdog, Bat te ry, Bat te ry, Bat tery, Bat tery, Battery, Battery, Bat tery, B atter y, B atter y, Batt ery, B atter y, B atter y, Ba ttery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Battery, Batt ery, Battery, Battery, Ba ttery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, S witchover, Switchover, S witchover, Switchover, S witchover, Switchover, Sw itchover, Switchover, Sw itchover, Backup, Backup, Backup, Backup, Back-

up, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write Protect, Write

Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect,

Write Protect, Writ e Pr otect, Write Prot ect, Wr ite Pr otect, Write Protect, Write Pr otect, Write Prot ect, Wr it e Pr otect, Write Prot ect, Wr ite Pr otect, Write Prot ect, I ndustri al,

Industrial, Industria l, Industrial, Industrial, Industrial, Indu strial, Industrial, Industr ial, Industrial, Industrial , vIndustrial, Indust rial, Industrial , SOIC, SOIC, SOIC, SO IC, SO-

IC, SOIC, SOIC, SO IC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC

Date Version Revision Details

Decemb er 20 01 1.0 Fir st Issu e

21-Jan-02 1.1 Fix table footnotes (Table 9, 10)

01-May-02 1.2 Modify reflow time and temperature footnote (Table 6)

05-Jun-02 1.3 Modify Data Retention text, Trip Points (Table 12)

10-Jun-02 1.4 Corrected Supply Voltage values (Table 6, 7)

03-Jul-02 1.5 Modify DC Characteristics, Crystal Electrical table footnotes, Preferred Default Values

(Table 9, 10, 5)

11-Oct-02 1.6 Add marketing status (Figure 3; Table 17); adjust footnotes (Figure 3; Table 9)

21-Jan-03 1.7 Add embedded crystal package option (Figure 2, 4, 23; Table 16); modified pre-

existing mechanical drawing (Figure 21; Table 14).

05-Mar-03 1.8 Co rre ct dim en sions (Figure 23; Table 16); remove SNAPHAT® packa ge optio n

12-Sep-03 2.0 Updated disclaimer, v2.2 template; add SOX18 package (Figure 3, 5, 22; Table 17, 15)

27-Apr-04 3.0 Reformatted; update characteristics (Figure 5, 4, 7, 14, 17, ; Table 1, 6, 9, 12, 17)

17-Jun-04 4.0 Reformatted; add Lead-free information; add dual footprint connections (Figure

6;Table 6, 17)

M41T81

30/30

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