FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC 1.0 * Figure 1: Block Diagram Features Develops the peripheral clocks required for 2-way and 4-way multi-processor clock-partitioned platforms, including: M Six buffered copies of the 66.67MHz 66REF reference input M Twelve 33.3MHz PCI clocks, developed as a divide-by-two of the 66REF reference input M Two buffered copies of the 14.318MHz 14REF reference input M Two 48MHz clocks, generated by a PLL from the 14REF reference input Serial-bus interface control of all clock outputs * Three clock management controls enable, disable and tristate banks of clock outputs independently of the serial interface Active-low PWR_DWN# signal allows shuts down the PLL and disables outputs low * Supports Test Mode and tristate output control to facilitate board testing * Available in a 56-pin SSOP and TSSOP Table 1: Clock Parameters SUPPLY VOLTAGE SUPPLY GROUP FREQUENCY (MHz) CK66_5 SEL_Q SEL_R SEL_S /2 SCL Output Control VDD_P PCI_0:5 PCI_6:7 SDA SMBus CK48_0 SKEW (MAX) VDD_R REF_0:1 Figure 2: Pin Configuration 56 VDD_R 14REF 2 55 REF_1 VDD_N 3 54 REF_0 66REF 4 53 VSS_R VSS_P 5 52 VDD_66 PCI_0 6 51 CK66_5 PCI_1 7 50 CK66_4 VDD_P 8 49 VSS_66 VSS_P 9 48 VSS_66 PCI_2 10 47 CK66_3 PCI_3 11 46 CK66_2 45 VDD_66 250ps VDD_P 12 PCI 12 3.3V VDD_P 33.33 300ps VSS_P 13 2 3.3V VDD_R 14.318 - CK48 2 3.3V VDD_48 48.008 - PCI_4 14 PCI_5 15 VDD_P 16 PCI_6 17 PCI_7 18 Table 2: Clock Offsets CK66 leads PCI 0 1.5ns MAX 3.5ns FS6159-01 VSS_N 1 66.67 REF VSS_R FS6159 VDD_66 TYP CK48_1 14REF 3.3V MIN VSS_P PWR_DWN# 6 PHASE PCI_8:11 VDD_48 CK66 RELATION VSS_66 VSS_48 * # PINS CK66_0:4 PLL * CLOCK GROUP VDD_66 66REF 44 VDD_66 43 CK66_1 42 CK66_0 41 VSS_66 40 VDD 39 VSS VSS_P 19 38 VDD_48 VDD_P 20 37 CK48_1 PCI_8 21 36 CK48_0 PCI_9 22 35 VSS_48 VSS_P 23 34 SEL_S PCI_10 24 33 PWR_DWN# PCI_11 25 32 VDD_S VDD_P 26 31 VSS_S SEL_Q 27 30 SCL SEL_R 28 29 SDA Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 2.27.02 IntFF FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 3: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active-low pin PIN TYPE NAME 2 DI 14REF DESCRIPTION One 14.318MHz clock input, used to develop the REF and CK48 clock outputs SUPPLY VDD_N 4 DI 66REF One 66.67MHz clock input, used to develop the CK66 and PCI clock outputs VDD_N 36, 37 DO CK48_0:1 Two 48MHz clock outputs VDD_48 42, 43, 46, 47, 50, 51 DO CK66_0:5 Six 66MHz clock outputs, developed as buffered copies of the 66REF reference input VDD_66 6, 7, 10, 11, 14, 15, 17, 18, 21, 22, 24, 25 DO PCI_0:11 Twelve 33.33MHz PCI clock outputs, developed as a divide-by-two of the 66REF reference input. Groups of PCI outputs can be disabled via SEL_Q, SEL_R, and SEL_S (see Table 4). Individual outputs can be disabled via the serial interface. VDD_P 33 DI PWR_DWN# Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all clocks in low state. VDD_S 54, 55 DO REF_0:1 Two 3.3V REF clock outputs, developed as buffered copies of the 14REF reference input VDD_R 30 DI SCL SMBus serial interface clock input VDD_S 29 DIO SDA SMBus serial interface data input/output VDD_S 27, 28, 34 DI SEL_Q SEL_R SEL_S Three clock management select inputs, used to enable, disable, or tristate groups of clock outputs VDD_S 40 P VDD 3.3V 5% power supply for PLL core - 38 P VDD_48 3.3V power supply for CK48 clock outputs - 44, 45, 52 P VDD_66 3.3V power supply for CK66 clock outputs - 3 P VDD_N 3.3V power supply for the 14REF and the 66REF reference inputs - 8, 12, 16, 20, 26 P VDD_P 3.3V power supply for the PCI clock outputs - 56 P VDD_R 3.3V power supply for the REF clock outputs - 32 P VDD_S 3.3V power supply for the serial interface and digital input pins - 39 P VSS Ground for the PLL core - 35 P VSS_48 Ground for the CK48 clock outputs - 41, 48, 49 P VSS_66 Ground for the CK66 clock outputs - 1 P VSS_N Ground for the 14REF and the 66REF reference inputs - 5, 9, 13, 19, 23 P VSS_P Ground for the PCI clock outputs - 53 P VSS_R Ground for REF clock outputs - 31 P VSS_S Ground for the serial interface and digital input pins - ISO9001 2.27.02 2 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC 2.0 Programming Information Table 4: Clock Enable Configuration CONTROL INPUTS (1) CLOCK OUTPUTS (MHz) PWR_DWN# SEL_Q SEL_R SEL_S CK48_0 CK48_1 CK66_0:4 CK66_5 REF_0:1 PCI_0:5 PCI_6:7 PCI_8:11 1 0 0 0 48.008 48.008 66.67 66.67 14.318 33.33 33.33 33.33 1 0 0 1 48.008 48.008 66.67 66.67 14.318 stopped low stopped low 33.33 1 0 1 0 48.008 48.008 66.67 66.67 14.318 stopped low 33.33 33.33 1 0 1 1 48.008 48.008 66.67 66.67 14.318 stopped low stopped low stopped low 1 1 0 0 tristate tristate tristate tristate tristate tristate tristate tristate 14.318 33.33 33.33 33.33 1. 1 1 0 1 48.008 48.008 66.67 stopped low 1 1 1 0 48.008 48.008 66.67 66.67 stopped low 33.33 33.33 33.33 1 1 1 1 48.008 stopped low 66.67 66.67 14.318 33.33 33.33 33.33 0 X X X stopped low stopped low stopped low stopped low stopped low stopped low stopped low stopped low Control inputs override any SMBus register settings in situations where the outputs are stopped low Table 5: Synthesis Offset 1. 3.0 CLOCK TARGET (MHz) ACTUAL (MHz) DEVIATION (ppm) CK48 (1) 48.00 48.0080 +167 Programming Interface This device supports the SMBus Block Write and Block Read commands. The device address is as follows: Table 6: Device Address 48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB requirements. A6 A5 A4 A3 A2 A1 A0 1 1 0 1 0 0 1 3.1 Block Write The Block Write command allows the bus host to write several bytes of data to sequential registers, starting with the Byte 0 Register. As shown in Figure 2, a Block Write starts with the seven-bit device address followed by a logic-low R/W bit. After an acknowledge of the device address and R/W bit by this device, a command code is containing all zeroes (0000 0000) is written. After the zero command code and an acknowledge, the bus host then issues a byte count that describes the number of data bytes to be written. The byte count must be a minimum of one byte and a maximum of 32 bytes. ISO9001 2.27.02 3 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 7: Byte Count BYTE COUNT 0000 0000 3.2 DESCRIPTION Not allowed: Must have at least one byte 0000 0001 Writes one byte (Byte 0) 0000 0010 Writes two bytes (Byte 0, 1 in order) 0000 0011 Writes three bytes (Byte 0, 1, 2 in order) 0000 0100 Writes four bytes (Byte 0, 1, 2, 3 in order) 0000 0101 Writes five bytes (Byte 0, 1, 2, 3, 4 in order) 0000 0110 to 0001 1111 These byte counts are ignored by this device 0010 0000 Maximum byte count supported (32) Block Read The Block Read command, shown in Figure 3, permits the host to read several bytes of data from sequential registers, starting by default at Register 0. To perform a Block Read procedure, the seven-bit device address is sent, followed by a logic-high R/W bit. Following an acknowledgement of the byte count by the bus host, this device will take command of the bus and will transmit all the data beginning with Register 0. After the last byte of data, the host does not acknowledge the final transfer but instead generates a STOP command. If a NO-acknowledge does not occur, the device releases the bus and the bus host will read all ones. If the host does not want to receive all the data, the host should not acknowledge the last data byte and instead issue a STOP command on the next clock. After an acknowledge of the byte count, data bytes may be written starting with Register 0 and incrementing sequentially. An acknowledge by this device between each byte of data must occur before the next data byte is sent. Figure 2: Block Write S DEVICE ADDRESS W A 7-bit Receive Device Address A Command Code BYTE COUNT = N A Byte Count Acknowledge WRITE Command From bus host to device A DATA BYTE N A P Data Data Acknowledge START Command DATA BYTE 1 Acknowledge Acknowledge STOP Command Acknowledge From device to bus host Figure 3: Block Read S DEVICE ADDRESS 7-bit Receive Device Address Repeat START R A BYTE COUNT = N Byte Count Acknowledge READ Command From bus host to device ISO9001 A DATA BYTE 1 A DATA BYTE N A P Data Data NO Acknowledge Acknowledge Acknowledge STOP Command From device to bus host 2.27.02 4 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC 3.3 Register Programming Table 10: Byte 2 Register A logic-one written to a valid bit location enables (turns on) the assigned output clock. Likewise, a logic-zero written to a valid bit location disables (turns off) the assigned output clock. Any unused or reserved register bits should be cleared to zero. These registers are expected to be configured at power-up and are not expected to change during normal modes of operation. Serial bits are read by this device starting with Byte 0 and proceeding to Byte 4. Bit 7 of each byte is read first, and bits are read in descending order down to Bit 0. Note that the SEL_Q, SEL_R and SEL_S pins will override any register settings when disabling outputs. Register settings will only affect enabled outputs. Upon application of VDD to the device, all register bits are set to one (1) so that all outputs are enabled and active. All programmed settings will be retained if the device is powered-down via PWR_DWN# low. After powering-up the device via PWR_DWN# the device will operate according to the internal register settings. BIT CLOCK PIN DESCRIPTION 7 CK66_0 42 1 = enabled, 0 = disabled 6 CK66_1 43 1 = enabled, 0 = disabled 5 CK66_2 46 1 = enabled, 0 = disabled 4 CK66_3 47 1 = enabled, 0 = disabled 3 CK66_4 50 1 = enabled, 0 = disabled 2 CK66_5 51 1 = enabled, 0 = disabled 1 (reserved) - Initialize to 0 0 (reserved) - Initialize to 0 Table 11: Byte 3 Register BIT CLOCK PIN 7 (reserved) - Initialize to 0 6 (reserved) - Initialize to 0 5 (reserved) - Initialize to 0 4 (reserved) - Initialize to 0 Table 8: Byte 0 Register 3 (reserved) - Initialize to 0 2 (reserved) - Initialize to 0 BIT DESCRIPTION 1 (reserved) - Initialize to 0 0 (reserved) - Initialize to 0 CLOCK PIN 7 PCI_0 6 1 = enabled, 0 = disabled 6 PCI_1 7 1 = enabled, 0 = disabled 5 PCI_2 10 1 = enabled, 0 = disabled 4 PCI_3 11 1 = enabled, 0 = disabled 3 PCI_4 14 1 = enabled, 0 = disabled 2 PCI_5 15 1 = enabled, 0 = disabled 1 PCI_6 17 1 = enabled, 0 = disabled 0 PCI_7 18 Table 12: Byte 4 Register BIT CLOCK PIN 7 (reserved) - Initialize to 0 6 (reserved) - Initialize to 0 5 (reserved) - Initialize to 0 4 (reserved) - Initialize to 0 3 (reserved) - Initialize to 0 DESCRIPTION 2 (reserved) - Initialize to 0 1 = enabled, 0 = disabled 1 (reserved) - Initialize to 0 0 (reserved) - Initialize to 0 1 = enabled, 0 = disabled Table 9: Byte 1 Register BIT 7 CLOCK PCI_8 PIN 21 6 PCI_9 22 1 = enabled, 0 = disabled 5 PCI_10 24 1 = enabled, 0 = disabled 4 PCI_11 25 1 = enabled, 0 = disabled 3 CK48_0 36 1 = enabled, 0 = disabled 2 CK48_1 37 1 = enabled, 0 = disabled 1 REF_0 54 1 = enabled, 0 = disabled 0 REF_1 55 1 = enabled, 0 = disabled ISO9001 DESCRIPTION DESCRIPTION 2.27.02 5 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC 4.0 4.2 Power Management It is expected that the clock management inputs and the register settings will be configured on power-up and will not change during normal operation. 4.1 Power Down The PWR_DWN# signal is an asynchronous, active-low LVTTL input that places the device in a low power inactive state without removing power from the device. All internal clocks are turned off, and all clock outputs are held low. The reference clocks for this device are developed by a reference clock device (FS6158). It is assumed that the PWR_DWN# signal is the same signal for both devices Since PWR_DWN# is asynchronous, the signal is synchronized internally to the falling edge of each individual clock as shown in Figure 4. Each clock stops immediately on its first falling edge after PWR_DWN#. Once powered down, both the SDA and SCL inputs are tristated. All register data is retained. Clock Enable Certain clock outputs may be disabled via either a 1. combination of logic states on the SEL_Q, SEL_R, and SEL_S clock management control input pins as shown in Table 4, or 2. the SMBus register bits, as shown in Section 3.3. Disabling a clock, as determined by the clock management control inputs, will override any SMBus register setting. Any active output, as determined by the clock management control inputs, can be disabled at any time by the SMBus register. To enable a clock output, both the control inputs and the SMBus register bits must by set appropriately. Enabled clocks will continue to run while disabled clocks are stopped. Note that if clocks are disabled while active, glitches can occur. Table 13: Latency Table PWR_ DWN# LATENCY SIGNAL STATE SIGNAL 0 Power OFF 1 Power ON MIN. MAX. Output: 0 clocks 1 clock Device: 0 clocks 1 REF clock 3ms Upon the release of PWR_DWN# (power-up), external circuitry should allow a minimum of 3ms for the PLL to lock before enabling any clocks. Figure 4: PWR_DWN# Timing Any Clock (internal) PWR_DWN# Any Clock (output) After REF outputs shut off... 3ms until clock is valid VCO Crystal Oscillator Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active. ISO9001 2.27.02 6 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC 5.0 Electrical Specifications Table 14: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. Supply Voltage (VSS = ground) MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 Junction Temperature TJ Lead Temperature (soldering, 10s) 125 C 125 C 260 C 2 kV Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 15: Operating Conditions PARAMETER Supply Voltage Operating Temperature Range SYMBOL VDD Load Capacitance ISO9001 MIN. TYP. MAX. Core and Input Buffers: (VDD, VDD_N, VDD_S) 3.135 3.3 3.465 Clock Buffers: (VDD_48, VDD_66, VDD_P, VDD_R) 3.135 3.3 3.465 TA Input Frequency Input Load Capacitance CONDITIONS/DESCRIPTION CXL CL UNITS V 0 70 14REF 14.318 66REF 66.667 66REF, 14REF C MHz 5 pF CK66 10 30 CK48 10 20 PCI 10 30 REF 10 20 pF 2.27.02 7 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 16: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic, with Loaded Outputs IDD All 3.3V supplies = 3.465V mA Supply Current, Static IDDs PWR_DWN# low, All supplies = 3.465V A Clock Inputs (14REF, 66REF) High-Level Input Voltage VIH 2.0 VDD+0.3 Low-Level Input Voltage VIL VSS-0.3 0.8 V II -5 5 A V Input Leakage Current V Digital Inputs (PWR_DWN#, SEL_Q, SEL_R, SEL_S) High-Level Input Voltage VIH 2.0 VDD+0.3 Low-Level Input Voltage VIL VSS-0.3 0.8 V II -5 5 A Input Leakage Current Serial Interface I/O (SCL, SDA) High-Level Input Voltage VIH VDD = 3.465V 2.52 VDD+0.3 V Low-Level Input Voltage VIL VDD = 3.465V VSS-0.3 1.08 V Hysteresis Voltage Vhys VDD = 3.465V 1.44 -1 V 1 A High-Level Input Current IIH Low-Level Input Current (pull-up) IIL VIL = 0V A Low-Level Output Sink Current (SDA) IOL VOH = 0.4V, VDD = 3.465V mA REF_0:1, CK48_0:1 Clock Outputs (Type 3 Clock Driver) High-Level Output Source Current Low-Level Output Sink Current Output Impedance IOH min VDD_R, VDD_48 = 3.135V, VO = 1.0V IOH max VDD_R, VDD_48 = 3.465V, VO = 3.135V -29 -23 IOL min VDD_R, VDD_48 = 3.135V, VO = 1.95V IOL max VDD_R, VDD_48 = 3.465V, VO = 0.4V 29 zOL Measured at 1.65V, output driving low 20 45 60 zOH Measured at 1.65V, output driving high 20 46 60 27 -10 10 mA mA A Tristate Output Current IOZ Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -41 mA Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 40 mA PCI_0:11, CK66_0:5 Clock Outputs (Type 5 Clock Driver) High Level Output Source Current Low Level Output Sink Current Output Impedance IOH min VDD_P, VDD_66 = 3.135V, VO = 1.0V IOH max VDD_P, VDD_66 = 3.465V, VO = 3.135V -33 -33 IOL min VDD_P, VDD_66 = 3.135V, VO = 1.95V IOL max VDD_P, VDD_66 = 3.465V, VO = 0.4V 30 zOL Measured at 1.65V, output driving low 12 55 zOH Measured at 1.65V, output driving high 12 55 -10 10 38 mA mA A Tristate Output Current IOZ Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA ISO9001 2.27.02 8 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 17: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Clock Offset tpd Propagation Delay CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V, CL = 30pF (measured on rising edges) 2.4 Rising edge on 66REF to rising edge on CK66 6.8 Rising edge on 66REF to rising edge on PCI 9.2 ns ns Tristate Enable Delay * tDZL, tDZH SEL_Q = 0, SEL_R = 0, SEL_S = 0 1.0 10 ns Tristate Disable Delay * tDLZ, tDHZ SEL_Q = 1, SEL_R = 0, SEL_S = 0 1.0 10 ns 3.0 ms 55 % 1000 ps Clock Stabilization (on power-up) * tSTB via PWR_DWN# REF_0:1 Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt Ratio of high pulse width to one clock period, measured at 1.5V tj(P) From rising edge to rising edge at 1.5V, CL = 20pF tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 20pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 20pF 45 1.0 4.0 1.0 4.0 ns ns CK48_0:1 Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * ISO9001 dt Ratio of high pulse width to one clock period, measured at 1.5V tj(P) From rising edge to rising edge at 1.5V, CL = 20pF tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 20pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 20pF 45 55 % 350 ps 1.0 4.0 1.0 4.0 ns ns 2.27.02 9 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 18: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 55 % PCI_0:11 Clock Outputs Ratio of high pulse width to one clock period, measured at 1.5V Duty Cycle * dt Clock Skew * tsk(o) PCI to PCI at 1.5V Additive Jitter, Period (peak-peak) * Rise Time * Fall Time * tj(P) From rising edge to rising edge at 1.5V, CL = 30pF tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 30pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 30pF 45 10 500 ps 500 ps 0.5 2.0 0.5 2.0 ns ns CK66_0:5 Clock Outputs Ratio of high pulse width to one clock period, measured at 1.5V Duty Cycle * dt Clock Skew * tsk(o) CK66 to CK66 at 1.5V Additive Jitter, Period (peak-peak) * tj(P) From rising edge to rising edge at 1.5V, CL = 30pF Rise Time * Fall Time * tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 30pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 30pF Figure 5: DC Measurement Points 45 55 10 % 250 ps 300 ps 0.5 2.0 0.5 2.0 ns ns Figure 6: Timing Diagram 3.3V tr tf 3.3V VOH = 2.4V 2.4V VIH = 2.0V 1.5V 50% VDD 1.5V VIL = 0.8V VOL = 0.4V 0.4V dt ISO9001 2.27.02 10 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 19: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION SCL STANDARD MODE MIN. MAX. 0 100 UNITS Clock frequency fSCL Bus free time between STOP and START tBUF 4.7 kHz s Set up time, START (repeated) tsu:STA 4.7 s Hold time, START thd:STA 4.0 s Set up time, data input tsu:DAT SDA 250 ns Hold time, data input thd:DAT SDA 0 s Output data valid from clock tAA Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP Rise time, data and clock tR SDA, SCL Fall time, data and clock tF SDA, SCL High time, clock tHI SCL 4.0 s Low time, clock tLO SCL 4.7 s 4.0 s Set up time, STOP tsu:STO 3.5 s 1000 ns 300 ns Figure 7: Bus Timing Data ~ ~ SCL ~ ~ thd:STA tsu:STA tsu:STO SDA ~ ~ ADDRESS OR DATA VALID START DATA CAN CHANGE STOP Figure 8: Data Transfer Sequence tHI SCL tR ~ ~ tF tLO tsu:STA thd:STA tAA tAA ~ ~ SDA IN tsu:DAT tsu:STO ~ ~ thd:DAT tBUF SDA OUT ISO9001 2.27.02 11 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 20: REF_0:1, CK48_0:1 Clock Outputs Voltage (V) High Drive Current (mA) MIN. TYP. MAX. Voltage (V) Low Drive Current (mA) MIN. TYP. MAX. 120 0 0 0 0 0 -38 -64 -102 100 0.2 8 13 18 0.2 -37 -64 -101 80 0.4 15 24 33 0.4 -37 -63 -100 0.6 22 33 47 0.6 -37 -63 -99 0.8 27 41 58 0.8 -36 -62 -98 1.0 31 48 68 1.0 -36 -61 -97 1.2 35 53 76 1.2 -35 -60 -95 1.4 37 57 82 1.4 -34 -59 -93 1.6 39 60 86 1.6 -33 -57 -90 1.8 39 61 88 1.8 -31 -54 -87 2.0 40 62 89 2.0 -29 -50 -81 2.2 40 63 90 2.2 -25 -46 -75 Output Current (mA) 60 40 20 0 -20 1 1.5 2 2.5 3 3.5 -60 -80 2.4 41 63 90 2.4 -21 -40 -67 2.6 41 63 90 2.6 -17 -33 -57 -120 2.8 41 63 91 2.8 -11 -25 -47 3.0 41 64 91 3.0 -5 -16 -34 64 91 3.2 -6 -21 91 3.4 3.4 0.5 -40 -100 3.2 0 30 50 Output Voltage (V) 90 Data in this table represents nominal characterization data only -5 Table 21: PCI_0:11, CK66_0:5 Clock Outputs Voltage (V) High Drive Current (mA) MIN. TYP. MAX. Voltage (V) 0 0 0 0 0.2 11 17 0.4 21 32 0.6 30 0.8 Low Drive Current (mA) MIN. TYP. MAX. 150 0 -49 -83 -132 125 24 0.2 -48 -83 -131 100 45 0.4 -48 -82 -130 45 64 0.6 -47 -81 -129 37 56 79 0.8 -47 -80 -127 1.0 43 65 92 1.0 -46 -79 -126 1.2 47 73 103 1.2 -46 -78 -124 1.4 50 78 112 1.4 -45 -76 -121 1.6 53 82 117 1.6 -43 -74 -117 1.8 54 84 120 1.8 -41 -70 -112 2.0 55 85 121 2.0 -37 -65 -105 2.2 55 85 122 2.2 -33 -59 -97 2.4 55 86 123 2.4 -28 -52 -87 -125 2.6 56 86 123 2.6 -22 -43 -74 -150 2.8 56 86 124 2.8 -14 -32 -60 3.0 56 87 124 3.0 -6 -20 -45 87 124 3.2 -7 -27 125 3.4 3.2 3.4 ISO9001 -7 Output Current (mA) 75 50 25 0 -25 0 0.5 1 1.5 2 2.5 3 3.5 -50 -75 -100 30 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only 2.27.02 12 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Package Information Table 22: 56-pin SSOP (0.300") Package Dimensions DIMENSIONS INCHES 56 MILLIMETERS MIN. MAX. MIN. MAX. A 0.095 0.110 2.41 2.79 A1 0.008 0.016 0.20 0.41 b 0.008 0.0135 0.20 0.34 c 0.005 0.010 0.13 0.25 D 0.720 0.730 18.29 18.54 E 0.395 0.420 10.03 10.67 E1 0.291 0.299 7.39 7.59 e 0.025 BSC E1 E AMERICAN MICROSYSTEMS, INC. 1 b SEATING PLANE e h x 45 0.64 BSC h 0.015 0.025 0.38 0.64 L 0.020 0.040 0.51 1.01 0 8 0 8 A c L D A1 Table 23: 56-pin SSOP (0.300") Package Characteristics PARAMETER SYMBOL Thermal Impedance, Junction to Free-Air JA Lead Inductance, Self L11 L12 Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 ISO9001 CONDITIONS/DESCRIPTION Air flow = 0 m/s TYP. UNITS 73 C/W Longest trace + wire 6.41 Shortest trace + wire 2.49 Longest trace + wire to first adjacent trace 3.65 Shortest trace + wire to first adjacent trace 1.35 Longest trace + wire to next adjacent trace 2.50 Shortest trace + wire to next adjacent trace 0.90 Longest trace + wire to VSS 0.94 Shortest trace + wire to VSS 0.50 Longest trace + wire to first adjacent trace 0.48 Shortest trace + wire to first adjacent trace 0.20 Longest trace + wire to next adjacent trace 0.07 Shortest trace + wire to next adjacent trace 0.02 nH nH pF pF 2.27.02 13 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC Table 24: 56-pin TSSOP (6.1mm) Package Dimensions DIMENSIONS INCHES MIN. MILLIMETERS MAX. MIN. MAX. A - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 b 0.0067 0.011 0.17 0.27 c 0.0035 0.008 0.09 0.20 D 0.547 0.555 13.9 14.1 E E1 e 0.318 BSC 0.236 0.244 0.018 S 1 E1 E AMERICAN MICROSYSTEMS, INC. 8.10 BSC 6.00 0.019 BSC L 56 6.20 1 0.50 BSC 0.030 0.45 0.008 - 0.20 - 0 8 0 8 b 0.75 2 12 REF 12 REF 3 12 REF 12 REF SEATING PLANE e A D A1 2 S c 3 L 1 Table 25: 56-pin TSSOP (6.1mm) Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self SYMBOL JA L11 L12 Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 ISO9001 CONDITIONS/DESCRIPTION Air flow = 0 m/s TYP. UNITS 81 C/W Longest trace + wire 4.04 Shortest trace + wire 1.38 Longest trace + wire to first adjacent trace 2.20 Shortest trace + wire to first adjacent trace 0.72 Longest trace + wire to next adjacent trace 1.43 Shortest trace + wire to next adjacent trace 0.48 Longest trace + wire to VSS 0.63 Shortest trace + wire to VSS 0.21 Longest trace + wire to first adjacent trace 0.31 Shortest trace + wire to first adjacent trace 0.07 Longest trace + wire to next adjacent trace 0.04 Shortest trace + wire to next adjacent trace 0.01 nH nH pF pF 2.27.02 14 FS6159-01 Auxiliary Motherboard Clock Generator/Buffer IC 6.0 Ordering Information DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11920-801 56-pin (0.300") SSOP 0C to 70C (Commercial) Tape and Reel 11920-811 56-pin (0.300") SSOP 0C to 70C (Commercial) Tubes 11920-201 56-pin (6.1mm) TSSOP 0C to 70C (Commercial) Tape and Reel 11920-211 56-pin (6.1mm) TSSOP 0C to 70C (Commercial) Tubes FS6159-01 2 Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Compa2 2 nies conveys a license under Philips I C Patent Rights to use these components in an I C system, provided 2 that the system conforms to the I C Standard Specification as defined by Philips. Copyright (c) 1999, 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 2.27.02 15