Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. 2.27.02
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FS6159
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1.0 Features
• Develops the peripheral clocks required for 2-way
and 4-way multi-processor clock-partitioned plat-
forms, including:
M Six buffered copies of the 66.67MHz 66REF ref-
erence input
M Twelve 33.3MHz PCI clocks, developed as a di-
vide-by-two of the 66REF reference input
M Two buffered copies of the 14.318MHz 14REF
reference input
M Two 48MHz clocks, generated by a PLL from the
14REF reference input
• Serial-bus interface control of all clock outputs
• Three clock management controls enable, disable
and tristate banks of clock outputs independently of
the serial interface
• Active-low PWR_DWN# signal allows shuts down the
PLL and disables outputs low
• Supports Test Mode and tristate output control to fa-
cilitate board testing
• Available in a 56-p in SSO P and TSSO P
Table 1: Clock Parameters
CLOCK
GROUP #
PINS SUPPLY
VOLTAGE SUPPLY
GROUP FREQUENCY
(MHz) SKEW
(MAX)
CK66 6 3.3V VDD_66 66.67 250ps
PCI 12 3.3V VDD_P 33.33 300ps
REF 2 3.3V VDD_R 14.318 -
CK48 2 3.3V VDD_48 48.008 -
Table 2: Clock Offsets
RELATION PHASE MIN TYP MAX
CK66 leads PCI 0° 1.5ns 3.5ns
Figure 1: Block Diagram
66REF
14REF
PWR_DWN#
FS6159
÷2
PCI_0:5
VDD_P
VSS_P
SCL
CK66_5
VDD_66
VSS_66
PLL
Output
Control
SMBus
SDA
SEL_Q
SEL_R
SEL_S
CK66_0:4
PCI_6:7
PCI_8:11
CK48_1
VDD_48
VSS_48
CK48_0
REF_0:1
VDD_R
VSS_R
Figure 2: Pin Configuration
1
48
2
3
4
5
6
7
8
47
46
45
44
43
42
41
14REF
VDD_N
VSS_N
VSS_P
PCI_0
PCI_4
REF_1
VDD_R
9
10
11
12
13
14
15
16VDD_P
PCI_6
PCI_7
PCI_8
VDD_P
VDD_P
PCI_10
17
18
19
20
21
22
23
PCI_11
VDD_P
PCI_2
40
39
38
37
36
35
34
33
CK66_5
VDD_66
VDD_66
CK66_4
32
31
30
29
SEL_S
VDD_48
VSS
24
FS6159-01
PCI_9
VSS_P
VSS_66
VSS_R
REF_0
25
26
27
28
VDD_S
66REF
PCI_3
VSS_S
VSS_66
PCI_5
CK48_1
VDD
CK66_0
CK66_1
CK66_2
CK66_3
VSS_66
PCI_1
52
51
50
49
56
55
54
53
VDD_P
SEL_Q
SEL_R
VSS_P
VSS_P
VSS_P
SDA
SCL
PWR_DWN#
VDD_66
CK48_0
VSS_48
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Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN TYPE NAME DESCRIPTION SUPPLY
2 DI 14REF One 14.318MHz clock input, used to develop the REF and CK48 clock outputs VDD_N
4 DI 66REF One 66.67MHz clock input, used to develop the CK66 and PCI clock outputs VDD_N
36, 37 DO CK48_0:1 Two 48MHz clock outputs VDD_48
42, 43, 46,
47, 50, 51 DO CK66_0:5 Six 66MHz cl ock outputs, developed as buff ered copi es of the 66REF reference input VDD_66
6, 7, 10, 11, 14,
15, 17, 18,
21, 22, 24, 25 DO PCI_0:11 Twelve 33.33MH z P CI clock outputs, developed as a divide-by-t wo of t he 66REF referenc e
input. Groups of PCI outputs can be disabled via SEL_Q, SEL_R, and SEL_S (see Table 4).
Individual outputs can be disabled via the serial interface. VDD_P
33 DI PWR_DWN# A synchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. VDD_S
54, 55 DO REF_0:1 Two 3.3V REF clock outputs, developed as buffered copies of the 14REF reference input VDD_R
30 DI SCL SMBus seri al interface clock input VDD_S
29 DIO SDA SMBus serial interface data i nput/ out put VDD_S
27, 28, 34 DI SEL_Q
SEL_R
SEL_S
Three clock management select inputs , us ed to enabl e, disable, or t ri st ate groups of clock
outputs VDD_S
40 P VDD 3.3V ± 5% power supply for PLL core -
38 P VDD_48 3.3V power supply for CK48 clock outputs -
44, 45, 52 P VDD_66 3.3V power supply f or CK66 clock out puts -
3 P VDD_N 3.3V power supply for the 14REF and the 66REF reference inputs -
8, 12, 16,
20, 26 P VDD_P 3.3V power supply f or the PCI cloc k outputs -
56 P VDD_R 3. 3V power supply for the REF clock outputs -
32 P VDD_S 3.3V power supply f or the serial int erf ace and digit al input pins -
39 P VSS Ground for the PLL core -
35 P VSS_48 Ground f or the CK48 clock outputs -
41, 48, 49 P VSS_66 Ground for the CK66 clock outputs -
1 P VSS_N Ground f or t he 14REF and the 66REF referenc e inputs -
5, 9, 13,
19, 23 P VSS_P Ground for the PCI clock outputs -
53 P VSS_R Ground for REF clock outputs -
31 P VSS_S Ground for t he serial int e rf ace and digit al input pins -
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2.0 Programming Information
Table 4: Clock Enable Configuration
CONTROL INPUTS (1) CLOCK OUTPUTS (MHz)
PWR_DWN# SEL_Q SEL_R SEL_S CK48_0 CK48_1 CK66_0:4 CK66_5 REF_0:1 PCI_0:5 PCI_6:7 PCI_8:11
1 0 0 0 48.008 48.008 66.67 66.67 14.318 33.33 33.33 33.33
1 0 0 1 48.008 48.008 66.67 66.67 14.318 stopped
low stopped
low 33.33
1 0 1 0 48.008 48.008 66.67 66.67 14.318 stopped
low 33.33 33.33
1 0 1 1 48.008 48.008 66.67 66.67 14.318 stopped
low stopped
low stopped
low
1 1 0 0 tristate tristate tristate tristate tristate tristate tristate tristate
1 1 0 1 48.008 48.008 66.67 stopped
low 14.318 33.33 33.33 33.33
1 1 1 0 48.008 48.008 66.67 66.67 stopped
low 33.33 33.33 33.33
1 1 1 1 48.008 stopped
low 66.67 66.67 14.318 33.33 33.33 33.33
0XXX
stopped
low stopped
low stopped
low stopped
low stopped
low stopped
low stopped
low stopped
low
1. Control inputs override any SMBus register settings in situations where the outputs are stopped low
Table 5: Synthesis Offset
CLOCK TARGET
(MHz) ACTUAL
(MHz) DEVIATION
(ppm)
CK48 (1) 48.00 48.0080 +167
1. 48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB
requirements.
3.0 Programming Interface
This device supports the SMBus Block Write and Block
Read commands. The device address is as follows:
Table 6: Device Address
A6 A5 A4 A3 A2 A1 A0
1101001
3.1 Block Write
The Block Write command allows the bus host to write
severa l bytes of data t o sequentia l registers , starting with
the Byte 0 Register. As shown in Figure 2, a Block Write
starts with the seven-bit device address followed by a
logic-low R/W bit. After an acknowledge of the device
address and R/W bit by this device, a command code is
containing all zeroes (0000 0000) is written.
After the zero command code and an acknowledge, the
bus host then issues a byte count that describes the
number of data bytes to be written. The byte count must
be a minimum of one byte and a maximum of 32 bytes.
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Table 7: Byte Count
BYTE COUNT DESCRIP TI ON
0000 0000 Not allowed: Must have at least one byte
0000 0001 Writes one byte (Byte 0)
0000 0010 Writes two bytes (Byt e 0, 1 in order)
0000 0011 Writes three bytes (Byte 0, 1, 2 in order)
0000 0100 Writes four bytes (Byte 0, 1, 2, 3 in order)
0000 0101 Writes five byt es (Byt e 0, 1, 2, 3, 4 in order)
0000 0110
to
0001 1111 These byte counts are ignored by this device
0010 0000 Maximum byte count supported (32)
After an acknowledge of the byte count, data bytes may
be written starting with Register 0 and incrementing se-
quentially. An acknowledge by this device between each
byte of data must occur before the next data byte is sent.
3.2 Block Read
The Block Read command, shown in Figure 3, permits
the host to read several bytes of data from sequential
registers, starting by default at Register 0. To perform a
Block Read procedure, the seven-bit device address is
sent, followed by a logic-high R/W bit.
Following an acknowledgement of the byte count by the
bus host, this device will take command of the bus and
will transmit all the data beginning with Register 0. After
the last byte of data, the host does not acknowledge the
final transfer but instead generates a STOP command. If
a NO-acknowledge does not occur, the device releases
the bus and the bus host will read all ones.
If the host does not want to receive all the data, the host
should not acknowledge the last data byte and instead
issue a STOP command on the next clock.
Figure 2: Block Write
AAA DATA BYTE 1
WRITE Command
Acknowledge
Command Code
Acknowledge
Data
Acknowledge
Data
STOP Command
DATA BYTE N
Acknowledge
Byte Count
Acknowledge
START
Command From bus host
to device From device
to bus host
7-bit Receive
Device Address
WS DEVICE ADDRESS A A BYTE COUNT = N P
Figure 3: Block Read
AR AA
Acknowledge
Data
Acknowledge
Data
STOP Command
Byte Count
NO Acknowledge
Repeat START REA D Command
Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device A ddress
SDEVICE ADDRESS BYTE COUNT = N ADATA BYTE 1 DATA BYTE N P
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3.3 Register Programming
A logic-one written to a valid bit location enables (turns
on) the assigned output clock. Likewise, a logic-zero
written to a valid bit location disables (turns off) the as-
signed output clock.
Any unus ed or r eserve d reg ister b its sho uld be c leare d to
zero. These registers are expected to be configured at
power-up and are not expected to change during normal
modes of operation. Serial bits are read by this device
starting with Byte 0 and proceeding to Byte 4. Bit 7 of
each byte is read first, and bits are read in descending
order down to Bit 0.
Note that the SEL_Q, SEL_R and SEL_S pins will over-
ride any register settings when disabling outputs. Regis-
ter settings will only affect enabled outputs.
Upon application of VDD to the device, all register bits
are set to one (1) so that all ou tputs are enabled and ac-
tive. Al l pr o gra m med settings will be retaine d if the de v ic e
is powered-do wn via PWR_DW N# low. Af ter po wering- up
the device via PWR_DWN# the device will operate ac-
cording to the internal register settings.
Table 8: Byte 0 Register
BIT CLOCK PIN DESCRIPTION
7 PCI_0 6 1 = enabl ed, 0 = disabl ed
6 PCI_1 7 1 = enabl ed, 0 = disabl ed
5 PCI_2 10 1 = enabled, 0 = disabled
4 PCI_3 11 1 = enabled, 0 = disabled
3 PCI_4 14 1 = enabled, 0 = disabled
2 PCI_5 15 1 = enabled, 0 = disabled
1 PCI_6 17 1 = enabled, 0 = disabled
0 PCI_7 18 1 = enabled, 0 = disabled
Table 9: Byte 1 Register
BIT CLOCK PIN DESCRIPTION
7 PCI_8 21 1 = enabled, 0 = disabled
6 PCI_9 22 1 = enabled, 0 = disabled
5 PCI_10 24 1 = enabled, 0 = disabled
4 PCI_11 25 1 = enabled, 0 = disabled
3 CK 48_0 36 1 = enabled, 0 = disabled
2 CK 48_1 37 1 = enabled, 0 = disabled
1 REF_0 54 1 = enabl ed, 0 = disabled
0 REF_1 55 1 = enabl ed, 0 = disabled
Table 10: Byte 2 Register
BIT CLOCK PIN DESCRIPTION
7 CK 66_0 42 1 = enabled, 0 = disabled
6 CK 66_1 43 1 = enabled, 0 = disabled
5 CK 66_2 46 1 = enabled, 0 = disabled
4 CK 66_3 47 1 = enabled, 0 = disabled
3 CK 66_4 50 1 = enabled, 0 = disabled
2 CK 66_5 51 1 = enabled, 0 = disabled
1 (reserved) - I ni tialize to 0
0 (reserved) - I ni tialize to 0
Table 11: Byte 3 Register
BIT CLOCK PIN DESCRIPTION
7 (reserved) - I ni tialize to 0
6 (reserved) - I ni tialize to 0
5 (reserved) - I ni tialize to 0
4 (reserved) - I ni tialize to 0
3 (reserved) - I ni tialize to 0
2 (reserved) - I ni tialize to 0
1 (reserved) - I ni tialize to 0
0 (reserved) - I ni tialize to 0
Table 12: Byte 4 Register
BIT CLOCK PIN DESCRIPTION
7 (reserved) - I ni tialize to 0
6 (reserved) - I ni tialize to 0
5 (reserved) - I ni tialize to 0
4 (reserved) - I ni tialize to 0
3 (reserved) - I ni tialize to 0
2 (reserved) - I ni tialize to 0
1 (reserved) - I ni tialize to 0
0 (reserved) - I ni tialize to 0
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4.0 Power Management
It is expected that the clock management inputs and the
register settings will be configured on power-up and will
not change during normal operation.
4.1 Clock Enable
Certain clock outputs may be disabled via either a
1. combination of logic states on the SEL_Q, SEL_R,
and SEL_S clock management control input pins as
shown in Table 4, or
2. the SMBus register bits, as shown in Section 3.3.
Disabling a clock, as determined by the clock manage-
ment contr ol inputs, wi ll override an y SMBus register s et-
ting.
Any active output, as determined by the clock manage-
ment control inputs, can be disabled at any time by the
SMBus register.
To enable a clock output, both the control inputs and the
SMBus register bits must by set appropriately. Enabled
clocks will continue to run while disabled clocks are
stopped. Note that if clocks are disabled while active,
glitches can occur.
4.2 Power Down
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
The reference clocks for this device are developed by a
reference clock device (FS6158). It is assumed that the
PWR_DWN# signal is the same signal for both devices
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to the falling edge of each individual
clock as s hown in Figure 4. Each clock s tops im mediately
on its first falling edge after PWR_DWN#.
Once powered down, both the SDA and SCL inputs are
tristated. All register data is retained.
Table 13: Latency Table
LATENCY
SIGNAL SIGNAL
STATE MIN. MAX.
Output: 0 clocks 1 c l ock
0Power
OFF Device: 0 clocks 1 REF clock
PWR_
DWN# 1Power
ON 3ms
Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.
Figure 4: PWR_DWN# Timing
Any Clock
(output)
PWR_DWN#
Any Clock
(internal)
VCO
Crystal
Oscillator
After REF
outputs shut off... 3ms until clock is valid
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
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5.0 Electrical Specifications
Table 14: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (V I < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ125 °C
Lead Temperature (soldering, 10s) 260 °C
Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage res ulting in a loss of funct ionality or performance may occur if this devi ce is subjected to a high-energy elec-
trostatic discharge.
Table 15: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Core and Input Buffers:
(VDD, VDD_N, VDD_S) 3.135 3.3 3.465
Supply Voltage VDD Cloc k B uffers:
(VDD_48, VDD_66, V DD_P, VDD_R) 3.135 3.3 3.465 V
Operating Temperature Range TA070°C
14REF 14.318
Input Frequency 66REF 66.667 MHz
Input Load Capacit ance CXL 66REF, 14REF 5 pF
CK66 10 30
CK48 10 20
PCI 10 30
Load Capacitance CL
REF 10 20
pF
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Tabl e 16: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs IDD All 3.3V supplies = 3.465V mA
Supply Current, Static IDDs PWR_DW N# low, Al l supplies = 3.465V µA
Clock Inputs (14REF, 66REF)
High-Level Input V olt age VIH 2.0 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 0.8 V
Input Leakage Current II-5 5 µA
Digital Inputs (P WR_D WN# , SEL_Q, SEL_R, SEL_S)
High-Level Input V olt age VIH 2.0 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 0.8 V
Input Leakage Current II-5 5 µA
Serial Interface I/O (SCL, SDA)
High-Level Input V olt age VIH VDD = 3.465V 2.52 VDD+0.3 V
Low-Level Input V oltage VIL VDD = 3.465V VSS-0.3 1.08 V
Hysteresis Voltage Vhys VDD = 3.465V 1.44 V
High-Level Input Current IIH -1 1 µA
Low-Level Input Current (pul l-up) IIL VIL = 0V µA
Low-Level Output Sink Current (SDA) IOL VOH = 0.4V, VDD = 3.465V mA
REF_0:1, CK48_0:1 Clock Outputs (Type 3 Clock Driver)
IOH min VDD_R, VDD_48 = 3.135V, VO = 1.0V -29
High-Level Output Sourc e Current IOH ma x V DD_R, VDD_48 = 3.465V, VO = 3.135V -23 mA
IOL min VDD_R, V DD_48 = 3.135V, VO = 1.95V 29
Low-Level Output Sink Current IOL max VDD_R, VDD_48 = 3.465V, VO = 0.4V 27 mA
zOL Measured at 1.65V, output driving low 20 45 60
Output Impedance zOH Measured at 1.65V, output driving high 20 46 60 Ω
Tristate Output Current IOZ -10 10 µA
Short Circuit Out put Source Current IOSH VO = 0V; shorted for 30s, max. -41 mA
Short Circuit Out put Sink Current IOSL VO = 3.3V; shorted for 30s, max. 40 mA
PCI_0:11, CK66_0: 5 Clock Outputs (Type 5 Clock Driver)
IOH min VDD_P, V DD_66 = 3.135V, VO = 1.0V -33
High Level Output Source Current IOH ma x V DD_P , V DD_66 = 3.465V, VO = 3.135V -33 mA
IOL min VDD_P, VDD_66 = 3.135V, VO = 1.95V 30
Low Level Output Sink Current IOL max VDD_P, VDD_66 = 3.465V, VO = 0.4V 38 mA
zOL Measured at 1.65V, output driving low 12 55
Output Impedance zOH Measured at 1.65V, output driving high 12 55 Ω
Tristate Output Current IOZ -10 10 µA
Short Circuit Out put Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA
Short Circuit Out put Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA
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Table 17: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Clock Offset tpd CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V,
CL = 30pF (measured on rising edges) 2.4 ns
Rising edge on 66REF to rising edge on CK66 6. 8
Propagation Delay Rising edge on 66REF to rising edge on PCI 9.2 ns
Tristate Enable Delay * tDZL, tDZH SEL_Q = 0, SEL_R = 0, SEL_S = 0 1.0 10 ns
Tristate Disable Delay * tDLZ, tDHZ SE L_Q = 1, SEL_R = 0, SEL_S = 0 1.0 10 ns
Clock Stabilization (on power-up) * t STB via PWR_DWN# 3.0 ms
REF_0:1 Clock Outputs
Duty Cycle * dtRatio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 20pF 1000 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 1.0
Rise Time * tr max Meas ured at 0.4V – 2.4V; CL = 20pF 4.0 ns
tf mi n Measured at 2.4V – 0.4V; CL = 10pF 1.0
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 20pF 4.0 ns
CK48_0:1 Clock Outputs
Duty Cycle * dtRat i o of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 20pF 350 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 1.0
Rise Time * tr ma x Measured at 0. 4V – 2.4V; CL = 20pF 4. 0 ns
tf mi n Measured at 2.4V – 0.4V; CL = 10pF 1.0
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 20pF 4.0 ns
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Table 18: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulati on is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
PCI_0:11 Clock Outputs
Duty Cycle * dtRatio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Clock Skew * tsk(o) PCI to PCI at 1.5V 500 ps
Additi ve Jitt er, P eri od (peak-peak ) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 30pF 10 500 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 0. 5
Rise Time * tr max Measured at 0.4V – 2.4V; CL = 30pF 2.0 ns
tf mi n Measured at 2.4V – 0.4V; CL = 10pF 0.5
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 30pF 2.0 ns
CK66_0:5 Clock Outputs
Duty Cycle * dtRatio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Clock Skew * tsk(o) CK66 to CK66 at 1.5V 250 ps
Additi ve Jitt er, P eri od (peak-peak ) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 30pF 10 300 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 0. 5
Rise Time * tr max Measured at 0.4V – 2.4V; CL = 30pF 2.0 ns
tf mi n Measured at 2.4V – 0.4V; CL = 10pF 0.5
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 30pF 2.0 ns
Figure 5: DC Measurement Points
V
IH
= 2.0V
V
IL
= 0.8V
V
OL
= 0.4V
V
OH
= 2.4V
1.5V
3.3V
Figure 6: Timing Diagram
0.4V
1.5V
2.4V
3.3V
d
t
t
f
t
r
50% V
DD
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Table 19: Serial Interface Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
STAND ARD MODE
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. MAX. UNITS
Clock frequency fSCL SCL 0 100 kHz
Bus free time between STOP and START tBUF 4.7 µs
Set up time, START (repeated) tsu:STA 4.7 µs
Hold time, START thd:STA 4.0 µs
Set up time, data input tsu:DAT SDA 250 ns
Hold time, data input thd:DAT SDA 0 µs
Output data valid from clock tAA Minimum delay to bridge undefined region of the fall-
ing edge of SCL to avoid unintended START or STOP 3.5 µs
Rise time, data and clock tRSDA, SCL 1000 ns
Fall time, data and clock tFSDA, SCL 300 ns
High time, clock tHI SCL 4.0 µs
Low time, clock tLO SCL 4.7 µs
Set up time, STOP tsu:STO 4.0 µs
Figure 7: Bus Timing Data
SCL
SDA
~
~~
~~
~
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID DATA CAN
CHANGE
Figure 8: Data Transfer Sequence
SCL
SDA
IN
t
hd:DAT
~
~
t
hd:STA
t
su:STA
t
su:STO
t
LO
t
HI
SDA
OUT
t
su:DAT
~
~~
~
t
BUF
t
R
t
F
t
AA
t
AA
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Table 20: REF_0:1, CK48_0:1 Clock Outputs
High Drive Current (mA) Low Drive Current (mA)
Voltage
(V) MIN. TYP. MAX. Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -38 -64 -102
0.2 8 13 18 0.2 -37 -64 -101
0.4 15 24 33 0.4 -37 -63 -100
0.6223347 0.6-37-63-99
0.8274158 0.8-36-62-98
1.0314868 1.0-36-61-97
1.2355376 1.2-35-60-95
1.4375782 1.4-34-59-93
1.6396086 1.6-33-57-90
1.8396188 1.8-31-54-87
2.0406289 2.0-29-50-81
2.2406390 2.2-25-46-75
2.4416390 2.4-21-40-67
2.6416390 2.6-17-33-57
2.8416391 2.8-11-25-47
3.0416491 3.0 -5-16-34
3.2 64 91 3.2 -6 -21
3.4 91 3.4 -5
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
00.511.522.533.5
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
Table 21: PCI_0:11, CK66_0:5 Clock Outputs
High Drive Current (mA) Low Drive Curren t (mA)
Voltage
(V) MIN. TYP. MAX. Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -49 -83 -132
0.2 11 17 24 0.2 -48 -83 -131
0.4 21 32 45 0.4 -48 -82 -130
0.6 30 45 64 0.6 -47 -81 -129
0.8 37 56 79 0.8 -47 -80 -127
1.0 43 65 92 1.0 -46 -79 -126
1.2 47 73 103 1.2 -46 -78 -124
1.4 50 78 112 1.4 -45 -76 -121
1.6 53 82 117 1.6 -43 -74 -117
1.8 54 84 120 1.8 -41 -70 -112
2.0 55 85 121 2.0 -37 -65 -105
2.2 55 85 122 2.2 -33 -59 -97
2.4 55 86 123 2.4 -28 -52 -87
2.6 56 86 123 2.6 -22 -43 -74
2.8 56 86 124 2.8 -14 -32 -60
3.0 56 87 124 3.0 -6 -20 -45
3.2 87 124 3.2 -7 -27
3.4 125 3.4 -7
-150
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
00.511.522.533.5
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
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Package Information
Table 22: 56-pin SSOP (0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.095 0.110 2.41 2.79
A10.008 0.016 0.20 0.41
b 0.008 0.0135 0.20 0.34
c 0.005 0.010 0.13 0.25
D 0.720 0.730 18.29 18.54
E 0.395 0.420 10.03 10.67
E10.291 0.299 7.39 7.59
e 0.025 BSC 0.64 BSC
h 0.015 0.025 0.38 0.64
L 0.020 0.040 0.51 1.01
θ0°8°0°8°
E
E
1
56
1
AMERICAN MIC ROSYSTEMS, INC.
b
DA
1
SEATING PLANE
A
e
c
L
θ
h × 45°
Table 23: 56-pin SSOP (0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 73 ° C/W
Longest trace + wire 6.41
Lead Inductanc e, Self L11 Shortest trace + wire 2.49 nH
Longest trace + wire to first adjacent trace 3.65
L12 Shortest trace + wire to first adjacent trace 1.35
Longest trace + wire to next adjacent trace 2.50
Lead Inductanc e, Mutual L13 S hort est trace + wire to next adjacent trace 0.90
nH
Longest trace + wire to VSS 0.94
Lead Capacitance, Bulk C11 Shortest trace + wire to VSS 0.50 pF
Longest trace + wire to first adjacent trace 0.48
C12 Shortest trace + wire to first adjacent trace 0.20
Longest trace + wire to next adjacent trace 0.07
Lead Capacitance, Mutual C13 Shortest trace + wire to next adjacent trace 0.02
pF
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Table 24: 56-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A - 0.047 - 1.20
A10.002 0.006 0.05 0.15
b 0.0067 0.011 0.17 0.27
c 0.0035 0.008 0.09 0.20
D 0.547 0.555 13.9 14.1
E 0.318 BSC 8.10 BSC
E10.236 0.244 6.00 6.20
e 0.019 BSC 0.50 BSC
L 0.018 0.030 0.45 0.75
S 0.008 - 0.20 -
θ10°8°0°8°
θ212° REF 12° REF
θ312° REF 12° REF
E
1
AMERICAN MICROSYSTEMS, INC.
E
1
56
be
DA
1
SEATING PLANE
Ac
L
θ
1
θ
3
θ
2
S
Table 25: 56-pin TSSOP (6.1mm) Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 81 ° C/W
Longest trace + wire 4.04
Lead Inductanc e, Self L11 Shortest trace + wire 1.38 nH
Longest trace + wire to first adjacent trace 2.20
L12 Shortest trace + wire to first adjacent trace 0.72
Longest trace + wire to next adjacent trace 1.43
Lead Inductanc e, Mutual L13 S hort est trace + wire to next adjacent trace 0.48
nH
Longest trace + wire to VSS 0.63
Lead Capacitance, Bulk C11 Shortest trace + wire to VSS 0.21 pF
Longest trace + wire to first adjacent trace 0.31
C12 Shortest trace + wire to first adjacent trace 0.07
Longest trace + wire to next adjacent trace 0.04
Lead Capacitance, Mutual C13 Shortest trace + wire to next adjacent trace 0.01
pF
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6.0 Ordering Information
DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11920-801 56-pin (0.300”) SS OP 0°C to 70°C (Commercial) Tape and Reel
11920-811 56-pin (0.300”) SS OP 0°C to 70°C (Commercial) Tubes
11920-201 56-pin (6.1mm) TSSOP 0°C to 70°C (Commercial) Tape and Reel
FS6159-01
11920-211 56-pin (6.1mm) TSSOP 0°C to 70°C (Commercial) Tubes
Purchase of I2C components of Amer ican Micr os ystem s, Inc., or one of its subl icens ed Ass ociat ed Com pa-
nies conveys a license under Philips I2C P aten t Ri ghts to use t hes e c omponents in a n I2C system , pr ovid ed
that the system conforms to the I2C Standard Specification as defined by Philips.
Copyright © 1999, 2000 American Microsystems, Inc.
Devices sold by AMI are covered b y the warranty and pat ent indem nific ation pro visions ap pearing in its T erms of Sale
only. AMI m akes no warrant y, express, s tatutor y im plied or by desc ript ion, regar ding the inf orm ation s et for th herein or
regarding t he f r eed om of the des cr ibed de vic es f rom patent inf r ingement. AMI m ak es no warranty of m erc hantabi l ity or
fitness for any pur poses. AMI reser ves the right to discont inue pro duction and c hange s pecif ications and prices a t any
time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring ex-
tended tem perature range, u nusual environm enta l requirem ents, or h igh reliab ilit y applications , such as m ilitary, m edi-
cal life-s uppor t or life-sust ain i ng e qu ipment, are sp ec if ic all y not r eco m mended witho ut add it ion al pr oc ess ing by AMI for
such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: t
g
p
@
amis.com
