512K x 8 Static RAM
WCFS4008V1C
February 11, 2002
Document #: 38-05223 Rev. **
1WCFS400 8V1C
Features
•High speed
—t
AA = 10 ns
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description
The WCFS4008V1C is a high-performance CMOS Static RAM
organized as 524K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The WCFS4008V1C is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground pinout.
14
15
Logic Block Diagram Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
CE
A
A16
A17
1
2
3
4
5
6
7
8
9
10
11
14 23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
A9
A18
18
17
19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A10
A
6
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15
29
30
V
CC
A
7
A
8
A
9
NC
NC
NC
NC
A
18
V
SS
NC
A
15
A
0
A
3
I/O
0
A
4
CE
A
17
A
12
A
1
A
2
18
17
20
19
I/O
1
27
28
25
26
22
21
23
24
NC
V
SS
WE
I/O
2
I/O
3
A
5
NC
A
16
V
CC
OE
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
13
A
11
A
10
NC
NC
NC
Selection Guide
WCFS4008V1C 10ns WCFS4008V1C 12ns
Maximum Access Time (ns) 10 12
Maximum Operating Current (mA) Comm’l 90 85
Maximum CMOS Standby Current (mA) Comm’l 10 10
WCFS4008V1C
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65×C to +150×C
Ambient Temperature with
Power Applied............................................–55×C to +125×C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range
Ambient
Temperature VCC
Commercial 0°C to +70°C3.3V ± 0.3V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions WCFS4008V1C 10ns WCFS4008V1C 12ns
Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA
2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC
+ 0.3
2.0 VCC
+ 0.3
V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1 +1 –1 +1 µA
ICC VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Comm’l 90 85 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40 40 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Comm’ll 10 10 mA
Capacitance[2]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V
8pF
COUT I/O Capacitance 8 pF
Note:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns
2. Tested initially and after any design or process changes that may affect these parameters.
WCFS4008V1C
3
AC Test Loads and Waveforms
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE (a)
R1 317Ω
R2
351Ω
OUTPUT
50Ω
Z0=50Ω
VTH = 1.5V
30pF*
(c)
(b)
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
Rise time > 1 V/ns Fall time:
> 1 V/ns
WCFS4008V1C
4
AC Switching Characteristics[3] Over the Operating Range
WCFS4008V1C 10ns WCFS4008V1C 12ns
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tpower[4] VCC(typical) to the first access 1 1 ns
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 56ns
tLZCE CE LOW to Low Z[6] 33ns
tHZCE CE HIGH to High Z[5, 6] 56ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 10 12 ns
WRITE CYCLE[7, 8]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 7 8 ns
tAW Address Set-Up to Write End 7 8 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 7 8 ns
tSD Data Set-Up to Write End 5 6 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[6] 33ns
tHZWE WE LOW to High Z[5, 6] 56ns
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4. tPOWER gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
WCFS4008V1C
5
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
WCFS4008V1C
6
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[12, 13]
Write Cycle No. 2 (WE Controlled, OE LOW)[13]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 14
Truth Table
CE OE WE I/O0 – I/O7Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Notes:
12. Data I/O is high-impedance if OE = VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
WCFS4008V1C
7
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
10 WCFS4008V1C-JC10 J 36-Lead (400-Mil) Molded SOJ Commercial
WCFS4008V1C-TC10 T 44-pin TSOP II
12 WCFS4008V1C-JC12 J 36-Lead (400-Mil) Molded SOJ
WCFS4008V1C-TC12 T 44-pin TSOP II
Package Diagrams
36-Lead (400-Mil) Molded SOJ J
WCFS4008V1C
8
Package Diagrams (continued)
44-Pin TSOP II T
512K x 8 Static RAM
WCFS4008V1C
February 11, 2002
Document #: 38-05223 Rev. **
Revision History
Document Title: WCFS4008V1C 32K x 8 3.3V Static RAM
Document Number: Document #: 38-05223 Rev. **
REV. ECN NO. ISSUE DATE ORIG. OF CHANGE
DESCRIPTION OF
CHANGE
** 113101 1/25/2002 XFL New Datasheet
