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FEATURES
Not Recommended for New Designs
TSB43AB22
SLLA208 – JUNE 2006
Integrated 1394a-2000 OHCI PHY/Link-Layer Controller
•PHY-Link logic performs system initializationand arbitration functions•Fully compliant with provisions of IEEE Std1394-1995 for a high-performance serial bus
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•PHY-Link encode and decode functionsand IEEE Std 1394a-2000 included for data-strobe bit level encoding•Fully interoperable with FireWire and i.LINK •PHY-Link incoming data resynchronized toimplementations of IEEE Std 1394 local clock•Compliant with Intel Mobile Power Guideline •Low-cost 24.576-MHz crystal provides2000 transmit and receive data at 100M bits/s,200M bits/s, and 400M bits/s•Full IEEE Std 1394a-2000 support includes:connection debounce, arbitrated short reset, •Node power class information signaling formultispeed concatenation, arbitration system power managementacceleration, fly-by concatenation, and port
•Serial ROM interface supports 2-wire serialdisable/suspend/resume
EEPROM devices•Power-down features to conserve energy in
•Two general-purpose I/Osbattery-powered applications include:
•Register bits give software control ofautomatic device power down during
contender bit, power class bits, link activesuspend, PCI power management for
control bit, and IEEE Std 1394a-2000 featureslink-layer, and inactive ports powered down
•Fabricated in advanced low-power CMOS•Ultralow-power sleep mode
process•Two IEEE Std 1394a-2000 fully compliant
•PCI and CardBus register supportcable ports at 100M bits/s, 200M bits/s, and
•Isochronous receive dual-buffer mode400M bits/s
•Out-of-order pipelining for asynchronous•Cable ports monitor line conditions for active
transmit requestsconnection to remote node
•Register access fail interrupt when the PHY•Cable power presence monitoring
SCLK is not active•Separate cable bias (TPBIAS) for each port
•PCI power-management D0, D1, D2, and D3•1.8-V core logic with universal PCI interfaces
power statescompatible with 3.3-V and 5-V PCI signaling
•Initial bandwidth available and initialenvironments
channels available registers•Physical write posting of up to three
•PME support per 1394 Open Host Controlleroutstanding transactions
Interface Specification•PCI burst transfers and deep FIFOs to
NOTE: Implements technology covered by one or more patentstolerate large host latency
of Apple Computer, Incorporated and SGS Thompson,Limited.•PCI_CLKRUN protocol•External cycle timer control for customizedsynchronization
•Extended resume signaling for compatibilitywith legacy DV components
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION
Not Recommended for New Designs
TSB43AB22
SLLA208 – JUNE 2006
The Texas Instruments TSB43AB22 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC)device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management InterfaceSpecification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller InterfaceSpecification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s,200M bits/s, and 400M bits/s. The TSB43AB22 device provides two 1394 ports that have separate cable bias(TPBIAS). The TSB43AB22 device also supports the IEEE Std 1394a-2000 power-down features forbattery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internalcontrol registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed throughconfiguration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, theTSB43AB22 device is compliant with the PCI Bus Power Management Interface Specification as specified by thePC 2001 Design Guide requirements. The TSB43AB22 device supports the D0, D1, D2, and D3 power states.
The TSB43AB22 design provides PCI bus master bursting, and it is capable of transferring a cacheline of dataat 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs areprovided to buffer the 1394 data.
The TSB43AB22 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2performance. The TSB43AB22 device also provides multiple isochronous contexts, multiple cacheline bursttransfers, advanced internal arbitration, and bus-holding buffers.
An advanced CMOS process achieves low power consumption and allows the TSB43AB22 device to operate atPCI clock rates up to 33 MHz.
The TSB43AB22 PHY-layer provides the digital and analog transceiver functions needed to implement atwo-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. Thetransceivers include circuitry to monitor the line conditions as needed for determining connection status, forinitialization and arbitration, and for packet reception and transmission.
The TSB43AB22 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. Anexternal clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop(PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided toprovide the clock signals that control transmission of the outbound encoded strobe and data information. A49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronizationof the received data.
Data bits to be transmitted through the cable ports are received from the integrated LLC and are latchedinternally in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, andtransmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively)as the outbound data-strobe information stream. During transmission, the encoded data information istransmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information istransmitted differentially on the twisted-pair A (TPA) cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and thereceivers for that port are enabled. The encoded data information is received on the TPA cable pair, and theencoded strobe information is received on the TPB cable pair. The received data-strobe information is decodedto recover the receive clock signal and the serial data bits. The serial data bits are resynchronized to the local49.152-MHz system clock and sent to the integrated LLC. The received data is also transmitted (repeated) onthe other active (connected) cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states duringinitialization and arbitration. The outputs of these comparators are used by the internal logic to determine thearbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of thiscommon-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of theremotely supplied twisted-pair bias voltage.
The TSB43AB22 device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. ThePHY layer contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remotereceiver, indicates the presence of an active connection. This bias voltage source must be stabilized by anexternal filter capacitor of 1.0 µF.
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Not Recommended for New Designs
TSB43AB22
SLLA208 – JUNE 2006
The line drivers in the TSB43AB22 device operate in a high-impedance current mode and are designed to workwith external 112- Ωline-termination resistor networks in order to match the 110- Ωcable impedance. Onenetwork is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected56- Ωresistors. The midpoint of the pair of resistors that is directly connected to the TPA terminals is connectedto its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected tothe TPB terminals is coupled to ground through a parallel R-C network with recommended values of 5 k Ωand220 pF. The values of the external line-termination resistors are designed to meet the standard specificationswhen connected in parallel with the internal receiver circuits. An external resistor connected between the R0 andR1 terminals sets the driver output current and other internal operating currents. This current-setting resistor hasa value of 6.34 k Ω ± 1%.
When the power supply of the TSB43AB22 device is off and the twisted-pair cables are connected, theTSB43AB22 transmitter and receiver circuitry present a high impedance to the cable and do not load theTPBIAS voltage at the other end of the cable.
When the device is in a low-power state (for example, D2 or D3) the TSB43AB22 device automatically enters alow-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, theTSB43AB22 device disables its internal clock generators and also disables various voltage and currentreference circuits, depending on the state of the ports (some reference circuitry must remain active in order todetect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest powerconsumption (the ultralow-power sleep mode) is attained when all ports are either disconnected or disabled withthe port interrupt enable bit cleared.
The TSB43AB22 device exits the low-power mode when bit 19 (LPS) in the host controller control register atOHCI offset 50h/54h is set to 1 or when a port event occurs which requires that the TSB43AB22 device tobecome active in order to respond to the event or to notify the LLC of the event (for example, incoming bias isdetected on a suspended port, a disconnection is detected on a suspended port, or a new connection isdetected on a nondisabled port). When the TSB43AB22 device is in the low-power mode, the internal49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19(LPS) in the host controller control register at OHCI offset 50h/54h is set to 1.
The TSB43AB22 device supports hardware enhancements to better support digital video (DV) and MPEG datastream reception and transmission. These enhancements are enabled through the isochronous receive digitalvideo enhancements register at OHCI offset A88h. The enhancements include automatic timestamp insertion fortransmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping forreceived DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous datacontexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIPformats. The TSB43AB22 device supports modification of the synchronization timestamp field to ensure that thevalue inserted via software is not stale—that is, the value is less than the current cycle timer when the packet istransmitted.
NOTE:
This product is for high-volume PC applications only. For a complete datasheet ormore information contact support@ti.com.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TSB43AB22PDT NRND TQFP PDT 128 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TSB43AB22PDTG4 NRND TQFP PDT 128 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
MECHANICAL DATA
MPQF013 – NOVEMBER 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PDT (S-PQFP-G128) PLASTIC QUAD FLATPACK
64
33 0,13 NOM
Gage Plane
0,25
0,45
0,75
Seating Plane
0,05 MIN
4087726/A 1 1/95
0,23
0,13
65
32
96
1
12,40 TYP
128
97
SQ
SQ
0,95
1,05
15,90
16,10
13,95
1,20 MAX
14,05
0,08
0,40 M
0,05
0°–5°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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