4Gb 200b: x32 LPDDR4 SDRAM Features LPDDR4 SDRAM MT53B128M32 Features Options Marking * VDD1/VDD2: 1.8V/1.1V * Array configuration - 128 Meg x 32 (2 - x16 channels) * Device configuration - 1 x 128M32 die in package * FBGA "green" package - 200-ball WFBGA (10mm x 14.5mm), O0.28 SMD - 200-ball WFBGA (10mm x 14.5mm), O0.35 SMD * Speed grade, cycle time - 625ps @ RL = 28/32 * Special option - standard * Operating temperature range - -30C to +85C - -40C to +95C * Revision * Ultra-low-voltage core and I/O power supplies - VDD1 = 1.70-1.95V; 1.8V nominal - VDD2/VDDQ = 1.06-1.17V; 1.10V nominal * Frequency range - 1600-10 MHz (data rate range: 3200-20 Mb/s/ pin) * 16n prefetch DDR architecture * 2-channel partitioned architecture for low RD/WR energy and low average latency * 8 internal banks per channel for concurrent operation * Single-data-rate CMD/ADR entry * Bidirectional/differential data strobe per byte lane * Programmable READ and WRITE latencies (RL/WL) * Programmable and on-the-fly burst lengths (BL = 16, 32) * Directed per-bank refresh for concurrent bank operation and ease of command scheduling * Up to 12.8 GB/s per die (2 channels x 6.4 GB/s) * On-chip temperature sensor to control self refresh rate * Partial-array self refresh (PASR) * Selectable output drive strength (DS) * Clock-stop capability * RoHS-compliant, "green" packaging * Programmable V SSQ (ODT) termination B 128M32 D1 NP DS -062 - WT IT :A Table 1: Key Timing Parameters Speed Grade Clock Rate (MHz) Data Rate (Mb/s/pin) WRITE Latency Set A WRITE Latency Set B READ Latency (DBI Disabled) READ Latency (DBI Enabled) -062 1600 3200 14 26 28 32 CCMTD-554574167-10461 200b_z00n_lpddr4.pdf - Rev. C 5/17 EN Short 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Gb 200b: x32 LPDDR4 SDRAM Features SDRAM Addressing The table below shows addressing for the 4Gb die density. Where applicable, a distinction is made between perchannel and per-die parameters. All bank, row, and column addresses are shown per-channel. Table 2: Device Addressing Configuration 128M32 (4Gb) Die per package 1 Device density (per die) 4Gb Device density (per channel) 2Gb Configuration 16Mb x 16 DQ x 8 banks x 2 channels x 1 rank Number of channels (per die) 2 Number of ranks per channel 1 Number of banks (per channel) 8 Array prefetch (bits) (per channel) 256 Number of rows (per bank) 16,384 Number of columns (fetch boundaries) 64 Page size (bytes) 2048 Channel density (bits per channel) 2,147,483,648 Total density (bits per die) 4,294,967,296 Bank address BA[2:0] x16 Burst starting address boundary Notes: Row addresses R[13:0] Column addresses C[9:0] 64-bit 1. The lower two column addresses (C0-C1) are assumed to be zero and are not transmitted on the CA bus. 2. Row and column address values on the CA bus that are not used for a particular density are "Don't Care." 3. For non-binary memory densities, only half of the row address space is valid. When the MSB address bit is HIGH, the MSB - 1 address bit must be LOW. CCMTD-554574167-10461 200b_z00n_lpddr4.pdf - Rev. C 5/17 EN Short 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 4Gb 200b: x32 LPDDR4 SDRAM Features Part Number and Part Marking Information Part Number Ordering Micron LPDDR4 devices are available in different configurations and densities. Verify valid part numbers by using Micron's part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Number Chart MT 53 D 348M32 D2 NP -062 A Micron Technology IT :B Design Revision :A, :B, :C, :D Product Family 53 = Mobile LPDDR4 SDRAM Operating Temperature Operating Voltage WT = -30C to +85C IT = -40C to +95C XT = -40C to +105C B = 1.10V D = 1.10V VDD2/0.60V VDDQ Automotive Certification (option) A = Package-level burn-in (Blank) = Standard Configuration 128M32 = 128 Meg x 32 256M32 = 256 Meg x 32 384M32 = 384 Meg x 32 512M32 = 512 Meg x 32 768M32 = 768 Meg x 32 1024M32 = 1024 Meg x 32 Cycle Time -062 = 625ps, tCK RL = 28/32 -053 = 535ps, tCK RL = 32/36 -046 = 468ps, tCK RL = 36/40 Addressing Package Codes D1 = LPDDR4, 1 die D2 = LPDDR4, 2 die D4 = LPDDR4, 4 die DS = 200-ball WFBGA 10 x 14.5 x 0.8mm (O0.35 SMD) DT = 200-ball VFBGA 10 x 14.5 x 0.95mm (O0.35 SMD) NP = 200-ball WFBGA 10 x 14.5 x 0.8mm (O0.28 SMD) NQ = 200-ball VFBGA 10 x 14.5 x 0.95mm (O0.28 SMD) FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron's FBGA part marking decoder is available at www.micron.com/decoder. Full specification can be acquired through a Micron representative and under NDA CCMTD-554574167-10461 200b_z00n_lpddr4.pdf - Rev. C 5/17 EN Short 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved.