30E D me 7929237 0030122 & Mm J-39-(( AY, Bieponttonse, SG S-THONSON _ _ BUZ21 CHIP N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN DIE FORM e DIE SIZE: 156 x 156 mils METALLIZATION: Top Al Back Au/Cr/Ni/Au BACKSIDE THICKNESS: 6100 A DIE THICKNESS: 16 + 2 mils * PASSIVATION: P-Vapox BONDING PAD SIZE: Source 40 x 34 mils Gate 15x19 mils RECOMMENDED WIRE BONDING: Source Al - max 15 mils Gate Al- max 7 mils Die geometry SCHEMATIC DIAGRAM o G s Voss Ros (on) Ip* 100 V 0.1 92 19A N-channel enhancement mode POWER MOS field effect transistor. Easy drive and very fast switching times make this POWER MOS ideal for high speed switching applications. Mc-0074 SOURCE McGarr Drain on backside * With Pihpe max. 1.67C/W June 1988 1/2 BUZ21 CHIP 306 D MM 7929237 0030123 6 GUARANTEED PROBED ELECTRICAL CHARACTERISTICS (T,;= 25C, Note 1) Parameters Test Conditions Min. Typ. | Max. | Unit Vier) oss Drain-source Ip= 250 pA Ves= 0 100 Vv breakdown voltage oo . T-39-11 loss Zero gate voltage Vpg= Max Rating 250 | wA drain current Vps= Max Rating x 0.8 T;= 125C 1000] pA lass Gate-body leakage Veg = +20 V 100 | nA current Ves (th) Gate threshold Vos =Ves Ip =1mA 2.1 4 Vv voltage Ros (on) Static drain-source Ves= 10 V Ip=1A 0.1 2 on resistance NOTES: 1 - Due to probe testing limitations dc parameters only are tested. They are measured using pulse techni- ques: pulse width <300 us, duty cycle <2% 2-For detailed device characteristics please refer to the discrete device datasheet 2l2 644