of the output voltage, at the expense of light-load efficiency,
the switchers can be commanded to stay in PWM-only mode
by setting bit 0 of R10 in the slave’s registers.
CURRENT LIMITING
A current limit feature exists for all regulators to help protect
the LP5552 and external components during overload condi-
tions. The switcher's current limit feature will trip around 1.2A
(typ). Once the fault has occurred and current limit has been
entered, the switcher will not resume operation until the output
current has decreased to a hysteretic low-level set point. Nor-
mal operation will proceed after the fault has been cleared.
Likewise, the LDOs all implement current limit and will turn off
their pass element when their trip point is reached. Please
refer to the Electrical Characteristics section for details.
SOFT START
Both switching regulators implement a digital soft-start fea-
ture to limit in-rush current during the Startup to Active state
transition. The voltage output of the switchers will be gradually
increased to the default value of 1.235V. An unloaded switch-
er output will reach its final value in 120µS (typ.) while a fully
loaded switcher – 800mA -- will reach its output in 135µS (typ).
Because the LP5552 uses voltage increments to handle soft-
start, its turn-on time is less dependent on output capacitance
and load current than regulators that gradually increase cur-
rent limit to implement soft-start.
LDO2
The on-board LDO2 regulator has special significance to the
LP5552. All digital data on the SCLK, SPWI, and the GPOx
pins while in push-pull mode, is referenced to this voltage.
This regulator is used internally to power the I/O drivers. As
such, this regulator must be on in order to communicate with
the LP5552. The user should ensure that this regulator does
not go into dropout or PWI communication will most likely not
be possible. If it is not desirable to use this regulator in the
system, the user can turn this regulator off by setting bit 4 of
R10 in Slave ‘N’ during system initialization while back-driving
the required I/O voltage onto the pin.
TRACKING, SLEW RATE LIMITING, AND LOW IQ BITS
There are 3 bits in each slave’s R13 register that determine
the performance and operational behavior of the VCOREx and
VO3/VO4 outputs. Their significance and interaction is de-
scribed below.
The Low IQ bit setting in R13, bit 0, of each slave allows the
selection of a lower IQ bias point at the expense of decreased
output current capability for VO3 and VO4. At reset, the default
setting is high IQ mode (i.e., bit 0 is cleared) which results in
a 50mA output capability for the associated LDO. If bit 0 is
set, the quiescent current draw of the part will decrease, but
the output current capability of the associated LDO will drop
to 5mA. Setting VO3 and VO4 up for low IQ mode is useful in
situations where just a trickle of current is required, such as
when maintaining some type of low-power memory.
The Tracking bit, bit 1 in R13, determines whether or not the
LDO3 voltage will track the VCORE1 voltage in Slave ‘N’. Slave
‘N+1’ has its own tracking bit which will determine whether
LDO4 tracks VCORE2. Each slave device can be independently
configured to tracking or independent mode. When set to op-
erate independently, LDO3 and LDO4 will maintain a voltage
output equal to the programmed value of R1 while in the Ac-
tive state. When set to operate in tracking mode, LDO3 and
LDO4 will track the output voltage of their associated switch-
er, attempting to maintain approximately a 25mV positive
offset.
There is some interaction between the Low IQ and Tracking
bits based on the state of the slave device, and that is detailed
in the following table:
TABLE 3. Tracking, IQ Bit, Slave State Truth Table
Input Output
Tracking, R13[1] Low IQ, R13[0] State LDO3/LDO4 Capability
0 0 Active 50mA
0 0 Sleep 50mA
0 1 Active 5mA
0 1 Sleep 5mA
1 0 Active 50mA
1 0 Sleep 50mA
1 1 Active 50mA
1 1 Sleep 5mA
The final bit, the Slew Rate Limiting bit (R13[2]), places a limit
on how fast the output voltage of the VCOREx regulators can
change. If slew rate limiting is not enabled while in tracking
mode (i.e., R13[2] is cleared), then the switcher will achieve
its new programmed value faster than the tracking LDO can
change its output. By setting the Slew Rate Limiting bit, the
LP5552 will attempt to keep the positive offset of the tracking
LDO in relation to the VCOREx output.
For AVS systems, the expected configuration is to have all 3
bits, R13[2:0] set to ‘1’. It generally will not make sense to set
the Slew Rate Limiting bit while not in tracking mode. Setting
all 3 bits will result in a system which has the following prop-
erties:
1. The tracking LDO will maintain positive offset from
VCOREx in Active state.
2. Tracking LDO will be 50mA output capable in Active
state, and 5mA capable in Sleep state.
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LP5552